U.S. patent number 9,347,993 [Application Number 13/919,984] was granted by the patent office on 2016-05-24 for test generation for test-per-clock.
This patent grant is currently assigned to Mentor Graphics Corporation. The grantee listed for this patent is Mentor Graphics Corporation. Invention is credited to Grzegorz Mrugalski, Janusz Rajski, Jedrzej Solecki, Jerzy Tyszer.
United States Patent |
9,347,993 |
Rajski , et al. |
May 24, 2016 |
Test generation for test-per-clock
Abstract
Aspects of the invention relate to test generation techniques
for test-per-clock. Test cubes may be generated by adding
constraints to a conventional automatic test pattern generator.
During a test cube merging process, a first test cube is merged
with one or more test cubes that are compatible with the first test
cube to generate a second test cube. The second test cube is
shifted by one bit along a direction of scan chain shifting to
generate a third test cube. The third test cube is then merged with
one or more test cubes in the test cubes that are compatible with
the third test cube to generate a fourth test cube. The shifting
and merging operations may be repeated for a predetermined number
of times.
Inventors: |
Rajski; Janusz (West Linn,
OR), Solecki; Jedrzej (Poznan, PL), Tyszer;
Jerzy (Poznan, PL), Mrugalski; Grzegorz
(Swardzez, PL) |
Applicant: |
Name |
City |
State |
Country |
Type |
Mentor Graphics Corporation |
Wilsonville |
OR |
US |
|
|
Assignee: |
Mentor Graphics Corporation
(Wilsonville, OR)
|
Family
ID: |
52020351 |
Appl.
No.: |
13/919,984 |
Filed: |
June 17, 2013 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20140372824 A1 |
Dec 18, 2014 |
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G01R
31/318563 (20130101); G01R 31/318544 (20130101); G01R
31/318307 (20130101) |
Current International
Class: |
G01R
31/28 (20060101); G01R 31/3183 (20060101); G01R
31/3185 (20060101) |
Field of
Search: |
;714/733,731,726-727 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
B Konemann, J. Mucha and G. Zwiehoff, Institut : "Built-In Logic
Block Observation Techniques" 1979 IEEE Test Conference, Cherry
Hill, New Jersey (1979). cited by applicant .
A. Krasniewski and S. Pilarski: "Circular Self-Test Path: A
Low-Cost BIST Technique for VLSI Circuits", IEEE Transactions on
Computer Aided Design, vol. 8, No. 1 (Jan. 1989). cited by
applicant.
|
Primary Examiner: Lamarre; Guy
Attorney, Agent or Firm: Klarquist Sparkman, LLP
Claims
What is claimed is:
1. A method for generating a test pattern for testing an electronic
circuit, comprising: by at least one processor of a computer,
generating a plurality of test cubes for testing the electronic
circuit; by the at least one processor of the computer, selecting,
from the plurality of test cubes, a first test cube to be applied
by one or more scan chains of the electronic circuit during the
testing; by the at least one processor of the computer, merging the
first test cube with one or more test cubes in the plurality of
test cubes that are compatible with the first test cube to generate
a second test cube to be applied by the one or more scan chains of
the electronic circuit during the testing; by the at least one
processor of the computer, shifting the second test cube by one bit
along a shift direction of the one or more scan chains in the
electronic circuit to generate a third test cube, such that the
last bit of the second test cube along the shift direction is the
second to last bit of the third test cube along the shift
direction; and by the at least one processor of the computer,
merging the third test cube with one or more test cubes in the
plurality of test cubes that are compatible with the third test
cube to generate a fourth test cube to be applied by the one or
more scan chains of the electronic circuit during the testing,
wherein at least one of the one or more test cubes that is
compatible with the third test cube is not compatible with the
first or second test cubes.
2. The method recited in claim 1, further comprising: by the at
least one processor of the computer, shifting the fourth test cube
by one bit along the shift direction of the one or more scan chains
in the electronic circuit to generate a fifth test cube; by the at
least one processor of the computer, merging the fifth test cube
with one or more test cubes in the plurality of test cubes that are
compatible with the fifth test cube to generate a sixth test cube
to be applied by the one or more scan chains of the electronic
circuit during the testing, wherein at least one of the one or more
test cubes that is compatible with the fifth test cube is not
compatible with the third or fourth test cubes; and repeating the
shifting and the merging for a predetermined number of times.
3. The method recited in claim 1, wherein the plurality of test
cubes are generated according to a configuration of multiple scan
chains of the electronic circuit: a first portion of the multiple
scan chains configured to operate in a shifting-launching mode, a
second portion of the multiple scan chains configured to operate in
a capturing-compacting-shifting mode, and a third portion of the
multiple scan chains configured to operate in a mission mode.
4. The method recited in claim 3, wherein the
capturing-compacting-shifting mode is a mode of compaction with
blocking.
5. The method recited in claim 3, wherein the
capturing-compacting-shifting mode is a mode of compaction without
blocking.
6. The method recited in claim 3, wherein the shifting-launching
mode is the only mode that allows a scan chain to have specified
bits.
7. One or more non-transitory computer-readable media storing
computer-executable instructions for causing one or more processors
to perform a method for generating a test pattern for testing an
electronic circuit, the method comprising: generating a plurality
of test cubes for testing the electronic circuit; selecting a first
test cube, from the plurality of test cubes, to be applied by one
or more scan chains of the electronic circuit during the testing;
merging the first test cube with one or more test cubes in the
plurality of test cubes that are compatible with the first test
cube to generate a second test cube to be applied by the one or
more scan chains of the electronic circuit during the testing;
shifting the second test cube by one bit along a direction of scan
chain shifting of the one or more scan chains of the electronic
circuit to generate a third test cube, such that the last bit of
the second test cube along the shift direction is the second to
last bit of the third test cube along the shift direction; and
merging the third test cube with one or more test cubes in the
plurality of test cubes that are compatible with the third test
cube to generate a fourth test cube to be applied by the one or
more scan chains of the electronic circuit during testing, wherein
at least one of the one or more test cubes that is compatible with
the third test cube is not compatible with the first or second test
cubes.
8. The one or more non-transitory computer-readable media recited
in claim 7, wherein the method for generating the test pattern for
testing the electronic circuit further comprises: shifting the
fourth test cube by one bit along the direction of scan chain
shifting of the one or more scan chains of the electronic circuit
to generate a fifth test cube; merging the fifth test cube with one
or more test cubes in the plurality of test cubes that are
compatible with the fifth test cube to generate a sixth test cube
to be applied by the one or more scan chains of the electronic
circuit during testing, wherein at least one of the one or more
test cubes that are compatible with the fifth test cube is not
compatible with the third or fourth test cubes; and repeating the
shifting and the merging for a predetermined number of times.
9. The one or more non-transitory computer-readable media recited
in claim 7, wherein the plurality of test cubes are generated
according to a configuration of scan chains of the electronic
circuit: a first portion of the scan chains of the electronic
circuit configured to operate in a shifting-launching mode, a
second portion of the scan chains of the electronic circuit
configured to operate in a capturing-compacting-shifting mode, and
a third portion of the scan chains of the electronic circuit
configured to operate in a mission mode.
10. The one or more non-transitory computer-readable media recited
in claim 9, wherein the compaction mode is a mode of compaction
with blocking.
11. The one or more non-transitory computer-readable media recited
in claim 9, wherein the compaction mode is a mode of compaction
without blocking.
12. The one or more non-transitory computer-readable media recited
in claim 9, wherein the shifting-launching mode is the only mode
that allows a scan chain to have specified bits.
13. A system comprising: one or more processors, the one or more
processors programmed to perform a method for generating a test
pattern for testing an electronic circuit, the method comprising:
generating a plurality of test cubes for testing the electronic
circuit; selecting, from the plurality of test cubes, a first test
cube to be applied by one or more scan chains of the electronic
circuit during the testing; merging the first test cube with one or
more test cubes in the plurality of test cubes that are compatible
with the first test cube to generate a second test cube to be
applied by the one or more scan chains of the electronic circuit
during the testing; shifting the second test cube by one bit along
a shift direction of the one or more scan chains in the electronic
circuit to generate a third test cube, such that the last bit of
the second test cube along the shift direction is the second to
last bit of the third test cube along the shift direction; and
merging the third test cube with one or more test cubes in the
plurality of test cubes that are compatible with the third test
cube to generate a fourth test cube to be applied by the one or
more scan chains of the electronic circuit during the testing,
wherein at least one of the one or more test cubes that is
compatible with the third test cube is not compatible with the
first or second test cubes.
14. The system recited in claim 13, wherein the method further
comprises: shifting the fourth test cube by one bit along the shift
direction of the one or more scan chains in the electronic circuit
to generate a fifth test cube; merging the fifth test cube with one
or more test cubes in the plurality of test cubes that are
compatible with the fifth test cube to generate a sixth test cube
to be applied by the one or more scan chains of the electronic
circuit during the testing, wherein at least one of the one or more
test cubes that is compatible with the fifth test cube is not
compatible with the third or fourth test cubes; and repeating the
shifting and the merging for a predetermined number of times.
15. The system recited in claim 13, wherein the plurality of test
cubes are generated according to a configuration of scan chains of
the electronic circuit: a first portion of the scan chains of the
electronic circuit configured to operate in a shifting-launching
mode, a second portion of the scan chains of the electronic circuit
configured to operate in a capturing-compacting-shifting mode, and
a third portion of the scan chains of the electronic circuit
configured to operate in a mission mode.
16. The system recited in claim 15, wherein the compaction mode is
a mode of compaction with blocking.
17. The system recited in claim 15, wherein the compaction mode is
a mode of compaction without blocking.
18. The system recited in claim 15, wherein the shifting-launching
mode is the only mode that allows a scan chain to have specified
bits.
Description
FIELD OF THE INVENTION
The present invention relates to the field of circuit testing
technology. Various implementations of the invention may be
particularly useful for scan chain-based testing.
BACKGROUND OF THE INVENTION
Since its introduction in the late 1960's, scan-based testing has
gained a wide acceptance as a structured design-for-test (DFT)
methodology. This methodology connects memory elements such as
flip-flops and latches in a circuit to form scan chains and uses
them to make internal nodes of the circuit highly controllable and
observable. The controllability and observability enables
high-quality automated test generation for large industrial circuit
designs.
A commonly used scheme of the scan-based testing is test-per-scan.
In a test-per-scan system, a test pattern is first shifted into
scan chains and subsequently applied to the circuit-under-test. The
test responses generated by the circuit-under-test are then
captured by and shifted out of the scan chains for analysis. In
this testing scheme, the shifting in and out operations require
much more clock cycles to perform than the actual testing (i.e.
launching and capturing) operation does. Moreover, in part due to
power concerns, the shifting clock is usually kept slower than the
clock for the circuit's normal operation. This further increases
time for the data loading and unloading operations.
Consider, for example, a circuit design with 100,000 scan cells.
These scan cells are divided into 500 scan chains, each 200 scan
cells long. Assume the shifting and the normal operating clock
frequencies of 50 MHz and 500 MHz, respectively. Applying 20,000
double-capture test patterns requires 4,000,000 shift cycles at 50
MHz and 40,000 capture cycles at 500 MHz. As a result, as low as 1%
of cycles, or just 0.1% of time, is spent on the actual testing
operation--applying test data and capturing test response data. If
a BIST (built-in self-test) method is used for the same circuit
design, the test time efficiency could be even lower. With 100K
single-capture test patterns, 20,000,000 cycles are needed for scan
shifting while only 100,000 cycles are needed for launching and
capturing. Using the same clock frequencies as the above example,
99.95% of test time is spent on scan shifting. The above two
examples demonstrate that the test-per-scan scheme, though well
developed and widely adopted, is not very efficient with respect to
testing time.
An alternative scheme, test-per-clock, has been developed mainly
for BIST. In a conventional test-per-clock BIST system, the outputs
of a test pattern generator are directly coupled to the inputs of
the circuit-under-test. Accordingly, a new test pattern is applied
to the circuit-under-test at every test clock cycle.
A 1979 paper by Konemann et al., "Built-in logic block observation
techniques," 1979 IEEE Test Conference, which is incorporated
herein by reference, describes such a system referred to as BILBO
(built-in logic block observer). A BILBO is composed of a flipflop
register with additional gates for shift and feedback operations.
Four different operational modes can be performed by the BILBO: a
mission mode (normal circuit functional mode with scan cells
working as latches), a linear shift register mode, a feedback mode,
and a reset mode for register resetting. In the feedback mode, the
BILBO can work either as a multiple-input signature register (MISR)
for compacting test responses or as a linear feedback shift
register (LFSR) for generating pseudorandom test patterns. The
latter is accomplished by keeping constant values at the parallel
inputs of the scan chain.
The 1979 paper describes an example of a test-per-clock
architecture with BILBOs working in pairs. One BILBO in a BILBO
pair is configured to operate in the feedback mode functioning as a
linear feedback shift register. This LFSR BILBO generates and
launches a test pattern every test clock cycle. In the meantime,
the other BILBO in the pair is configured to operate also in the
feedback mode but functioning as a multiple-input signature
generator. This MISR BILBO captures a test response every test
clock cycle and compacts it with its previously compacted test
response to form a new compacted test response. After a number of
test clock cycles, a test response signature is eventually shifted
out of the MISR BILBO by switching its operational mode from the
feedback mode to the linear shift register mode. The unloaded test
response signature can then be analyzed.
Another test-per-clock BIST system is described in a 1989 paper by
Krasniewski et al., "Circular self-test path: a low cost BIST
technique for VLSI circuits," IEEE Trans. CAD, vol. 8, pp. 46-55,
1989, which is incorporated herein by reference. This system uses a
feedback shift register with the last flipflop being supplied to
the first flipflop. This shift register serves simultaneously for
test pattern generation and test response compaction.
Compared to the test-per-scan scheme, the test-per-clock scheme is
more time-efficient because no slow shifting operation is needed
for every test pattern. However, the conventional test-per-clock
BIST scheme may have a problem on power consumption. In the
traditional test-per-clock BIST scheme, all scan chains change
their contents every clock cycle no matter whether they are used
for pattern generation or for test response compaction. This can
lead to excessive circuit toggling and thus power dissipation.
Moreover, the traditional test-per-clock scheme has been developed
mainly for BIST. It is desirable to develop a new test-per-clock
scheme that not only is more time-efficient than the test-per-scan
scheme but also addresses the limitations of the existing
test-per-clock scheme. Disclosed below are techniques related to a
new test-per-clock scheme, in particular, test generation
techniques for the new test-per-clock scheme to be applicable to
deterministic testing.
BRIEF SUMMARY OF THE INVENTION
Aspects of the invention relate to test generation techniques for
test-per-clock. Test cubes may be generated by adding constraints
to a conventional automatic test pattern generator. The constraints
may be based on configurations of scan chains. In a configuration
of the scan chains, a first portion of the scan chains is
configured to operate in a shifting-launching mode; a second
portion of the scan chains is configured to operate in a
capturing-compacting-shifting mode; and a third portion of the scan
chains is configured to operate in a mission mode. The
capturing-compacting-shifting mode may be a mode of
capturing-compacting-shifting with blocking or a mode of
capturing-compacting-shifting without blocking. The
shifting-launching mode may be the only mode that allows a scan
chain to have specified bits.
During a test cube merging process, a first test cube is selected
from test cubes generated for a particular scan chain
configuration. The first test cube is then merged with one or more
test cubes in the test cubes that are compatible with the first
test cube to generate a second test cube.
The second test cube is shifted by one bit along a direction of
scan chain shifting to generate a third test cube. The third test
cube is then merged with one or more test cubes in the test cubes
that are compatible with the third test cube to generate a fourth
test cube. The shifting and merging operations may be repeated for
a predetermined number of times.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 illustrates an example of a test architecture for
test-per-clock based on dynamically partitioned and reconfigurable
scan chains that may be employed by various embodiments of the
invention.
FIG. 2 illustrates a flow chart describing methods of
test-per-clock based on dynamically-partitioned configurable scan
chains that may be employed by various embodiments of the
invention.
FIG. 3 illustrates an example of how the scan chains 121-125 in
FIG. 1 interact with each other during testing.
FIG. 4 illustrates a flow chart describing methods of test cube
merging that may be employed by various embodiments of the
invention.
FIG. 5 illustrates an example of a test cube merging process for
one scan chain according to various embodiments of the
invention.
FIG. 6 illustrates a programmable computer system with which
various embodiments of the invention may be employed.
DETAILED DESCRIPTION OF THE INVENTION
Various aspects of the present invention relate to test generation
techniques for test-per-clock. In the following description,
numerous details are set forth for the purpose of explanation.
However, one of ordinary skill in the art will realize that the
invention may be practiced without the use of these specific
details. In other instances, well-known features have not been
described in details to avoid obscuring the present invention.
Some of the techniques described herein can be implemented in
software instructions stored on a computer-readable medium,
software instructions executed on a computer, or some combination
of both. Some of the disclosed techniques, for example, can be
implemented as part of an electronic design automation (EDA) tool.
Such methods can be executed on a single computer or on networked
computers.
The detailed description of a method or a device sometimes uses
terms like "merge" and "shift" to describe the disclosed method or
the device function/structure. Such terms are high-level
abstractions. The actual operations or functions/structures that
correspond to these terms will vary depending on the particular
implementation and are readily discernible by one of ordinary skill
in the art. It should also be appreciated by one of ordinary skill
in the art that the term "coupled" means "connected directly or
indirectly."
Although the operations of the disclosed methods are described in a
particular sequential order for convenient presentation, it should
be understood that this manner of description encompasses
rearrangements, unless a particular ordering is required by
specific language set forth below. For example, operations
described sequentially may in some cases be rearranged or performed
concurrently. Moreover, for the sake of simplicity, the disclosed
flow charts and block diagrams typically do not show the various
ways in which particular methods can be used in conjunction with
other methods.
FIG. 1 illustrates an example of a test architecture for
test-per-clock that may be employed by various embodiments of the
invention. The test architecture 100 comprises a test stimuli
source 110, scan chains 121-125, a test response collector 130, a
configuration register 140 and a configuration source 150. The test
stimuli source 110 may be an ATE (automated test equipment), a test
data decompressor driven by an ATE, a PRPG (pseudorandom pattern
generator), or any device that can supply test patterns in some
form. The ATE is commonly used for deterministic testing. The
deterministic testing usually employs test patterns generated by
ATPG (automatic test pattern generation). To test a large circuit,
compressed test patterns are often used.
Before being shifted into scan chains, the compressed test patterns
are decompressed by the test data decompressor. For
non-deterministic testing such as BIST, the PRPG can serve as the
test stimuli source.
The test response collector 130 in the test architecture 100 may be
the same ATE used as the test stimuli source 110, a test response
compactor, or any device that can collect and perhaps analyze test
responses shifted out of the scan chains. The test response
compactor may compact test responses spatially, temporally, or
both. The spatial compaction may be achieved by using a spatial
compactor constructed with elementary gates such as AND, OR, NAND
and NOR gates. The temporal compaction may be accomplished by
using, for example, a multiple-input signature register (MISR).
The test stimuli source 110 and the test response collector 130
described above are similar to those used in a conventional test
architecture. The scan chains 121-125 in the test architecture 100,
however, are configured differently from conventional scan chains.
Unlike conventional scan chains, scan chains used in various
embodiments of the invention can operate, depending on a control
signal, in one of at least three modes: a shifting-launching mode,
a capturing-compacting-shifting mode and a mission mode. In the
mission mode, scan chains perform regular circuit functions; in the
shifting-launching and capturing-compacting-shifting modes, scan
chains are used for testing the circuit. Specifically, scan chains
in the shifting-launching mode are responsible for controlling the
internal states of the circuit-under-test. They shift test data in
and applying them to the circuit-under-test every clock cycle.
Moreover, they do not capture any test responses. Scan chains in
the capturing-compacting-shifting mode, on the other hand, are
responsible for collecting test response data generated by the
circuit-under-test. They shift out one bit of a previously
compacted test response signal while compacting remaining bits of
the previously compacted test response signal with a
currently-captured test response signal to form a currently
compacted test response signal.
In FIG. 1, the scan chains 121, 123 and 125 are shown to work in
the shifting-launching mode, the capturing-compacting-shifting mode
and the mission mode, respectively. The control signal for mode
switching is generated by the configuration source 150 and applied
to the scan chains 121, 123 and 125 by the configuration register
140. FIG. 1 only illustrates one configuration (partition) of the
scan chains. Different partitions of the scan chains can be
obtained by varying the control signal. The content of the
configuration register 140 can be reloaded during a test session,
depending on various requirements. In particular, the control
signal may be varied with test patterns applied. The configuration
source 150 may be an on-chip device or an external device.
As seen in the figure, a majority of the scan chains operate in the
mission mode. This arrangement can alleviate power issues because
logic states associated with these scan chains closely resemble
those when the circuit works in its designed functional mode. Only
a small portion of the scan chains may cause extrinsic circuit
toggling. In a conventional at-speed scan test, by contrast, a
capture clock burst is applied to all scan chains which can result
in a sudden current change within a few nanoseconds and thereby
circuit failures.
FIG. 2 illustrates a flow chart 200 describing methods of
test-per-clock based on dynamically-partitioned configurable scan
chains that may be employed by various embodiments of the
invention. FIG. 3 illustrates an example of how the scan chains
121-125 in FIG. 1 interact with each other during testing. To
simplify the figure, only one scan chain is used to represent scan
chains in each operation mode. For ease of understanding, methods
of test-per-clock based on dynamically partitioned and
reconfigurable scan chains that may be employed according to
various embodiments of the invention will be described with
reference to the flow chart 200 in FIG. 2 and the test architecture
100 illustrated in FIG. 3. It should be appreciated, however, that
alternate implementations of a test architecture may be used to
perform the methods of test-per-clock based on
dynamically-partitioned configurable scan chains illustrated by the
flow chart 200 according to various embodiments of the invention.
Likewise, the test architecture 100 may be employed to perform
other methods of test-per-clock based dynamically-partitioned
configurable scan chains according to various embodiments of the
invention.
In operation 210, test stimuli are shifted from a stimuli source
(test stimuli source 110) into a first portion of a plurality of
scan chains in a circuit (scan chains 121) one bit per scan chain
to form a new test pattern as illustrated by an arrow 350. The
connections between the test stimuli source 110 and the scan chains
123 and 125 are blocked as illustrated by arrows 370 with broken
lines.
Immediately after being formed, in operation 220, the new test
pattern is applied to the circuit. The new test pattern propagates
through the combinational part of the circuit until a test response
reaches a second portion of the plurality of scan chains (scan
chains 123) as illustrated by an arrow 310. A circuit response
caused by the new test pattern also reaches a third portion of the
plurality of scan chains (scan chains 125) as illustrated by an
arrow 320. This circuit response will circulate within the circuit
and eventually reach the scan chains 123 as illustrated by arrows
330.
In operation 230, the scan chains 123 shift out previously
compacted test response data one bit per scan chain to the test
response collector 130 as illustrated by an arrow 360. The
connections between the test response collector 130 and the scan
chains 121 and 125 are blocked as illustrated by arrows 380 with
broken lines.
At about the same time as the operation 230, in operation 240, the
test response corresponding to the new test pattern is compacted
with the previously compacted test response data to generate newly
compacted test response data in the scan chains 123. As shown in
FIG. 3, the scan chains 123 are also employed to drive the circuit
as illustrated by arrows 340, which is referred to as a mode of
capturing-compacting-shifting without blocking. This functionality
can be disabled if needed and the scan chains operate in a mode
referred to as a mode of capturing-compacting-shifting with
blocking.
As noted previously, the scan chains 121, 123 and 125 are
configured to operate in the shifting-launching mode, the
capturing-compacting-shifting mode and the mission mode,
respectively, based on the control signal stored in the
configuration register 140. The above four operations may be
performed once for every clock cycle for a predetermined number of
times. At the end, a different control signal may be loaded into
the configuration register 140 to reconfigure the scan chains. The
reconfigured scan chains are then employed for the next test
pattern(s). This dynamic partitioning and reconfiguring approach
contrasts not only the conventional scan method but also the BILBO
approach discussed in the background section.
Another difference between various embodiments of the present
invention and the BILBO-based techniques may lie in the operation
of test response compaction. As previously noted, a BILBO scan
chain in the feedback mode works as a multiple-input signature
generator for compacting test responses: Test responses are
captured and compacted for a number of clock cycles (corresponding
to the same number of test patterns) to generate a signature. No
bit of the compacted test response signal is shifted out during
that time period. Instead, the signature is shifted out after a
number of test patterns are applied. By contrast, a scan chain in
the capturing-compacting-shifting mode according to various
embodiments of the invention does not have a feedback loop.
Moreover, one bit of previously compacted test response data is
shifted out every clock cycle.
By adopting the test-per-clock scheme, various embodiments of the
invention remove the lengthy scan shift-in phase used in the
test-per-scan scheme and perform launch-capture testing every clock
cycle. This allows more test patterns to be applied within a
certain period of time and may improve the fault coverage.
Alternatively, one can choose to apply the same number of test
patterns as that of a conventional scan test, yet in a much shorter
period of time, thereby reducing the test cost.
By dynamically partitioning and reconfiguring the scan chains, the
disclosed test-per-clock scheme can allow the majority of scan
chains to operate in the mission mode to alleviate power issues
without significant impact on test generation and fault coverage.
The control signal remains static after a given configuration is
established. It can, therefore, be placed and routed with no rigid
timing constrains similar to those of scan enable signals whose
distribution and delivery, especially for the at-speed test
purpose, must meet non-flexible timing closure conditions. The
low-power capabilities may enable applying test patterns at higher,
close to the functional, frequency, which can further increase
fault coverage metrics.
Conventional automatic test pattern generation and test cube
merging techniques are designed for test-per-scan. To apply the
disclosed test-per-clock scheme to deterministic testing, new
automatic test pattern generation and test cube merging techniques
need to be developed. FIG. 4 illustrates a flow chart 400
describing methods of test cube merging that may be employed by
various embodiments of the invention.
Initially, in operation 410, a test cube (referred to as the first
test cube) is selected from a plurality of test cubes. The
plurality of test cubes may be generated by adding various
constrains to a conventional automatic test pattern generator. One
such constraint that may be employed by various embodiments of the
invention is force scan cells in the mission mode to operate as
non-scan memory elements. The automatic test pattern generator is
only allowed to specify stimuli and justification data in scan
cells in the shifting-launching mode. The observation values of
these scan cells in the shifting-launching mode are set to unknown
value (X) as they do not observe data arriving from the
circuit-under-test. Meanwhile, scan cells in the
capturing-compacting-shifting mode are not allowed to specify
stimuli but are allowed to capture test responses. Whenever a fault
propagates to a scan chain in the capturing-compacting-shifting
mode, it is temporarily marked as detected. This conjecture may be
invalidated after additional analysis of fault aliasing. The
control signals used to configure scan cells are constrained to
appropriate values. It prevents data produced by the circuit from
being captured during subsequent cycles of sequential fault
simulation.
Next, in operation 420, the first test cube is merged with one or
more test cubes in the plurality of test cubes that are compatible
with the first test cube to generate a second test cube. Two test
cubes are compatible if they do not have conflicting specified
bits. This merging operation can be performed following how a
conventional merging operation performs. The merged test cube
usually has more specified bits than the original test cubes.
Next, in operation 430, the second test cube is shifted by one bit
along a direction of scan chain shifting to generate a third test
cube. Suppose bits 0 and N are the last and first bits of a test
cube to be shifted into scan chains, respectively. The operation
430 shifts the second test cube to form the third test cube such
that for each scan chain, bit 0 of the second test cube becomes bit
1 of the third test cube and bit N-1 of the second test cube
becomes bit N of the third test cube. Bit 0 of the third test cube
has an unspecified value.
Next, in operation 440, the third test cube is merged with one or
more test cubes in the plurality of test cubes that are compatible
with the third test cube to generate a fourth test cube. Due to the
shifting operation 430, some test cubes, incompatible with the
second test cube, become compatible with and thus can be merged
with the third test cube.
Similar to operation 430, the fourth test cube may be shifted by
one bit along the direction of scan chain shifting to generate a
fifth test cube. Also similar to operation 440, the fifth test cube
may be merged with one or more test cubes in the test cubes that
are compatible with the fifth test cube to generate a sixth test
cube. Such shifting and merging operations may be repeated for a
predetermined number of times.
FIG. 5 illustrates an example of the above process for one scan
chain. In clock cycle 1, two test cubes, 530 and 540, are merged
for loading scan chain 500. In clock cycle 2, the content of the
scan chain 500, the merging result of test cubes 510 and 520, is
shifted right (direction of scan chain shifting) by one bit. As a
result, test cube 520 becomes compatible with and thus merged with
the current content of the scan chain 500. Next, in clock cycle 3,
the content of the scan chain 500 is shifted again by one bit along
the direction of scan chain shifting. The shifted content of the
scan chain 500 is then merged with the test cube 510 to form new
content of the scan chain 500. Under this scheme, many originally
incompatible test cubes may be merged and the filling rate can be
significantly increased.
Various embodiments of the invention may be implemented through the
execution of software instructions by a computing device, such as a
programmable computer. FIG. 6 shows an illustrative example of such
a programmable computer (a computing device 601). As seen in this
figure, the computing device 601 includes a computing unit 603 with
a processing unit 605 and a system memory 607. The processing unit
605 may be any type of programmable electronic device for executing
software instructions, but will conventionally be a microprocessor.
The system memory 607 may include both a read-only memory (ROM) 609
and a random access memory (RAM) 611. As will be appreciated by
those of ordinary skill in the art, both the read-only memory (ROM)
609 and the random access memory (RAM) 611 may store software
instructions for execution by the processing unit 605.
The processing unit 605 and the system memory 607 are connected,
either directly or indirectly, through a bus 613 or alternate
communication structure, to one or more peripheral devices. For
example, the processing unit 605 or the system memory 607 may be
directly or indirectly connected to one or more additional memory
storage devices, such as a "hard" magnetic disk drive 615, a
removable magnetic disk drive 617, an optical disk drive 619, or a
flash memory card 621. The processing unit 605 and the system
memory 607 also may be directly or indirectly connected to one or
more input devices 623 and one or more output devices 625. The
input devices 623 may include, for example, a keyboard, a pointing
device (such as a mouse, touchpad, stylus, trackball, or joystick),
a scanner, a camera, and a microphone. The output devices 625 may
include, for example, a monitor display, a printer and speakers.
With various examples of the computer 601, one or more of the
peripheral devices 615-625 may be internally housed with the
computing unit 603. Alternately, one or more of the peripheral
devices 615-625 may be external to the housing for the computing
unit 603 and connected to the bus 613 through, for example, a
Universal Serial Bus (USB) connection.
With some implementations, the computing unit 603 may be directly
or indirectly connected to one or more network interfaces 627 for
communicating with other devices making up a network. The network
interface 627 translates data and control signals from the
computing unit 603 into network messages according to one or more
communication protocols, such as the transmission control protocol
(TCP) and the Internet protocol (IP). Also, the interface 627 may
employ any suitable connection agent (or combination of agents) for
connecting to a network, including, for example, a wireless
transceiver, a modem, or an Ethernet connection. Such network
interfaces and protocols are well known in the art, and thus will
not be discussed here in more detail.
It should be appreciated that the computer 601 is illustrated as an
example only, and it not intended to be limiting. Various
embodiments of the invention may be implemented using one or more
computing devices that include the components of the computer 601
illustrated in FIG. 6, which include only a subset of the
components illustrated in FIG. 6, or which include an alternate
combination of components, including components that are not shown
in FIG. 6. For example, various embodiments of the invention may be
implemented using a multi-processor computer, a plurality of single
and/or multiprocessor computers arranged into a network, or some
combination of both.
Some other embodiments of the invention may be implemented by
software instructions, stored on a non-transitory computer-readable
medium, for instructing one or more programmable computers/computer
systems to perform operations such as those shown in the flow chart
400 in FIG. 4. As used herein, the term "non-transitory
computer-readable medium" refers to computer-readable medium that
are capable of storing data for future retrieval, and not
propagating electro-magnetic waves. The non-transitory
computer-readable medium may be, for example, a magnetic storage
device, an optical storage device, a "punched" surface type device,
or a solid state storage device.
CONCLUSION
While the invention has been described with respect to specific
examples including presently preferred modes of carrying out the
invention, those skilled in the art will appreciate that there are
numerous variations and permutations of the above described systems
and techniques that fall within the spirit and scope of the
invention as set forth in the appended claims. For example, while
specific terminology has been employed above to refer to electronic
design automation processes, it should be appreciated that various
examples of the invention may be implemented using any desired
combination of electronic design automation processes.
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