U.S. patent number 8,423,814 [Application Number 12/728,101] was granted by the patent office on 2013-04-16 for programmable drive strength in memory signaling.
This patent grant is currently assigned to NetLogic Microsystems, Inc.. The grantee listed for this patent is Marc Loinaz. Invention is credited to Marc Loinaz.
United States Patent |
8,423,814 |
Loinaz |
April 16, 2013 |
**Please see images for:
( Certificate of Correction ) ** |
Programmable drive strength in memory signaling
Abstract
Embodiments of the invention relate to programmable data
register circuits and programmable clock generation circuits For
example, some embodiments include a buffer circuit for receiving
input data and sending output data signals along a series of signal
lines with a signal strength, and a signal modulator configured to
determine the signal strength based on a control input. Some
embodiments include a clock generation circuit for receiving clock
reference and sending output clock signals along a series of signal
lines with a signal character, and a signal modulator configured to
determine the signal character based on a control input.
Inventors: |
Loinaz; Marc (Palo Alto,
CA) |
Applicant: |
Name |
City |
State |
Country |
Type |
Loinaz; Marc |
Palo Alto |
CA |
US |
|
|
Assignee: |
NetLogic Microsystems, Inc.
(Irvine, CA)
|
Family
ID: |
44648167 |
Appl.
No.: |
12/728,101 |
Filed: |
March 19, 2010 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20110231692 A1 |
Sep 22, 2011 |
|
Current U.S.
Class: |
713/500; 713/600;
711/154 |
Current CPC
Class: |
G06F
12/0246 (20130101); G06F 1/08 (20130101) |
Current International
Class: |
G06F
1/00 (20060101); G06F 13/00 (20060101); G06F
5/06 (20060101) |
Field of
Search: |
;713/500,600 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
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Action dated Oct. 14, 2011. cited by applicant .
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applicant .
U.S. Appl. No. 12/185,750, filed Aug. 4, 2008, Stefanos
Sidiropoulos. cited by applicant .
U.S. Appl. No. 12/828,125, filed Jun. 30, 2010, Cirit, Halil. cited
by applicant .
U.S. Appl. No. 12/828,153, filed Jun. 30, 2010, Cirit, Halil. cited
by applicant .
Sidiropoulos et al., Adaptive Bandwidth DLLs and PLLs using
Regulated Supply CMOS Buffers, 2000 Symposium on VLSI Circuits
Digest of Technical Papers. cited by applicant .
Mansuri et al., A Low-Power Low-Jitter Adaptive-Bandwidth PLL and
Clock Buffer, ISSCC 2003/Session 24/Clock Generation/Paper 24.5,
ISSCC 2003/Feb. 12, 2003/Salon 8/3:45PM, 2003 IEEE International
Solid-State Circuits Conference. cited by applicant .
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Design Parameters, IEEE Journal of Solid-State Circuits, vol. 37,
No. 11, Nov. 2002. cited by applicant .
Maxim et al., A Low-Jitter 125-1250-MHz Process-Independent and
Ripple-Poleless 0.18-.mu.m CMOS PLL Based on a Sample-Reset Loop
Filter, IEEE Journal of Solid-State Circuits, vol. 36, No. 11, Nov.
2001. cited by applicant .
Maneatis, Self-Biased High-Bandwidth Low-Jitter 1-to-4096
Multiplier Clock Generator PLL, IEEE Journal of Solid-State
Circuits, vol. 38, No. 11, Nov. 2003. cited by applicant .
Sidiropoulos, A Semidigital Dual Delay-Locked Loop, IEEE Journal of
Solid-State Circuits, vol. 32, No. 11, Nov. 1997. cited by
applicant .
U.S. Appl. No. 10/167,495, Jun. 21, 2002, Sidiropoulos et al.,
Office Action dated Mar. 30, 2011. cited by applicant .
U.S. Appl. No. 11/930,978, Oct. 31, 2007, Sidiropoulos et al.,
Office Action dated Mar. 18, 2011. cited by applicant .
U.S. Appl. No. 11/781,172, Sidiropoulos et al., filed Jul. 23, 2010
cited by applicant .
U.S. Appl. No. 12/728,113, Loinaz, et al., filed Mar. 19, 2010.
cited by applicant.
|
Primary Examiner: Suryawanshi; Suresh
Attorney, Agent or Firm: Sterne, Kessler, Goldstein &
Fox P.L.L.C.
Claims
What is claimed is:
1. A circuit comprising: a storage configured to store a signal
control; a plurality of memory integrated circuits; an intermediate
circuit configured to receive memory signaling input and to send
output signals along signal lines to the plurality of memory
integrated circuits with a predetermined drive strength based on
the signal control; and a plurality of signal modulators, coupled
to the signal lines, configured to condition the signal lines based
on the signal control.
2. The circuit of claim 1, wherein the storage comprises:
non-volatile memory.
3. The circuit of claim 2, wherein a controller circuit comprises
the non-volatile memory and is coupled to the circuit to provide
the signal control.
4. The circuit of claim 1, wherein each of the plurality of signal
modulators comprises: a current modulation block configured to
adjust an output signal current level of its corresponding output
signal based on the signal control.
5. The circuit of claim wherein the signal modulator comprises: an
impedance matching block configured to substantially match an
impedance of the intermediate circuit to an impedance of its
corresponding memory integrated circuit from among the plurality of
memory integrated circuits.
6. The circuit of claim 1, wherein one of the memory integrated
circuits is configured as a dual inline memory module.
7. The circuit of claim 6, wherein the one of the memory integrated
circuit is a dynamic random access memory IC.
8. The circuit of claim 6, wherein the signal control is configured
to optimize signal strengths for the plurality of memory integrated
circuits.
9. The circuit of claim 1, wherein the intermediate circuit
comprises a data buffer circuit and the memory signaling input
comprises data.
10. The circuit of claim 1, wherein the intermediate circuit
comprises a clock generator circuit and the memory signaling input
comprises a clock.
11. The circuit of claim 1, wherein the intermediate circuit
comprises a fully buffered integrated circuit.
12. A programmable data register circuit, comprising: a buffer
circuit configured to receive input data and to send output data
along a series of signal lines; a memory configured to store a
control value; and a plurality of signal modulators, wherein each
signal modulator is coupled to a signal line in the series of
signal lines and configured to adjust a signal strength of the
output data within the signal line based on a corresponding signal
control input from among a plurality of signal control inputs,
wherein the corresponding signal control input is generated based
on the stored control value.
13. The programmable data register circuit of claim 12, further
comprising: a controller block configured to provide the signal
control input to each signal modulator.
14. The programmable data register circuit of claim 13, further
comprising: a plurality of input pins, coupled to the controller
block, configured to receive external input to control generation
of the plurality of signal control inputs in the controller
block.
15. The programmable data register circuit of claim 13, wherein the
memory comprises a non-volatile memory module coupled to the
controller block.
16. The programmable data register circuit of claim 15, wherein the
controller block uses the control value in generating the plurality
of signal control inputs.
17. The programmable data register circuit of claim 16, wherein the
control value is stored in said non-volatile memory module during a
calibration cycle.
18. The programmable data register circuit of claim 16, wherein the
controller block is configured to determine values of the plurality
of signal control inputs during operation.
19. The programmable data register circuit of claim 16, wherein the
control value is determined and programmed into the non-volatile
memory module during manufacturing and testing of the circuit.
20. The programmable data register circuit of claim 13, wherein the
signal control input for each of the plurality of signal modulators
are not all the same.
21. The programmable data register circuit of claim 13, further
comprising: at least one memory integrated circuit, coupled to said
programmable data register circuit, configured to receive the
output data.
22. The programmable data register circuit of claim 21, wherein
said at least one memory integrated circuit is a dynamic random
access memory IC.
23. The programmable data register circuit of claim 21, further
comprising: a plurality of memory integrated circuits and wherein
the plurality of signal control inputs optimize signal strengths of
the plurality of memory integrated circuits.
24. A method of optimizing signaling between a memory signaling
circuit and a plurality of memory integrated circuits in a memory
module, comprising: determining a preferable output control signal
character given the number of memory integrated circuits within the
module; setting a memory signaling control value representing the
preferable output control signal character; receiving signaling
input; and sending memory control signals with a character based on
the memory signaling control value.
25. The method of claim 24, wherein the preferable output control
signal character includes an output impedance with which the memory
control signals are sent.
26. The method of claim 24, wherein the preferable output control
signal character includes a current with which the memory controls
signals are sent.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention is directed toward the field of memory
signaling circuits, and more particularly to a programmable data
buffer circuit and a programmable clock generator circuit.
2. Art Background
Many memory signal distribution methods rely on clock generation
and data buffering integrated circuits (IC). A typical application
for such ICs is a registered dual inline memory module (DIMM) 100,
as shown in FIG. 1. The memory module input clock is fed to a
phase-locked loop (PLL) based IC. The PLL-based IC 110 receives the
input clock on a clock input 111. The PLL-based IC 110 outputs a
plurality of clocks to the DRAM ICs 130-1 to 130-N, and to the
register IC 120. Both the DRAM and register ICs are mounted on the
memory module. The register receives data input 121 and outputs a
plurality of data signals to the DRAM ICs 130-1 to 130-N.
A given IC design, for either register or clock, is often sold for
use in a variety of memory module configurations. This requires
that the IC be able to drive signals to a variable number of memory
ICs, depending on the implementation. Current designs must
sacrifice precision for this versatility, driving a set of memory
ICs at a signal strength that fails to optimize for either quality
or speed.
What is needed is a method and/or device that permits tuning of
signaling strength to implementation details in an economical
fashion.
Further, what is needed is a method and/or device that, even when
designed on a per-system or per-system basis, permits tuning at the
per-lot level.
SUMMARY OF THE DISCLOSURE
Embodiments of the present invention preserve certain advantages of
the prior art while introducing additional flexibility to permit a
single design or class of designs to accommodate a wider range of
applications. These embodiments not only perform feedback-based
adjustment of the distributed data, but also permit individual
tuning of data drive strength or current drive for each
distribution line. Thus, data drive strength or current drive can
be tuned to the skews present in the actual components being used
for a given manufactured lot. The actual tuning can take place at
manufacturing time, at each boot-up, or continuously during
operation.
In one aspect, embodiments of the invention relate to programmable
memory signaling circuits. For example, a programmable memory
signaling circuit may comprise an intermediate circuit and a signal
modulator. The intermediate circuit is configured for receiving
memory signaling input and sending output memory signals along a
series of signal lines with a signal character. The signal
modulator is configured to determine the signal character based on
a signal control input.
In another aspect, embodiments of the invention relate to
programmable data register circuits. For example, some embodiments
relate to a programmable data register circuit comprising a buffer
circuit for receiving input data and sending output data along a
series of signal lines, and a plurality of signal modulators,
wherein each signal modulator is coupled to a signal line in the
series and each signal modulator is configured to adjust a signal
strength within the signal line.
In a further aspect, some embodiments relate to dual inline memory
modules (DIMM). For example, a DIMM comprising a programmable
memory signaling circuit (or programmable memory register circuit)
as set forth above, and further comprising at least one memory
integrated circuit. Preferably the memory IC is coupled to the
programmable memory signaling circuit or register circuit for
receiving one of the output memory signals (or output data
signals).
In still another aspect, some embodiments relate to methods of
optimizing signaling. For example, a method of optimizing signaling
between a memory signaling circuit and a plurality of memory
integrated circuits in a memory module. One such method comprises
these steps: determining a preferable output signal character given
the number of memory integrated circuits within the module, setting
a memory signaling control value representing the preferable output
control signal character, receiving signaling input, and sending
memory control signals with a character based on the signaling
control value.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a block diagram of a prior art implementation of a data
buffer and clock buffer in a dual inline memory module.
FIG. 2a is a block diagram of a dual inline memory module
incorporating programmable data buffer and clock generator signal
strengths consistent with some embodiments of the present
invention.
FIG. 2b is a block diagram of a dual inline memory module
incorporating a programmable clock generator and data buffer
consistent with some embodiments of the present invention.
FIG. 2c is a block diagram of a dual inline memory module
incorporating a programmable clock generator and data buffer
consistent with some embodiments of the present invention.
FIG. 3a is a block diagram of a memory register IC incorporating
programmable signal strength consistent with some embodiments of
the present invention.
FIG. 3b is a block diagram of a clock generator IC incorporating
programmable signal strength consistent with some embodiments of
the present invention.
FIG. 4 is a block diagram of a programmable data buffer and clock
generator IC implemented in a dual inline memory module consistent
with some embodiments of the present invention.
FIG. 5 is a circuit diagram of a memory signaling modulator
consistent with some embodiments of the present invention.
DETAILED DESCRIPTION
This disclosure sets forth an architecture for a memory signaling
IC which overcomes limitations of conventional memory signaling ICs
by employing on-chip programmable drive generator(s) to
appropriately adjust data signal drive to the implementation.
Structure
FIGS. 2a-2c illustrate functional/block diagrams of programmable
memory signaling systems consistent with embodiments of the present
invention.
FIG. 2a illustrates an implementation 200a including programmable
clock signaling and programmable data signaling consistent with
some embodiments of the present invention. The system 200a
comprises a clock generator 210, a register module 220, a
controller module 240, and a plurality of memory modules 230-1 to
230-N.
The clock generator 210 is coupled to the memory modules 230-1 to
230-N through a clock signaling assembly 213 and to the register
module 220 through the output line 215. The clock generator 210 is
supplied with a reference signal through the input 211 and
generates a clock output. The clock output is provided to the
memory modules 230-1 to 230-N and to the register module 220.
The register module 220 is coupled to the memory modules 230-1 to
230-N through a data signaling assembly 223 and to the clock
generator 210 through the clock output line 215. The register
module 220 is supplied through the data input 221 and generates
data output, which it provides to memory modules 230-1 to
230-N.
The controller module 240 is coupled to the clock signaling
assembly 213 and the data signaling assembly 223. As illustrated,
the clock signaling assembly 213 comprises an array of N signaling
lines coupled to N signal modulators 216 to 218. Similarly, the
data signaling assembly 223 comprises an array of N signaling lines
coupled to N signal modulators 226 to 228. The clock signal control
lines 245 couple the controller module 240 to each of the signal
modulators within the clock signaling assembly 213. The data signal
control lines 243 couple the controller module 240 to each of the
signal modulators within the data signaling assembly 223. The
controller module 240 receives control input from control pin
241.
The clock output of clock generator 210 is supplied to each of a
plurality of signal modulators 216 to 218 in the clock signaling
assembly 213. Each signal modulator 216 to 218 modulates the clock
output signal based on a control input from the controller module
240. Similarly, the data output of register module 220 is supplied
to each of a plurality of signal modulators 226 to 228 in the data
signaling assembly 223. Each signal modulator 226 to 228 modulates
the clock output signal based on a control input from the
controller module 240. Preferably the signal modulators modulate
the signals by adjusting the strength or current of the
signals.
Preferably the clock generator 210, the register module 220, the
controller module 240, the signal modulators 226 to 228, and the
signal modulators 216 to 218 are all mounted on-chip relative to
one another. However, in some embodiments these components are
spread among multiple chips. Further, in some embodiments, a system
includes programmable register elements but not programmable clock
elements.
Some embodiments of the invention include a dual inline memory
module comprising the elements of implementation 200a.
FIG. 2b illustrates an implementation 200b including programmable
clock signaling and programmable data signaling consistent with
some embodiments of the present invention. The system 200b
comprises a clock generator 250, a register module 260, a
controller module 270, and a plurality of memory modules 230-1 to
230-N.
The clock generator 250 is coupled to the memory modules 230-1 to
230-N through a clock signaling assembly 255 and to the register
module 260 through the output line 253. The clock generator 250 is
supplied with a reference signal through the input 251 and
generates a clock. The clock is provided to the register module 260
through the output line 253. The clock is also used to generate a
clock signal provided to the memory modules 230-1 to 230-N through
the clock signaling assembly 255. As illustrated, the clock
signaling assembly 255 comprises an array of N signaling lines. The
clock of clock generator 250 is modulated and provided through the
clock signaling assembly 255 to the memory modules. Preferably, the
signal is modulated based on a control input from the controller
module 270. Preferably modulation of the clock includes adjustment
of the clock signal strength, and, in some embodiments, the clock
phase.
The register module 260 is coupled to the memory modules 230-1 to
230-N through a data signaling assembly 263. The register module
260 is supplied with data through the input 261 and generates a
data signal based on that data. The data signal is provided to the
memory modules 230-1 to 230-N through the data signaling assembly
263. As illustrated, the clock signaling assembly 263 comprises an
array of N signaling lines. The data signal modulated and provided
through the data signaling assembly 263 to the memory modules.
Preferably the signal is modulated based on a control input from
the controller module 270. Preferably modulation of the data signal
includes adjustment of the data signal strength.
The controller module 270 is coupled to the clock generator 250 and
the register module 260. The clock control line 275 couples the
controller module 270 to the clock generator 250. The data control
line 273 couples the controller module 270 to the register module
260. The controller module 270 receives control input from control
pin 271. Further, the controller module 270 includes the
non-volatile memory 272 configured to store control values.
Preferably the clock generator 250, the register module 260, and
the controller module 270 are all mounted on-chip relative to one
another. However, in some embodiments these components are spread
among multiple chips. Further, in some embodiments, a system
includes programmable register elements but not programmable clock
elements.
Some embodiments of the invention include a dual inline memory
module comprising the elements of implementation 200b.
FIG. 2c illustrates an implementation 200c including programmable
clock signaling and programmable data signaling consistent with
some embodiments of the present invention. The system 200c
comprises a clock generator 280, a register module 290, and a
plurality of memory modules 230-1 to 230-N.
The clock generator 280 comprises a non-volatile memory 282 and is
coupled to the memory modules 230-1 to 230-N through a clock
signaling assembly 285 and to the register module 290 through the
output line 283. The clock generator 280 is supplied with a
reference signal through the input 281 and generates a clock. The
clock is provided to the register module 290 through the output
line 283. The clock is also used to generate a clock signal
provided to the memory modules 230-1 to 230-N through the clock
signaling assembly 285. As illustrated, the clock signaling
assembly 285 comprises an array of N signaling lines. The clock of
clock generator 280 is modulated and provided through the clock
signaling assembly 285 to the memory modules. Preferably the signal
is modulated based on control values stored in the NVM 282. Most
preferably these values are set through a control input 287.
Preferably modulation of the clock includes adjustment of the clock
signal strength, and in some embodiments, the phase of the
clock.
The register module 290 comprises a non-volatile memory 292 is
coupled to the memory modules 230-1 to 230-N through a clock
signaling assembly 293. The register module 290 is supplied with
data through the input 291 and generates a data signal based on
that data. The data signal is provided to the memory modules 230-1
to 230-N through the data signaling assembly 293. As illustrated,
the clock signaling assembly 293 comprises an array of N signaling
lines. The data signal modulated and provided through the data
signaling assembly 293 to the memory modules. Preferably the signal
is modulated based on control values stored in the NVM 292. Most
preferably these values are set through a control input 295.
Preferably modulation of the clock includes adjustment of the clock
signal strength.
Preferably the clock generator 280 and the register module 290 are
mounted on-chip relative to one another. However, in some
embodiments these components are spread among multiple chips.
Further, in some embodiments, a system includes programmable
register elements but not programmable clock elements.
Some embodiments of the invention include a dual inline memory
module comprising the elements of implementation 200c.
FIG. 3a illustrates a functional/block diagram of a programmable
data buffer 300a consistent with some embodiments of the present
invention. The programmable data buffer 300a is preferably
implemented in a single IC and comprises a non-volatile memory 301,
a current modulation module 302, an impedance matching module 303,
and a processing module 304. In some embodiments the circuit is
implemented in more than one IC.
The processing module 304 receives data through the "Data In"
input, processes the data, and outputs a signal. The current
modulation 302 and impedance matching 303 modules receive High and
Low Reference inputs, and generate a Drive signal based on values
stored in the NVM 301. The buffer 300a outputs a data signal based
on the output of the processing module 304 and the Drive
signal.
FIG. 3b illustrates a functional/block diagram of a programmable
clock generator 300a consistent with some embodiments of the
present invention. The programmable clock generator 300a is
preferably implemented in a single IC and comprises a non-volatile
memory 311, a current modulation module 312, an impedance matching
module 313, and a processing module 314. In some embodiments the
circuit is implemented in more than one IC.
The processing module 314 receives a reference clock through the
Clock In input, processes the data, and outputs a clock signal. The
current modulation 312 and impedance matching 313 modules generate
a Drive signal based on values stored in the NVM 311. The clock
generator 300b outputs a clock signal based on the output of the
processing module 314 and the Drive signal.
FIGS. 3a and 3b both include signal modulators. In both FIGS. 3a
and 3b. the signal modulators comprise current modulators and
impedance matchers. In some embodiments of the present invention
signal modulators include only current modulators, while some
embodiments include only impedance matchers. FIG. 5 illustrates a
circuit 500 implementing both current modulation 510 and impedance
matching 520 consistent with some embodiments of the present
invention.
In the circuit 500, logic 535 provides data input signals in a
complementary configuration into the current modulator 510 (i.e., a
first data signal is input to p-type transistor 511 and a second
data signal, the complement of the first data signal, is input to
n-type transistor 516). Within the current modulator 510, the
transistors 511 and 516 provide high/low signaling capability while
the variable resistors 512 and 517 provide signal current
modulation. An output signal is passed from the current modulator
510 to the impedance matcher 520.
Within the impedance matcher 520, the first switch 521 and first
capacitor 522 provide impedance matching within a first range,
while the second switch 526 and second capacitor 527 provide
impedance matching within a second range.
Both the current modulator and the impedance matcher are controlled
by controller 530. In some embodiments controller 530 is off-chip.
Preferably, however, the controller 530 is on-chip. Also controller
530 preferably comprises a non-volatile memory. Though the
switching within the current modulator 510 are depicted as CMOS,
other switching technologies are possible. Preferably, the variable
resistors within the current modulator 510 provide resistance in
the range of 10 to 60 Ohms. Preferably, the capacitors within the
impedance matcher provide capacitance in the range of 100
femto-Farads to 2 pico-Farads.
FIG. 4 illustrates a clock generator and data buffer with
programmable signal strength implemented on a single IC 480 and
incorporated in a dual-in-line-memory module ("DIMM") 400
consistent with some embodiments of the present invention. The IC
480 comprises a clock generator 450, a register module 420, and a
controller module 440. The IC 480 is coupled to a plurality of
memory modules 430-1 to 430-N.
The clock generator 450 is coupled to the memory modules 430-1 to
430-N through a clock signaling assembly 453 and to the register
module 420 through the output line 414. The clock generator 450 is
supplied with a reference signal through the input 411 and
generates a clock output. The clock output is provided to the
memory modules 430-1 to 430-N and to the register module 420.
The register module 420 is coupled to the memory modules 430-1 to
430-N through a data signaling assembly 423 and to the clock
generator 450 through the clock output line 414. The register
module 420 is supplied through the data input 421 and generates
data output, which it provides to memory modules 430-1 to
430-N.
The controller module 440 is coupled to the clock signaling
assembly 453 and the data signaling assembly 423. As illustrated,
the clock signaling assembly 453 comprises an array of N signaling
lines coupled to N signal modulators 456 to 458. Similarly, the
data signaling assembly 423 comprises an array of N signaling lines
coupled to N signal modulators 426 to 428. The clock signal control
lines 445 couple the controller module 440 to each of the signal
modulators within the clock signaling assembly 453. The data signal
control lines 443 couple the controller module 440 to each of the
signal modulators within the data signaling assembly 423. The
controller module 440 receives control input from control pin
441.
The clock output of clock generator 450 is supplied to each of a
plurality of signal modulators 456 to 458 in the clock signaling
assembly 453. Each signal modulator 456 to 458 modulates the clock
output signal based on a control input from the controller module
440. Similarly, the data output of register module 420 is supplied
to each of a plurality of signal modulators 426 to 428 in the data
signaling assembly 423. Each signal modulator 426 to 428 modulates
the clock output signal based on a control input from the
controller module 440. Preferably the signal modulators modulate
the signals by adjusting the strength of the signals, and in some
embodiments, adjusting the phase of the clock signals.
In some embodiments, a system such as in FIG. 4 includes
programmable register elements but not programmable clock
elements.
Programming
Consistent with the present invention, the specific signal
strengths in programmable modes of an IC can be fixed during
manufacturing, determined at each system boot-up, or re-set on a
relatively continuous basis.
In applications, such as registered DIMMs, that do not provide for
a calibration cycle on boot-up, the extended skew calibration mode
is preferably entered only during testing and manufacturing.
Preferably appropriate control values are stored in a non-volatile
memory (NVM). Exemplary NVMs include EEPROM or FLASH memory; the
NVM can be located either on-chip or off-chip.
In applications that provide for boot-up calibration cycles, an
appropriate delay is preferably set on each boot-up via logic
programmed into the controller block. For example, such logic can
be programmed into a controller block via firmware.
Advantages
Embodiments of the present invention preserve certain advantages of
the prior art while introducing additional flexibility to permit a
single design or class of designs to accommodate a wider range of
applications. These embodiments not only perform adjustment of the
distributed signals, but also permit individual tuning of signal
strength within each distribution line. Thus, signal strength can
be tuned to the skews present in the actual components being used
for a given manufactured lot. The actual tuning can take place at
manufacturing time, at each boot-up, or continuously during
operation.
Though the preferred application envisioned for embodiments of the
present invention is in registered memory modules, the invention
applies to other applications that require variable drive
strength.
Although the present invention has been described in terms of
specific exemplary embodiments, it will be appreciated that various
modifications and alterations might be made by those skilled in the
art without departing from the spirit and scope of the invention.
The scope of the invention is not limited to the exemplary
embodiments described and should be ascertained by inspecting the
appended claims.
* * * * *