U.S. patent application number 10/328119 was filed with the patent office on 2003-05-15 for system and method for adjusting phase offsets.
Invention is credited to Cao, Jun.
Application Number | 20030091139 10/328119 |
Document ID | / |
Family ID | 25497215 |
Filed Date | 2003-05-15 |
United States Patent
Application |
20030091139 |
Kind Code |
A1 |
Cao, Jun |
May 15, 2003 |
System and method for adjusting phase offsets
Abstract
Systems and methods that adjust phase offsets are provided. In
one embodiment, a phase detector may include, for example, a delay
block coupled to a first exclusive OR (XOR) gate via a first delay
element; a first sequential device coupled the first XOR gate via a
second delay element; a second sequential device coupled to the
first sequential device and coupled to a second XOR gate via a
third delay element; and a third sequential device coupled to the
second sequential device and coupled to the second XOR gate via a
fourth delay element.
Inventors: |
Cao, Jun; (Irvine,
CA) |
Correspondence
Address: |
MCANDREWS HELD & MALLOY, LTD
500 WEST MADISON STREET
SUITE 3400
CHICAGO
IL
60661
|
Family ID: |
25497215 |
Appl. No.: |
10/328119 |
Filed: |
December 23, 2002 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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10328119 |
Dec 23, 2002 |
|
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09955693 |
Sep 18, 2001 |
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Current U.S.
Class: |
375/376 |
Current CPC
Class: |
H03L 7/087 20130101;
H03L 7/091 20130101; H04L 7/033 20130101; H03K 3/356043 20130101;
H03K 5/133 20130101; H03K 2005/00208 20130101; H03L 7/14 20130101;
H03L 7/113 20130101; H03D 13/003 20130101 |
Class at
Publication: |
375/376 |
International
Class: |
H03D 003/24 |
Claims
What is claimed is:
1. A phase detector, comprising: a delay block coupled to a first
exclusive OR (XOR) gate via a first delay element; a first
sequential device coupled the first XOR gate via a second delay
element; a second sequential device coupled to the first sequential
device and coupled to a second XOR gate via a third delay element;
and a third sequential device coupled to the second sequential
device and coupled to the second XOR gate via a fourth delay
element.
2. The phase detector according to claim 1, wherein the first delay
element comprises a variable capacitor.
3. The phase detector according to claim 2, wherein the variable
capacitor comprises a transistor.
4. The phase detector according to claim 1, wherein the first
sequential device comprises a flip flop.
5. The phase detector according to claim 1, wherein the second
sequential device comprises a latch.
6. The phase detector according to claim 1, wherein the third
sequential device comprises a latch.
7. The phase detector according to claim 1, wherein the delay block
comprises a delay cell.
8. The phase detector according to claim 1, wherein the delay block
is adapted to incorporate a time delay that is approximately equal
to the clock-to-output time delay of the first sequential
device.
9. The phase detector according to claim 1, wherein a clock signal
with an adjustable frequency is coupled to the first sequential
device and to the second sequential device.
10. The phase detector according to claim 9, wherein an inverse of
the clock signal with the adjustable frequency is coupled to the
third sequential device.
11. The phase detector according to claim 1, wherein a particular
phase offset between a clock signal and a data signal may be locked
by setting a particular time delay for the first delay element, the
second delay element, the third delay element and the fourth delay
element.
12. The phase detector according to claim 11, wherein the
particular time delay for each of the delay elements is
different.
13. The phase detector according to claim 1, wherein a locked phase
relationship between a clock signal and a data signal is adjusted
by adjusting a time delay in at least one of the first delay
element, the second delay element, the third delay element and the
fourth delay element.
14. The phase detector according to claim 1, wherein the phase
detector only adjusts a phase relationship between a clock signal
and a data signal when the data signal is in transition.
15. The phase detector according to claim 1, wherein an amount of
phase offset locked in between the clock signal and the data signal
is independent of data signal pattern.
16. The phase detector according to claim 1, wherein the phase
detector is part of a clock and data recovery circuit.
17. The phase detector according to claim 16, wherein the clock and
data recovery circuit does not charge or discharge current in its
phase adjustment loop.
18. The phase detector according to claim 1, wherein the first
delay element comprises a programmable time delay.
19. A system for adjusting a locked phase offset between a data
signal and a clock signal, comprising: a phase detector in which
one or more data paths used in generating an error signal or a
reference signal comprise a respective delay element; a loop filter
coupled to the phase detector; and a voltage controlled oscillator
coupled to the loop filter and an output of the voltage controlled
oscillator coupled to an input of the phase detector.
20. The system according to claim 19, wherein every data path used
in generating the error signal or the reference signal comprises
the respective delay element.
21. A method for adjusting a locked phase offset between a data
signal and a clock signal, comprising: adjusting a time delay in a
respective delay element disposed in each data path of a phase
detector.
22. The method according to claim 21, further comprising: adjusting
the locked phase offset between the data signal and the clock
signal independent of data signal pattern.
23. The method according to claim 21, further comprising: adjusting
phase relationship between the data signal and the clock signal
only during a transition in the data signal.
24. A method for adjusting a locked phase offset between a data
signal and a clock signal, comprising: adjusting a first time delay
in a first data path of a phase detector; and adjusting a second
time delay in a second data path of the phase detector.
Description
RELATED APPLICATION
[0001] This application is a continuation-in-part of U.S. patent
application Ser. No. 09/955,693 entitled "Linear Phase Detector for
High-Speed Clock and Data Recovery" and filed on Sep. 18, 2001.
INCORPORATION BY REFERENCE
[0002] The above-referenced United States patent application is
hereby incorporated herein by reference in its entirety.
BACKGROUND OF THE INVENTION
[0003] High-speed data communication relies heavily on clock and
data recovery (CDR) circuits. CDR circuits extract clock
information from an incoming data signal (e.g., an incoming data
stream) and employ the extracted clock signal to regenerate the
data signal, thereby reducing noise from the original data signal
and preventing noise accumulation along the communication
lines.
[0004] A CDR circuit employs a full-rate phase-lock loop. When the
loop is locked, the CDR circuit should generate a clock signal with
the exact frequency of the incoming data signal and fix the phase
relationship between the generated clock signal and the incoming
data signal. In a conventional phase detector, the conventional
lock position is such that the latching clock edge is at the center
between the data transitions.
[0005] However, optimal data regeneration does not always occur at
the conventional lock position of a conventional phase detector.
For example, different asymmetries and jitter may occur in the data
signal, especially if the data signal is propagating long
distances. In addition, the data signal may be further degraded due
to the severe dispersion and distortion that may occur in the
particular communications medium (e.g., fiber, wire, cable, air,
etc.).
[0006] Further limitations and disadvantages of conventional and
traditional approaches will become apparent to one of ordinary
skill in the art through comparison of such systems with the
present invention as set forth in the remainder of the present
application with reference to the drawings.
BRIEF SUMMARY OF THE INVENTION
[0007] Aspects of the present invention may be found in, for
example, systems and methods that adjust phase offsets. In one
embodiment, the present invention may provide a phase detector. The
phase detector may include, for example, a delay block coupled to a
first exclusive OR (XOR) gate via a first delay element; a first
sequential device coupled the first XOR gate via a second delay
element; a second sequential device coupled to the first sequential
device and coupled to a second XOR gate via a third delay element;
and a third sequential device coupled to the second sequential
device and coupled to the second XOR gate via a fourth delay
element.
[0008] In another embodiment, the present invention may provide a
system that adjusts a locked phase offset between a data signal and
a clock signal. The system may include, for example, a phase
detector in which one or more data paths used in generating an
error signal or a reference signal comprise a respective delay
element; a loop filter coupled to the phase detector; and a voltage
controlled oscillator coupled to the loop filter and an output of
the voltage controlled oscillator coupled to an input of the phase
detector.
[0009] In yet another embodiment, the present invention may provide
a method that adjusts a locked phase offset between a data signal
and a clock signal. The method may comprise, for example, adjusting
a time delay in a respective delay element disposed in each data
path of a phase detector.
[0010] In yet another embodiment, the present invention may provide
a method that adjusts a locked phase offset between a data signal
and a clock signal. The method may comprise, for example, adjusting
a first time delay in a first data path of a phase detector; and
adjusting a second time delay in a second data path of the phase
detector
[0011] These and other features and advantages of the present
invention may be appreciated from a review of the following
detailed description of the present invention, along with the
accompanying figures in which like reference numerals refer to like
parts throughout.
BRIEF DESCRIPTION OF THE DRAWINGS
[0012] FIG. 1 shows an embodiment of an optical receiver according
to the present invention.
[0013] FIG. 2 shows an embodiment of a clock and data recovery
(CDR) circuit according to the present invention.
[0014] FIG. 3 shows a diagram illustrating an embodiment of a phase
detector according to the present invention.
[0015] FIG. 4 shows a diagram illustrating an embodiment of a phase
detector according to the present invention.
[0016] FIG. 5 shows a diagram illustrating an embodiment of a delay
element according to the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0017] Some aspects of the present invention may relate to systems
and methods that adjust phase offsets, for example, in phase locked
loops. Some embodiments according to the present invention may find
application in use with, for example, phase detectors or clock and
data recovery circuits.
[0018] FIG. 1 shows an embodiment of an optical receiver according
to the present invention. Although illustrated with respect to an
optical receiver, the present invention need not be so limited. The
optical receiver 100 may include, for example, a photodiode 110, a
first resistor 120, a pre-amplifier 130, an amplifier 140, a DC
offset correction circuit 150, a second resistor 160, a clock and
data recovery (CDR) circuit 170 and a link and data detect (LDD)
circuit 180. The CDR circuit 170 may include, for example, two
outputs 190, 200. The first output 190 may provide, for example, a
data signal; and the second output 200 may provide, for example, a
clock signal. The LDD circuit 180 may include, for example, two
outputs 210, 220. The first output 210 may provide, for example, a
squelch signal; and the second output 220 may provide, for example,
a valid link signal.
[0019] An optical data path 230 may be coupled to the optical
receiver 100 via the photodiode 110. The photodiode 110 and the
first resistor 120 (e.g., a sensing resistor) may be in series and
coupled between electrical ground and a voltage source VCC. A node
between the photodiode 110 and the first resistor 120 may be
coupled to an input of the pre-amplifier 130. An output of the
pre-amplifier 130 may be coupled to a first input of the amplifier
140. An output of the amplifier 140 may be coupled to respective
inputs of the DC offset correction circuit 150, the CDR circuit and
the LDD circuit 180. The DC offset correction circuit 150 may be
coupled to a second input of the amplifier 140 via a second
resistor 160. The CDR circuit 170 and the LDD circuit 180 may also
be directly coupled to each other.
[0020] In operation, an optical data signal may be carried by the
optical data path 230. The optical data signal may be received by
the photodiode 110 which may generate a current as a function of
the received optical data signal. The generated current may result
in a particular voltage across the first resistor 120. The voltage
may be amplified by the pre-amplifier 130 and amplifier 140.
Offsets in the amplified voltage may be, for example, reduced by
the DC offset correction circuit 150 which may provide a feedback
loop back to the amplifier 140 via the second resistor 160. The
output of the amplifier 130 may drive the CDR circuit 170 and the
LDD circuit 180. The CDR circuit 170 may extract a clock signal
from the amplified data signal and provide the clock signal on the
second output 200 of the CDR circuit 170. The CDR circuit 270 may
also use the clock signal to retime the data for output on the
first output 190 of the CDR circuit 170. If the LDD circuit 160
senses either a data or link signal from the amplifier 140, then a
valid link signal may be asserted on the first output 210 of the
LDD circuit 160. If the LDD circuit 160 senses a data signal from
the amplifier 140, a receive squelch signal may be deasserted on
the second output 200.
[0021] FIG. 2 shows an embodiment of a CDR circuit according to the
present invention. The CDR circuit 170 may include, for example, a
data retimer 240, a phase detector 250, a frequency detector 260, a
loop filter 270 and a voltage controlled oscillator (VCO) 280. The
CDR circuit 170 may include, for example, two inputs 290, 300. The
first input 290 may provide, for example, a data signal received
from the amplifier 140. The second input 300 may provide, for
example, a reference clock signal. The CDR circuit 170 may include,
for example, two outputs 190, 200. The first output 190 may
provide, for example, a retimed data signal. The second output 200
may provide, for example, a clock signal. The first input 290 of
the CDR circuit 170 may be coupled to respective inputs of the data
retimer 240 and the phase detector 250. The second input 300 of the
CDR circuit 170 may be coupled to an input of the frequency
detector 260. A loop 350 may provide a feedback loop from an output
345 of the VCO 280 to respective inputs of the data retimer 240,
the phase detector 250 and the frequency detector 260. An output of
the data retimer 240 may coupled to the first output 190 of the CDR
circuit 170. A first output 310 and a second output 320 of the
phase detector 250 may be coupled to a first input and a second
input of the loop filter 270. The first output 310 of the phase
detector 250 may provide, for example, an error signal. The second
output 320 of the phase detector 250 may provide, for example, a
reference signal. An output 330 of the frequency detector 260 may
be coupled to a third input of the loop filter 270. The loop filter
270 may be coupled to the VCO 280 via an output 340. The output 340
may provide, for example, a control signal such as, for example, a
control voltage signal or a tuning signal. The output 345 of the
VCO 280 may be coupled to the second output 200 of the CDR circuit
170 and may be coupled to the loop 350. The VCO 280 may be coupled
to the data retimer 240, the phase detector 250 and the frequency
detector 260 via the loop 350.
[0022] Although illustrated as separate components, the present
invention also contemplates different levels of integration. For
example, the phase detector 250 may be integrated, at least in
part, with the frequency detector 260. In addition, although many
of the signals are illustrated as single-ended signals, the present
invention also contemplates that some signals may be represented as
differential signals. For example, the reference clock signal
provided on the second input 300 of the CDR circuit 170 may be a
single-ended signal provided on a single line or a differential
signal provided on at least two lines. Other examples of signals
that may be represented as single-ended signals or differential
signals include, for example, the data signal, the error signal and
the reference signal.
[0023] In operation, a startup of the CDR circuit 170 may be
initiated, for example, by turning on a power supply, receiving a
valid link via the receiver 100 or other events or conditions. A
reference clock signal (e.g., a system clock signal) may be
provided at the second input 300 of the CDR circuit 170. The
reference clock signal may be, for example, a relatively
low-frequency signal generated by a stable oscillation source
(e.g., a crystal). The frequency detector 260 may compare the
reference clock signal with the output 345 of the VCO 280, which
may be carried via the loop 350 to an input of the frequency
detector 260. In one example, the output 345 of the VCO 280 may be
divided down in frequency by, for example, a divider before being
compared in the frequency detector 260 with the reference clock
signal (e.g., a low-frequency system clock). The signal comparison
may include, for example, calculating a difference signal. The
frequency detector 260 may provide an output signal, which may be a
function of the signal comparison. The output signal of the
frequency detector 260 may then be filtered by the loop filter
270.
[0024] The loop filter 270 may provide a control signal (e.g., a
voltage control signal for controlling the VCO 280) on output 340.
The control signal may be used by the VCO 280 to adjust, for
example, the frequency of the output 345 of the VCO 280 and thus,
the output 200 (e.g., a clock signal) of the CDR circuit 170. If
the frequency of the signal on the output 345 of the VCO 280 is too
high, then loop filter 270 may provide a control signal on the
output 340 such that the VCO 280 may lower the frequency of its
output. If the frequency of the signal on the output 345 of the VCO
280 is too low, then the loop filter 270 may provide a control
signal on the output 340 such that the VCO 280 may increase the
frequency of its output. Since the loop 350 may provide the output
345 of the VCO 280 to the frequency detector 260 as a feedback
signal, the frequency of the output 345 of the VCO 280 may be
adjusted with greater precision until, for example, a particular
threshold condition is satisfied.
[0025] The phase detector 250 may operate concurrently or
sequentially with the frequency detector 260. In one embodiment,
for example, the frequency detector 230 may first tune the output
345 of the VCO 280 to approximately the desired frequency before
the phase detector 250 activates. The phase detector 250 may
receive, for example, a data signal at a first input and may
receive, for example, the output 345 of the VCO 280, via the loop
350, at a second input. The data signal may be carried, for
example, on the first input 290 of the CDR circuit 170 which may be
coupled to the first input of the phase detector 250. In one
example, the output of the amplifier 140 may be coupled to the CDR
circuit 170 and may provide the data signal to the first input 290
of the CDR circuit 170. The phase detector 250 may adjust the
frequency and/or the phase of the output 345 of the VCO 280 by
comparing the output signal carried by the output 345 of the VCO
280 and the data signal. In one embodiment, the phase detector 250
may determine a phase relationship between the VCO 280 output
signal and the data signal. For example, the phase detector 250 may
compare transitions in the data signal to the rising edges or the
falling edges of a clock signal provided by output 345 of the VCO
280. The phase detector 250 may produce an error signal on the
first output 310 of the phase detector 250 that may be proportional
to the phase relationship. The phase detector 250 may also produce
a reference signal on the second output 310 of the phase detector
250. The reference signal may be, for example, subtracted from the
error signal to generate a correction signal that is independent of
the data signal pattern, but is dependent on the phase error.
[0026] The loop filter 270 may then subtract and filter the error
signal and the reference signal in generating a control signal
(e.g., a voltage signal) on the output 340 of the loop filter 270.
If the data signal provided by the first input 290 and the clock
signal provided by the output 345 of the VCO 280 do not have the
desired phase relationship, then the control signal may be used to
correct the phase error. For example, if the data signal comes too
soon (i.e., the data signal is advanced in time relative to the
clock signal), then the phase detector 250 may increase the error
signal (e.g., an error voltage signal) on the second output 310 of
the phase detector 250. This may result in a change in the control
signal on the output 340 which may, in turn, increase the frequency
of the output signal (i.e., the clock signal) on the output 345 of
the VCO 280. As the frequency of the clock signal increases, its
edges come sooner in time (i.e., the edges advance in time). Thus,
for example, the rising edges of the clock come in better alignment
with the transitions or other reference points in the data signal.
The feedback may insure that the data signal and the clock signal
have the desired phase relationship for retiming the data via the
data retimer 240. When the desired phase relationship is reached
via the feedback, then the loop may be deemed locked. Thus, the CDR
circuit 170 may include one or more phase-locked loops.
[0027] The data retimer 240 may generate retimed data. The data
retimer 240 may receive, for example, the data signal provided by
the first input of the CDR circuit 170 at a first input of the data
retimer 240 and may receive, for example, the clock signal provided
by the output 345 of the VCO 280 at a second input of the data
retimer 240. The data retimer 240 may generate retimed data using,
for example, the data signal and the clock signal. The output of
the data retimer 240 may be coupled, for example, to the first
output 190 of the CDR circuit.
[0028] FIG. 3 shows a diagram illustrating an embodiment of a phase
detector according to the present invention. The phase detector 250
may include, for example, a delay block 350, a first sequential
device 360, a second sequential device 370, a third sequential
device 380, a first exclusive OR (XOR) gate 390 and a second XOR
gate 400. In one embodiment, the first sequential device (FSD) 360
may be, for example, a flip flop; and the second sequential device
(SSD) 370 and the third sequential device (TSD) 380 may be, for
example, latches. In one example, the flip flop may be a
negative-edge triggered device (i.e., the flip flop may change
state on the falling edges of the clock signal). The latch may be
adapted to pass data when its clock input is high and to latch data
when its clock input is low.
[0029] A data input 410 to the phase detector 250 may be coupled to
an input of the delay block 350 and to an input to the FSD 360. The
data input 410 may be coupled, for example, to a first input of the
phase detector 250 which, in turn, may be coupled to the first
input 290 of the CDR circuit 170. The output of the FSD 360 and the
output of the delay block 350 may be coupled to respective inputs
of the first XOR gate 390. The output 430 of the first XOR gate 390
may provide, for example, an error signal that may be carried by
the first output 310 of the phase detector 250. The output of the
FSD 360 may be coupled to an input of the SSD 370. The output of
the SSD 370 may be coupled to an input of the TSD 380. The clock
input 420 may be coupled to the FSD 360, the SSD 370 and the TSD
380 and may provide a clock for each of the sequential devices. In
one example, the TSD 380 may use the inverted clock signal as a
clock signal. The clock input 420 may be coupled, for example, to a
second input of the phase detector 250 which, in turn, may be
coupled to the output 345 of the VCO 280 via the loop 350. The
output of the SSD 370 and the output of the TSD 380 may be coupled
to respective inputs of the second XOR gate 400. The output 440 of
the second XOR gate 400 may provide, for example, a reference
signal that may be carried by the second output 320 of the phase
detector 250.
[0030] In operation, a data signal may be provided by the data
input 410 and received by the FSD 360 and the delay block 350. The
FSD 360 may be, for example, a flip flop. The flip flop may be
clocked by a clock signal provided by the clock input 420. The
clock signal may have been generated, for example, by the VCO 280.
For example, on each falling edge of the clock signal, data in the
data signal may be latched by the flip flop and may be held at its
output. In one embodiment, the output signal of the flip flop may
be the data signal retimed to follow a falling edge of the clock
signal. The SSD 370 and the TSD 380 may be, for example, latches.
The output signal of the flip flop may be passed by the latch of
the SSD 370 when the clock signal is high or may be latched when
the clock signal is low. In one embodiment, the output signal of
the latch of the SSD 370 may be the output signal of the flip flop
delayed by half a clock cycle. The output signal of the latch of
the SSD 370 may be passed by the latch of the TSD 380 when the
clock signal is low or may be latched when the clock signal is
high. In one embodiment, the output signal of the latch of the TSD
380 may be the output signal of the latch of the SSD 370 delayed by
half a clock cycle.
[0031] The delay block 350 may delay the data signal received from
the data input 410 by a particular time delay. In one embodiment,
the delay through the delay block 350 may be approximately equal to
the clock-to-output delay of the flip flop of the FSD 360. The
clock-to-output delay for a flip flop may be the delay of the
output changing in response to a clock edge. The first XOR gate 400
may produce an output signal on the output 430 of the first XOR
gate 400. The output signal of the first XOR gate 390 may be a
function of the exclusive OR between the output of the delay block
350 and the output of the flip flop 360. The output signal of the
first XOR gate 390 may be an error signal. The second XOR gate 400
may produce an output signal on the output 440 of the second XOR
gate 400. The output signal of the second XOR gate 390 may be a
function of the exclusive OR between the output of the latch of the
SSD 370 and the output of the latch of the TSD 380. The output
signal of the second XOR gate 390 may be a reference signal.
[0032] FIG. 4 shows a diagram illustrating an embodiment of a phase
detector according to the present invention. The phase detector 250
may include many of the same components as described above
including, for example, the FSD 360, the SSD 370, the TSD 380, the
first XOR gate 390 and the second XOR gate 400. In FIG. 4, the
delay block 350 is illustrated as a delay cell 450. The phase
detector 350 may also include, for example, a first delay element
460, a second delay element 470, a third delay element 480 and a
fourth delay element 490. The first delay element 460 may be
disposed between the output of the delay cell 450 and the first
input of the first XOR gate 390. The second delay element 470 may
be disposed between the output of the FSD 360 and the second input
of the first XOR gate 390. The third delay element 480 may be
disposed between the output of the SSD 370 and the first input of
the second XOR gate 400. The fourth delay element 490 may be
disposed between the output of the TSD 380 and the second input of
the second XOR gate 400. As illustrated, a delay element has been
disposed in each of the four data paths. However, a delay element
need not be present in each data path. Each delay element 460, 470,
480, 490 may be set to a particular delay time. The delay setting
for a particular delay element may be changed. In one example, the
delay settings may be programmable.
[0033] Although illustrated as separate components, the present
invention also contemplates various degrees of integration. For
example, the first delay element 460 may be integrated, at least in
part, with the delay cell or with the first XOR gate 390.
Similarly, the other delay elements 470, 480, 490 may be
integrated, at least in part, with the sequential devices 360, 370,
380 or with the XOR gates 390, 400. Moreover, although illustrated
as singled-ended signals, at least some of the signals may be
represented as differential signals such as, for example, the error
signal, the reference signal, the clock signal and the data signals
carried on the four data paths. A differential signal may employ at
least two lines, whereas a single-ended signal might employ only a
single line. A delay element may be present in at least one of the
lines carrying a differential signal in a data path.
[0034] FIG. 5 shows a diagram illustrating an embodiment of a delay
element according to the present invention. Delay elements may be
realized in any number of conventional manners. In one example, the
delay element may include, for example, a variable capacitor 500.
The variable capacitor 500 may be disposed between electrical
ground and the line to which the delay element may be adding delay.
The variable capacitor 500 may be formed in any number of
conventional manners. In one example, the variable capacitor 500
may include conventionally configured transistors.
[0035] In operation, the delay elements 460, 470, 480, 490 may
provide delays (e.g., different delays) which may, in turn,
generate different phase-locking points (e.g., phase offsets)
between the data signal and the clock signal. In one example, delay
elements 460, 470 may provide delays to each of the inputs of the
first XOR gate 390; and delay elements 480, 490 may provide delays
to each of the inputs of the second XOR gate 400. By using a delay
element for each branch input to the XOR gate 390, a wider range of
delay mismatches may be available. However, a delay element need
not be present in each branch input to the XOR gates. In one
example, a relatively small amount of delay in each of the input
branches of the XOR gates may generate a relatively large amount of
relative delay between the data signal and the clock signal. In
some applications such as, for example, some applications related
to high-speed data recovery, introducing small delays in the data
signal may help in preserving data integrity.
[0036] In some applications, the phase detector may lock the phase
relationship between the clock signal and the data signal such that
the latching clock edge is at the center between the data
transitions. However, the data signal may be severely distorted and
dispersed due to, for example, the data signal traveling over very
long distances. The data signal may be subject to, for example, an
asymmetrical jitter distribution. In such cases, the optimal phase
relationship between the clock signal and the data signal may not
be with the latching clock edge centered between the data
transitions. Thus, through the use of the delay elements 460, 470,
480, 490, the locking point in the phase relationship between the
clock signal and the data signal may be shifted (i.e., a particular
phase offset chosen) so as to, for example, minimize the bit error
rate (BER) or to provide optimum data regeneration.
[0037] One or more embodiments according to the present invention
may have one or more of the advantages as set forth below.
[0038] By using delay elements to generate a different phase-lock
position, the CDR circuit 170 may not accumulate charge. In one
example, when no data is being received or when a long chain of
ones or zeroes is being received, the CDR circuit may not
accumulate charge. The accumulation of charge may have the
potential of pushing the loop out of lock. Compare, e.g., "Method
and Apparatus for High Speed Signal Recovery," U.S. patent
application Ser. No. 10/159,788 to Momtaz et al., assigned to the
same assignee as the present application and filed on May 30, 2002.
The above-referenced application is hereby incorporated by
reference in its entirety.
[0039] One or more embodiments according to the present invention
may generate the desired phase-offset from inside of the phase
detector and the amount of phase-offset does not change with the
input data pattern.
[0040] One or more embodiments according to the present invention
may be used in, for example, linear-type phase detectors,
binary-type (e.g., bang-bang type) phase detectors and other types
of phase detectors.
[0041] According to one or more embodiments of the present
invention, since the delay elements are added on the data path, the
delay elements may be effective when there is a transition.
Accordingly, the phase detector may only adjust the phase
relationship between the clock signal and the data signal when the
data signal is changing. Thus, the phase adjustment amount may be
independent of the input data pattern.
[0042] While the present invention has been described with
reference to certain embodiments, it will be understood by those
skilled in the art that various changes may be made and equivalents
may be substituted without departing from the scope of the present
invention. In addition, many modifications may be made to adapt a
particular situation or material to the teachings of the present
invention without departing from its scope. Therefore, it is
intended that the present invention not be limited to the
particular embodiment disclosed, but that the present invention
will include all embodiments falling within the scope of the
appended claims.
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