U.S. patent number 7,338,874 [Application Number 11/488,239] was granted by the patent office on 2008-03-04 for highly integrated semiconductor device with silicide layer that secures contact margin and method of manufacturing the same.
This patent grant is currently assigned to Samsung Electronics Co., Ltd.. Invention is credited to Young-gun Ko, Myoung-hwan Oh.
United States Patent |
7,338,874 |
Oh , et al. |
March 4, 2008 |
Highly integrated semiconductor device with silicide layer that
secures contact margin and method of manufacturing the same
Abstract
Provided are a highly integrated semiconductor device with a
silicide layer, which can secure a contact margin, and a method of
manufacturing the highly integrated semiconductor device. The
highly integrated semiconductor device includes a gate electrode
formed on a semiconductor substrate. A source region and a drain
region are formed in predetermined upper portions of the
semiconductor substrate on two sides of the gate electrode such
that each of the source region and the drain region includes a
lightly doped drain (LDD) region and a heavily doped region. A
silicide layer is formed on the gate electrode, the source region,
and the drain region. The silicide layer has a sufficient thickness
to function as an ohmic contact and is formed on the LDD region and
the heavily doped region of each of the source region and the drain
region.
Inventors: |
Oh; Myoung-hwan (Yongin-si,
KR), Ko; Young-gun (Seongnam-si, KR) |
Assignee: |
Samsung Electronics Co., Ltd.
(KR)
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Family
ID: |
34192193 |
Appl.
No.: |
11/488,239 |
Filed: |
July 18, 2006 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20060255413 A1 |
Nov 16, 2006 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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10862996 |
Jun 8, 2004 |
7098514 |
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Foreign Application Priority Data
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Aug 22, 2003 [KR] |
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03-58287 |
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Current U.S.
Class: |
438/300; 438/607;
257/E21.43; 257/E29.268; 257/E21.438 |
Current CPC
Class: |
H01L
29/6659 (20130101); H01L 29/6653 (20130101); H01L
29/665 (20130101); H01L 29/66628 (20130101); H01L
29/6656 (20130101); H01L 29/7835 (20130101) |
Current International
Class: |
H01L
21/336 (20060101) |
Field of
Search: |
;438/300,491,495,532,607,923 ;257/E21.43 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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690 32 917 |
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Jul 1999 |
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DE |
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0 420 748 |
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Jan 1999 |
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EP |
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10-0361533 |
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Nov 2002 |
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KR |
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Primary Examiner: Chaudhari; Chandra
Attorney, Agent or Firm: Mills & Onello LLP
Parent Case Text
This application is a divisional of U.S. application Ser. No.
10/862,996, filed on Jun. 8, 2004, now U.S. Pat. No. 7,098,514,
which relies for priority upon Korean Patent Application No.
10-2003-0058287, filed on Aug. 22, 2003, the contents of which are
herein incorporated by reference in their entirety.
Claims
What is claimed is:
1. A method of manufacturing a highly integrated semiconductor
device, the method comprising: forming a gate electrode on a
semiconductor substrate; forming an offset spacer along sidewalls
of the gate electrode; growing predetermined portions of the
semiconductor substrate on the both sides of the gate electrode to
a predetermined thickness to form a selective epitaxial growth
layer; forming a source region and a drain region in the
predetermined grown portions of the semiconductor substrate on the
both sides of the gate electrode such that each of the source
region and the drain region includes a lightly doped drain region
and a heavily doped region; and forming a silicide layer on the
gate electrode, the source region, and the drain region, wherein
the silicide layer is formed on each of the lightly doped drain
region and the heavily doped region, and wherein the forming of the
source region and the drain region and the forming of the silicide
layer include: implanting low concentration impurities into the
predetermined portions of the semiconductor substrate on the two
sides of the gate electrode to form the lightly doped drain
regions; forming the silicide layer on the lightly doped drain
regions; forming an insulating spacer along sidewalls of the gate
electrode; and implanting high concentration impurities into
predetermined portions of the semiconductor to form the heavily
doped regions such that the insulating spacer is disposed between
the heavily doped regions and the semiconductor substrate.
2. The method of claim 1, wherein the offset spacer has a minimum
thickness necessary to insulate conductive layers from each
other.
3. The method of claim 2, wherein the forming of the offset spacer
includes: reoxidizing the gate electrode and the semiconductor
substrate; depositing an insulating layer on the resultant
structure to a predetermined thickness; and anisotropically etching
the insulating layer.
4. The method of claim 1, wherein the forming of the source region
and the drain region includes removing the insulating spacer.
5. The method of claim 1, wherein the forming of the silicide layer
includes: depositing a transition metal layer on the resultant
structure of the semiconductor substrate having the source region
and the drain region formed therein, and the gate electrode;
thermally processing the transition metal layer to form the
silicide layer; and removing remaining portions of the transition
metal layer.
6. The method of claim 5, wherein the transition metal layer is
made of a metal selected from the group consisting of titanium,
cobalt, nickel, platinum, and a combination of these metals.
7. The method of claim 5, wherein the transition metal layer is
made of a metal selected from titanium and cobalt, the thermally
processing step includes: first thermally processing the transition
metal layer at a temperature of 350 to 600.degree. C.; and second
thermally processing the first thermally processed transition metal
layer at a temperature of 500 to 900.degree. C.
8. The method of claim 5, wherein the transition metal layer is
made of nickel, the thermally processing step includes thermally
processing the transition metal layer at a temperature of 350 to
600.degree. C.
9. The method of claim 1, further comprising forming a self-aligned
spacer along sidewalls of the offset spacer, after the forming of
the silicide layer.
10. A method of manufacturing a highly integrated semiconductor
device, the method comprising: forming a gate electrode on a
semiconductor substrate; forming an offset spacer along sidewalls
of the gate electrode with a minimum thickness necessary to
insulate conductive layers from each other; growing predetermined
portions of the semiconductor substrate on the both sides of the
gate electrode to a predetermined thickness to form a selective
epitaxial growth layer; forming a source region and a drain region
in the predetermined grown portions of the semiconductor substrate
on the both sides of the gate electrode such that each of the
source region and the drain region includes a lightly doped drain
region and a heavily doped region; forming a first silicide layer
on the gate electrode, the source region, and the drain region;
forming an insulating spacer along two sides of the offset spacer;
and forming a second silicide layer on predetermined portions of
the first silicide layer on the both sides of the offset spacer and
on the gate electrode.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to a highly integrated semiconductor
device and a method of manufacturing the highly integrated
semiconductor device, and more particularly, to a highly integrated
semiconductor device with a silicide layer that can secure a
contact margin, and a method of manufacturing the highly integrated
semiconductor device.
2. Description of the Related Art
As the degree of integration of a semiconductor device increases,
the area and line width of the semiconductor device decreases,
resulting in an increase of an interconnection resistance and a
contact resistance of the semiconductor device. Such an increase in
resistance reduces the operating speed of the semiconductor
device.
To reduce the interconnection resistance and contact resistance, a
method of forming a self-aligned silicide (SALICIDE) layer on a
gate electrode, a source region, and a drain region of a metal
oxide semiconductor (MOS) transistor has been suggested in Silicon
processing for the VLSI Era (Vol. 4, page 604).
A conventional highly integrated semiconductor device comprising a
self-aligned silicide layer will be described with reference to
FIGS. 1 and 2.
Referring to FIG. 1, a gate insulating layer 15 and a polysilicon
layer 18 are sequentially deposited on a semiconductor substrate
10, for example, a silicon substrate, and predetermined portions of
the gate insulating layer 15 and the polysilicon layer 18 are
patterned to form a gate electrode 20. Low concentration impurity
ions are implanted into predetermined portions of the semiconductor
substrate 10 on both sides of the gate electrode 20 to form lightly
doped drain (LDD) regions 25a and 25b. Next, an insulating spacer
30 is formed along both sidewalls of the gate electrode 20, and
heavily doped regions 35a and 35b are formed in predetermined
portions of the semiconductor substrate 10 on both sides of the
spacer 30, thereby forming a source region 40a and a drain region
40b. Next, a transition metal layer (not shown) is deposited on the
resultant structure, and a heat treatment is performed. The gate
electrode 20, the source region 40a, and the drain region 40b,
which are made of silicon, react with the transition metal layer,
such that a silicide layer 45 is formed on the gate electrode 20,
the source region 40a, and the drain region 40b. Next, unreacted
portions of the transition metal layer are removed. Since the
silicide layer 45, which has a low resistance, is formed on the
gate electrode 20, the source region 40a, and the drain region 40b,
which are to be connected to a metal layer later, an
interconnection resistance and a contact resistance are
reduced.
Referring to FIG. 2, an interlayer insulating layer 50 is deposited
on the resultant structure of FIG. 1, and is etched until the
source region 40a and the drain region 40b are exposed, thereby
forming a contact hole 55a.
However, as the degree of integration of the semiconductor device
increases, the areas of the source region 40a and the drain region
40b decrease. Because of a lack of a margin necessary for the
contact hole, misalignment may occur during a photolithography
process performed to form the contact hole. If misalignment occurs,
a contact hole 55 passing through the spacer 30 may be formed,
thereby exposing the LDD region 25a, as shown in FIG. 2. Since the
LDD region 25a exposed by the contact hole 55 has a relatively low
impurity concentration and a high resistance, a contact resistance
between the LDD region 25a and the metal layer (not shown)
increases when the LDD region 25a contacts the metal layer
later.
Furthermore, with the reduced line width of the gate electrode in
the highly integrated semiconductor device, the depths of the
source region 40a and the drain region 40b are also decreasing. As
a consequence, a design rule of less than 0.1 .mu.m requires a
junction depth less than approximately 800 .ANG..
If the silicide layer 45 is formed on the source region 40a and the
drain region 40b having a shallow junction depth, the silicide
layer must also be thin, and the silicon of which the source region
40a and the drain region 40b are made is mostly used to form the
silicide layer 45, causing a junction leakage current.
SUMMARY OF THE INVENTION
The present invention provides a highly integrated semiconductor
device comprising: a semiconductor substrate; a gate electrode
disposed on a predetermined portion of the semiconductor substrate;
an epitaxial layer formed on predetermined portions of the
semiconductor substrate on both sides of the gate electrode such
that the gate electrode is recessed a predetermined depth into the
epitaxial layer; a source region and a drain region formed in the
epitaxial layer and predetermined upper portions of the
semiconductor substrate below the epitaxial layer such that each of
the source region and the drain region includes a lightly doped
drain region and a heavily doped region; an offset spacer formed
along the sidewalls of the gate electrode and insulating the gate
electrode from the source region and the drain region; and a
silicide layer formed on the gate electrode, the source region, and
the drain region, wherein the silicide layer is formed on the
lightly doped drain region and the heavily doped region of each of
the source region and the drain region.
In one embodiment, the silicide layer has a sufficient thickness to
function as an ohmic contact layer.
The epitaxial layer can be a silicon layer or a silicon-germanium
layer. The epitaxial layer can have a thickness ranging
approximately from 250 to 350 .ANG.. Each of the source region and
the drain region can have a depth ranging from 800 to 1000
.ANG..
The offset spacer can have a minimum thickness necessary to
insulate conductive layers from each other. The offset spacer can
have a thickness ranging from 150 to 250 .ANG..
In one embodiment, the silicide layer is thinner than the epitaxial
layer.
The silicide layer can be composed of a metal selected from the
group consisting of titanium, cobalt, nickel, platinum, and a
combination of these metals.
In one embodiment, the semiconductor substrate is a
silicon-on-insulator substrate.
The highly integrated semiconductor device can further include a
self-aligned spacer, which is formed along sidewalls of the offset
spacer. According to another aspect of the present invention, there
is provided a highly integrated semiconductor device comprising: a
semiconductor substrate; a gate electrode disposed on the
semiconductor substrate; an epitaxial layer disposed on
predetermined portions of the semiconductor substrate on both sides
of the gate electrode such that the gate electrode is recessed a
predetermined depth into the epitaxial layer; a source region and a
drain region formed in the epitaxial layer and predetermined upper
portions below the epitaxial layer such that each of the source
region and the drain region includes a lightly doped drain region
and a heavily doped region; an offset spacer formed along the
sidewalls of the gate electrode and insulating the gate electrode
from the source region and the drain region; an insulating spacer
formed along both sides of the offset spacer; and a silicide layer
formed on the gate electrode, the source region, and the drain
region, wherein a portion of the silicide layer formed on the
heavily doped region is thicker than a portion of the silicide
layer formed on the lightly doped drain region. According to still
another aspect of the present invention, there is provided a method
of manufacturing a highly integrated semiconductor device, the
method comprising: forming a gate electrode on a semiconductor
substrate; forming an offset spacer along sidewalls of the gate
electrode; growing predetermined portions of the semiconductor
substrate on two sides of the gate electrode to a predetermined
thickness to form a selective epitaxial growth layer; forming a
source region and a drain region in the predetermined grown
portions of the semiconductor substrate on the two sides of the
gate electrode such that each of the source region and the drain
region includes a lightly doped drain region and a heavily doped
region; and forming a silicide layer on the gate electrode, the
source region, and the drain region, wherein the silicide layer is
formed on each of the lightly doped drain region and the heavily
doped region.
In one embodiment, the offset spacer has a minimum thickness
necessary to insulate conductive layers from each other. Forming of
the offset spacer can include: reoxidizing the gate electrode and
the semiconductor substrate; depositing an insulating layer on the
resultant structure to a predetermined thickness; and
anisotropically etching the insulating layer.
In one embodiment, the forming of the source region and the drain
region includes: implanting low concentration impurities into the
predetermined portions of the semiconductor substrate on the both
sides of the gate electrode to form the lightly doped drain
regions; forming a lightly doped drain spacer along sidewalls of
the gate electrode; implanting high concentration impurities into
predetermined portions of the semiconductor substrate to form the
heavily doped regions such that the lightly doped drain space is
disposed between the heavily doped regions and the gate electrode;
and removing the lightly doped drain spacer.
In one embodiment, forming of the source region and the drain
region and the forming of the silicide layer include: implanting
low concentration impurities into the predetermined portions of the
semiconductor substrate on the two sides of the gate electrode to
form the lightly doped drain regions; forming the silicide layer on
the lightly doped drain regions; forming an insulating spacer along
sidewalls of the gate electrode; and implanting high concentration
impurities into predetermined portions of the semiconductor to form
the heavily doped regions such that the insulating spacer is
disposed between the heavily doped regions and the semiconductor
substrate. Forming of the silicide layer can include: depositing a
transition metal layer on the resultant structure of the
semiconductor substrate having the source region and the drain
region formed therein, and the gate electrode; thermally processing
the transition metal layer to form the silicide layer; and removing
remaining portions of the transition metal layer. The transition
metal layer can be made of a metal selected from the group
consisting of titanium, cobalt, nickel, platinum, and a combination
of these metals. In one embodiment, if the transition metal layer
is made of a metal selected from titanium and cobalt, the thermally
processing step includes: first thermally processing the transition
metal layer at a temperature of 350 to 600.degree. C.; and second
thermally processing the first thermally processed transition metal
layer at a temperature of 500 to 900.degree. C. If the transition
metal layer is made of nickel, the thermally processing step can
include thermally processing the transition metal layer at a
temperature of 350 to 600.degree. C.
The method can further include forming a self-aligned spacer along
sidewalls of the offset spacer, after the forming of the silicide
layer.
According to yet another aspect of the present invention, there is
provided a method of manufacturing a highly integrated
semiconductor device, the method comprising: forming a gate
electrode on a semiconductor substrate; forming an offset spacer
along sidewalls of the gate electrode with a minimum thickness
necessary to insulate conductive layers from each other; growing
predetermined portions of the semiconductor substrate on two sides
of the gate electrode to a predetermined thickness to form a
selective epitaxial growth layer; forming a source region and a
drain region in the predetermined grown portions of the
semiconductor substrate on the two sides of the gate electrode such
that each of the source region and the drain region includes a
lightly doped drain region and a heavily doped region; forming a
first silicide layer on the gate electrode, the source region, and
the drain region; forming an insulating spacer along two sides of
the offset spacer; and forming a second silicide layer on
predetermined portions of the first silicide layer on the two sides
of the offset spacer and on the gate electrode.
BRIEF DESCRIPTION OF THE DRAWINGS
The foregoing and other objects, features and advantages of the
invention will be apparent from the more particular description of
a preferred embodiment of the invention, as illustrated in the
accompanying drawings in which like reference characters refer to
the same parts throughout the different views. The drawings are not
necessarily to scale, emphasis instead being placed upon
illustrating the principles of the invention.
FIGS. 1 and 2 are cross-sectional views of a conventional highly
integrated semiconductor device.
FIG. 3 is a cross-sectional view of a highly integrated
semiconductor device according to a first preferred embodiment of
the present invention.
FIGS. 4A through 4D are cross-sectional views illustrating a method
of manufacturing the highly integrated semiconductor device of FIG.
3.
FIGS. 5A and 5B are cross-sectional views for explaining a modified
example of the highly integrated semiconductor device of FIG.
3.
FIG. 6 is a cross-sectional view of a highly integrated
semiconductor device according to a second preferred embodiment of
the present invention.
FIG. 7 is a cross-sectional view of a highly integrated
semiconductor device according to a third preferred embodiment of
the present invention.
FIG. 8 is a cross-sectional view of a highly integrated
semiconductor device according to a fourth preferred embodiment of
the present invention.
DETAILED DESCRIPTION OF THE INVENTION
The present invention will now be described more fully with
reference to the accompanying drawings, in which preferred
embodiments of the invention are shown. The sizes of elements in
the drawings are exaggerated to provide visual clarity and permit
clear description.
FIG. 3 is a cross-sectional view of a highly integrated
semiconductor device according to a first embodiment of the present
invention, and FIGS. 4A through 4D are cross-sectional views
illustrating a method of manufacturing the highly integrated
semiconductor device of FIG. 3.
Referring to FIG. 3, a gate electrode 110 is formed on a
semiconductor substrate 100. The semiconductor substrate 100 may
be, for example, a silicon substrate or a silicon-germanium
substrate. The gate electrode 110 includes a gate insulating layer
105 and a polysilicon layer 107. The gate electrode 110 is recessed
a predetermined thickness into the semiconductor substrate 100.
That is, the surface of the semiconductor substrate 100 on both
sides of the gate electrode 110 is elevated to a predetermined
thickness so as to overlap the sidewalls of the gate electrode 110.
Predetermined portions of the semiconductor substrate 100 that
partially overlap the sidewalls of the gate electrode 110 may be a
selective epitaxial growth (SEG) layer 120 made of silicon or
silicon-germanium. The thickness d of the predetermined portions of
the semiconductor substrate 100, namely, the SEG layer, ranges from
100 to 1000 .ANG., and preferably, from 250 to 350 .ANG.. A thin
offset spacer 115 is formed along the sidewalls of the gate
electrode 110. The offset spacer 115 is interposed between the gate
electrode 110 and the predetermined portions of the semiconductor
substrate 100 to insulate the gate electrode 110 from the
predetermined portions of the semiconductor substrate 100. The
offset spacer 115 may be a silicon oxide (SiO2) layer, a silicon
nitride (SiN) layer, a silicon oxynitride (SiON) layer, or a
combination of the silicon oxide layer, the silicon nitride layer
and the silicon oxynitride layer. It is preferable that the offset
spacer 115 have a minimum thickness necessary to insulate the gate
electrode 110 from the predetermined portions of the semiconductor
substrate 100. In one embodiment, the minimum thickness ranges from
150 to 250 .ANG.. The silicon oxide layer used as the offset spacer
115 may have a thickness in the range of 50 to 100 .ANG., and the
silicon nitride layer used as the offset spacer 115 may have a
thickness in the range of 100 to 150 .ANG..
A source region 150a and a drain region 150b are formed in
predetermined upper portions of the semiconductor substrate 100 and
include the SEG layer 120. The source region 150a includes a
lightly doped drain (LDD) region 130a and a heavily doped region
140a, and the drain region 150b includes an LDD region 130b and a
heavily doped region 140b. The source region 150a and the drain
region 150b are formed in the SEG layer 120 and in the
predetermined upper portions of the semiconductor substrate 100
under the SEG layer 120. The source region 150a and the drain
region 150b have a shallow junction depth below an initial surface
100a of the semiconductor substrate 100 but have a sufficient
junction depth by virtue of the SEG layer 120. The junction depth
of the source region 150a and the drain region 150b ranges
approximately from 800 to 1000 .ANG..
A silicide layer 160 having a predetermined thickness is formed on
the gate electrode 110, the source region 150a, and the drain
region 150b. It is preferable that the silicide layer 160 have a
sufficient thickness to function as an ohmic contact layer without
being lost during a contact with conductive interconnection lines
later. For example, the sufficient thickness may be in the range of
100 to 1000 .ANG.. Since the LDD regions 130a and 130b are not
covered by the offset spacer 115, the silicide layer 160 having the
thickness suitable for the ohmic contact function is also uniformly
formed on the LDD regions 130a and 130b.
An interlayer insulating layer 180 is formed on the resultant
structure of the semiconductor substrate 100 having the silicide
layer 160 formed thereon. A contact hole 185 is formed in the
interlayer insulating layer 180 to expose the source region 150a
and/or the drain region 150b. The conductive interconnection lines
(not shown) are formed in the contact hole 180. Even if the LDD
regions 130a and 130b are exposed due to misalignment during the
formation of the contact hole 185, contact resistance does not
greatly increase since the silicide layer 160, which has a low
resistance, is formed on the LDD regions 130a and 130b, which have
high resistances because of forming the silicide layer 160 on the
LDD regions 130a and 130b. Accordingly, the contact hole 185 can be
formed over the entire area of the LDD regions 130a and 130b,
thereby increasing a contact margin.
A method of manufacturing the highly integrated semiconductor
device will now be described.
Referring to FIG. 4A, the semiconductor substrate 100 is prepared.
The semiconductor substrate 100 may be, for example, a silicon
substrate or a silicon-germanium substrate that is doped with
impurities. The gate insulating layer 105 and the polysilicon layer
107 are sequentially deposited on the semiconductor substrate 100,
and are anisotropically etched to form the gate electrode 110. To
repair damage that may occur during the etching process for forming
the gate electrode 110, surfaces of the semiconductor substrate 100
and the gate electrode 110 are reoxidized. A reoxidized layer (not
shown) may be formed on the surfaces of the semiconductor substrate
100 and the gate electrode 110 during the reoxidization. An
insulating layer thinner than a general LDD spacer, for example, a
silicon oxide layer, a silicon nitride layer, or a silicon
oxynitride layer, is deposited on the resultant structure and acts
as a spacer. It is preferable that the insulating layer have a
minimum thickness, e.g., 100 to 200 .ANG., necessary to insulate
conductive layers from each other. Next, the insulting layer is
anisotropically blanket-etched to form the offset spacer 115 along
the sidewalls of the gate electrode 110. The offset spacer 115 may
include the reoxidized layer and the insulating layer. The
reoxidized layer on the gate electrode 110 and the semiconductor
substrate 100 is removed during the etching process for forming the
offset spacer 115.
Next, the resultant structure is subjected to selective epitaxial
growth to a predetermined thickness to form SEG layers 120 and 125.
Since the SEG layers 120 and 125 are grown only on layers
containing silicon, they are grown only on the semiconductor
substrate 100 and the polysilicon layer 107. The SEG layers 120 and
125 have a thickness ranging from 100 to 1000 .ANG., and
preferably, from 250 to 350 .ANG.. Since the SEG layer 120 is
formed and thus the predetermined portions of the semiconductor
substrate 100 are elevated to the predetermined thickness d, the
gate electrode 110 is recessed in the semiconductor substrate 100
by a predetermined depth. Reference numeral 100a denotes an initial
surface of the semiconductor substrate 100 shown in dashed
lines.
Referring to FIG. 4B, low concentration impurity ions are implanted
into the SEG layer 120 and the predetermined portions of the
semiconductor substrate 100 under the SEG layer 120 to form the LDD
regions 130a and 130b. The low concentration impurity ions are
preferably implanted so that the LDD regions 130a and 130b are
thicker than the SEG layer 120.
Referring to FIG. 4C, the insulating layer is deposited on the
resultant structure, and then anisotropically blanket-etched to
form an LDD spacer 135 along the offset spacer 115. The LDD spacer
135 may be a silicon oxide layer or a silicon nitride layer. High
concentration impurity ions are implanted into predetermined
portions of the semiconductor substrate 100, in which the LDD
regions 130a and 130b are formed, beyond the edges of the LDD
spacer 135 to form heavily doped regions 140a and 140b. As a
consequence, the source region 150a and the drain region 150b are
formed. The source region 150a and the drain region 150b have a
shallow junction depth of 500 to 800 .ANG. below the initial
surface 100a of the semiconductor substrate 100, but have a
relatively large junction depth of approximately 800 to 1000 .ANG.
below the surface of the SEG layer 120, which is lifted from the
surface of the semiconductor substrate 100.
Referring to FIG. 4D, the LDD spacer 135 is removed using a
conventional method to expose the LDD regions 130a and 130b. Next,
a refractory transition metal layer 155 is formed on the resultant
structure. The transition metal layer 155 may be made of a metal
selected from the group consisting of titanium (Ti), cobalt (Co),
nickel (Ni), platinum (Pt), and a combination of the titanium,
cobalt, nickel, and platinum. The transition metal layer 155 has a
thickness of 100 to 1000 .ANG., and preferably, 100 to 200
.ANG..
Referring to FIG. 3, the resultant structure is thermally processed
to form the silicide layer 160 to a thickness of 100 to 1000 .ANG.,
and preferably, 100 to 200 .ANG., on the gate electrode 110, the
source region 150a and the drain region 150b. If the transition
metal layer is made of titanium or cobalt, the resultant structure
of the semiconductor substrate 100 is first thermally processed at
a temperature of 350 to 600.degree. C. and then second thermally
processed at a temperature of 500 to 900.degree. C. to form the
silicide layer of a stable phase. On the other hand, if the
transition metal layer is made of nickel, the resultant structure
of the semiconductor substrate 100 is thermally processed once at a
temperature of 350 to 650.degree. C. to form the silicide layer of
a stable phase. Next, unreacted portions of the transition metal
layer, that is, portions of the transition metal layer remaining on
the offset spacer 115 and a separating layer (not shown) are
removed by a wet etching process. Accordingly, the silicide layer
160 is formed on the gate electrode 110, the source region 150a,
and the drain region 150b.
The silicide layer 160 can be formed between the forming of the LDD
regions 130a and 130b and the forming of the LDD spacer 135. That
is, after the LDD regions 130a and 130b are formed as shown in FIG.
4B, the transition metal layer (not shown) is deposited on the
semiconductor substrate 100 and then thermally processed to form
the silicide layer 160 on the LDD regions 130a and 130b and the
gate electrode 110, as shown in FIG. 5A.
Referring to FIG. 5B, the LDD spacer 135 is formed along the sides
of the offset spacer 115 using a conventional method. Next, high
concentration impurities are implanted into the LDD regions 130a
and 130b on which the silicide layer 160 is formed to form the
heavily doped regions 140a and 140b. The LDD spacer 135 is then
removed.
Referring to FIG. 3, the interlayer insulating layer 180 is
deposited on the resultant structure, and a photoresist pattern
(not shown) is formed by a conventional photolithography process on
the interlayer insulating layer 180 and exposes the source region
150a and the drain region 150b. Next, the interlayer insulating
layer 180 is etched using the photoresist pattern as an etch mask
to form the contact hole 185. Next, the photoresist pattern is
removed. Since the silicide layer 160, which has a thickness large
enough to function as an ohmic contact layer, is also formed on the
LDD regions 130a and 130b, a contact area and a contact margin
increase, and a contact resistance decreases even if the LDD
regions 130a and 130b are exposed due to some misalignment.
According to this embodiment, the silicide layer 160 having the
sufficient thickness to serve as the ohmic contact layer is formed
on the heavily doped regions 140a and 140b and the LDD regions 130a
and 130b. Hence, the contact area extends from the heavily doped
regions 140a and 140b to the LDD regions 130a and 130b, thereby
securing a sufficient contact margin.
Further, since the silicide layer 160 having a low resistance is
formed on the LDD regions 130a and 130b having a relatively low
impurity concentration, a sheet resistance of the LDD regions 130a
and 130b is reduced. Consequently, a parasitic resistance decreases
and the performance of the semiconductor device is enhanced.
Furthermore, since the source region 150a and the drain region 150b
are formed in the SEG layer 120, which is elevated from the
semiconductor substrate 100, a sufficient junction depth is
ensured. Since a sufficient amount of silicon is provided during
the forming of the silicide layer while securing the source region
150a and the drain region 150b, a junction leakage current is
reduced.
FIG. 6 is a cross-sectional view of a highly integrated
semiconductor device according to a second embodiment of the
present invention.
In the same manner as described in the first embodiment, the
silicide layer 160 is formed on the gate electrode 110, the source
region 150a, and the drain region 150b. Next, a self-aligned spacer
165 is formed along the sidewalls of the offset spacer 115 that is
formed along the sidewalls of the gate electrode 110. The
self-aligned spacer 165 may be a silicon nitride layer, and may be
thicker than the offset spacer 115.
Since a self-aligned contact (SAC) pad (not shown) can be formed on
the source region 150a and the drain region 150b on the sides of
the gate electrode 110 by virtue of the self-aligned spacer 165,
the highly integrated semiconductor device according to the second
embodiment of the present invention can be used as a transistor in
a dynamic random access memory (DRAM) cell.
FIG. 7 is a cross-sectional view of a highly integrated
semiconductor device according to a third embodiment of the present
invention.
The highly integrated semiconductor device can be formed on a
silicon-on-insulator (SOI) substrate instead of the semiconductor
substrate 100 made of silicon. Referring to FIG. 7, an SOI
substrate 200 is prepared. The SOI substrate 200 includes a base
substrate 210, a silicon oxide film-buried layer 220, and a silicon
layer 230. The SOI substrate 200 can be formed by bonding two
wafers or implanting oxygen into a wafer using ion
implantation.
Next, the gate electrode 110 and the source and drain regions 150a
and 150b are sequentially formed in the SOI substrate 200 in the
same manner as described in the first embodiment of the present
invention. Since the silicon layer 230 of the SOI substrate 200 has
the same properties as the semiconductor substrate 100 of the first
embodiment of the present invention, the highly integrated
semiconductor device can be manufactured through the same processes
as described in the first embodiment of the present invention.
According to the third embodiment of the present invention, the
bottom surfaces of the source region 150a and the drain region 150b
are separated from the silicon oxide film-buried layer 220 by a
predetermined distance. However, the bottom surface of the source
region 150a and the drain region 150b may be in contact with the
silicon oxide film-buried layer 220, respectively.
The highly integrated semiconductor device of the third embodiment
can obtain the same effect as that of the previous embodiments and
further reduces latch-up caused by parasitic resistance.
FIG. 8 is a cross-sectional view of a highly integrated
semiconductor device according to a fourth embodiment of the
present invention.
To reduce the resistance of the source region 150a and the drain
region 150b, a second silicide layer 170 is formed on a
predetermined portion of the source region 150a and the drain
region 150b.
That is, after the self-aligned spacer 165 is formed along the
sidewalls of the offset spacer 115, which is formed along the
sidewalls of the gate electrode 110 in the same manner as described
in the second embodiment, a second transition metal layer (not
shown) is formed on the resultant structure of the highly
integrated semiconductor. The second transition metal layer may be
the same as or different from the first transition metal layer. For
example, the second transition metal layer may be made of titanium,
cobalt, nickel, or platinum. Next, the portion of the semiconductor
substrate 100 on which the second transition metal layer is formed
is thermally processed at a predetermined temperature to form the
second silicide layer 170. Here, the thermal processing step can be
performed once or twice depending on a metal of the transition
metal layer, similarly to the first embodiment of the present
invention.
The second silicide layer 170 is formed on the gate electrode 110
and the heavily doped regions 140a and 140b of the source region
150a and the drain region 150b, which are exposed by the
self-aligned spacer 165. Because of the second silicide layer 170,
a total silicide layer 175 including the first silicide layer 160
and the second silicide layer 170 formed on the gate electrode 110
is thicker than the first silicide layer 160, and the total
silicide layer 175 formed on the source region 150a and the drain
region 150b has a stepped shape.
Since the second silicide layer 170 is further formed on the gate
electrode 110, the source region 150a, and the drain region 150b,
the resistance of the gate electrode 110, the source region 150a,
and the drain region 150b is further reduced.
As described above, the silicide layer having the sufficient
thickness to function as the ohmic contact layer is uniformly
formed on the LDD regions. Accordingly, even if the LDD regions are
exposed due to misalignment resulting from the forming of the
contact hole, a contact resistance is not increased. In addition,
since the LDD regions can be used as a contact area, a sufficient
contact margin of the highly integrated semiconductor device is
secured.
Moreover, since the silicide layer having the predetermined
thickness is formed on the LDD regions having the relatively low
concentration, the resistance of the LDD regions is reduced and a
parasitic resistance is prevented from increasing.
Since the source region and the drain region are formed in the SEG
layer, which is lifted from the substrate, a sufficient junction
depth is obtained. Consequently, a sufficient amount of silicon can
be provided during the forming of the silicide layer while securing
the source region and the drain region of the predetermined depth,
thereby reducing a junction leakage current.
While the present invention has been particularly shown and
described with reference to exemplary embodiments thereof, it will
be understood by those of ordinary skill in the art that various
changes in form and details may be made therein without departing
from the spirit and scope of the present invention as defined by
the following claims.
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