U.S. patent number 7,952,422 [Application Number 12/511,658] was granted by the patent office on 2011-05-31 for methods and apparatus for varying a supply voltage or reference voltage using independent control of diode voltage in asymmetrical double-gate devices.
This patent grant is currently assigned to International Business Machines Corporation. Invention is credited to Ching-Te Chuang, Keunwoo Kim, Jente Benedict Kuang, Hung Cai Ngo, Kevin John Nowka.
United States Patent |
7,952,422 |
Chuang , et al. |
May 31, 2011 |
Methods and apparatus for varying a supply voltage or reference
voltage using independent control of diode voltage in asymmetrical
double-gate devices
Abstract
Methods and apparatus are provided for varying one or more of a
supply voltage and reference voltage in an integrated circuit,
using independent control of a diode voltage in an asymmetrical
double-gate device. An integrated circuit is provided that is
controlled by one or more of a supply voltage and a reference
voltage. The integrated circuit comprises an independently
controlled asymmetrical double-gate device to adjust one or more of
the supply voltage and the reference voltage. The independent
control may comprise, for example, a back gate bias. The
independently controlled asymmetrical double-gate device may be
employed in a number of applications, including voltage islands,
static RAM, and to improve the power and performance of a
processing unit.
Inventors: |
Chuang; Ching-Te (South Salem,
NY), Kim; Keunwoo (Somers, NY), Kuang; Jente Benedict
(Austin, TX), Ngo; Hung Cai (Williamson County, TX),
Nowka; Kevin John (Georgetown, TX) |
Assignee: |
International Business Machines
Corporation (Armonk, NY)
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Family
ID: |
37803882 |
Appl.
No.: |
12/511,658 |
Filed: |
July 29, 2009 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20090302929 A1 |
Dec 10, 2009 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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11216666 |
Aug 31, 2005 |
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Current U.S.
Class: |
327/534;
327/544 |
Current CPC
Class: |
G11C
5/147 (20130101); G11C 11/412 (20130101); G11C
11/417 (20130101) |
Current International
Class: |
H03K
3/01 (20060101) |
Field of
Search: |
;327/534,540,544
;713/320,322 |
References Cited
[Referenced By]
U.S. Patent Documents
Other References
Nowak et al., "Turning Silicon on its Edge," IEEE Circuits &
Devices Magazine, pp. 20-31, Jan./Feb. 2004. cited by other .
Zhang et al., "A 3-GHz 70Mb SRAM in 65nm CMOS Technology with
Integrated Column-Based Dynamic Power Supply," 2005 IEEE
International Solid State Circuits Conference, Session
26/Non-Volatile Memory, pp. 474-475 (2005). cited by other .
U.S. Appl. No. 11/106,913, filed Apr. 5, 2005, Keunwoo et al. cited
by other .
Nowak et al, "Turning Silicon on its Edge," IEEE Circuits &
Devices Magazine, pp. 20-31, Jan./Feb. 2004. cited by other .
Zhang et al, "A 3-GHz 70Mb SRAM in 65nm CMOS Technology with
Integrated Column-Based Dynamic Power Supply," 2005 IEEE
International Solid State Circuits Conference, Session
26/Non-Volatile Memory, pp. 474-475 (2005). cited by other.
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Primary Examiner: Wells; Kenneth B.
Attorney, Agent or Firm: Ryan, Mason & Lewis, LLP
Government Interests
STATEMENT OF GOVERNMENT RIGHTS
This invention was made with Government support under Contract No.
NBCH3039004 awarded by Defense Advanced Research Projects Agency
(DARPA). The Government has certain rights in this invention.
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is a divisional of U.S. patent application Ser.
No. 11/216,666, filed Aug. 31, 2005, incorporated by reference
herein.
Claims
What is claimed is:
1. A processor unit, comprising: an oscillator; at least one
independently controlled asymmetrical double-gate device that
provides a variable clamping function and state retention; a phase
detector to compare an output of said oscillator to a reference
signal; and a charge pump to adjust a back-gate bias of said at
least one independently controlled asymmetrical double-gate device
based on said comparison.
2. The processor unit of claim 1, wherein said adjusted back-gate
bias improves a power performance of said processing unit.
3. The processor unit of claim 1, wherein said adjusted back-gate
bias maintains a required performance with a reduced supply
voltage.
4. The integrated circuit of claim 1, wherein said independent
control comprises said back gate bias.
5. The integrated circuit of claim 1, wherein said asymmetrical
double-gate device is a pMOS device comprising: a p+ polysilicon
gate for a first gate; and an n+ polysilicon gate for a second
gate, wherein a threshold voltage, V.sub.T, is independently
controlled by a bias of said first or second gates.
6. The integrated circuit of claim 1, wherein a gate of said
independently controlled asymmetrical double-gate device is
employed to control a clamping voltage.
Description
FIELD OF THE INVENTION
The present invention relates generally to techniques for varying a
voltage by a diode voltage in various integrated circuits and, more
particularly, to techniques for providing a variable diode voltage
using independently controlled asymmetrical double-gate
devices.
BACKGROUND OF THE INVENTION
A number of techniques have been proposed or suggested for
containing power/leakage, improving performance, and extending
scaling, including voltage islands, dynamic V.sub.DD, and separate
supplies for logic and SRAM. For example, one commonly used
technique drops the supply voltage (or raises the Ground voltage)
through a metal oxide semiconductor (MOS) diode by one threshold
voltage, V.sub.T. MOS diodes are also widely used in power-gating
structures for logic and static random access memories (SRAM) to
clamp the virtual V.sub.DD or virtual Ground (or both) to maintain
adequate voltage across the memory elements for proper state
retention, as illustrated in FIG. 1. FIG. 1 is a circuit diagram of
a conventional CMOS circuit 100 having an integrated circuit 150,
such as logic or memory elements, a power-gating switch 110 and a
diode clamp 120.
It is desirable to have a variable V.sub.T diode to compensate for
process variations, V.sub.T fluctuations or both. Furthermore, in
SRAM applications, it is desirable to have a higher supply voltage
during a read operation to maintain adequate noise margin, and a
lower supply voltage during a write operation to facilitate
writing. While well/body bias in bulk CMOS or PD/SOI devices have
been proposed for used in modulating the threshold voltage,
V.sub.T, the effect, in general, is quite limited. FIG. 2 is a
schematic cross-section of a bulk-Si (or SOI) field effect
transistor (FET) 200. As shown in FIG. 2, a large reverse well/body
bias 220 causes an exponential increase in the reverse junction
leakage including band-to-band tunneling current, while a forward
well/body bias 210 results in an exponential increase in the
forward diode leakage. Furthermore, it is known that the V.sub.T
modulation effect diminishes with device scaling due to a low body
factor in the scaled, low V.sub.T transistor. Finally, the
distributed RC for the well/body contact limits the viable
operating frequency.
E. Nowak et al., "Turning Silicon on its Edge," IEEE Circuits
Devices Mag. 20-31 (January/February, 2004), incorporated by
reference herein, discloses a V.sub.T modulation technique that
employs double-gate devices. The disclosed V.sub.T modulation
technique uses asymmetrical gates, where the two gate electrodes
consist of materials of differing work functions. FIG. 3 is a
schematic cross-section of an asymmetrical double-gate nFET 300. As
shown in FIG. 3, the front gate 310 typically uses n+ polysilicon
and the back gate 320 typically consists of p+ polysilicon. For an
asymmetrical pFET, a p+ polysilicon gate would be used for the
front-gate and an n+ polysilicon gate would be used for the
back-gate. In such an implementation, the predominant front-channel
has a significantly lower V.sub.T and much larger current drive
compared with the "weak" back-channel.
As shown in FIG. 3, the disclosed asymmetrical double-gate devices
couple the front gate and back gate using a connection 330. The
threshold voltage, V.sub.T, is a function of the fixed back gate
voltage. Thus, the disclosed asymmetrical double-gate devices
cannot be used to provide a variable V.sub.T diode and thereby
control the virtual V.sub.DD or virtual Ground in the integrated
circuit 100 of FIG. 1. A need exists for improved techniques for
variable V.sub.T modulation. A further need exists for techniques
for varying a supply voltage or a reference voltage (or both) using
independently controlled asymmetrical double-gate devices.
SUMMARY OF THE INVENTION
Generally, methods and apparatus are provided for varying one or
more of a supply voltage and reference voltage in an integrated
circuit, using independent control of a diode voltage in an
asymmetrical double-gate device. According to one aspect of the
invention, an integrated circuit is provided that is controlled by
one or more of a supply voltage and a reference voltage. The
integrated circuit comprises an independently controlled
asymmetrical double-gate device to adjust one or more of the supply
voltage and the reference voltage. The independent control may
comprise, for example, a back gate bias. In a pMOS implementation,
the asymmetrical double-gate device comprises a p+ polysilicon gate
for a first gate; and an n+ polysilicon gate for a second gate,
wherein the threshold voltage, V.sub.T, is independently controlled
by a bias of the first or second gates.
According to another aspect of the invention, a plurality of
voltage islands may be provided in an integrated circuit that each
provide a different voltage level. Each voltage island comprises an
independently controlled asymmetrical double-gate device to provide
one of the different voltage levels. According to yet another
aspect of the invention, a power gating circuit is provided that
comprises at least one integrated circuit; and an independently
controlled asymmetrical double-gate device that provides a variable
threshold voltage, V.sub.T. The power gating circuit may also
comprise an asymmetrical double-gate device to serve as a power
switch. The independently controlled asymmetrical double-gate
device of the present invention may also be employed in static RAM
devices having a plurality of memory cells. Each memory cell has an
independently controlled asymmetrical double-gate device that
provides a variable threshold voltage, V.sub.T.
In addition, the adjusted back-gate bias can be employed in a
processing unit to improve power and performance of the processing
unit. A processor unit according to the present invention
comprises: (i) an oscillator; (ii) at least one independently
controlled asymmetrical double-gate device that provides a variable
threshold voltage, V.sub.T; (iii) a phase detector to compare an
output of the oscillator to a reference signal; and (iv) a charge
pump to adjust a back-gate bias of the at least one independently
controlled asymmetrical double-gate device based on the
comparison.
A more complete understanding of the present invention, as well as
further features and advantages of the present invention, will be
obtained by reference to the following detailed description and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of a CMOS circuit;
FIG. 2 is a schematic cross-section of a bulk-Si (or SOI) field
effect transistor;
FIG. 3 is a schematic cross-section of an asymmetrical double-gate
nFET employed by the present invention;
FIG. 4 is a circuit diagram of a CMOS circuit incorporating
features of the present invention;
FIG. 5 illustrates a plurality of voltage islands incorporating one
or more independently controlled asymmetrical double-gate devices
of the present invention;
FIG. 6 illustrates a power gating structure incorporating one or
more independently controlled asymmetrical double-gate devices of
the present invention;
FIG. 7 illustrates the relevant portions of an SRAM incorporating
one or more independently controlled asymmetrical double-gate
devices in each cell according to the present invention;
FIG. 8 illustrates a column based dynamic V.sub.DD scheme for
Read/Write operations in an SRAM using one or more independently
controlled variable diode-drop asymmetrical double-gate devices;
and
FIG. 9 depicts an "on-the-fly" virtual supply regulator that
optimizes the power-performance of a processor unit using the
independently controlled variable diode-drop asymmetrical
double-gate device of the present invention.
DETAILED DESCRIPTION OF PREFERRED EMBODIMENTS
The present invention provides techniques for varying a supply
voltage or a reference voltage using one or more independently
controlled asymmetrical double-gate devices. The present invention
recognizes that the front-channel V.sub.T (and current) of the
asymmetrical double-gate devices can be modulated using independent
control, such as back-gate biasing, through gate-to-gate coupling.
This V.sub.T modulation mechanism is significantly stronger than
the existing well body bias in bulk CMOS and PD/SOI devices, as
discussed above in conjunction with FIG. 2. Furthermore, the effect
improves with device scaling due to stronger gate-to-gate coupling
in thinner film or thinner gate oxides (or both), and the frequency
is only limited by the gate RC, in the same manner as core
logic.
According to one aspect of the invention, a variable threshold
voltage, V.sub.T, is provided using independently controlled
asymmetrical double-gate devices. FIG. 4 is a circuit diagram of a
CMOS circuit 400 incorporating features of the present invention.
As shown in FIG. 4, the CMOS circuit 400 comprises an integrated
circuit 450, such as logic or memory elements, and one or more
asymmetrical double-gate nFET devices 410, for example, associated
with the virtual ground (footer) or virtual supply voltage
(header), or both.
In the exemplary embodiment of FIG. 4, the virtual ground (VGND) is
clamped by the diode connected front gate of an asymmetrical
double-gate nFET device 410 that uses an n+ polysilicon gate for
the front-gate and a p+ polysilicon gate for the back-gate. In
addition, the drain terminal of the asymmetrical double-gate nFET
device 410 is coupled to the front gate, as shown in FIG. 4. The
back gate of the asymmetrical double-gate device 410 is used to
independently control the voltage drop across the MOS diode 420,
using a bias signal, VGND control.
It is noted that the circuit 415 is an equivalent representation of
the asymmetrical double-gate nFET device 410. The diode 420
represents the strong current associated with the front gate of the
asymmetrical double-gate nFET device 410, and the open circuit 430
represents the very small current associated with the back gate of
the asymmetrical double-gate nFET device 410.
Although not shown in FIG. 4, the virtual VDD (VVDD) can also be
clamped by an independently controlled asymmetrical double-gate
pFET device that uses a p+ polysilicon gate for the front-gate and
an n+ polysilicon gate for the back-gate. The back gate of the
asymmetrical double-gate device 410 would be used to independently
control the voltage drop across the MOS diode 420, using a bias
signal, VVDD control.
As previously indicated, the exemplary back-gate biasing of the
asymmetrical double-gate device 410 is used to modulate the
front-gate V.sub.T through gate-to-gate coupling. Since the diode
drop (V.sub.d) is physically associated with V.sub.T and the
V.sub.T modulation effect is significant, the disclosed
independently controlled asymmetrical double-gate devices 410 can
provide a wide range of diode voltage for clamping VGND or VVDD (or
both).
Among other benefits, the disclosed asymmetrical double-gate
devices are scalable as the gate-to-gate coupling effect improves
with device scaling (for thin silicon film and thin gate
dielectric). In addition, the operating frequency is only limited
by the gate RC (in a similar manner to the core logic. The
disclosed asymmetrical double-gate devices are area efficient since
a single device is used for the diode and tuning. Moreover, in
power-gating applications, the diode can also serve as the power
switch, thus further improving the area, density, power, and
performance. The back-gate bias does not increase the junction
leakage, while well-body bias can cause significant increase in
reverse/forward junction leakage and band-to-band tunneling
leakage. Finally, in dynamic V.sub.DD applications, the burden of
charge movement to charge/discharge of voltage rail capacitance is
smaller than that of an equivalent parallel pass gate voltage
switch. As a result, the virtual supply settling time can be
shorter in design.
As discussed hereinafter, the wide tuning range for the diode
voltage makes the present invention useful for the following
applications: (1) Dynamic Von; (2) Voltage islands; (3) Power
gating; (4) Separate V.sub.DD for logic and SRAM; (5) Dynamic
V.sub.DD for SRAM Read/Write (High V.sub.DD for Read, low V.sub.DD
for Write); and (6) Compensation for process variations and V.sub.T
fluctuation.
The present invention is well suited for emerging asymmetrical
double-gate technologies including planar double-gate devices,
FinFETs, and TriGate technologies. The present invention is also
applied to fully depleted SOI devices with back-gating
capability.
Voltage Islands
FIG. 5 illustrates an integrated circuit 500 having a plurality of
voltage islands 510-1 through 510-3 incorporating one or more
independently controlled asymmetrical double-gate devices 520 of
the present invention. As shown in the exemplary embodiment of FIG.
5, individual independently controlled diode-connected asymmetrical
double-gate pFETs 520-1 through 520-3, each with different
back-gate biases, bias I through bias III, are used to provide
different virtual V.sub.DDs for corresponding individual voltage
islands 510-1 through 510-3. For example, each sub-circuit 530-1
through 530-3 may need a different supply voltage, provided by a
corresponding voltage island 510.
Power Gating
FIG. 6 illustrates a power gating structure 600 incorporating one
or more independently controlled asymmetrical double-gate devices
610 of the present invention. The power gating structure 600 of
FIG. 6 improves the speed, relative to the implementation of FIG.
4. Generally, two transistors are employed to provide higher
currents and faster speed. The power switches 605 are embodied as
front gate to back gate coupled asymmetrical double-gate devices
300 (FIG. 3).
In an active mode, the corresponding power switch 605 is ON and the
back gate is ON. The power switch 605 shunts the diode and the
virtual GND is close to GND (and the virtual V.sub.DD is close to
V.sub.DD). In a standby mode, the power switch 605 is OFF, and the
back-gates are biased to provide the proper diode voltages to clamp
the virtual GND and virtual V.sub.DD at the desired levels. It is
noted that due to the capability of wide range diode voltage
provided by the present invention, the power switches 605 can
actually be removed. With the back-gate biased at full V.sub.DD to
the footer or at full "0" to the header, the diode voltage drops
are negligible, and the diodes themselves can serve as the power
switches as well.
Separate V.sub.DD for Logic and SRAM
FIG. 7 illustrates the relevant portions of an SRAM 700
incorporating one or more independently controlled diode-connected
asymmetrical double-gate devices 710 according to the present
invention in one or more cells 720-1 through 720-n. In the
implementation shown in FIG. 7, the independently controlled
diode-connected asymmetrical double-gate devices 710 serve both as
the power switches and the variable diode-voltage clamps. In a
standby mode, the diode voltages can be tuned to maintain adequate
voltage across the cells for state retention and to reduce the
leakage current. FIG. 7 illustrates the levels for VGND control and
the levels for VVDD control would be complementary, as would be
apparent to a person of ordinary skill.
Dynamic V.sub.DD for SRAM Read/Write
According to another aspect of the invention, the disclosed
back-gate controlled variable diode-drop scheme can be applied to a
dynamic Read/Write supply voltage for SRAM. As previously
indicated, for SRAMs in scaled technologies, it is desirable to
have a higher supply voltage during a read operation, to maintain
an adequate noise margin, and a lower supply voltage during a write
operation, to facilitate writing.
FIG. 8 illustrates a column based dynamic V.sub.CC scheme for
Read/Write operations in an SRAM 800 using one or more
independently controlled variable diode-drop asymmetrical
double-gate devices 810. The implementation shown in FIG. 8 has the
following advantages: (a) only one regular supply is required and
the back-gate bias is used to control/change the voltage across the
SRAM cells (conventional techniques require two external power
supplies, or the use of on-chip voltage generator/regulator to
provide the extra supply level); (b) requires only a header diode
or a footer diode (conventional techniques require two pass
transistors to perform the MUX function); (c) it is only necessary
to route either the virtual GND control line or the virtual
V.sub.DD control line (conventional techniques require routing two
supply lines); and (d) the virtual supply control line only needs
to charge/discharge the back-gate capacitance, and the voltage rail
is charged/discharged by the front-gate current. Thus, the virtual
supply settling time is shorter (conventional techniques require
the drain of the pass transistors to be connected directly to the
virtual supply line, hence a large amount of charges have to be
moved to charge/discharge the voltage rail capacitance).
FIG. 9 depicts an "on-the-fly" virtual supply regulator 900 that
optimizes the power-performance of a processing unit 950 using the
back-gate controlled variable diode-drop asymmetrical double-gate
device 910 of the present invention. When a whole processor unit is
gated, an oscillator (OSC) 960 is designed to match the unit cycle
time within a predefined margin. As shown in FIG. 9, the output of
the oscillator 960 goes through a level shifter 920, and is then
compared with a clock signal CLKG through a phase detector 930. If
the output of the oscillator 960 is slower than CLKG, the charge
pump 940 will lower the back-gate bias for the pFET header diode to
speed up the unit. If the output of the oscillator 960 is faster
than CLKG, the charge pump 940 will raise the back-gate bias to
slow it down. Thus, the unit 950 will maintain its required
performance at the lowest supply voltage (hence lowest power).
It is to be understood that the embodiments and variations shown
and described herein are merely illustrative of the principles of
this invention and that various modifications may be implemented by
those skilled in the art without departing from the scope and
spirit of the invention.
* * * * *