U.S. patent number 7,348,261 [Application Number 10/438,947] was granted by the patent office on 2008-03-25 for wafer scale thin film package.
This patent grant is currently assigned to International Business Machines Corporation. Invention is credited to David Vincent Caletka, Seungbae Park, Sanjeev Balwant Sathe.
United States Patent |
7,348,261 |
Caletka , et al. |
March 25, 2008 |
Wafer scale thin film package
Abstract
A chip module having a chip with a flexible multilayer
redistribution thin film attached thereto for connection to a
substrate. The thin film acts as both a redistribution medium with
multiple layers of redistribution metallurgy for chip power and
signals and as a compliant medium to relieve stresses caused by
thermal expansion mismatch between chip and substrate. Modules
comprising chip and thin film may be fabricated at the chip or
wafer level. The upper surface of the thin film has an array of
pads matching the array of pads on the chip or wafer while the
lower surface has pads matching those of the substrate. The
multilayer thin film is first formed on a temporary substrate and
then the chip is attached to the thin film before release from the
temporary substrate. After release, the module is ready for
mounting to the second level packaging substrate, such as a chip
carrier or PCB. Where the multilayer thin film is formed directly
on a wafer, the wafer is then diced to form the module.
Inventors: |
Caletka; David Vincent
(Apalachin, NY), Park; Seungbae (Fishkill, NY), Sathe;
Sanjeev Balwant (Binghamton, NY) |
Assignee: |
International Business Machines
Corporation (Armonk, NY)
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Family
ID: |
28455097 |
Appl.
No.: |
10/438,947 |
Filed: |
May 15, 2003 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20030199121 A1 |
Oct 23, 2003 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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09626904 |
Jul 27, 2000 |
6627998 |
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Current U.S.
Class: |
438/459;
257/E23.146; 257/E21.503; 438/690; 438/759; 438/977; 438/940;
438/464 |
Current CPC
Class: |
H01L
24/29 (20130101); H01L 25/0655 (20130101); H01L
23/525 (20130101); H01L 24/32 (20130101); H01L
24/81 (20130101); H01L 21/563 (20130101); H01L
23/3114 (20130101); H01L 25/50 (20130101); H05K
3/3436 (20130101); H01L 2924/014 (20130101); H01L
2224/73203 (20130101); Y02P 70/50 (20151101); H01L
2224/0231 (20130101); H01L 24/16 (20130101); H01L
2224/81801 (20130101); H01L 2924/1579 (20130101); H01L
2924/01076 (20130101); H05K 2201/2036 (20130101); H01L
2924/0132 (20130101); H01L 2924/01322 (20130101); H01L
2924/01033 (20130101); H01L 2224/29299 (20130101); H01L
2224/29 (20130101); H01L 2224/29101 (20130101); H01L
2924/01005 (20130101); H01L 2924/01078 (20130101); H01L
2924/15787 (20130101); H01L 2224/2929 (20130101); H01L
2224/10122 (20130101); H01L 2224/11001 (20130101); H01L
2924/00013 (20130101); H01L 2924/0665 (20130101); Y10S
438/977 (20130101); H01L 2224/29011 (20130101); H01L
2924/01006 (20130101); H01L 2224/02333 (20130101); H01L
2924/00011 (20130101); H01L 2224/16225 (20130101); H01L
2224/83101 (20130101); H01L 2924/12042 (20130101); H01L
2924/30107 (20130101); H01L 2224/0401 (20130101); H01L
2924/15311 (20130101); H05K 2201/10977 (20130101); H01L
2924/0101 (20130101); Y02P 70/613 (20151101); H01L
2924/10253 (20130101); H01L 2224/02319 (20130101); H01L
2224/16111 (20130101); H01L 2224/83194 (20130101); H01L
2924/01029 (20130101); Y10S 438/94 (20130101); H01L
2224/81192 (20130101); H01L 2224/2919 (20130101); H01L
2924/01039 (20130101); H01L 2224/29111 (20130101); H01L
2224/73103 (20130101); H01L 2224/81138 (20130101); H01L
2924/0133 (20130101); H01L 2924/0665 (20130101); H01L
2924/00 (20130101); H01L 2924/0133 (20130101); H01L
2924/01029 (20130101); H01L 2924/01047 (20130101); H01L
2924/0105 (20130101); H01L 2924/0133 (20130101); H01L
2924/01047 (20130101); H01L 2924/0105 (20130101); H01L
2924/01083 (20130101); H01L 2924/0132 (20130101); H01L
2924/0105 (20130101); H01L 2924/01082 (20130101); H01L
2224/2919 (20130101); H01L 2924/0665 (20130101); H01L
2924/00014 (20130101); H01L 2224/13111 (20130101); H01L
2924/01082 (20130101); H01L 2924/00014 (20130101); H01L
2224/13111 (20130101); H01L 2924/01029 (20130101); H01L
2924/01047 (20130101); H01L 2924/00014 (20130101); H01L
2224/2929 (20130101); H01L 2924/0665 (20130101); H01L
2924/00014 (20130101); H01L 2224/29299 (20130101); H01L
2924/00014 (20130101); H01L 2224/13111 (20130101); H01L
2924/01047 (20130101); H01L 2924/01083 (20130101); H01L
2924/00014 (20130101); H01L 2924/00013 (20130101); H01L
2224/29099 (20130101); H01L 2924/00013 (20130101); H01L
2224/29199 (20130101); H01L 2924/00013 (20130101); H01L
2224/29299 (20130101); H01L 2924/00013 (20130101); H01L
2224/2929 (20130101); H01L 2924/10253 (20130101); H01L
2924/00 (20130101); H01L 2924/12042 (20130101); H01L
2924/00 (20130101); H01L 2224/73103 (20130101); H01L
2924/00012 (20130101); H01L 2224/73203 (20130101); H01L
2924/00012 (20130101); H01L 2924/00011 (20130101); H01L
2224/81805 (20130101) |
Current International
Class: |
H01L
21/30 (20060101); H01L 21/46 (20060101); H01L
21/469 (20060101) |
Field of
Search: |
;438/459,464,690,759,940,977,FOR405,FOR485 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
Primary Examiner: Graybill; David E
Attorney, Agent or Firm: Jordan; John A. Steinberg; William
H.
Parent Case Text
This is a divisional application of prior application Ser. No.,
09/626,904 filed Jul. 27, 2000 now U.S. Pat. No. 6,627,998.
Claims
What is claimed is:
1. A method of forming a chip module comprising: providing a chip
having an array of conductive pads; providing a temporary glass
substrate; forming conductive pads on said temporary glass
substrate positioned for connection to a packaging substrate for
said chip module; providing a flexible redistribution thin film
having first and second surfaces and having multiple layers of
redistribution metallurgy with said flexible redistribution thin
film formed on said temporary glass substrate so that said first
surface is positioned on said glass substrate with said conductive
pads formed thereon and said second surface is exposed; forming an
array of conductive pads on said exposed second surface of said
flexible redistribution thin film matching the array of conductive
pads on said chip; attaching respective ones of said array of
conductive pads on said chip to respective ones of said array of
conductive pads on said exposed second surface of said flexible
redistribution thin film by solder ball connections so as to form
an array of solder ball connections each having space between it
and adjacent solder ball connections and filling said space between
said solder ball connections with an epoxy before removal from said
temporary substrate; and removing by laser ablation said flexible
redistribution thin film and chip from said temporary glass
substrate to thereby expose said first surface of said flexible
redistribution thin film with said first surface having included
thereon said conductive pads formed on said glass substrate.
2. The method as set forth in claim 1 wherein conductive pads for
connection to a packaging substrate are formed on said first
surface of said flexible redistribution thin film after said step
of removing.
3. The method of claim 1 wherein said temporary glass substrate is
a temporary borosilicate glass substrate.
4. The method as set forth in claim 1 wherein said laser in said
step of removing by laser ablation is a 308 nm excimer laser.
5. The method as set forth in claim 1 wherein said thin film
comprises alternate layers of polyimide and circuitry to provide
both a redistribution medium for signal and power redistribution
from chip to said packaging substrate and a compliant medium to
provide relief to stress on electrical connections caused by
thermal mismatch between chip and said packaging substrate.
6. A method of forming a chip module comprising: providing a chip
having an array of conductive pads; providing a temporary glass
substrate; forming conductive pads on said temporary glass
substrate positioned for connection to a packaging substrate for
said chip module; providing a flexible redistribution thin film
having first and second surfaces separating alternate layers of
polyimide and circuitry to provide both a redistribution medium for
signal and power redistribution from said chip to said packaging
substrate and a compliant medium for stress relief caused by
thermal mismatch between said chip and said packaging substrate
with said flexible redistribution thin film formed on said
temporary glass substrate so that said first surface is positioned
on said glass substrate with said conductive pads formed thereon
and said second surface is exposed; forming an array of conductive
pads on said exposed second surface of said flexible redistribution
thin film matching the array of conductive pads on said chip;
attaching respective ones of said array of conductive pads on said
chip to respective ones of said array of conductive pads on said
exposed second surface of said flexible redistribution thin film by
solder ball connections so as to form an array of solder ball
connections each having space between it and adjacent solder ball
connections and filling said space between said solder ball
connections with an epoxy before removal from said temporary
substrate; and removing by laser ablation said flexible
redistribution thin film and chip from said temporary glass
substrate to thereby expose said first surface of said flexible
redistribution thin film with said first surface having included
thereon said conductive pads formed on said glass substrate.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to electronic packaging and methods
of fabricating same. More particularly, the present invention
relates to semiconductor chip packaging using a multilayer thin
film for chip attachment to a substrate.
2. Background and Related Art
Ever increasing industry demand for smaller and smaller electronic
packages with low profile, higher area density and increasing
number of input/output connections (I/Os) has led to increasing
demand for the Chip Scale Package (CSP). Use of such packages may
be found in small portable products, such as cellular phones,
pagers, and the like. However, it is known that CSPs have somewhat
limited applications because of the limited number of I/Os due to
solder interconnect reliability constraints. As feature sizes of
the semiconductor chip packages decrease, as in the case of CSPs,
and the I/O connection count increases, so too will the number of
chips packaged in a given area. This will increase the heat
dissipated by each of the chips which will, in turn, increase the
thermal mismatch stresses between chip and substrate, the latter of
which will decrease the interconnect reliability of the package.
Various efforts have been made in the prior art to address the
thermal mismatch problem. In addition, various efforts have been
made to improve interconnect reliability and reduce cost by, for
example, fabricating CSPs at the wafer level. However, these
efforts have not been totally successful and have involved
relatively complex and costly assemblies with limited
capability.
In view of the limitations of prior art chip packaging mentioned
hereinabove, there continues a need for a relatively simple, low
profile, high density, chip packaging approach which has high
interconnect reliability and high I/O connection count, and which
may use relatively low-cost wafer scale processing.
SUMMARY OF THE INVENTION
In accordance with the principles of the present invention, a
relatively simple chip packaging approach is provided using
multilayer thin film technology. The flexible thin film acts as
both a redistribution layer and a stress relief layer between chip
and second level interconnect substrate. More particularly, the
flexible multilayer thin film acts to provide multiple layers of
redistribution metallurgy for both power and signals in the X-Y
plane (e.g. fanout or grid change) and also provides sufficient
flexibility to connections in both the Z-direction and X-Y plane to
relieve stresses caused by the thermal expansion mismatch between
semiconductor chip and second level interconnect substrate, such
as, a PCB.
The flexible multilayer thin film is first mounted on either a
silicon die or wafer. The upper surface of the thin film has an
array of pads matching the array of pads on the die or wafer while
the lower surface has pads matching those of the second level
interconnect substrate. The mounting of the multilayer thin film on
a die creates a module for mounting to the second level substrate,
such as a chip carrier or PCB. Where the multilayer thin film is
formed directly on a wafer, the wafer is then diced to form the
modules.
Accordingly, it is an object of the present invention to provide an
improved semiconductor chip package and method for making same.
It is a further object of the present invention to provide a chip
package having a flexible multilayer redistribution thin film
attached thereto to form a low profile, low vertical inductance,
module.
It is yet a further object of the present invention to provide a
chip module comprising a flexible multilayer thin film attached to
the chip which thin film acts as both a redistribution medium and
stress relief medium between chip and next level of packaging.
It is another object of the present invention to provide a chip
module formed by fabricating a flexible multilayer redistribution
thin film on a wafer before dicing.
It is yet another object of the present invention to provide a chip
package and method of making same which acts to increase
interconnection reliability and I/O count and provide simple, low
cost, assembly.
These foregoing and other objects, features and advantages of the
invention will be apparent from the following more particular
description of a preferred embodiment of the invention, as
illustrated in the accompanying drawings, wherein like reference
members represent like parts of the invention.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 shows a cross-section of a partially assembled chip module,
made in accordance with the present invention.
FIG. 2 shows a cross-section of a partially assembled chip package
made in accordance with the present invention.
FIG. 3a shows a cross-section of an assembled chip package, made in
accordance with the present invention.
FIG. 3b shows an exploded view of a portion of the chip package
shown in FIG. 3a.
FIG. 4 shows a cross-sectional view of an alternative embodiment of
the chip package shown in FIG. 3a.
FIG. 5 shows another embodiment of the chip package in accordance
with the present invention.
FIG. 6a shows a further embodiment wherein the flexible multilayer
redistribution thin film is first fabricated on a wafer.
FIG. 6b shows a cross-section of the thin-film-on-wafer of FIG.
6a.
FIG. 6c shows an exploded view of the cross-section of FIG. 6b.
DETAILED DESCRIPTION
With reference to FIG. 1, there is shown a cross-sectional view of
a partially assembled chip module which view is used to facilitate
a description of the process for creating the flexible multilayer
redistribution thin film and attaching to a chip, in accordance
with the present invention. Multilayer thin film 1 is first formed
upon master glass substrate 3. The thin film may be formed by any
of a variety of thin film lithography techniques known to those
skilled in the art.
Fabrication of the thin film structure using conventional
lithographic processing steps necessarily begins with selecting a
flat, rigid substrate to ensure good feature resolution. For ease
of removal of the thin film after completion of its formation,
glass has been selected. To reduce thermal expansion mismatch
between the chip and glass substrate 3, a borosilicate glass with a
CTE similar to silicon is selected, such as that sold under the
Trademark BOROFLOAT. The glass surface for deposit may first be
cleaned and then a thin release layer 8 microns thick is deposited.
The release layer (not shown) is typically the same material as is
used to form the thin film structure and may be deposited by
spinning onto glass substrate 3. For example, a polymer, such as,
polyimide may be used. The polymer release layer is then properly
cured. Pads 5 may then be formed on the substrate or,
alternatively, formed after the module is completed. Where pads 5
are formed at this point, they are formed in a pattern matching the
pattern of the second level package to which it is to be attached.
The pads may be BGA pads, for example, formed by sputtering or
electroplating, for example, 10-20 microns of metal, such as
copper.
A first layer of polyimide or other polymer, such as, a filled
PTFE, or a polymer material sold under the trademark [Teflon.RTM.,
Teflon.RTM. is a registered trademark of E.I. du Pont de Nemours
& Company)] TEFLON, 10-11 microns thick is then spun onto the
release layer with or without pads, depending upon process choice.
A pattern of vias selected according to the pattern of pads formed
on the glass substrate matching the pads on the second level
package to which it will be attached, is then ablated by laser
ablation into the first layer of polyimide. The vias are then
filled with conductive material to the underlying pads. This may be
done by electroplating copper to the copper pads or filling with an
electrically conductive adhesive. It is clear that other metals may
also be used instead of copper. Where pads have not yet been
formed, the vias may be electrolessly plated with copper.
A layer of copper is then deposited on the first layer of polyimide
and in contact with the conductively filled vias. The layer of
copper may be 5-6 microns thick and can be electroplated. The layer
of copper is then masked with a layer of resist according to the
selected metallurgical pattern of the overall redistribution
pattern to leave copper lines contacting selected vias. The layer
of copper is then etched, for example, by reactive ion etching.
Then a second layer of polyimide is deposited upon the first layer
of polyimide and copper lines. A pattern of vias is then ablated
into the second layer of polyimide at selected locations to the
underlying copper lines and the vias are plated with copper.
Another layer of copper is then deposited upon the second layer of
polyimide and copper plated vias. The second layer of copper is
etched according to the desired metallurgical pattern and the
process repeats until the overall redistribution pattern is
achieved.
When the final layer of polyimide is formed, the pattern of metal
filled vias is selected to match the pattern of conductive pads
(not shown) on chip 7. Pads are then formed on these vias. Such pad
may be, for example, C4 pads. FIG. 3b shows a typical 3 level
redistribution thin film. It is clear that any desired number of
layers of polyimide and metal may be employed, depending upon the
complexity of the redistribution pattern. It is also clear that any
of a variety of deposition and etching techniques may be employed
to form the layers of material, vias and metallurgical
patterns.
Again, with reference to FIG. 1, after forming the multilayer
redistribution thin film on substrate 3 with a pattern of C4 pads
on its top surface matching the pattern of pads on chip 7, high
melt C4 solder balls 9, for example, are attached to the pads, as
shown. Chip 7 is then positioned and attached by C4 melting of the
high melt solder, as is known to those skilled in the art. Other
alloy systems may also be used in place of the high melt solder,
such as, eutectic SnPb, SnAgCu or SnAgBi. After attaching chip 7 to
thin film 1, the chip is underfilled with any of a variety of
underfills, such as an epoxy, to bond chip 7 to thin film 1. The
epoxy may be with or without fillers. Examples of such epoxies are
epoxies sold under the trademarks HYSOL, NAMICS [Hysol, Namics] and
RCE. The underfill step may be carried out by dispensing with a
dispensing needle from the edge of the chip where the epoxy will
penetrate by capillary action.
After the underfill step, the resulting module comprising chip 7
and thin film 1 is separated from glass substrate 3. This may be
done by laser ablation, such as, with a 308 nm excimer laser. The
detached surface of the module is then cleaned by etching, and if
pads have not been previously formed, to prepare for the formation
of the BGA pads. These pads may be formed, for example, by ablating
a pattern of recesses for the pad areas and then plating therein a
10-20 micron layer of copper, according to the underlying pattern
of vias matching the second level package to which it will be
connected.
After separation from glass substrate 3, the resulting module 11
(with chip, C4-s, underfill, thin film and BGA pads) as shown in
FIG. 2, is attached to a second level package, such as, PCB 13. PCB
13 is shown, for example, with an array of low temperature melt
solder balls 15 matching pads 5 on module 11, as hereinabove
described. Solder balls 15 are formed on BGA pads 16. As described
above, other alloy systems may also be used in place of the low
melt solder, such as, eutectic SnPb, SnAgCu or SnAgBi. Spacer 17 is
used for alignment and reinforcement. Examples of such spacers are
layers of material sold under the trademarks KAPTON or EKJ
[DuPont.RTM. or Kapton.RTM., Kapton.RTM. is a registered trademark
of E.I du Pont de Nemours & Company], 150-200 microns thick
punched or drilled with holes for aligning solder balls 15 to pads
5. The spacer not only acts to align but also acts to provide
stress relief to the solder ball interconnections by redistributing
stress due to thermal expansion mismatch. The spacer may be joined
to the thin film redistribution layer and PCB by either a
thermoplastic adhesive or adhesive tape. After alignment, the low
temperature melt solder is heated to reflow the solder and make
connection of chip module to PCB. It is clear that rather than use
a spacer to align module 11 to PCB 13, module 11 may be otherwise
aligned in contact with solder balls 15 and heated to form the
connection, and then a reworkable underfill dispensed to support
the connection.
The resulting assembled package is shown in FIG. 3a. An expanded
view of a portion of FIG. 3a is shown in FIG. 3b. C4 connections 21
in FIG. 3b are shown separated by underfill 19. For demonstration
purposes, a 3 level thin film is shown with via filled conductors
23 and layers of metallurgy 25 between the three layers of
polyimide 27. It is clear that more than 3 levels of thin film may
be employed, depending upon the degree of redistribution required.
Spacer 17 surrounds solder connection 29, the latter making contact
with BGA pads 5 of module 11 and pads 16 of PCB 13. Although
reference has been made to mounting module 11 on a PCB, it is clear
that other carriers may be used, such as an organic or ceramic
carrier.
FIG. 4 shows an alternative embodiment of the chip package shown in
FIG. 3a. As can be seen, 2 modules 11 are mounted on PCB 13. It is
clear that more than 2 modules could be mounted on the PCB.
FIG. 5 shows a further embodiment where the carrier 31 for modules
11 is a substrate mounted on PCB 13. Carrier 31 may be an organic
or ceramic carrier.
With reference to FIG. 6, there is shown a further embodiment
wherein the flexible multilayer redistribution film is first
fabricated on a wafer. FIG. 6a shows a front view of a wafer upon
which individual chip multilayer redistribution thin film 33
patterns are formed. The individual patterns of thin film 33 for
each chip are as described above, for purposes of redistribution of
power and signal or grid change in the X-Y plane (parallel to the
chip). FIG. 6b shows a cross-section of FIG. 6a wherein the
individual chip patterns 33 of the overall thin film layer 34 are
shown respectively formed directly on the array of chips of wafer
35. FIG. 6c shows an exploded view of FIG. 6b with BGA pads 37
shown on the final layer of an individual chip multilayer
redistribution thin film. Metallurgical pattern 39 and vias 41, at
the cross-section taken, are shown by way of example.
Fabrication of the overall multilayer thin film on wafer 35 is
similar to that described above for fabrication of the chip level.
However, it is clear that via, masking and etching patterns for the
individual chip multilayer redistribution thin films 33 may vary,
one from the other, or may be the same throughout the wafer.
Fabrication directly on wafer 35 begins by spinning, for example, a
layer of polyimide 10 to 11 microns thick onto the wafer covering
the array of chips connection pads (not shown) on the wafer. Vias
are then ablated in the polyimide to expose the array of chip
connection pads. The vias are filled by electroplating, for
example, to the chip pads to form conductive columns 41. Typically,
copper would be plated to copper pads. Next, a layer of copper is
deposited upon the layer of polyimide and copper filled vias and
the process continues, as described above, to form layers of metal
39 of the multilayer metallurgical redistribution pattern. The
final layer of polyimide is fabricated with a pattern of vias on
the individual chip multilayer redistribution thin film matching
the pattern of pads on the PCB to which it will be attached. As a
final step in fabricating at the wafer level to form a wafer scale
package, a pattern of BGA pads 37 is formed on the vias which
pattern, then, matches the pattern of PCB pads. The wafer may then
be diced using conventional dicing techniques, as is known to those
skilled in the art. The resulting module, comprising chip and
flexible multilayer redistribution thin film may then be attached
to a carrier in the variety of way described above. It should be
noted that whether the flexible multilayer redistribution thin film
module is formed at the wafer level, as described with respect to
FIG. 6, or at the chip level, as described with respect to FIG. 1,
the resulting thin film of the module can be made, dimensionally,
to an area the same size as the chip area to which it is
attached.
It will be understood from the foregoing description that various
modifications and changes may be made in the preferred embodiment
of the present invention without departing from its true spirit. It
is intended that this description is for purposes of illustration
only and should not be construed in a limiting sense. The scope of
this invention should be limited only by the language of the
following claims.
* * * * *