U.S. patent number 7,082,071 [Application Number 10/881,022] was granted by the patent office on 2006-07-25 for integrated ddr/sdr flow control managers that support multiple queues and mux, demux and broadcast operating modes.
This patent grant is currently assigned to Integrated Device Technology, Inc.. Invention is credited to Mario Au, Srinivas Satish Babu Bamdhamravuri, David Stuart Gibson, Uksong Kang, Roland T. Knaack, Mario Montana, Stewart Speed.
United States Patent |
7,082,071 |
Knaack , et al. |
July 25, 2006 |
Integrated DDR/SDR flow control managers that support multiple
queues and MUX, DEMUX and broadcast operating modes
Abstract
An integrated circuit chip includes a plurality of independent
FIFO memory devices that are each configured to support all four
combinations of DDR and SDR write modes and DDR and SDR read modes
and collectively configured to support all four multiplexer,
demultiplexer, broadcast and multi-Q operating modes.
Inventors: |
Knaack; Roland T. (Duluth,
GA), Gibson; David Stuart (Suwanee, GA), Montana;
Mario (Los Gatos, CA), Au; Mario (Fremont, CA),
Speed; Stewart (Sunnyvale, CA), Bamdhamravuri; Srinivas
Satish Babu (Duluth, GA), Kang; Uksong (Duluth, GA) |
Assignee: |
Integrated Device Technology,
Inc. (San Jose, CA)
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Family
ID: |
34084819 |
Appl.
No.: |
10/881,022 |
Filed: |
June 30, 2004 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20050018514 A1 |
Jan 27, 2005 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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10459224 |
Jun 11, 2003 |
6778454 |
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09972265 |
Oct 5, 2001 |
6795360 |
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60532090 |
Dec 23, 2003 |
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60495907 |
Aug 18, 2003 |
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60314393 |
Aug 23, 2001 |
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Current U.S.
Class: |
365/221; 365/191;
365/233.13 |
Current CPC
Class: |
G06F
5/06 (20130101) |
Current International
Class: |
G11C
7/00 (20060101) |
Field of
Search: |
;365/221O,191X,233X
;711/104 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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0 421 627 |
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Sep 1990 |
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EP |
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0 978 842 |
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Feb 2000 |
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EP |
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08202618 |
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Aug 1996 |
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JP |
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Other References
Invitation to Pay Additional Fees, Annex to Form PCT/ISA/206,
Communication Relating to the Results of the Partial International
Search, PCT/US02/26516, Oct. 13, 2003. cited by other.
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Primary Examiner: Nguyen; VanThu
Attorney, Agent or Firm: Myers Bigel Sibley & Sajovec
PA
Parent Case Text
REFERENCE TO PRIORITY APPLICATION
This application is a continuation-in-part (CIP) of U.S.
application Ser. No. 10/459,224, filed Jun. 11, 2003, now U.S. Pat.
No. 6,778,454, which is a continuation of U.S application Ser. No.
09/972,265, filed Oct. 5, 2001, now U.S. Pat. No. 6,795,360, which
derives priority from U.S. Provisional Application Ser. No.
60/314,393, filed Aug. 23, 2001. This application also derives
priority from U.S. Provisional Application Ser. No. 60/532,090,
filed Dec. 23, 2003 and U.S. Provisional Application Ser. No.
60/495,907, filed Aug. 18, 2003. The disclosures of all these
applications are hereby incorporated herein by reference.
Claims
That which is claimed is:
1. An integrated circuit chip, comprising: a plurality of first-in
first-out (FIFO) memory devices that are each configured to support
all four combinations of DDR and SDR write modes and DDR and SDR
read modes and collectively configured to support at least three of
the following multi-FIFO operating modes: multiplexer,
demultiplexer, broadcast and multi-queue.
2. The integrated circuit chip of claim 1, wherein at least two of
the FIFO memory devices are configured to operate independently of
each other with separate read and write clock control when the
integrated circuit chip is disposed in a dual or higher FIFO
mode.
3. The integrated circuit chip of claim 1, wherein said plurality
of first-in first-out (FIFO) memory devices are collectively
configured to support all four multiplexer, demultiplexer,
broadcast and multi-queue operating modes.
4. The integrated circuit chip of claim 2, further comprising a
write clock generator that is configured to receive at least four
external write clock signals and distribute them as at least four
internal write clock signals when the integrated circuit chip is
disposed in a quad or higher FIFO mode.
5. The integrated circuit chip of claim 1, wherein each of said
plurality of FIFO memory devices is associated with a corresponding
plurality of pairs of global write I/O lines and a corresponding
plurality of pairs of global read I/O lines that are independent
from the corresponding plurality of pairs of global write I/O
lines.
6. The integrated circuit chip of claim 1, wherein each of said
plurality of FIFO memory devices comprises a plurality of memory
arrays therein that are accessed one-at-a-time when the respective
FIFO memory device is being written to.
7. The integrated circuit chip of claim 1, further comprising a
data input bus having x8N pairs of differential signal lines that
are configured to support either two x2N input data ports or four
xN input data ports.
8. The integrated circuit chip of claim 7, wherein the data input
bus comprises a plurality of pairs of differential data input (DIN)
signal lines that are shielded from each other over at least a
majority of their length.
9. The integrated circuit chip of claim 1, wherein said plurality
of FIFO memory devices have write data paths that share a
differential data input bus.
10. The integrated circuit chip of claim 1, wherein said plurality
of FIFO memory devices have write data paths that share a
differential data input bus; and wherein a first one of said
plurality of FIFO memory devices comprises a first write I/O
control circuit that is electrically coupled to the differential
data input bus by a first N:1 multiplexer, where N is an integer
greater than four.
11. The integrated circuit chip of claim 10, wherein said plurality
of FIFO memory devices have read data paths that share a
differential data output bus; and wherein a first one of said
plurality of FIFO memory devices comprises a first read I/O control
circuit that is electrically coupled to the differential data
output bus by a first 1:N multiplexer.
Description
FIELD OF THE INVENTION
The present invention relates to integrated circuit memory devices
and, more particularly, to first-in first-out (FIFO) memory
devices.
BACKGROUND OF THE INVENTION
Semiconductor memory devices can typically be classified on the
basis of memory functionality, data access patterns and the nature
of the data storage mechanism. For example, distinctions are
typically made between read-only memory (ROM) devices and
read-write memory (RWM) devices. The RWM devices typically have the
advantage of offering both read and write functionality with
comparable data access times. Typically, in RWM devices, data can
be stored in flip-flops for "static" memory devices or as preset
levels of charge on a capacitor in "dynamic" memory devices. As
will be understood by those skilled in the art, static memory
devices retain their data as long as a supply of power is
maintained, however, dynamic memory devices require periodic data
refreshing to compensate for potential charge leakage. Because RWM
devices use active circuitry to store data, they belong to a class
of memory devices known as "volatile" memory devices because data
stored therein will be lost upon termination of the power supply.
ROM devices, on the other hand, may encode data into circuit
topology (e.g., by blowing fuses, removing diodes, etc.). Because
this latter type of data storage may be hardwired, the data cannot
be modified, but can only be read. ROM devices also typically
belong to a class of memory devices known as "nonvolatile" memory
devices because data stored therein will typically not be lost upon
termination of the power supply. Other types of memory devices
include nonvolatile read-write (NVRWM) memory devices. These types
of nonvolatile memory devices may operate as erasable programmable
read-only memory (EPROM) devices, electrically erasable
programmable read-only memory (E.sup.2PROM) devices and flash
memory devices, for example.
An additional memory classification is typically based on the order
in which data can be accessed. Here, most memory devices belong to
the random-access class, which means that memory locations can be
read from or written to in random order. Notwithstanding the fact
that most memory devices provide random-access, typically only
random-access RWM memories use the acronym RAM. Alternatively,
memory devices may restrict the order of data access to achieve
shorter data access times, reduce layout area and/or provide
specialized functionality. Examples of such specialized memory
devices include buffer memory devices such as first-in first-out
(FIFO) memory devices, last-in first-out (LIFO or "stack") memory
devices, shift registers and content-addressable memory (CAM)
devices.
A final classification of semiconductor memories is based on the
number of data input and data output ports associated with the
memory cells therein. For example, although most memory devices
have unit cells therein that provide only a single port, which is
shared to provide an input and output path for transfer of data,
memory devices with higher bandwidth requirements often have cells
therein with multiple input and output ports. However, the addition
of ports to unit memory cells typically increases the complexity
and layout area requirements for these higher bandwidth memory
devices.
Single-port memory devices are typically made using static RAM
cells if fast data access times are a requirement, and dynamic RAM
cells if low cost is a primary requirement. Many FIFO memory
devices use dual-port RAM based designs with self-incrementing
internal read and write pointers to achieve fast fall-through
capability. As will be understood by those skilled in the art,
fall-through capability is typically measured as the time elapsing
between the end of a write cycle into a previously empty FIFO and
the time an operation to read that data may begin. Exemplary FIFO
memory devices are more fully described and illustrated at section
2.2.7 of a textbook by A. K. Sharma entitled "Semiconductor
Memories: Technology, Testing and Reliability", IEEE Press
(1997).
In particular, dual-port SRAM-based FIFOs typically utilize
separate read and write pointers to advantageously allow read and
write operations to occur independently of each other and achieve
fast fall-through capability as data written into a dual-port SRAM
FIFO can be immediately accessed for reading. Since these read and
write operations may occur independently, independent read and
write clocks having different frequencies may be provided to enable
the FIFO to act as a buffer between peripheral devices operating at
different rates. Unfortunately, a major disadvantage of typical
dual-port SRAM-based FIFOs is the relatively large unit cell size
for each dual-port SRAM cell therein. Thus, for a given
semiconductor chip size, dual-port buffer memory devices typically
provide less memory capacity relative to single-port buffer memory
devices. For example, using a standard DRAM cell as a reference
unit cell consuming one (1) unit of area, a single-port SRAM unit
cell typically may consume four (4) units of area and a dual-port
SRAM unit cell typically may consume sixteen (16) units of area.
Moreover, the relatively large unit cells of a dual-port SRAM FIFO
limit the degree to which the number of write operations can exceed
the number of read operations before the FIFO becomes full.
To address these limitations of dual-port buffer memory devices,
single-port buffer memory devices have been developed to, among
other things, achieve higher data capacities for a given
semiconductor chip size. For example, U.S. Pat. No. 5,546,347 to Ko
et al. entitled "Interleaving Architecture And Method For A High
Density FIFO", assigned to the present assignee, discloses a memory
device that has high capacity and uses relatively small single-port
memory cells. However, the use of only single port memory cells
typically precludes simultaneous read and write access to data in
the same memory cell, which means that single-port buffer memory
devices typically have slower fall-through time than comparable
dual-port memory devices. Moreover, single-port buffer memory
devices may use complicated arbitration hardware to control
sequencing and queuing of reading and writing operations.
U.S. Pat. No. 5,371,708 to Kobayashi also discloses a FIFO memory
device containing a single-port memory array, a read data register
for holding read data from the memory array and a write data
register for holding data to be written into the memory array. A
bypass switch is also provided for transferring data from the write
data register to the read data register so that the memory array
can be bypassed during testing of the FIFO to detect the presence
of defects therein. However, like the above-described single-port
buffer memory devices, simultaneous read and write access to data
is not feasible.
Commonly assigned U.S. Pat. Nos. 5,978,307, 5,982,700 and 5,998,478
disclose FIFO memory devices having generally fast fall-through
capability. These memory buffers contain a tri-port memory array of
moderate capacity having nonlinear columns of tri-port cells
therein, which collectively form four separate registers, and a
substantially larger capacity supplemental memory array (e.g., DRAM
array) having cells therein with reduced unit cell size. The
tri-port memory array has a read port, a write port and a
bidirectional input/output port. The tri-port memory array
communicates internally with the supplemental memory array via the
bidirectional input/output port and communicates with external
devices (e.g., peripheral devices) via the read and write data
ports. Efficient steering circuitry is also provided by a
bidirectional crosspoint switch that electrically couples terminals
(lines IO and IOB) of the bidirectional input/output port in
parallel to bit lines (BL and BLB) in the supplemental memory array
during a write-to-memory time interval and vice versa during a
read-from-memory time interval.
U.S. Pat. Nos. 6,240,031, 6,377,071 and 6,400,642, which are
related and commonly assigned to Cypress Semiconductor Corp.,
disclose a pair of FIFOs that are configured to operate internally
in a ping-pong fashion during read and write cycles. Each FIFO in
the pair operates at half the frequency of an external clock in
order to provide DDR read functions and DDR write functions. U.S.
Pat. No. 6,134,180 to Kim et al. discloses a synchronous random
access memory (RAM) device that supports burst write operations and
burst read operations at single and dual data rates. However,
unlike a FIFO memory device, the RAM device disclosed in the '180
patent does not support write and read operations to and from a
memory core during overlapping time intervals.
Notwithstanding the above described memory devices, there still
exists a need to develop higher speed FIFO memory devices having
expanded functionality and increased data capacity. There also
exists a need for FIFO memory devices that provide faster data
transfer for such applications as network, video,
telecommunications and data communications.
SUMMARY OF THE INVENTION
First-in first-out (FIFO) memory devices according to first
embodiments of the present invention include a plurality of memory
devices that are configured to support any combination of dual data
rate (DDR) or single data rate (SDR) write modes, which operate
in-sync with a write clock signal (WCLK), and DDR or SDR read
modes, which operate in-sync with a read clock signal (RCLK). These
FIFO memory devices also provide flexible x4N, x2N and xN bus
matching on both read and write ports and enable data to be written
and read on both rising and falling edges of the write and read
clock signals. These FIFO memory devices represent a significant
alternative to increasing data rate without extending the width of
input or output busses or the internal speed of the devices. They
are also effective in applications that require buffering large
amounts of data and matching busses of unequal sizes. Custom flag
generation and retransmit circuitry is also provided that can
efficiently handle any combination of DDR and SDR read and write
modes.
These FIFO memory devices may include write control circuitry that
provides the plurality of memory devices with write data in-sync
with rising and falling edges of the write clock signal when the
FIFO memory device is disposed in the DDR write mode. Likewise,
read control circuitry may be included that receives read data from
the plurality of memory devices in-sync with rising and falling
edges of the read clock signal when the FIFO memory device is
disposed in the DDR read mode. The write control circuitry may also
be configured to provide the plurality of memory devices with write
data in-sync with leading edges of the write clock signal when the
FIFO memory device is disposed in a single data rate (SDR) write
mode. The read control circuitry may be configured to receive read
data from the plurality of memory devices in-sync with leading
edges of the read clock signal when the FIFO memory device is
disposed in a single data rate (SDR) read mode.
According to one aspect of these first embodiments, the plurality
of memory devices may include first and second memory devices that,
during the DDR write mode, receive write data in an alternating
back-and-forth sequence on alternating rising and falling edges of
the write clock signal. These first and second memory devices may
also provide read data in an alternating back-and-forth sequence
during the DDR read mode. According to another aspect of these
first embodiments, the plurality of memory devices include first,
second, third and fourth memory devices configured in a preferred
quad arrangement. Moreover, when operating in a DDR write mode that
supports a x4N write data width, where N is a positive integer, the
write control circuitry provides each of the memory devices in the
quad arrangement with 4N bits of write data in a sequence that is
synchronized with leading and trailing edges of two (2) consecutive
cycles of the write clock signal. Alternatively, when operating in
a DDR write mode that supports a x2N write data width, the write
control circuitry provides each of the memory devices in the quad
arrangement with 4N bits of write data in a sequence that is
synchronized with trailing edges of four (4) consecutive cycles of
the write clock signal. Finally, when operating in a DDR write mode
that supports a xN write data width, the write control circuitry
provides each of the memory devices in the quad arrangement with 4N
bits of write data in a sequence that is synchronized with trailing
edges of every other one of eight (8) consecutive cycles of the
write clock signal.
According to still further aspects of these first embodiments, when
operating in an SDR write mode and supporting the x4N write data
width, the write control circuitry provides each of the memory
devices in the quad arrangement with 4N bits of write data in a
sequence that is synchronized with leading edges of four (4)
consecutive cycles of the write clock signal. When operating in an
SDR write mode and supporting the x2N write data width, the write
control circuitry provides each of the memory devices in the quad
arrangement with 4N bits of write data in a sequence that is
synchronized with leading edges of every other one of eight (8)
consecutive cycles of the write clock signal. Finally, when
operating in an SDR write mode and supporting the xN write data
width, the write control circuitry provides each of the memory
devices in the quad arrangement with 4N bits of write data in a
sequence that is synchronized with leading edges of every fourth
one of sixteen (16) consecutive cycles of the write clock signal.
Analogous operations are also performed when the FIFO memory
devices are operating in any combination of DDR and SDR read
modes.
First-in first-out (FIFO) memory devices according to second
embodiments of the present invention include a plurality of memory
devices and an input multiplexer that provides the plurality of
memory devices with write data in-sync with rising and falling
edges of a write clock signal when the FIFO memory device is
disposed in a dual data rate (DDR) write mode. The FIFO memory
devices may also include an output multiplexer that receives read
data from the plurality of memory devices in-sync with rising and
falling edges of a read clock signal when the FIFO memory device is
disposed in a DDR read mode. The input multiplexer may comprise an
input data buffer and a master latch electrically coupled to an
output of the input data buffer. A first bus matching circuit may
also be provided that supports any combination of x4N, x2N and xN
write modes. This first bus matching circuit is electrically
coupled to an output of the master latch. A slave latch is also
provided. This slave latch has inputs that are electrically coupled
to corresponding outputs of the first bus matching circuit. The
outputs of the slave latch are electrically coupled to the
plurality of memory devices.
The output multiplexer may also include a second bus matching
circuit having inputs that are electrically coupled to receive read
data from the plurality of memory devices. First and second output
registers may also be provided having inputs that are electrically
coupled to first and second output ports of the second bus matching
circuit. According to a preferred aspect of these second
embodiments, the output multiplexer includes a redirect multiplexer
having first and second inputs that are electrically coupled to the
first and second output ports and an output electrically coupled to
an input of the first output register. This redirect multiplexer is
preferably responsive to a single date rate select signal. This
single data rate select signal enables the second output register
to be bypassed when the FIFO memory device is disposed in a single
data rate (SDR) read mode of operation.
First-in first-out (FIFO) memory devices according to third
embodiments of the present invention may include a plurality of
multi-port cache memory devices that are configured to support any
combination of dual data rate (DDR) or single data rate (SDR) write
modes and DDR or SDR read modes. These multi-port cache memory
devices may include first and second quad-port cache memory
devices. Each of these quad-port cache memory devices may include a
data input register, a multiplexer and an output register. The data
input register may have an input electrically coupled to a first
port of the quad-port cache memory device and an output
electrically coupled to a second port of the quad-port cache memory
device. The multiplexer is responsive to at least one select signal
and has a first input electrically coupled to the output of the
data input register and a second input electrically coupled to a
third port of the quad-port cache memory device. The output
register has an input electrically coupled to an output of the
multiplexer and an output electrically coupled to a fourth port of
the quad-port cache memory device.
First-in first-out (FIFO) memory devices according to fourth
embodiments of the present invention may include a plurality of
memory devices that are configured to support a dual data rate
(DDR) read mode that operates in-sync with leading and trailing
edges of a read clock signal and read control circuitry that can
handle retransmit operations. This read control circuitry may mark
data read from the FIFO memory device in response to a trailing
edge of a first cycle of the read clock signal during the DDR read
mode. This marking operation may be responsive to an active mark
signal. The read control circuitry may also perform retransmit
operations that are responsive to an active retransmit signal.
These retransmit operations may include retransmitting data in
pairs by commencing the retransmission with data previously read
from the FIFO memory device in response to a leading edge of the
first cycle of the read clock signal before following with the
marked read data that was originally read on the trailing edge of
the first cycle of the read clock signal.
The embodiments of the present invention also preferably include
flag circuitry that can address empty, almost empty, full and
almost full conditions within a FIFO memory device having DDR read
and write modes. This flag circuitry preferably evaluates an empty
(or almost empty) condition in the FIFO memory device by comparing
a write counter value that is generated off a trailing edge of the
write clock signal against a read counter value that is generated
off a leading edge of the read clock signal when the FIFO memory
device is disposed in the DDR write mode. This flag circuitry may
also evaluate a full (or almost full) condition in the FIFO memory
device by comparing a read counter value that is generated off a
trailing edge of the read clock signal against a write counter
value that is generated off a leading edge of the write clock
signal when the FIFO memory device is disposed in the DDR read
mode. Other FIFO memory device embodiments may also be provided
that include more than two (2) or four (4) memory devices that
operate in tandem to provide any combination of DDR and SDR
modes.
Integrated circuit devices according to further embodiments of the
present invention include an integrated circuit substrate (e.g.,
chip) having a plurality of independently operable FIFO memory
devices therein. Each of these plurality of FIFO memory devices are
configured to support all four combinations of DDR and SDR write
modes and DDR and SDR read modes. These four combinations include:
DDR write with DDR read, DDR write with SDR read, SDR write with
DDR read and SDR write with SDR read. These FIFO memory devices are
also configured to support all four of the following multi-FIFO
operating modes: multiplexer, demultiplexer, broadcast and
multi-queue. Each of the FIFO memory devices includes a plurality
of arrays of memory elements therein that are accessed
one-at-a-time when the respective FIFO memory device is being
written to. The plurality of arrays may include four memory arrays
that are arranged in quadrants and written to one-at-a-time and
read from one-at-a-time. Lookahead word line precharging operations
may also be performed to eliminate word line driving operations
from the speed path during write and read cycles.
The plurality of FIFO memory devices may be collectively configured
to support a multi-queue mode of operation that provides
independent write path and read path queue switching. The write
path queue switching is free of write word fall-through and the
read path queue switching is free of read word fall-through. This
enables the write path to be queue switched on every write cycle in
both SDR and DDR write modes and the read path to be queue switched
on every read cycle in both SDR and DDR read modes. The multi-queue
mode of operation can also support write queue pointer changes that
are free of corresponding write operations.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a high-level block diagram of a first-in first-out (FIFO)
memory device according to an embodiment of the present
invention.
FIG. 2 is a block diagram of a FIFO memory device that utilizes a
quad arrangement of memory devices therein, according to an
embodiment of the present invention.
FIG. 3 is a block diagram illustrating features of a preferred data
input multiplexer according to the FIFO memory device of FIG.
2.
FIG. 4 is a block diagram illustrating features of a preferred data
output multiplexer according to the FIFO memory device of FIG.
2.
FIG. 5 is a timing diagram that illustrates operations performed by
the FIFO memory device of FIG. 2 when the memory device is
configured in a x40 dual data rate (DDR) write mode of
operation.
FIG. 6A is a timing diagram that illustrates operations performed
by the FIFO memory device of FIG. 2 when the memory device is
configured in a x40 dual data rate (DDR) read mode of
operation.
FIG. 6B is another timing diagram that illustrates operations
performed by the FIFO memory device of FIG. 2 when the memory
device is configured in a x40 dual data rate (DDR) read mode of
operation.
FIG. 7 is a timing diagram that illustrates operations performed by
the FIFO memory device of FIG. 2 when the memory device is
configured in a x10 single data rate (SDR) write mode of
operation.
FIG. 8 is a timing diagram that illustrates operations performed by
the FIFO memory device of FIG. 2 when the memory device is
configured in a x10 single data rate (SDR) read mode of
operation.
FIGS. 9A 9F are block diagrams that illustrate how multiple
independent FIFOs within a multi-FIFO memory device can be
configured to support quad, dual, mux, demux, broadcast and
multi-queue modes of operation, according to embodiments of the
present invention.
FIG. 10A is a block diagram of an integrated multi-FIFO memory
device according to embodiments of the present invention.
FIG. 10B is a block diagram that illustrates a quad arrangement of
memory arrays and spine control circuitry that define a memory core
portion of a FIFO memory device in FIG. 10A.
FIG. 11A illustrates a shared portion of a write data path
associated with the multi-FIFO memory device of FIG. 10A, which
includes a write clock generator, data input drivers and a 80b-bit
wide data input bus.
FIGS. 11B 11C illustrates the routing of write data through a
plurality of data input (DIN) muxes, according to the multi-FIFO
memory device of FIG. 10A.
FIG. 11D is a detailed illustration of a portion of a data input
mux illustrated by FIG. 11B.
FIG. 11E is a block diagram of a portion of the data input control
and driver circuit illustrated by FIG. 10A.
FIG. 11F is a block diagram of a portion of the data input bus and
prechargers illustrated by FIG. 10A.
FIG. 11G is an electrical schematic of a precharger illustrated by
FIG. 11F.
FIG. 11H is a timing diagram that illustrates operation of a
portion of the write data path illustrated by FIG. 10A and FIGS.
11A 11G.
FIG. 12A is an electrical schematic of a bit slice of the write IO
control logic of FIG. 10A, according to embodiments of the present
invention.
FIG. 12B is a timing diagram that illustrates operation of the
write IO control logic of FIG. 12A.
FIG. 13A is an electrical schematic of a bit slice of the write
spine control logic of FIG. 10A, according to embodiments of the
present invention.
FIG. 13B illustrates a routing relationship between write
input/output (IO) lines and write bit lines associated with one
segment of the write spine control logic of FIG. 10A.
FIG. 13C illustrates a routing relationship between write
input/output (IO) lines and write bit lines in the write spine
control logic of FIG. 10A.
FIG. 14A is a block diagram that illustrates the vertical read path
in the multi-FIFO device of FIG. 10A.
FIG. 14B is a bit slice of the vertical read path illustrated by
FIG. 14A.
DESCRIPTION OF PREFERRED EMBODIMENTS
The present invention now will be described more fully with
reference to the accompanying drawings, in which preferred
embodiments of the invention are shown. This invention may,
however, be embodied in many different forms and should not be
construed as being limited to the embodiments set forth herein;
rather, these embodiments are provided so that this disclosure will
be through and complete, and will fully convey the scope of the
invention to those skilled in the art. Like reference numerals
refer to like elements throughout and signal lines and signals
thereon may be referred to by the same reference characters.
Signals may also be synchronized and/or undergo minor boolean
operations (e.g., inversion) without being considered different
signals. The suffix X (or prefix symbol "/") to a signal name may
also denote a complementary data or information signal or an active
low control signal, for example. Active low signals may be changed
to active high signals and the description of such signals as
active low signals should not be construed as limiting the
embodiments described herein to the use of only such signals.
First-in first-out (FIFO) memory devices 100 according to first
embodiments of the present invention may include a data path
defined by an input register 202, a core memory block 214, which
may contain a plurality of memory devices therein, and an output
register 212 that provides data to an output buffer 228. An offset
register 204 having serial-in SI and serial-out SO pins is also
provided. This offset register 204 is provided for retaining
programmable offset information that is relevant to the flag logic
circuit 206. The offset register 204 may also provide a parallel
input-to-output data path that bypasses the core memory block 214.
A write control logic circuit 216 and a write pointer 218 are also
provided along with a read control logic circuit 210 and a read
pointer 208. The FIFO memory devices 100 also include bus
configuration logic 220, a reset logic circuit 222 and JTAG
boundary scan control circuitry 224. An HSTL I/O control circuit
226 is also provided. The operation of these components of the FIFO
memory devices 100 is more fully described herein and in U.S.
application Ser. No. 60/314,393, filed Aug. 23, 2001, entitled
"FIFO Memory Device Having Dual Data Rate (DDR) Capability," the
disclosure of which is hereby incorporated herein by reference.
These FIFO memory devices 100 are configured to support any
combination of dual data rate (DDR) or single data rate (SDR) write
modes that operate in-sync with a write clock signal (WCLK) and DDR
or SDR read modes that operate in-sync with a read clock signal
(RCLK). As illustrated by FIG. 1, these FIFO memory devices 100
provide flexible x4N, x2N and xN bus matching on the write (data
input) and read (data output) ports, where N is a positive integer
(e.g., N=10). Advantageously, these FIFO memory devices 100 support
writing and reading of data on both rising and falling edges of the
write and read clock signals. Custom flag generation and mark and
retransmit circuitry is also provided that can efficiently handle
any combination of DDR and SDR read and write modes. These FIFO
memory devices 100 also provide extended memory capacity. In
particular, the FIFO memory devices 100 preferably include first,
second, third and fourth memory devices that are configured in a
preferred quad arrangement. In addition to providing high capacity,
this quad arrangement increases the minimum acceptable read and
write cycle times by increasing the spacing between consecutive
read and write accesses to each memory device. FIFO memory devices
100, according to other embodiments of the present invention, may
also include arrangements based on two (2), six (6), eight (8) or
other even and odd combinations of memory devices.
Each FIFO memory device 100, according to the first embodiment, may
have a data input port (Dn) and a data output port (Qn), both of
which can assume either a 40-bit, 20-bit, or a 10-bit data width.
These data widths are determined by the state of external control
pins: Input Width (IW), Output Width (OW), and Bus-Matching (BM)
pin, during a Master Reset cycle. The input port is controlled by a
Write Clock (WCLK) input and a Write Enable (/WEN) input. Data
present on the Dn data inputs can be written into the FIFO on every
rising and falling edge of WCLK when /WEN is asserted and the Write
Single Data Rate (/WSDR) pin is held HIGH. Data can be selected to
write only on the rising edges of WCLK if /WSDR is asserted. The
Write Enable input /WEN should be a controlled signal and not tied
to ground, because /WEN should be HIGH during the time when the
Master Reset (/MRS) pulse is LOW. In addition, the /WSDR pin should
be tied HIGH or LOW, because it is not a controlled signal and
typically cannot be changed during FIFO operation. Write operations
can be selected for either Single or Double Data Rate mode. For
Single Data Rate operation, writing into the FIFO requires the
Write Single Data Rate (/WSDR) pin to be asserted. Data will be
written into the FIFO memory device 100 on the rising edge of WCLK
when the Write Enable (/WEN) is asserted. For Double Data Rate
operations, writing into the FIFO memory device requires /WSDR to
be deasserted. Data will be written into the FIFO on both rising
and falling edges of WCLK when /WEN is asserted.
The output port Qn is controlled by a Read Clock (RCLK) input and a
Read Enable (/REN) input. Data is read from the FIFO on every
rising and falling edge of RCLK when /REN is asserted and the Read
Single Data Rate (/RSDR) pin is held HIGH. Data can be selected to
read only on the rising edges of RCLK if /RSDR is asserted. The
READ ENABLE input /REN should be a controlled signal and not tied
to ground, because /REN should be HIGH during the time when the
Master Reset (/MRS) pulse is LOW. In addition, the /RSDR pin should
be tied HIGH or LOW, because it typically cannot be changed during
FIFO operation. Read operations can be selected for either Single
or Double Data Rate mode. Similar to the write operations, reading
from the FIFO in single data rate requires the Read Single Data
Rate (/RSDR) pin to be asserted. Data will be read from the FIFO on
the rising edge of RCLK when the Read Enable (/REN) is asserted.
For Double Data Rate operations, reading into the FIFO requires
/RSDR to be deasserted. Data will be read out of the FIFO memory
device 100 on both rising and falling edges of RCLK when /REN is
asserted. The frequencies of both the RCLK and WCLK signals may
vary from a low frequency to the maximum frequency (f.sub.MAX) with
complete independence. There are typically no restrictions on the
frequency of RCLK relative to WCLK.
The input port can be selected for either 2.5V LVTTL or HSTL
operation. This operation is selected by the state of the HSTL
input. A write chip select input (/WCS) is provided for use when
the write port is in the HSTL mode. During HSTL operation, the /WCS
input can be used to disable write port inputs, effectively
disabling write operations. The output port can be selected for
either 2.5V LVTTL or HSTL operation. This operation is selected by
the state of the HSTL input. When the read port is setup for HSTL
mode, the Read Chip Select (/RCS) input also has the benefit of
disabling the read port inputs, providing additional power
savings.
There is the option of selecting different data rates on the input
and output ports of the FIFO memory device 100. There are a total
of four combinations to choose from, Double Data Rate to Double
Data Rate (DDR to DDR), DDR to Single Data Rate (DDR to SDR), SDR
to DDR, and SDR to SDR. The rates can be set up using the /WSDR and
/RSDR pins. For example, to set up the input to output combination
of DDR to SDR, /WSDR will be HIGH and /RSDR will be LOW. Read and
write operations are initiated on the rising edge of RCLK and WCLK,
respectively, and not on the falling edge. If /REN or /WEN is
asserted after a rising edge of WCLK or RCLK, respectively, no read
or write operations will occur on the falling edge of that same
clock pulse. When the FIFO memory device 100 is disposed in the DDR
write mode, data is preferably always written in pairs on the
rising and falling edges of WCLK. Data also is read in pairs when
the FIFO memory device is disposed in the DDR read mode. This
requirement of data being read or written in pairs impacts the flag
and retransmit operations, as described more fully hereinbelow.
An Output Enable (/OE) input is provided for high-impedance control
of the outputs. A read Chip Select (/RCS) input is also provided
for synchronous enable/disable of the read port control input,
/REN. The /RCS input is synchronized to the read clock, and also
provides high-impedance controls to the Qn data outputs. When /RCS
is disabled, /REN will be disabled internally and the data outputs
will be in high-impedance states. Unlike the Read Chip Select
signal however, /OE is not synchronous to RCLK. Outputs are
high-impedanced shortly after a delay time when the /OE transitions
from LOW to HIGH.
The Echo Read Enable (/EREN) and Echo Read Clock (/ERCLK) outputs
are used to provide tighter synchronization between the data being
transmitted from the Qn outputs and the data being received by
another device. In particular, data read from the read port is
available on the output bus based on the timing of /EREN and ERCLK.
This feature is useful when data is being read at high-speed where
synchronization is important.
The FIFO memory devices 100 of FIG. 1 may operate in IDT Standard
mode or First Word Fall Through (FWFT) mode. In IDT Standard mode,
the first word written to an empty FIFO will not appear on the data
output lines unless a specific read operation is performed. A read
operation, which consists of activating /REN and enabling a rising
RCLK edge, will shift the word from internal memory to the data
output lines. In FWFT mode, the first word written into an empty
FIFO is clocked directly to the data output lines after three
transitions of RCLK. A read operation does not have to be performed
to access the first word written to the FIFO. However, subsequent
words written to the FIFO do require a LOW on /REN for access. The
state of the FWFT input during Master Reset determines the timing
mode in use. For applications requiring more data storage capacity
than a single FIFO can provide, the FWFT timing mode permits depth
expansion by chaining FIFOs in series (i.e. the data outputs of one
FIFO are connected to the corresponding data inputs of the next).
No external logic is required.
The FIFO memory device preferably has four flag pins, /ER(/OR)
(Empty Flag or Output Read), /FF(/IR) (Full Flag or Input Ready),
/PAE (Programmable Almost-Empty flag), and /PAF (Programmable
Almost-Full flag). The /EF and /FF functions are selected in IDT
Standard mode. The /IR and /OR functions are selected in FWFT mode.
The /PAE and /PAF flags are always available for use, irrespective
of timing mode. The /PAE and /PAF flags can be programmed
independently to switch at any point in memory. Programmable
offsets mark the location within the internal memory that activates
the /PAE and /PAF flags and can only be programmed serially. To
program the offsets, the serial input enable pin /SEN is made
active and data can be loaded via the Serial Input (/SI) pin at the
rising edge of the serial clock SCLK. To read out the offset
registers serially, the serial read enable pin /SREN is set active
and data can be read out via the Serial Output (SO) pin at the
rising edge of SCLK. Four default offset settings are also
provided, so that /PAE can be marked at a predefined number of
locations from the empty boundary and the /PAF threshold can also
be marked at similar predefined values from the full boundary. The
default offset values are set during Master Reset by the state of
the FSEL0 and FSEL1 pins.
The flag logic circuit 206 preferably evaluates an empty (or almost
empty) condition in the FIFO memory device 100 by comparing a write
counter (i.e., pointer) value that is generated off a trailing edge
of an internal write clock signal (e.g., WCNTRCLK derived from
WCLK) against a read counter (i.e., pointer) value that is
generated off a leading edge of an internal read clock signal
(e.g., RCNTRCLK derived from RCLK) when the FIFO memory device 100
is disposed in the DDR write mode. This flag logic circuit 206 may
also evaluate a full (or almost full) condition in the FIFO memory
device 100 by comparing a read counter value that is generated off
a trailing edge of the internal read clock signal against a write
counter value that is generated off a leading edge of the internal
write clock signal when the FIFO memory device is disposed in the
DDR read mode. Additional components and functional description of
the flag logic circuit 206 are illustrated and described at pages
51-56 of the aforementioned U.S. application Ser. No.
60/314,393.
During Master Reset (/MRS), the following events occur: the read
and write pointers are set to the first location of the internal
FIFO memory, and the FWFT pin selects IDT Standard mode or FWFT
mode. The Partial Reset signal (/PRS) also sets the read and write
pointers to the first location of the memory. However, the timing
mode (IDT Standard vs. FWFT) and the values stored in the
programmable offset registers before Partial Reset remain
unchanged. The flags are updated according to the timing mode and
offsets in effect at the time of the partial reset. The Partial
Reset signal /PRS is useful for resetting a device in
mid-operation, when reprogramming programmable flags would be
undesirable. The timing of the /PAE and /PAF flags are synchronous
to RCLK and WCLK, respectively. The /PAE flag is asserted upon the
rising edge of RCLK only and not WCLK. Similarly the /PAF flag is
asserted and updated on the rising edge of WCLK only and not
RCLK.
This device includes a Retransmit from Mark feature that utilizes
two control inputs, MARK and /RT (Retransmit). If the MARK input is
enabled with respect to RCLK, the memory location being read at
that point will be marked. Any subsequent retransmit operation
(when /RT goes LOW), will reset the read pointer to this "marked"
location.
If, at any time, the FIFO is not actively performing an operation,
the chip will automatically power down. Once in the power down
state, the standby supply current consumption is minimized.
Initiating any operation (by activating control inputs) will
immediately take the device out of the power down state. A JTAG
test port also is provided and the FIFO has fully functional
boundary Scan features, compliant with IEEE 1449.1 Standard Test
Access Port and Boundary Scan Architecture.
Retransmit from Mark Operation
The Retransmit from Mark feature allows FIFO data to be read
repeatedly starting at a user-selected position. The FIFO memory
device 100 is first put into a retransmit mode that will "mark" a
beginning word and also set a pointer that will prevent ongoing
FIFO write operations from over-writing retransmit data. The
retransmit data can be read repeatedly any number of times from the
"marked" position. The FIFO memory device 100 can be taken out of
retransmit mode at any time to allow normal device operation. The
"mark" position can be selected any number of times, each selection
over-writing the previous mark location. In Double Data Rate, data
will always be marked in pairs. If the data marked was read on a
falling edge of RCLK, then the marked data will be the unit of data
read from the rising and falling edge of that particular cycle of
RCLK. FIG. 23 from the aforementioned U.S. application Ser. No.
60/314,393 provides a timing diagram for this retransmit mode.
Retransmit operation is available in both IDT standard and FWFT
modes.
During the IDT standard mode, the FIFO memory device 100 is put
into retransmit mode by a Low-to-High transition on RCLK when the
MARK input is HIGH and /EF is HIGH. The rising RCLK edge marks the
data present in the FIFO output register as the first retransmit
data. Again, the data is marked in pairs. Thus if the data marked
was read on the falling edge of RCLK, the first part of retransmit
will read out the data originally read on the rising edge of RCLK,
followed by the data originally read on the falling edge (the
marked data) of the same cycle of the read clock signal RCLK. The
FIFO remains in retransmit mode until a rising edge on RCLK occurs
while MARK is LOW.
Once a marked location has been set, a retransmit can be initiated
by a rising edge on RCLK while the Retransmit input (/RT) is LOW.
The device indicates the start of retransmit setup by setting /EF
LOW, which prevents normal read operations. When /EF goes HIGH,
retransmit setup is complete and read operations may begin starting
with the first unit of data at the MARK location. Write operations
may continue as normal during all retransmit functions, however
write operations that cross over the "marked" location will be
prevented.
During FWFT mode, the FIFO memory device 100 is put into retransmit
mode by a rising RCLK edge when the MARK input is HIGH and /OR is
LOW. The rising RCLK edge marks the data present in the FIFO output
register as the first retransmit data. The FIFO remains in
retransmit mode until a rising RCLK edge occurs while MARK is LOW.
Once a marked location has been set, a retransmit can be initiated
by a rising RCLK edge while the Retransmit input (/RT) is LOW. The
device indicates the start of retransmit setup by setting /OR HIGH,
preventing read operations. When /OR goes LOW, retransmit setup is
complete and on the next rising RCLK edge, after /RT goes HIGH, the
contents of the first retransmit location are loaded onto the
output register. Since FWFT mode is selected, the first word
appears on the outputs regardless of /REN. A LOW on /REN is not
required for the first word. Reading all subsequent words requires
a LOW on /REN to enable the rising RCLK edge. FIG. 24 from the
aforementioned U.S. application Ser. No. 60/314,393 provides a
timing diagram for the retransmit in the FWFT mode. Before a
retransmit can be performed, there should be at least 1280 bits of
data between the write pointer and the marked location. These 1280
bits of data correspond to 32 pieces of 40-bit data, 64 pieces of
20-bit data or 128 pieces of 10-bit data. Once the marked location
has been set, the write pointer will not increment past the marked
location, preventing overwrites of retransmit data.
The data and control signals illustrated by the FIFO memory device
100 of FIG. 1 will now be more fully described.
Data IN (D0 D39)
(D0 D39) are data inputs for the 40-bit wide data, (D0 D19) are
data inputs for the 20-bit wide data, or (D0 D9) are data inputs
for 10-bit wide data. Other data widths are also possible.
Master Reset (/MRS)
A Master Reset is accomplished whenever the /MRS input is taken to
a LOW state. This operation sets the internal read and write
pointers to the first location of the memory device. /PAE will go
LOW and /PAF will go HIGH. If FWFT is LOW during Master Reset, then
IDT Standard mode along with /EF and /FF are selected. /EF will go
LOW and /FF will go HIGH. If FWFT is HIGH, then the First Word Fall
Through (FWFT) mode, along with /IR and /OR, are selected. /OR will
go HIGH and /IR will go LOW. All control settings such as OW, IW,
BM, FWFT, FSEL0 and FSEL1 are defined during the Master Reset
cycle. During a Master Reset, the output register 212 is
initialized to all zeros. A Master Reset is required after power up
before a write operation can take place. Aspects of the Master
Reset operation are more fully illustrated by FIG. 8 of the
aforementioned U.S. application Ser. No. 60/314,393.
Partial Reset (/PRS)
A Partial Reset is accomplished whenever the /PRS input is taken to
a LOW state. As in the case of the Master Reset, the internal read
and write pointers are set to the first location of the memory
device. /PAE goes LOW and /PAF goes HIGH. Whichever mode was active
at the time of Partial Reset will remain active after Partial
Reset. If IDT Standard mode is active, then /FF will go HIGH and
/EF will go LOW. If the First Word Fall Through mode is active,
then /OR will go HIGH and /IR will go LOW. Following Partial Reset,
all values in the offset registers remain unchanged. The output
register is initialized to all zeros. Partial Reset is useful for
resetting the read and write pointers to zero without affecting the
values of the programmable flag offsets and the timing mode of the
FIFO. These aspects of the Partial Reset are more fully illustrated
by FIG. 9 of the aforementioned U.S. application Ser. No.
60/314,393.
First Word Fall Through (FWFT)
During Master Reset, the state of the FWFT input determines whether
the device will operate in IDT Standard mode or First Word Fall
Through (FWFT) mode. If, at the time of the Master Reset, FWFT is
LOW, then IDT Standard mode will be selected. This mode uses the
Empty Flag (/EF) to indicate whether or not there are any words
present in the FIFO memory device 100. It also uses the Full Flag
function (/FF) to indicate. whether or not the FIFO memory device
100 has any free space for writing. In IDT Standard mode, every
word read from the FIFO, including the first, should be requested
using the Read Enable (/REN) and RCLK. If, at the time of Master
Reset, FWFT is HIGH, then FWFT mode will be selected. This mode
uses Output Ready (/OR) to indicate whether or not there is valid
data at the outputs (Qn) to be read. It also uses the Input Ready
(/IR) signal to indicate whether or not the FIFO memory device 100
has any free space for writing. In the FWFT mode, the first word
written to an empty FIFO goes directly to Qn after three RCLK
rising edges and it is not necessary to set /REN LOW. Subsequent
words must be accessed using the Read Enable (/REN) signal and
RCLK.
Write Clock (WCLK)
A write cycle is initiated on the rising and/or falling edge of the
WCLK input. If the Write Single Data Rate (/WSDR) pin is selected,
data will be written only on the rising edge of WCLK, provided that
/WEN and /WCS are LOW. If the /WSDR is not selected, data will be
written on both the rising and falling edges of WCLK, provided that
/WEN and /WCS are LOW. Data setup and hold times must be met with
respect to the LOW-to-HIGH transition of the WCLK. It is
permissible to stop the WCLK. Note that while WCLK is idle, the
/FF, /IR, and /PAF flags will not be updated. The write and read
clocks can operate asynchronously relative to each other.
Write Enable (/WEN)
When the /WEN input is LOW, data may be loaded into the FIFO memory
device 100 on the rising edge of every WCLK cycle if the device is
not full. Data is stored in the memory device sequentially and
independently of any ongoing read operation. When /WEN is HIGH, no
new data may be written in the memory device. To prevent data
overflow in the IDT Standard mode, /FF will go LOW, inhibiting
further write operations. Upon completion of a valid read cycle,
/FF will go HIGH, allowing a write to occur. The /FF is updated by
two WCLK cycles+t.sub.SKEW after the RCLK cycle. To prevent data
overflow in the FWFT mode, /IR will go HIGH, inhibiting further
write operations. Upon the completion of a valid read cycle, /IR
will go LOW, allowing a write to occur. The /IR flag is updated by
two WCLK cycles+t.sub.SKEW after the valid RCLK cycle. /WEN is
ignored when the FIFO is full in either IDT Standard mode or FWFT
mode.
Write Signal Data Rate (/WSDR)
When the Write Single Data Rate signal is LOW, the write port will
be set to Single Data Rate mode. In this mode, all write operations
are based only on the rising edge of WCLK, provided that /WEN and
/WCS are LOW. When /WSDR is HIGH, the read port will be set to
Double Data Rate mode. In this mode, all write operations are based
on both the rising and falling edge of WCLK, provided that /WEN and
/WCS are LOW.
Read Clock (RCLK)
A read cycle is initiated on the rising and/or falling edge of the
RCLK input. If the Read Single Data Rate (/RSDR) pin is selected,
data will be read only on the rising edge of RCLK, provided that
/REN and /RCS are LOW. If the /RSDR is not selected, data will be
read on both the rising and falling edge of RCLK, provided that
/REN and /RCS are LOW. Data setup and hold times must be met with
respect to the LOW-to-HIGH transition of the RCLK. It is
permissible to stop the RCLK. The /EF(/OR) and /PAE flags will not
be updated while RCLK is idle.
Read Enable (/REN)
When Read Enable is LOW, data may be read from the memory device.
When the /REN input is HIGH, the output register holds the previous
data and no new data may be loaded into the output register. The
data outputs Q0-Qn maintain the previous data. In IDT Standard
mode, every word accessed at Qn, including the first word written
to an empty FIFO, must be requested using /REN, provided that the
Read Chip Select (/RCS) is LOW. When the last word has been read
from the FIFO, the Empty Flag (/EF) will go LOW, inhibiting further
read operations. /REN is ignored when the FIFO is empty. Once a
write is performed, /EF will go HIGH allowing a read to occur. Both
/RCS and /REN must be active LOW for data to be read out on the
rising edge of RCLK. In FWFT mode, the first word written to an
empty FIFO automatically goes to the outputs Qn on the third valid
LOW-to-HIGH transition of RCLK+t.sub.SKEW after the first write.
/REN and /RCS do not need to be asserted LOW for the first word to
fall through to the output register. All subsequent words require
that a read operation be executed using /REN and /RCS. The
LOW-to-HIGH transition of RCLK after the last word has been read
from the FIFO will make Output Ready (/OR) go HIGH and this will
inhibit subsequent read operations.
Read Single Data Rate (/RSDR)
When the Read Single Data Rate pin is LOW, the read port will be
set to Single Data Rate mode. In this mode, all read operations are
based only on the rising edge of RCLK, provided that /REN and /RCS
are LOW. When /RSDR is HIGH, the read port will be set to Double
Data Rate mode. In this mode, all read operations are based on both
the rising and falling edge of RCLK, provided that /REN and /RCS
are LOW.
Serial Clock (SCLK)
The serial clock is used to load and read data in the programmable
offset registers. Data from the Serial Input (SI) can be loaded
into the offset registers on the rising edge of SCLK provided that
/SEN is LOW. Data can be read from the offset registers via the
Serial Output (SO) on the rising edge of SCLK provided that /SREN
is LOW.
Serial Enable (/SEN)
The /SEN input is an enable signal used for serial programming of
the programmable offset registers. It is used in conjunction with
SI and SCLK when programming the offset registers. When /SEN is
LOW, data at the Serial In (SI) input can be loaded into the offset
register, one bit for each LOW-to-HIGH transition of SCLK. When
/SEN is HIGH, the offset registers retain the previous settings and
no offsets are loaded. /SEN functions the same way in both IDT
Standard and FWFT modes.
Serial Read Enable (/SREN)
The /SREN output is an enable used for reading the value of the
programmable offset registers. It is used in conjunction with SI
and SCLK when reading from the offset registers. When /SREN is LOW,
data can be read out of the offset register from the SO output, one
bit for each LOW-to-HIGH transition of SCLK. When /SREN is HIGH,
reading of the offset registers will stop. Whenever /SREN is
activated, values in the offset registers are read starting from
the first location in the offset registers and not from where the
last offset value was read. /SREN functions the same way in both
IDT Standard and FWFT modes.
Serial IN (SI)
This pin acts as a serial input for loading /PAE and /PAF offsets
into the programmable offset registers. It is used in conjunction
with the Serial Clock (SCLK) and the Serial Enable (/SEN). Data
from this input can be loaded into the offset register, one bit for
each LOW-to-HIGH transition of SCLK provided that /SEN is LOW.
Serial Out (SO)
This pin acts as a serial output for reading the values of the /PAE
and /PAF offsets in the programmable offset registers. It is used
in conjunction with the Serial Clock (SCLK) and the Serial Enable
Output (/SREN). Data from the offset register can be read out using
this pin, one-bit for each LOW-to-HIGH transition of SCLK provided
that /SREN is LOW.
Output Enable (/OE)
When Output Enable is LOW, the parallel output buffers receive data
from the output register. When /OE is HIGH, the output data bus
(Qn) goes into a high-impedance state. During Master or Partial
Reset, the /OE is the only input that can place the output data bus
into high-impedance. During reset the /RCS input can be HIGH or LOW
and has no effect on the output data bus.
Read Chip Select (/RCS)
The Read Chip Select input provides synchronous control of the Read
output port. When /RCS goes LOW, the next rising edge of RCLK
causes the Qn outputs to go to the low-impedance state. When /RCS
goes HIGH, the next RCLK rising edge causes the Qn outputs to
return to high-impedance. During a Master or Partial Reset, the
/RCS input has no effect on the Qn output bus. /OE provides
high-impedance control of the Qn outputs. If /OE is LOW, the Qn
data outputs will be low-impedance regardless of /RCS until the
first rising edge of RCLK after a reset is complete. Then, if /RCS
is HIGH, the data outputs will go to high-impedance states. The
/RCS input does not affect the operation of the flags. For example,
when the first word is written to an empty FIFO, the /EF signal
will still go from LOW to HIGH based on a rising edge of RCLK,
regardless of the state of the /RCS input.
When operating the FIFO memory device 100 in FWFT mode, the first
word written to an empty FIFO will be clocked through to the output
register based on RCLK, regardless of the state of /RCS. If /RCS is
HIGH when an empty FIFO is written into, the first word will fall
through to the output register, but will not be available on the Qn
outputs because they are in high-impedance states. The user must
take /RCS active LOW to access this first word, placing the output
bus in low-impedance. /REN should remain HIGH for at least one
cycle after /RCS has gone LOW. A rising edge of RCLK with /RCS and
/REN LOW will read out the next word. The /RCS pin must also be
active (LOW) in order to perform a Retransmit.
Write Chip Select (/WCS)
The /WCS disables all Write Port inputs (data only) if it is held
HIGH. To perform normal operations on the write port, the /WCS must
be enabled.
HSTL Select (HSTL)
Many of the inputs or outputs can be setup to be either HSTL or
LVTTL compatible. If HSTL is HIGH, the HSTL operation of those
signals will be selected. If HSTL is LOW, then LVTTL will be
selected. Configuring a FIFO memory device to support HSTL and
LVTTL logic levels is more fully described at page 14 and Table 6
of the aforementioned U.S. application Ser. No. 60/314,393.
Bus-Matching (BM, IW, OW)
The pins BM, IW, and OW are used to define the input and output bus
widths. During Master Reset, the state of these pins is used to
configure the device bus sizes, as illustrated by TABLE 5. All
flags will operate on the word/byte size boundary as defined by the
selection of bus width.
Flag Select Bits (FSEL0 and FSEL1)
These pins will select default offset values for the /PAE and /PAF
flags during Master Reset. The status of these inputs should not
change after Master Reset.
Data Out (Q0 Q39)
(Q0 Q39) are data outputs for 40-bit wide data, (Q0 Q19) are data
outputs for 20-bit wide data, or (Q0 Q9) are data outputs for
10-bit wide data.
Full Flag (/FF(/IR))
This is a dual-purpose pin. In IDT Standard mode, the Full Flag
(/FF) function is selected. When the FIFO is full, /FF will go LOW,
inhibiting further write operations. When /FF is HIGH, the FIFO is
not full.
In FWFT mode, the Input Ready (/IR) function is selected. /IR goes
LOW when memory space is available for writing in data. When there
is no longer any free space left, /IR goes HIGH, inhibiting further
write operations. The /IR status not only measures the contents of
the FIFO memory, but also counts the presence of a word in the
output register. Thus, in FWFT mode, the total number of writes
necessary to deassert /IR is one greater than needed to assert /FF
in IDT Standard mode. /FF(/IR) is synchronous and updated on the
rising edge of WCLK. /FF(/IR) are double register-buffered
outputs.
When the FIFO device is in Retransmit mode, the full flag is
determined based on a comparison of the write pointer to the
"marked" location. This differs from normal mode where the full
flag is determined based on a comparison of the write pointer to
the read pointer.
Empty Flag (/EF(/OR))
This is a dual-purpose pin. In the IDT Standard mode, the Empty
Flag (/EF) function is selected. When the FIFO is empty, /EF will
go LOW, inhibiting further read operations. When /EF is HIGH, the
FIFO is not empty. In FWFT mode, the Output Ready (/OR) function is
selected. /OR goes LOW at the same time that the first word written
to an empty FIFO appears valid on the outputs. /OR stays LOW after
the RCLK LOW to HIGH transition that shifts the last word from the
FIFO memory to the outputs. /OR goes HIGH only with a true read
(RCLK with /REN=LOW). The previous data stays at the outputs,
indicating the last word was read. Further data reads are inhibited
until /OR goes LOW again. /EF(/OR) is synchronous and updated on
the rising edge of RCLK. In IDT Standard mode, /EF is a double
register-buffered output. In FWFT mode, /OR is a triple
register-buffered output.
Programmable Almost-Full Flag (/PAF)
The Programmable Almost-Full flag (/PAF) will go LOW when the FIFO
reaches the almost-full condition. The offset from the full
condition, which defines the point at which the FIFO device is
"almost" full, is programmable. When the FIFO memory device 100 is
in Retransmit mode, the programmable almost full flag is determined
based on a comparison of the write pointer to the "marked"
location. This differs from normal mode where the almost full flag
is determined based on a comparison of the write pointer to the
read pointer.
Programmable Almost-Empty Flag (/PAE)
The Programmable Almost-Empty flag (/PAE) will go LOW when the FIFO
device reaches the almost-empty condition. In the IDT Standard
mode, /PAE will go LOW when there are n words or less in the FIFO.
The offset "n" is the empty offset value. This empty offset value
is maintained at a default value until overwritten by a
programmable value.
Echo Read Clock (ERCLK)
The Echo Read Clock output is provided in both HSTL and LVTTL
modes, selectable via HSTL. The ERCLK is a free-running clock
output, and will always follow the RCLK input regardless of /REN
and /RCS. The ERCLK output follows the RCLK input with an
associated delay. This delay provides the user with a more
effective read clock source when reading data from the Qn outputs.
This is especially helpful at high speeds when variables within the
device may cause changes in the data access times. These variations
in access time may be caused by ambient temperature, supply
voltage, or device characteristics. The ERCLK output also
compensates for trace length delays between the Qn data outputs and
receiving device inputs. Any variations affecting the data access
time will also have a corresponding effect on the ERCLK output
produced by the FIFO device. Therefore, the ERCLK output level
transitions should always be at the same position in time relative
to the data outputs. ERCLK is guaranteed by design to be slower
than the slowest data output (Qn). FIGS. 4, 27 and 28 of the
aforementioned U.S. application Ser. No. 60/314,393 illustrate
additional timing aspects related to the Echo Read Clock.
Echo Read Enable (/EREN)
The Echo Read Enable output is provided in both HSTL and LVTTL
modes, selectable via HSTL. The /EREN output is provided to be used
in conjunction with the ERCLK output and provides the reading
device with a more effective scheme for reading data from the Qn
output port at high speeds. A rising edge of RCLK will cause /EREN
to go active (LOW) if both /REN and /RCS are active (LOW). /EREN is
an ANDed function of /RCS and /REN. If the FIFO device is empty,
/EREN will be held high.
Referring now to FIG. 2, a block diagram of a FIFO memory device
110 according to another embodiment of the present invention will
be described. In particular, FIG. 2 illustrates a data path of a
FIFO memory device 110 that utilizes a preferred quad arrangement
of memory devices therein. This quad arrangement of memory devices
enables the FIFO memory device 110 to efficiently support any
combination of DDR or SDR write modes with any combination of DDR
or SDR read modes. The quad arrangement is illustrated as
comprising a first pair of memory devices 150a and 150b, shown as
AH and AL, and a second pair of memory devices 160a and 160b, shown
as BH and BL. According to one preferred aspect of this embodiment,
each of the memory devices AH, AL, BH and BL within the quad
arrangement may constitute a quad-port cache memory device. Each
quad-port cache memory device may have a data capacity of 1.31M
SRAM cells (i.e., 1,310,720 SRAM cells). This data capacity for
each quad-port cache may be achieved with four (4) blocks of memory
cells, each having a capacity of 516.times.640 (512 rows+4
redundant rows), and two blocks of column redundancy memory
(516.times.160 each).
Additional aspects of these preferred quad-port cache memory
devices are more fully described in commonly assigned U.S. Pat. No.
6,546,461, the disclosure of which is hereby incorporated herein by
reference. Each of the four blocks of memory cells within a memory
device (AH, AL, BH, BL) may be constructed as side-by-side pairs of
the quad-port memory devices illustrated by FIGS. 1 4 of the '461
patent, with each cache in each pair having a width of 160 bits
(N=40). In particular, each memory device AH, AL, BH and BL may
include four pairs of quad-port memory devices (e.g., QPCACHE0 7)
coupled to four (4) blocks of 516.times.640 SRAM cells. These
quad-port memory devices may include a data input register, a
multiplexer and an output register. As illustrated by FIG. 3 of the
'461 patent, the data input register may have an input electrically
coupled to a first port of the quad-port cache memory device and an
output electrically coupled to a second port of the quad-port cache
memory device. The multiplexer is responsive to at least one select
signal and has a first input electrically coupled to the output of
the data input register and a second input electrically coupled to
a third port of the quad-port cache memory device. The output
register has an input electrically coupled to an output of the
multiplexer and an output electrically coupled to a fourth port of
the quad-port cache memory device.
The FIFO memory device 110 of FIG. 2 also includes a clock control
circuit 120 that is responsive to the read clock signal RCLK and
write clock signal WCLK. These clock signals RCLK and WCLK may be
free-running and typically represent externally generated clock
signals. The clock control circuit 120 is also illustrated as being
responsive to control signals BM (bus-matching), IW (input-width)
and OW (output-width), the active low write single data rate signal
(/WSDR) and the active low read single data rate signal (/RSDR).
The function of these signals is more fully described above with
respect to the FIFO memory device 100 of FIG. 1. The clock control
circuit 120 generates read and write counter clock signals RCNTRCLK
and WCNTRCLK as internal read and write clock signals that, when
active, are in-sync with the read and write clock signals RCLK and
WCLK, respectively. The read and write counter clock signals
RCNTRCLK and WCNTRCLK are typically not free-running. The clock
control circuit 120 also generates internal read and write clock
signals that are provided to each of the pair of memory devices
150a, 150b and 160a, 160b in the quad arrangement. These internal
read and write clock signals are illustrated as WCLK_AH, RCLK_AH,
WCLK_AL, RCLK_AL, WCLK_BH, RCLK_BH and WCLK_BL, RCLK_BL. These
internal read and write clock signals may be generated using read
and write clock control circuits having multi-bit counters therein,
such as those illustrated in the aforementioned U.S. application
Ser. No. 60/314,393. However, other techniques for generating
internal clock signals that do not require the use of counters may
also be used. As illustrated and described more fully hereinbelow
with respect to FIGS. 3 4, the data path of FIG. 2 also includes
write control circuitry and read control circuitry. According to a
preferred aspect of the data path, the write control circuitry and
read control circuitry comprise an input multiplexer 130 (shown as
DIN_MUX) and an output multiplexer 170 (shown as DOUT_MUX),
respectively. Both the input and output multiplexers 130 and 170
perform bus matching functions and enable any combination of x4N,
x2N and xN data widths at the input port D0-Dn and output port Q0
Qn. These input and output multiplexers 130 and 170 are shown as
being directly responsive to the write counter clock WCNTRCLK and
read counter clock RCNTRCLK signals.
When the FIFO memory device 110 of FIG. 2 is disposed in a x40 DDR
write mode, the internal write clock signals WCLK_AH, WCLK_AL,
WCLK_BH and WCLK_BL that are provided to the quad arrangement of
memory devices 150a, 150b and 160a, 160b, respectively, will be
generated in-sync with rising and falling edges of the write
counter clock signal WCNTRCLK. In particular, each leading and
trailing edge of two (2) consecutive cycles of the write counter
clock signal WCNTRCLK will trigger a leading edge of a respective
cycle of WCLK_AH, WCLK_AL, WCLK_BH and WCLK_BL. This aspect of the
clock control circuit 120 is illustrated by TABLE 1, where the two
consecutive cycles of the write counter clock signal WCNTRCLK are
illustrated as WCLK1/2, /WCLK1/2, WCLK2/2 and IWCLK2/2.
Alternatively, when the FIFO memory device 110 is disposed in a x20
DDR write mode, the internal write clock signals WCLK_AH, WCLK_AL,
WCLK_BH and WCLK_BL will be generated in-sync with consecutive
trailing edges of the write counter clock signal WCNTRCLK. Thus,
each trailing edge of four (4) consecutive cycles of the write
counter clock signal WCNTRCLK will trigger a leading edge of a
respective cycle of WCLK_AH, WCLK_AL, WCLK_BH and WCLK_BL. This
aspect of the clock control circuit 120 is also illustrated by
TABLE 1, where the trailing edges of the four consecutive cycles of
the write counter clock signal WCNTRCLK are illustrated as
/WCLK1/4, /WCLK2/4, /WCLK3/4 and /WCLK4/4. Furthermore, when the
FIFO memory device 110 is disposed in a x10 DDR write mode, the
internal write clock signals WCLK_AH, WCLK_AL, WCLK_BH and WCLK_BL
will be generated in-sync with trailing edges of every other cycle
of the write counter clock signal WCNTRCLK. Thus, each trailing
edge of every one of eight (8) consecutive cycles of the write
counter clock signal WCNTRCLK will trigger a leading edge of a
respective cycle of WCLK_AH, WCLK_AL, WCLK_BH and WCLK_BL. In TABLE
1, the trailing edges of every other one of eight consecutive
cycles of the write counter clock signal WCNTRCLK are illustrated
as /WCLK2/8, /WCLK4/8, /WCLK6/8 and /WCLK8/8.
TABLE-US-00001 TABLE 1 DDR40 DDR20 DDR10 SDR40 SDR20 SDR10 WCLK_AH
WCLK1/2 /WCLK1/4 /WCLK2/8 WCLK1/4 WCLK2/8 WCLK4/16 WCLK_AL /WCLK1/2
/WCLK2/4 /WCLK4/8 WCLK2/4 WCLK4/8 WCLK8/16 WCLK_BH WCLK2/2 /WCLK3/4
/WCLK6/8 WCLK3/4 WCLK6/8 WCLK12/16 WCLK_BL /WCLK2/2 /WCLK4/4
/WCLK8/8 WCLK4/4 WCLK8/8 WCLK16/16
In contrast, when the FIFO memory device 110 is disposed in a x40
SDR write mode, the internal write clock signals WCLK_AH, WCLK_AL,
WCLK_BH and WCLK_BL will be generated in-sync with leading edges of
four (4) consecutive cycles of the write counter clock signal
WCNTRCLK. In TABLE 1, the leading edges of four consecutive cycles
of the write counter clock signal WCNTRCLK are illustrated as
WCLK1/4, WCLK2/4, WCLK3/4 and WCLK4/4. When the FIFO memory device
110 is disposed in a x20 SDR write mode, the internal write clock
signals WCLK_AH, WCLK_AL, WCLK_BH and WCLK_BL will be generated
in-sync with leading edges of every other one of eight (8)
consecutive cycles of the write counter clock signal WCNTRCLK. In
TABLE 1, the leading edges of every other one of eight consecutive
cycles of the write counter clock signal WCNTRCLK are illustrated
as WCLK2/8, WCLK4/8, WCLK6/8 and WCLK8/8. Finally, when the FIFO
memory device 110 is disposed in a x10 SDR write mode, the internal
write clock signals WCLK_AH, WCLK_AL, WCLK_BH and WCLK_BL will be
generated in-sync with leading edges of every fourth one of sixteen
(16) consecutive cycles of the write counter clock signal WCNTRCLK.
In TABLE 1, the leading edges of every fourth one of sixteen
consecutive cycles of the write counter clock signal WCNTRCLK are
illustrated as WCLK4/16, WCLK8/16, WCLK12/16 and WCLK16/16.
The clock control circuit 120 also generates the internal read
clock signals RCLK_AH, RCLK_AL, RCLK_BH and RCLK_BL from the read
counter clock signal RCNTRCLK. As illustrated by TABLE 2, which is
similar to TABLE 1, depending on the particular read mode (DDR or
SDR) and read bus matching characteristics, the leading edges of
each cycle of the internal read clock signals RCLK_AH, RCLK_AL,
RCLK_BH and RCLK_BL may be generated off leading or trailing edges
of particular cycles of the read counter clock signal RCNTRCLK.
TABLE-US-00002 TABLE 2 DDR40 DDR20 DDR10 SDR40 SDR20 SDR10 RCLK_AH
RCLK1/2 /RCLK1/4 /RCLK2/8 RCLK1/4 RCLK2/8 RCLK4/16 RCLK_AL /RCLK1/2
/RCLK2/4 /RCLK4/8 RCLK2/4 RCLK4/8 RCLK8/16 RCLK_BH RCLK2/2 /RCLK3/4
/RCLK6/8 RCLK3/4 RCLK6/8 RCLK12/16 RCLK_BL /RCLK2/2 /RCLK4/4
/RCLK8/8 RCLK4/4 RCLK8/8 RCLK16/16
The write control circuitry associated with the FIFO memory device
110 of FIG. 2 preferably includes an input multiplexer 130 that
operates to route write data to each of the memory devices in the
quad arrangement. As illustrated by FIG. 3, the input multiplexer
130 includes an input port that receives data from an input bus,
shown as D[39:0], and a plurality of output ports. These output
ports, which include WDA[79:40], WDA[39:0] and WDB[79:40],
WDB[39:0], are coupled to the quad arrangement of memory devices
150a and 150b, shown as AH and AL, and memory devices 160a and
160b, shown as BH and BL. The input multiplexer 130 also comprises
an input register 132 that receives data from the input bus and a
pair of master latches 134a and 134b having inputs that are coupled
to an output of the input register 132. As illustrated, the master
latches 134a and 134b are responsive to a first pair of
complementary internal clock signals DPCLK and DPCLKB that are
preferably generated from the external write clock signal WCLK. The
first pair of complementary internal clock signals DPCLK and DPCLKB
may have timing that is similar to (or the same as) the
complementary write counter clock signals WCNTRCLK and WCNTRCLKB,
respectively. In particular, up until the point the FIFO is full,
the internal clock signals DPCLK and DPCLKB may have the same
timing as the write counter clock signals WCNTRCLK and WCNTRCLKB
and once the FIFO is full, the write counter clock signals WCNTRCLK
and WCNTRCLKB are suspended while the internal clock signals DPCLK
and DPCLKB continue to run. The outputs of the master latches 134a
and 134b are electrically coupled to input ports DA[39:0] and
DB[39:0] associated with write bus matching circuitry 138. The
write bus matching circuitry 138 is also responsive to the write
counter clock signal WCNTRCLK, the active low write single data
rate signal /WSDR, and the bus matching control signals BM, IW and
OW.
As illustrated by TABLE 3, the write bus matching circuitry 138
routes write data received at the pair of input ports DA[39:0] and
DB[39:0] to a slave latch 142 that passes this write data to the
plurality of output ports WDA[79:40], WDA[39:0], WDB[79:40] and
WDB[39:0]. The slave latch 142 is responsive to a pair of multi-bit
data input latch signals DINLDA[7:0] and DINLDB[7:0]. These data
input latch signals may be generated by a clock control circuit 136
that is internal to the input multiplexer 130. This clock control
circuit 136 is responsive to the write counter clock signal
WCNTRCLK and the write single data rate signal /WSDR. The timing of
the data input latch signals DINLDA[7:0] and DINLDB[7:0], in
response to the write counter clock signal WCNTRCLK and the write
single data rate signal /WSDR, will be described more fully with
respect to the timing diagrams of FIGS. 5 and 7.
The write bus matching circuitry 138 and the slave latch 142
collectively perform the bus matching operations illustrated by
TABLES 3 and 4. In particular, these tables illustrate that during
DDR40 write mode, 40 bits of data from the input port DA[39:0] will
be written into memory device AH via output port WDA[79:40]. This
writing operation will occur in-sync with a leading edge of a first
of two consecutive cycles of the write counter clock signal
WCNTRCLK (WCLK1/2). Following this, 40 bits of data from the input
port DB[39:0] will be written into memory device AL via output port
WDA[39:0]. This writing operation will occur in-sync with a
trailing edge of the first of two cycles of the write counter clock
signal WCNTRCLK (/WCLK1/2). Next, 40 bits of data from the input
port DA[39:0] will be written into memory device BH via output port
WDB[79:40]. This writing operation will occur in-sync with a
leading edge of a second of the two consecutive cycles of the write
counter clock signal WCNTRCLK (WCLK2/2). Finally, 40 bits of data
from the input port DB[39:0] will be written into memory device BL
via output port WDB[39:0]. This writing operation will occur
in-sync with a trailing edge of a second of the two consecutive
cycles of the write counter clock signal WCNTRCLK (/WCLK2/2). These
tables also illustrate the bus matching and write timing associated
with all other combinations of write modes. In particular, TABLE 3
indicates that during any combination of single data rate write
mode, only the first port DA[39:0] of the two input ports to the
write bus matching circuitry 138 will be utilized.
TABLE-US-00003 TABLE 3 OUTPUT PORT DDR40 DDR20 DDR10 SDR40 SDR20
SDR10 AH WDA[79:70] DA[39:30] DA[19:10] DA[9:0] DA[39:30] DA[19:10]
DA[9:0] WDA[69:60] DA[29:20] DA[9:0] DB[9:0] DA[29:20] DA[9:0]
DA[9:0] WDA[59:50] DA[19:10] DB[19:10] DA[9:0] DA[19:10] DA[19:10]
DA[9:0] WDA[49:40] DA[9:0] DB[9:0] DB[9:0] DA[9:0] DA[9:0] DA[9:0]
AL WDA[39:30] DB[39:30] DA[19:10] DA[9:0] DA[39:30] DA[19:10]
DA[9:0] WDA[29:20] DB[29:20] DA[9:0] DB[9:0] DA[29:20] DA[9:0]
DA[9:0] WDA[19:10] DB[19:10] DB[19:10] DA[9:0] DA[19:10] DA[19:0]
DA[9:0] WDA[9:0] DB[9:0] DB[9:0] DB[9:0] DA[9:0] DA[9:0] DA[9:0] BH
WDB[79:70] DA[39:30] DA[19:10] DA[9:0] DA[39:30] DA[19:10] DA[9:0]
WDB[69:60] DA[29:20] DA[9:0] DB[9:0] DA[29:20] DA[9:0] DA[9:0]
WDB[59:50] DA[19:10] DB[19:10] DA[9:0] DA[19:10] DA[19:10] DA[9:0]
WDB[49:40] DA[9:0] DB[9:0] DB[9:0] DA[9:0] DA[9:0] DA[9:0] BL
WDB[39:30] DB[39:30] DA[19:10] DA[9:0] DA[39:30] DA[19:10] DA[9:0]
WDB[29:20] DB[29:20] DA[9:0] DB[9:0] DA[29:20] DA[9:0] DA[9:0]
WDB[19:10] DB[19:10] DB[19:10] DA[9:0] DA[19:10] DA[19:10] DA[9:0]
WDB[9:0] DB[9:0] DB[9:0] DB[9:0] DA[9:0] DA[9:0] DA[9:0]
TABLE-US-00004 TABLE 4 OUTPUT PORT DDR40 DDR20 DDR10 SDR40 SDR20
SDR10 AH WDA[79:70] WCLK1/2 WCLK1/4 WCLK1/8 WCLK1/4 WCLK1/8
WCLK1/16 WDA[69:60] WCLK1/2 WCLK1/4 /WCLK1/8 WCLK1/4 WCLK1/8
WCLK2/16 WDA[59:50] WCLK1/2 /WCLK1/4 WCLK2/8 WCLK1/4 WCLK2/8
WCLK3/16 WDA[49:40] WCLK1/2 /WCLK1/4 /WCLK2/8 WCLK1/4 WCLK2/8
WCLK4/16 AL WDA[39:30] /WCLK1/2 WCLK2/4 WCLK3/8 WCLK2/4 WCLK3/8
WCLK5/16 WDA[29:20] /WCLK1/2 WCLK2/4 /WCLK3/8 WCLK2/4 WCLK3/8
WCLK6/16 WDA[19:10] /WCLK1/2 /WCLK2/4 WCLK4/8 WCLK2/4 WCLK4/8
WCLK7/16 WDA[9:0] /WCLK1/2 /WCLK2/4 /WCLK4/8 WCLK2/4 WCLK4/8
WCLK8/16 BH WDB[79:70] WCLK2/2 WCLK3/4 WCLK5/8 WCLK3/4 WCLK5/8
WCLK9/16 WDB[69:60] WCLK2/2 WCLK3/4 /WCLK5/8 WCLK3/4 WCLK5/8
WCLK10/16 WDB[59:50] WCLK2/2 /WCLK3/4 WCLK6/8 WCLK3/4 WCLK6/8
WCLK11/16 WDB[49:40] WCLK2/2 /WCLK3/4 /WCLK6/8 WCLK3/4 WCLK6/8
WCLK12/16 BL WDB[39:30] /WCLK2/2 WCLK4/4 WCLK7/8 WCLK4/4 WCLK7/8
WCLK13/16 WDB[29:20] /WCLK2/2 WCLK4/4 /WCLK7/8 WCLK4/4 WCLK7/8
WCLK14/16 WDB[19:10] /WCLK2/2 /WCLK4/4 WCLK8/8 WCLK4/4 WCLK8/8
WCLK15/16 WDB[9:0] /WCLK2/2 /WCLK4/4 /WCLK8/8 WCLK4/4 WCLK8/8
WCLK16/16
The read control circuitry associated with the FIFO memory device
110 of FIG. 2 preferably includes an output multiplexer 170 that
operates to route read data received from each of the memory
devices in the quad arrangement. As illustrated by FIG. 4, the
output multiplexer 170 includes read bus matching circuitry 172
having a plurality of input data ports QPA[79:40], QPA[39:0],
QPB[79:40] and QPB[39:0] that receive read data from the memory
devices AH, AL, BH and BL within the quad arrangement. The bus
matching circuitry 172 is also responsive to the read counter clock
RCNTRCLK, the bus matching control signals BM, IW and OW and the
active low read signal data rate signal /RSDR. As illustrated by
TABLE 5, the binary value of the bus matching control signals
establish the routing configuration of the input and output
multiplexers 130 and 170.
TABLE-US-00005 TABLE 5 BM IW OW Write Port Width Read Port Width L
L L .times.40 .times.40 H L L .times.40 .times.20 H L H .times.40
.times.10 H H L .times.20 .times.40 H H H .times.10 .times.40
The read bus matching circuitry 172 also has input data ports that
receive a unit of marked read data (MKDATA, MKDATAB) from a pair of
mark registers 174a and 174b when the FIFO memory device 110 is
disposed in a retransmit from mark (RTM) DDR read mode. As
illustrated, these mark registers 174a and 174b are responsive to a
pair of mark data clock signals MKDCLK and MKDCLKB that may be
derived from the read counter clock signal RCNTRCLK. The timing of
these mark data clock signals MKDCLK and MKDCLKB during normal read
operations is more fully illustrated by the timing diagrams of
FIGS. 6A 6B.
The output ports QPOUTA and QPOUTB of the read bus matching
circuitry 172 are coupled to respective first and second output
registers 182a and 182b. These output registers 182a and 182b have
outputs that are electrically coupled to output pins Q[39:0] of the
FIFO memory device 110, shown as output pad 184. The outputs of the
first and second output registers 182a and 182b are also fed back
to the inputs of the mark registers 174a and 174b so that these
mark registers always retain the currently available read data.
However, in response to an active mark signal MARK during a x40,
x20 or x10 DDR read mode, the unit of marked read data is fed from
the first and second output registers 182a and 182b to the mark
registers 174a and 174b and held until a retransmit request is
received. During SDR read mode, only one of the pair of mark
registers is active. As illustrated and described more fully
hereinbelow with respect to the timing diagram of FIGS. 6A 6B, the
mark data clock signals MKDCLK and MKDCLKB are suspended once an
active mark request has been received in order to prevent the
marked data from being overwritten by subsequent read data on the
next cycle of the read clock signal RCLK.
Referring still to the output multiplexer 170 of FIG. 4, a redirect
multiplexer 178 is provided to redirect the output port QPOUTB of
the read bus matching circuitry 172 to the first output register
182a, when the FIFO memory device 110 is disposed in an SDR read
mode and the second output register 182b is held inactive. The
first and second output registers 182a and 182b are responsive to a
pair of pad read clock signals PADRCLK and PADRCLKB. The timing of
these pad read clock signals is more fully illustrated by FIGS. 6A
6B and 8. The mark data clock signals MKDCLK and MKDCLKB, the pad
read clock signals PADRCLK and PADRCLKB and the single data rate
select signal SDR_SEL are generated by a clock control circuit 176.
This clock control circuit is responsive to the read counter clock
signal RCNTRCLK and the active low read single data rate signal
/RSDR. The binary value of the single data rate select signal
SDR_SEL can be used to control whether the output port QPOUTA or
QPOUTB is directed to the first output register 182a when the FIFO
memory device 100 is disposed in the SDR read mode.
As illustrated by TABLES 6 and 7, during the DDR read mode, read
data from the memory device AH, which is received at the input port
QPA[79:40] of the read bus matching circuitry 172, passes to the
output port QPOUTA, and is latched in the first output register
182a in-sync with a leading edge of a first of two consecutive
cycles of the read counter clock signal RCNTRCLK. During the next
half cycle of the read counter clock signal RCNTRCLK, read data
from the memory device AL, which is received at the input port
QPA[39:0] of the read bus matching circuitry 172 and passes to the
output port QPOUTB, is latched in the second output register 182b
in-sync with a trailing edge of the first of two consecutive cycles
of the read counter clock signal RCNTRCLK. During the second cycle
of the read counter clock signal RCNTRCLK, read data from the
memory device BH, which is received at the input port QPB[79:40]
and passes to the output port QPOUTA, is latched in the first
output register 182a in-sync with a leading edge of a second of two
consecutive cycles of the read counter clock signal RCNTRCLK.
Finally, during the second half of the second cycle, read data from
the memory device BL, which is received at the input port QPB[39:0]
and passes to the output port QPOUTB, is latched in the second
output register 182b in-sync with a trailing edge of the second of
two consecutive cycles of the read clock signal RCNTRCLK. TABLES 6
and 7 also illustrate timing and bus matching for all other read
mode operations. During SDR read mode, all data provided to the
output port QPOUTB is routed through the redirect multiplexer 178
to the first output register 182a and the second output register
182b is held inactive (PADRCLKB is held low).
TABLE-US-00006 TABLE 6 INPUT PORT DDR40 DDR20 DDR10 SDR40 SDR20
SDR10 AH QPA[79:70] QPOUTA[39:30] QPOUTA[19:10] QPOUTA[9:0]
QPOUTA[39:30] QPOUTA- [19:10] QPOUTA[9:0] QPA[69:60] QPOUTA[29:20]
QPOUTA[9:0] QPOUTB[9:0] QPOUTA[29:20] QPOUTA[9:0- ] QPOUTB[9:0]
QPA[59:50] QPOUTA[19:10] QPOUTB[19:10] QPOUTA[9:0] QPOUTA[19:10]
QPOUTB[1- 9:10] QPOUTA[9:0] QPA[49:40] QPOUTA[9:0] QPOUTB[9:0]
QPOUTB[9:0] QPOUTA[9:0] QPOUTB[9:0] QP- OUTB[9:0] AL QPA[39:30]
QPOUTB[39:30] QPOUTA[19:10] QPOUTA[9:0] QPOUTB[39:30] QPOUTA-
[19:10] QPOUTA[9:0] QPA[29:20] QPOUTB[29:20] QPOUTA[9:0]
QPOUTB[9:0] QPOUTB[29:20] QPOUTA[9:0- ] QPOUTB[9:0] QPA[19:10]
QPOUTB[19:0] QPOUTB[19:10] QPOUTA[9:0] QPOUTB[19:10] QPOUTB[19- :0]
QPOUTA[9:0] QPA[9:0] QPOUTB[9:0] QPOUTB[9:0] QPOUTB[9:0]
QPOUTB[9:0] QPOUTB[9:0] QPOU- TB[9:0] BH QPB[79:70] QPOUTA[39:30]
QPOUTA[19:10] QPOUTA[9:0] QPOUTA[39:30] QPOUTA- [19:10] QPOUTA[9:0]
QPB[69:60] QPOUTA[29:20] QPOUTA[9:0] QPOUTB[9:0] QPOUTA[29:20]
QPOUTA[9:0- ] QPOUTB[9:0] QPB[59:50] QPOUTA[19:10] QPOUTB[19:10]
QPOUTA[9:0] QPOUTA[19:10] QPOUTB[1- 9:10] QPOUTA[9:0] QPB[49:40]
QPOUTA[9:0] QPOUTB[9:0] QPOUTB[9:0] QPOUTA[9:0] QPOUTB[9:0] QP-
OUTB[9:0] BL QPB[39:30] QPOUTB[39:30] QPOUTA[19:10] QPOUTA[9:0]
QPOUTB[39:30] QPOUTA- [19:10] QPOUTA[9:0] QPB[29:20] QPOUTB[29:20]
QPOUTA[9:0] QPOUTB[9:0] QPOUTB[29:20] QPOUTA[9:0- ] QPOUTB[9:0]
QPB[19:10] QPOUTB[19:10] QPOUTB[19:10] QPOUTA[9:0] QPOUTB[19:10]
QPOUTB[1- 9:10] QPOUTA[9:0] QPB[9:0] QPOUTB[9:0] QPOUTB[9:0]
QPOUTB[9:0] QPOUTB[9:0] QPOUTB[9:0] QPOU- TB[9:0]
TABLE-US-00007 TABLE 7 OUTPUT PORT DDR40 DDR20 DDR10 SDR40 SDR20
SDR10 AH QPA[79:70] RCLK1/2 RCLK1/4 RCLK1/8 RCLK1/4 RCLK1/8
RCLK1/16 QPA[69:60] RCLK1/2 RCLK1/4 /RCLK1/8 RCLK1/4 RCLK1/8
RCLK2/16 QPA[59:50] RCLK1/2 /RCLK1/4 RCLK2/8 RCLK1/4 RCLK2/8
RCLK3/16 QPA[49:40] RCLK1/2 /RCLK1/4 /RCLK2/8 RCLK1/4 RCLK2/8
RCLK4/16 AL QPA[39:30] /RCLK1/2 RCLK2/4 RCLK3/8 RCLK2/4 RCLK3/8
RCLK5/16 QPA[29:20] /RCLK1/2 RCLK2/4 /RCLK3/8 RCLK2/4 RCLK3/8
RCLK6/16 QPA[19:10] /RCLK1/2 /RCLK2/4 RCLK4/8 RCLK2/4 RCLK4/8
RCLK7/16 QPA[9:0] /RCLK1/2 /RCLK2/4 /RCLK4/8 RCLK2/4 RCLK4/8
RCLK8/16 BH QPB[79:70] RCLK2/2 RCLK3/4 RCLK5/8 RCLK3/4 RCLK5/8
RCLK9/16 QPB[69:60] RCLK2/2 RCLK3/4 /RCLK5/8 RCLK3/4 RCLK5/8
RCLK10/16 QPB[59:50] RCLK2/2 /RCLK3/4 RCLK6/8 RCLK3/4 RCLK6/8
RCLK11/16 QPB[49:40] RCLK2/2 /RCLK3/4 /RCLK6/8 RCLK3/4 RCLK6/8
RCLK12/16 BL QPB[39:30] /RCLK2/2 RCLK4/4 RCLK7/8 RCLK4/4 RCLK7/8
RCLK13/16 QPB[29:20] /RCLK2/2 RCLK4/4 /RCLK7/8 RCLK4/4 RCLK7/8
RCLK14/16 QPB[19:10] /RCLK2/2 /RCLK4/4 RCLK8/8 RCLK4/4 RCLK8/8
RCLK15/16 QPB[9:0] /RCLK2/2 /RCLK4/4 /RCLK8/8 RCLK4/4 RCLK8/8
RCLK16/16
Referring now to the timing diagram of FIG. 5, x40 DDR write
operations may commence by setting the external active low write
chip select EX_WCSL (/WCS) LOW and then setting the external active
low write enable signal EX_WENL (/WEN) LOW. As described above, the
receipt of a free-running external write clock signal EX_WCLK can
be used to generate true and complementary internal write counter
clock signals WCNTRCLK and WCNTRCLKB that control, among other
things, the timing of write operations within the FIFO memory
devices 100 and 110. As illustrated, the leading (e.g., rising)
edge of every other cycle of the internal write counter clock
signal WCNTRCLK triggers a leading edge of the write clock signal
associated with memory device AH (WCLK_AH). The trailing (e.g.,
falling) edge of every other cycle of the internal write counter
clock signal WCNTRCLK triggers a leading edge of the write clock
signal associated with memory device AL (WCLK_AL). Write clock
signals WCLK_BH and WCLK_BL are also generated in a similar
manner.
The leading edge of the internal write counter clock signal
WCNTRCLK that triggered a leading edge of write clock signal
WCLK_AH also triggers the leading edges of four data input latch
signals DINLDA[7:4]. This operation to generate the data input
latch signals is performed by the clock control circuit 136
illustrated by FIG. 3. These data input latch signals DINLDA[7:4]
cause the slave latch 142 to latch four sets of x10 data and
provide this write data to the memory device AH via the output port
WDA[79:40] of the slave latch 142. This write data is illustrated
as DIN[39:0]. The trailing edge of the internal write counter clock
signal WCNTRCLK that triggered a leading edge of write clock signal
WCLK_AL also triggers the leading edges of another four data input
latch signals DINLDA[3:0]. These data input latch signals
DINLDA[3:0] cause the slave latch 142 to latch four sets of x10
data and provide this data to the memory device AL via the output
port WDA[39:0] of the slave latch 142. Similarly, the leading edges
of WCLK_BH and WCLK_BL trigger the generation of active data input
latch signals DINLDB[7:4] and DINLDB[3:0], respectively.
Referring now to the timing diagram of FIGS. 6A 6B, x40 DDR read
operations may commence by setting the external active low read
chip select EX_RCSL (/RCS) LOW and setting the external active low
read enable signal EX_RENL (/REN) LOW. The receipt of a
free-running external read clock signal EX_RCLK can be used to
generate true and complementary internal read counter clock signals
RCNTRCLK and RCNTRCLKB (not shown) that control, among other
things, the timing of read operations within the FIFO memory
devices 100 and 110. As illustrated, the leading (e.g., rising)
edge of every other cycle of the external read clock signal EX_RCLK
triggers a leading edge of the internal read counter clock signal
RCNTRCLK, which in turn triggers the leading edge of the read clock
signal associated with memory device AH (RCLK_AH). The trailing
(e.g., falling) edge of every other cycle of the external read
clock signal EX_RCLK indirectly triggers a leading edge of the read
clock signal associated with memory device AL (RCLK_AL). Read clock
signals RCLK_BH and RCLK_BL are also generated in a similar
manner.
The clock control circuit 176 illustrated by FIG. 4 also generates
a first pulse train as an active high pad read clock signals
PADRCLK in-sync with leading edges of the external read clock
signal EX_RCLK and a second pulse train of complementary active
high pad read clock signals PADRCLKB in-sync with trailing edges of
the external read clock signal EX_RCLK. These pad read clock
signals operate to latch read data into the first and second output
registers 182a and 182b. The latching of this read data results in
an output data Q[39:0] stream that changes in response to each
leading and trailing edge of the external read clock signal
EX_RCLK. The clock control circuit 176 also operates to generate a
pair of complementary mark data clock signals MKDCLK and MKDCLKB,
which are provided to separate mark registers 174a and 174b. These
mark data clock signals operate to latch a unit (i.e., pairs) of
marked read data MKDATA[39:0] and MKDATAB[39:0] into the mark
registers.
The timing diagrams of FIGS. 6A 6B also illustrate the external
active high mark signal EX_MARK and the external active low
retransmit signal EX_RTL (/RT). In particular, as illustrated by
FIG. 6A, the rising edge of the mark signal EX_MARK shortly after
the rising edge of a cycle of EX_RCLK that resulted in the latching
of read data Q[39:0]=69 into the first output register 182a, will
trigger the latching of that same data Q[39:0]=69 into the first
mark register 174a followed by the latching of the following data
Q[39:0]=70 into the second mark register 174b. Thereafter, while
the external mark signal EX_MARK remains high, no subsequent read
data is provided to the mark registers. This enables the mark
registers to immediately provide the first marked unit of read data
to the output Q[39:0] (via the read bus matching circuitry 172) in
response to an active low retransmit signal /RT. While the first
marked unit data is being provided without delay, the read pointer
within the FIFO memory device can be reset to the next read
location following the marked location and then the above described
read operations can proceed to read subsequent entries. Similarly,
as illustrated by the timing diagram of FIG. 6B, the rising edge of
the mark signal EX_MARK shortly after the falling edge of a cycle
of EX_RCLK that resulted in the latching of read data Q[39:0]=70
into the second output register 182b, will trigger the latching of
that same data Q[39:0]=70 into the second mark register 174b.
Thereafter, while the external mark signal EX_MARK remains high, no
subsequent read data is provided to the mark registers.
A combination of read control circuitry provided in part by the
clock control circuit 176 and components of the output multiplexer
170 may be used to mark data read from the FIFO memory device 110
in response to a trailing edge of a first cycle of an internal read
clock signal during the DDR read mode. The retransmit operations
performed by this circuitry may include retransmitting data in
pairs by commencing the retransmission with data previously read
from the FIFO memory device in response to a leading edge of the
first cycle of the read clock signal before following with the
marked read data that was originally read on the trailing edge of
the first cycle of the read clock signal.
The timing diagrams of FIGS. 7 8 are similar to the timing diagrams
of FIGS. 5 and 6A 6B, however, the write and read modes have been
changed from x40 DDR write and read to x10 SDR write and read. In
particular, FIG. 7 is a timing diagram that illustrates single data
rate write operations with x10 bus matching. As illustrated, four
consecutive internal write counter clock signals WCNTRCLK are
needed before a x40 write operation is performed to one of the
memory devices AH, AL, BH and BL. Each leading edge of the write
counter clock signal WCNTRCLK latches in 10 new bits of data from
the data input port DIN[9:0]. In response to each leading edge of
the write counter clock signal WCNTRCLK, the clock control circuit
136 of FIG. 3 generates a respective one of the sixteen (16) data
input latch signals DINLDA[7], DINLDA[6}, . . . , DINLDB[7], . . .
, DINLDB[0]. Four of these signals will need to be received by the
slave latch 142 in sequence before a x40 write operation can be
performed to the memory devices AH, AL, BH and BL.
FIG. 8 is a timing diagram that illustrates single data rate read
operations with x10 bus matching. As illustrated, four consecutive
external read clock signals EX_RCLK are needed before a x40 read
operation can be performed from the memory devices AH, AL, BH and
BL. Because the single data rate mode is active, the complementary
active high pad read clock signal PADRCLKB is not generated, which
means the second output register 182b remains inactive. Each
leading edge of the external read clock signal EX_RCLK triggers an
active high pulse on the pad read clock signal line PADRCLK and the
latching of x10 bits of new read data into the first output
register 182a and to the output port Q[9:0].
FIGS. 9A 9F illustrate further embodiments of the present invention
that utilize multiple independently operable FIFO memory devices on
a monolithic substrate (e.g., integrated circuit chip) to provide
various modes of operation. In particular, FIG. 9A illustrates an
integrated DDR/SDR flow control device 300a having a plurality of
FIFO memory devices therein that are integrated together on an
integrated circuit substrate. These plurality of FIFO memory
devices, which are shown as FIFO 0-FIFO 3 in the illustrated
embodiment, are collectively configured to support a quad FIFO mode
of operation at various capacities, with each FIFO configured to
operate independently of the other FIFOs. The integrated circuit
substrate is illustrated as including 40 input pins D[39:0] and 40
output pins Q[39:0], which are segmented into four groups of ten
pins. Each FIFO is illustrated as being responsive to a
corresponding write clock signal, shown as WCLKn, where n=0, 1, 2
or 3. These write clock signals WCLKn may be asynchronously timed
relative to each other. Each FIFO is also illustrated as being
responsive to a corresponding read clock signal, shown as RCLKn,
and these read clock signals RCLKn may also be asynchronously timed
relative to each other and relative to the write clock signals
WCLKn.
The active low control signals /WENn and /WCSn on the write side of
the substrate represent the write enable signals and write chip
select signals, respectively. The active low control signals /RENn,
/RCSn and /OEn on the read side of the substrate represent the read
enable signals, read chip select signals and output enable signals,
respectively. The read side of the substrate is also responsive to
a plurality of echo read clocks /ECLKn and echo read enable signals
/ERENn.
The flow control device 300a is illustrated as generating a
plurality of flag and other control signals that can support depth
cascading of multiple devices. On the write side of the device
300a, these flag related control signals include the full flag
signals /FFn, programmable almost-full flag signals /PAFn and input
ready signals /IRn. On the read side of the device 300a, these flag
related control signals include the empty flag signals /EFn,
programmable almost-empty flag signals /PAEn and output ready
signals /ORn. These control signals represent conventional FIFO
control signals, which are more fully described in the
aforementioned U.S. application Ser. No. 60/314,393. The use of
these control signals to support depth cascading is more fully
described in commonly assigned U.S. application Ser. No.
10/721,974, filed Nov. 24, 2003, the disclosure of which is hereby
incorporated herein by reference.
The quad mode may be achieved in the flow control device 300a by
setting a mode pin (MD1) high (e.g., to a logic 1 level) on an
integrated circuit package or chip carrier (not shown) containing
the monolithic substrate. When disposed in the quad mode, the
"input width" pins (IW[1 :0]) and "output width" pins (OW[1:0]) of
the packaged device are set to achieve x10 write and x10 read data
widths at the external data ports (D[9:0], D[19:10], D[29:20],
D[39:30] and Q[9:0], Q[19:10], Q[29:20], Q[39:30]), as shown in
TABLE 8. The settings on the write DDR pins (WDDR) and read DDR
pins (RDDR) of the packaged device control whether the internal bus
widths are x10 or x20 for a given FIFO. Accordingly, by setting the
pins WDDR and RDDR high for a respective FIFO, an internal bus word
width of x20 is achieved for both write and read operations. This
means that two external x10 write words will be clocked into the
device 300a on consecutive rising and falling edges of a respective
write clock signal WCLKn and processed internally as one x20 write
word. This dual data rate mode translates to a x80 internal write
bus operation when all FIFOs are disposed in a WDDR mode. (See,
e.g., TABLE 16). Similarly, when a FIFO is disposed in a RDDR mode,
one internal x20 read word from the FIFO will be clocked out of the
device 300a on consecutive rising and falling edges of a respective
read clock signal RCLKn as two x10 read words.
TABLE-US-00008 TABLE 8 External Word Internal Word QUAD MODE PIN
SETTINGS Width Width WDDR IW1 IW0 RDDR OW1 OW0 IN OUT IN OUT L L L
L L L 10 10 10 10 H L L L L L 10 10 20 10 L L L H L L 10 10 10 20 H
L L H L L 10 10 20 20
In FIG. 9B, an integrated DDR/SDR flow control device 300b is
illustrated that supports a dual FIFO mode of operation, with FIFOs
0 and 2 being active and FIFOs 1 and 3 being disabled. In the
device 300b, the mode pin (MD1) may be held low to set the
dual-FIFO mode of operation and the input width pin IW0 and output
width pin OW0 may be set high to reflect x20 external bus operation
at the write and read ports, respectively. This x20 external bus
operation translates into x40 internal bus operation in the write
path when the write DDR pin (WDDR) is set high and x40 internal bus
operation in the read path when the read DDR pin (RDDR) is set
high. The available configurations of the external and internal
word widths are illustrated more fully by TABLE 9.
TABLE-US-00009 TABLE 9 External Internal DUAL MODE PIN SETTINGS
Word Width Word Width WDDR IW1 IW0 RDDR OW1 OW0 IN OUT IN OUT L L L
L L L 10 10 10 10 L L L L L H 10 20 10 20 L L H L L L 20 10 20 10 L
L H L L H 20 20 20 20 H L L L L L 10 10 20 10 H L L L L H 10 20 20
20 H L H L L L 20 10 40 10 H L H L L H 20 20 40 20 L L L H L L 10
10 10 20 L L L H L H 10 20 10 40 L L H H L L 20 10 20 20 L L H H L
H 20 20 20 40 H L L H L L 10 10 20 20 H L L H L H 10 20 20 40 H L H
H L L 20 10 40 20 H L H H L H 20 20 40 40
In FIG. 9C, an integrated DDR/SDR flow control device 300c is
illustrated that supports a MUX mode of operation, with each
independent FIFO representing a respective queue. The device 300c
has four independent write ports and one common read port Q[39:0]
that may be configured to support x10, x20 and x40 word widths. The
output select signal OS[1:0] identifies which one of the four FIFOs
is to be read from during a respective read cycle. The MUX mode of
operation may be achieved by setting mode pin MD1 high and mode pin
MD0 low on a package containing a substrate that is configured to
support MUX, DEMUX and MULTI-Q modes. As illustrated by TABLE 10,
the maximum internal write word width is x20 when the DDR write
mode is selected. The maximum internal read word width is x80 when
the DDR read mode is selected, the read port is set to x40 and the
output width pins OW1 and OW0 are set high and low, respectively,
to reflect the x40 read port setting.
TABLE-US-00010 TABLE 10 External Word Internal Word MUX MODE PIN
SETTINGS Width Width WDDR IW1 IW0 RDDR OW1 OW0 IN OUT IN OUT L L L
L L L 10 10 10 10 L L L L L H 10 20 10 20 L L L L H L 10 40 10 40 H
L L L L L 10 10 20 10 H L L L L H 10 20 20 20 H L L L H L 10 40 20
40 L L L H L L 10 10 10 20 L L L H L H 10 20 10 40 L L L H H L 10
40 10 80 H L L H L L 10 10 20 20 H L L H L H 10 20 20 40 H L L H H
L 10 40 20 80
In FIG. 9D, an integrated DDR/SDR flow control device 300d is
illustrated that supports a DEMUX mode of operation, with each
independent FIFO representing a respective queue. The device 300d
has four independent read ports and one common write port D[39:0]
that may be configured to support x10, x20 and x40 word widths. The
input select signal IS[1:0] identifies which one of the four FIFOs
is to be written to during a respective write cycle. The DEMUX mode
of operation may be achieved by setting mode pin MD1 low and mode
pin MD0 low. As illustrated by TABLE 11, the maximum internal write
word width is x80 when the DDR write mode is selected, the write
port is set to x40 and the input pins IW1 and IW0 are set high and
low, respectively. The maximum internal read word width is x20 when
the DDR read mode is selected.
TABLE-US-00011 TABLE 11 External Word Internal Word DEMUX MODE PIN
SETTINGS Width Width WDDR IW1 IW0 RDDR OW1 OW0 IN OUT IN OUT L L L
L L L 10 10 10 10 L L H L L L 20 10 20 10 L H L L L L 40 10 40 10 H
L L L L L 10 10 20 10 H L H L L L 20 10 40 10 H H L L L L 40 10 80
10 L L L H L L 10 10 10 20 L L H H L L 20 10 20 20 L H L H L L 40
10 40 20 H L L H L L 10 10 20 20 H L H H L L 20 10 40 20 H H L H L
L 40 10 80 20
In FIG. 9E, an integrated DDR/SDR flow control device 300e is
illustrated that supports a BROADCAST mode of operation, with each
independent FIFO representing a respective queue. The device 300e
has four independent read ports and one common write port D[39:0]
that may be configured to support x10, x20 and x40 word widths.
This mode of operation may be achieved by setting mode pin MD1 low
and mode pin MD0 high. As illustrated by TABLE 12, the maximum
internal write word width is x80 when the DDR write mode is
selected, the write port is set to x40 and the input pins IW1 and
IW0 are set high and low, respectively. The maximum internal read
word width is x20 when the DDR read mode is selected. In order to
guarantee data consistency when the broadcast mode is selected,
write operations can only be performed if all queues have available
space. Composite flags may be generated for this purpose to signify
when at least one of the four FIFOs has become full.
TABLE-US-00012 TABLE 12 External Word Internal Word BROADCAST MODE
PIN SETTINGS Width Width WDDR IW1 IW0 RDDR OW1 OW0 IN OUT IN OUT L
L L L L L 10 10 10 10 L L H L L L 20 10 20 10 L H L L L L 40 10 40
10 H L L L L L 10 10 20 10 H L H L L L 20 10 40 10 H H L L L L 40
10 80 10 L L L H L L 10 10 10 20 L L H H L L 20 10 20 20 L H L H L
L 40 10 40 20 H L L H L L 10 10 20 20 H L H H L L 20 10 40 20 H H L
H L L 40 10 80 20
In FIG. 9F, an integrated DDR/SDR flow control device 300f is
illustrated that supports a multi-Q mode of operation, with each
independent FIFO representing a respective queue. The device 300f
has one common read port Q[39:0] and one common write port D[39:0]
that may be configured to support x10, x20 and x40 word widths. The
write and read paths are independent and support independent write
path and read path queue switching. The user selectable write queue
is independent of the user selectable read queue, which means the
input select signal IS[1:0] and output select signal OS[1:0] can be
set independently. As illustrated by TABLE 13, the maximum internal
write word width is x80 when the DDR write mode is selected, the
write port is set to x40 and the input pins IW1 and IW0 are set
high and low, respectively. Similarly, the maximum internal read
word width is x80 when the DDR read mode is selected, the read port
is set to x40 and the output pins OW1 and OW0 are set high and low,
respectively.
As described more fully hereinbelow, this multi-Q mode of operation
supports write path queue switching that is free of write word
fall-through and read path queue switching that is free of read
word fall-through. The multi-Q mode of operation also supports
write path queue switching on every write cycle in both SDR and DDR
write modes and independent read path queue switching on every read
cycle in both SDR and DDR read modes. Moreover, the multi-queue
mode of operation supports write queue pointer changes that are
free of corresponding write operations (i.e., the write queue
pointer can be changed in the absence of a write operation).
TABLE-US-00013 TABLE 13 External Word Internal MULTI-Q MODE PIN
SETTING Width Word Width WDDR IW1 IW0 RDDR OW1 OW0 IN OUT IN OUT L
L L L L L 10 10 10 10 L L L L L H 10 20 10 20 L L L L H L 10 40 10
40 L L H L L L 20 10 20 10 L L H L L H 20 20 20 20 L L H L H L 20
40 20 40 L H L L L L 40 10 40 10 L H L L L H 40 20 40 20 L H L L H
L 40 40 40 40 H L L L L L 10 10 20 10 H L L L L H 10 20 20 20 H L L
L H L 10 40 20 40 H L H L L L 20 10 40 10 H L H L L H 20 20 40 20 H
L H L H L 20 40 40 40 H H L L L L 40 10 80 10 H H L L L H 40 20 80
20 H H L L H L 40 40 80 40 L L L H L L 10 10 10 20 L L L H L H 10
20 10 40 L L L H H L 10 40 10 80 L L H H L L 20 10 20 20 L L H H L
H 20 20 20 40 L L H H H L 20 40 20 80 L H L H L L 40 10 40 20 L H L
H L H 40 20 40 40 L H L H H L 40 40 40 80 H L L H L L 10 10 20 20 H
L L H L H 10 20 20 40 H L L H H L 10 40 20 80 H L H H L L 20 10 40
20 H L H H L H 20 20 40 40 H L H H H L 20 40 40 80 H H L H L L 40
10 80 20 H H L H L H 40 20 80 40 H H L H H L 40 40 80 80
Referring now to TABLES 14 15, the write side and read side pin
assignments reflect the destination and source FIFOs during write
and read operations, respectively, in all of the six modes of
operation illustrated by FIGS. 9A 9F.
TABLE-US-00014 TABLE 14 WORD DATA INPUT PINS MODE WIDTH D[39:30]
D[29:20] D[19:10] D[9:0] QUAD/MUX 10 F3[9:0] F2[9:0] F1[9:0]
F0[9:0] DUAL 10 N/A F2[9:0] N/A F0[9:0] 20 F2[19:10] F2[9:0]
F0[19:10] F0[9:0] DEMUX/ 10 N/A N/A N/A Fn[9:0] MULTI-Q/ 20 N/A N/A
Fn[19:10] Fn[9:0] BROADCAST 40 Fn[39:30] Fn[29:20] Fn[19:10]
Fn[9:0]
TABLE-US-00015 TABLE 15 WORD DATA OUTPUT PINS MODE WIDTH Q[39:30]
Q[29:20] Q[19:10] Q[9:0] QUAD/DEMUX/ 10 F3[9:0] F2[9:0] F1[9:0]
F0[9:0] BROADCAST DUAL 10 Tri-State F2[9:0] Tri-State F0[9:0] 20
F2[19:10] F2[9:0] F0[19:10] F0[9:0] MUX/MULTI-Q 10 Tri-State
Tri-State Tri-State Fn[9:0] 20 Tri-State Tri-State Fn[19:10]
Fn[9:0] 40 Fn[39:30] Fn[29:20] Fn[19:10] Fn[9:0]
The integrated DDR/SDR flow control devices of FIGS. 9A 9F will now
be described more fully with respect to FIGS. 10A 10B, which
illustrate a multi-FIFO device 400 that is configured on a
monolithic integrated circuit substrate. The multi-FIFO device 400
includes four independent FIFO devices, shown as FIFO0-FIFO3. These
four FIFO devices are disposed at the corners of a central memory
core, which is surrounded by pipelined write path circuitry,
pipelined read path circuitry and flag and control logic. This
memory core may comprise multi-port SRAM cells (e.g., dual-port
cells) in some embodiments, however, other multi-port memory
technologies may be used as well. As illustrated, the memory
elements for FIFO0-FIFO3 are disposed in a quad arrangement in the
top right, bottom right, top left and bottom left corners of the
central memory core, respectively. A quad arrangement of memory
arrays also applies to each FIFO. This quad arrangement is shown
as: TR Quad, TL Quad, BR Quad and BL Quad. Each quadrant of memory
elements represents a separate memory array having its own word
line decoder, word line redundancy, etc (not shown).
As illustrated, the two top quadrants of memory elements (i.e., TR
and TL quads) within each FIFO are separated by write/read spine
control logic from the two bottom quadrants of memory elements
(i.e., BR and BL quads). The write/read spine control logic within
each FIFO is responsive to respective internal write clock and read
clock signals: WCLKMn and RCLKMn, where n=0, 1, 2, 3. These
internal write and read clock signals are generated by respective
second write and read clock generators, shown as WCLKGEN2 and
RCLKGEN2. These internal clock signals may be generated at
frequencies equal to about 200 MHz and higher.
The multi-FIFO device 400 will be described herein as having a
total capacity of 5.24 Meg, with each FIFO having a capacity of
1.31 Meg and each of the four quadrant of memory elements within
each FIFO having a capacity of 512.times.640 memory elements, where
512 equals the number of active rows and 640 equals the number of
active columns (excluding redundant rows and columns, not shown
herein).
The write/read spine control logic associated with each FIFOn
receives write data from a plurality of pairs of differential write
IO lines during write operations and passes read data onto a
plurality of pairs of differential read IO lines during read
operations. These write and read IO lines extend in a vertical
direction across the memory core. These write IO lines are
electrically connected to a respective write IO control circuit at
the top of the memory core and the read IO lines are electrically
connected to a respective read IO control circuit at the bottom of
the memory core. These write and read IO control circuits are
responsive to internal write and read clock signals WCLKNn and
RCLKNn, which are generated by the second write and read clock
generators WCLKGEN2 and RCLKGEN2.
Each of the four write IO control circuits that is located adjacent
a top of the memory core receives write data from a data input bus
(DIN BUS), which is illustrated as spanning an entire width of the
integrated circuit substrate. As illustrated more fully by FIGS.
11B 11D, the write data is routed from the data input bus to the
write IO control circuits using a plurality of data input
multiplexers (DIN MUXES), which may be 8:1 multiplexers, as
described herein. This write data is provided from data input pins
on a packaged device, which are coupled to respective data input
pads (shown as DIN PADS[39:0]), to data input control logic and
drivers, which are electrically coupled to the data input bus DIN
BUS. As illustrated by FIG. 10A and more fully by FIG. 11A, the
data input control logic and drivers are responsive to internal
write clock signals WCLKDn, which are generated by a first internal
write clock generator WCLKGEN1. This first internal write clock
generator WCLKGEN1 is illustrated as being responsive to four
external write clock signals EXTWCLKn, which are provided to pins
of the packaged device. These external write clock signals EXTWCLKn
are typically asynchronous relative to each other.
The four read IO control circuits that are located adjacent a
bottom of the memory core includes bus drivers that are configured
to drive a data output bus (DOUT BUS) with read data passed down
from the write/read spine control logic. In particular, the bus
drivers within the read IO control circuits are configured to drive
the data output bus via the data output multiplexers, which may be
configured as 1:8 multiplexers. This read data passes from the data
output bus to the data output control logic, which includes
off-chip drivers that are electrically connected to data output
pads (shown as DOUT PADS[39:0]). The data output control logic and
off-chip drivers are responsive to a plurality of internal read
clock signals RCLKDn, which are generated by a first internal read
clock generator RCLKGEN1. This first internal read clock generator
RCLKGEN1 is illustrated as being responsive to four external read
clock signals EXTRCLKn, which are provided to pins of the packaged
device. These external read clock signals EXTRCLKn are typically
asynchronous relative to each other. Although illustrated by
separate blocks, the first and second write clock generators
WCLKGEN1 and WCLKGEN2 may be configured as one contiguous write
clock generator circuit that is responsive to the external write
clock signals EXTWCLKn. Similarly, the first and second read clock
generators RCLKGEN1 and RCLKGEN2 may be configured as one
contiguous read clock generator circuit that is responsive to the
external read clock signals EXTRCLKn.
The separate and independent nature of the pipelined write paths
for the four FIFOs, which include the write IO control logic and
write spine control logic, and the separate and independent nature
of the pipelined read paths, which include the read spine control
logic and the read IO control logic, operate to support independent
write path and read path queue switching when the plurality of FIFO
memory devices are disposed in a multi-Q mode of operation. The
pipelined nature of the write paths, which share a common data
input bus (DIN BUS), and the pipelined nature of the read paths,
which share a common data output bus (DOUT BUS), support write path
queue switching that is free of write word fall-through and read
path queue switching that is free of read word fall-through. In
other words, none of the independent write path and read path
pipelines need to be purged of data associated with a respective
FIFO (i.e., queue) when a queue switching operation is being
performed during a multi-Q mode of operation. Write path and read
path queue switching can also be performed every write or every
read cycle, respectively, in both SDR and DDR modes. This is
because the read and write pipelines associated with a queue need
not be refilled when a queue switching operation is being
performed. The independent nature of the four pipelined read paths
is best illustrated by FIGS. 14A 14B and the same degree of
independent pipelining applies to the write paths as well.
The flag logic illustrated in FIG. 10A is configured to evaluate an
empty condition (or almost empty condition) in a FIFOn by comparing
a write counter value that is generated off a trailing edge of the
write clock signal WCLKn against a read counter value that is
generated off a leading edge of the read clock signal RCLKn when
the FIFOn is disposed in the DDR write mode. This flag logic is
further configured to evaluate a full condition (or almost full
condition) in the FIFOn by comparing a read counter value that is
generated off a trailing edge of the read clock signal RCLKn
against a write counter value that is generated off a leading edge
of the write clock signal WCLKn when the FIFO memory device is
disposed in the DDR read mode.
Each of the four FIFOs illustrated by FIG. 10A may be configured in
accordance with the FIFO 410 of FIG. 10B. This FIFO 410 may be
partitioned into sixteen (16) segments that span 1280 columns of
memory elements. The FIFO 410 includes a top pair of quadrants 412a
of memory elements and a bottom pair of quadrants 412b of memory
elements. These top and bottom pairs of quadrants 412a and 412b are
separated by write/read spine control logic 414, which is
responsive to respective write and read clock signals WCLKM and
RCLKM. Each quad of memory elements includes 512 rows of memory
elements plus two additional rows of memory elements that are used
to prevent the overwrite of data that has not been read from the
FIFO 410 when the FIFO 410 is full. In particular, if the FIFO 410
is being operated with its full depth, then the two additional rows
in the bottom quadrants 412b of the FIFO 410 can be written to when
the FIFO 410 is at the full condition. In this case, if the read
pointer is still pointing to the first row in the top quadrants
412a, then write operations performed at the full condition will
not operate to overwrite the data in the first row of the top
quadrants 412a. The data that is written into the additional rows
of memory elements will be available for reading once the full
condition is removed.
As illustrated by FIG. 10B, each quadrant of memory elements is
electrically coupled to: (i) 640 pairs of differential write bit
lines WBL/WBLX<0:639> that are driven rail-to-rail by the
write spine control logic 414 during write operations and (ii) 640
pairs of differential read bit lines RBL/RBLX<0:639> that are
sensed by the read spine control logic 414 during read operations.
Each segment of memory elements spans 80 columns within a quadrant
and is associated with ten (10) pairs of write IO lines and ten
(10) pairs of read IO lines. As described herein, each pair of
write IO lines and read IO lines is shielded from an immediately
adjacent pair of write or read IO lines by a noise suppressing
shield line that may be held at a positive supply voltage (e.g.,
Vdd). Accordingly, each segment of 80 columns of memory elements is
overlapped by 60 vertical IO and shield lines, which may be formed
using a high level of metallization. These 60 vertical lines
include: 20 shield lines and 40 write IO lines in the region
extending between the write IO control logic and the top write/read
spine control logic (for FIFO0 or FIFO2), or 20 shield lines and 20
write IO lines and 20 read IO lines in the region extending between
the top write/read spine control logic and bottom write/read spine
control logic, or 20 shield lines and 40 read IO lines in the
region extending between the bottom write/read spine control logic
(for FIFO1 or FIFO3) and the read IO control logic.
In FIG. 11A, aspects of the data input bus (DIN BUS) and data input
drivers illustrated by FIG. 10A are illustrated in greater detail.
In particular, a quad grouping of data input drivers 420a 420d are
illustrated as being electrically coupled to respective segments of
a data input bus 430 (DIN BUS). When provided with write data and
configured to operate at a single data rate (SDR), the data input
drivers DINDRVs_0 associated with DIN PADS 0 9 provide write data
to the first segment of horizontal data input bus lines DIN
BUS<0:9>. However, when configured to operate at a dual data
rate (DDR), the data input drivers DlNDRVs_0 provide write data to
the first segment of horizontal data input bus lines DIN
BUS<0:9> on a leading edge of the corresponding write clock
signal WCLKD0 and then provide write data to the fifth segment of
horizontal data input bus lines DIN BUS<40:49> on a trailing
edge of the corresponding write clock signal WCLKD0. Likewise, the
data input drivers DINDRVs_1 associated with DIN PADS 10 19 can be
configured to provide write data to the second and sixth segments
of horizontal data input bus lines DIN BUS<10:19> and
<50:59> and the data input drivers DINDRVs_2 associated with
DIN PADS 20 29 can be configured to provide write data to the third
and seventh segments of horizontal data input bus lines DIN
BUS<20:29> and <60:69>. Finally, the data input drivers
DINDRVs_3 associated with DIN PADS 20 39 can be configured to
provide write data to the fourth and eighth segments of horizontal
data input bus lines DIN BUS<30:39> and <70:79>.
The data input multiplexers (DIN MUXES) associated with the right
side (or left side) of the data input bus (DIN BUS) of FIG. 10A are
illustrated by FIGS. 11B 11D. In particular, FIG. 11B illustrates
the 8:1 multiplexers 432 (MUX0 MUX7) associated with the right
quadrants of memory elements in FIFO0 and FIFO1 (or FIFO2 and
FIFO3) and FIG. 11C illustrates the 8:1 multiplexers 432 (MUX8
MUX15) associated with the left quadrants of memory elements in
FIFO0 and FIFO1 (or FIFO2 and FIFO3). Control circuitry (not shown)
is provided so that these multiplexers can support the modes of
operation illustrated by FIGS. 9A 9F. The 40 vertical wires
associated with each MUX include 10 pairs of differential write
signal lines that terminate with the write IO control logic for
FIFO0 (or FIFO2) and 10 pairs of write differential signal lines
that terminate with the write IO control logic for FIFO1 (or
FIFO3). These pairs of differential write signal lines are
described herein using the notation: WPROG and WPROGX.
In FIG. 11D, a one-eighth portion of MUX0 is illustrated in greater
detail. Each horizontal pair of differential data input bus lines
in the DIN BUS is illustrated as being shielded from an adjacent
pair of differential data input bus lines by a respective shield
line, which may be held at a fixed potential (e.g., Vdd). These
shield lines operate to reduce noise caused by signal coupling
between adjacent pairs of lines. Each multiplexer element that may
be opened or closed to provide a routing path is illustrated by a
dotted circle. When writing from DIN BUS<0:9> to segment 0 of
FIFO0 (or FIFO 2), 10 bits of write data will pass from the
horizontal data input bus to the vertical lines
WPROG/WPROGX<0:9> associated with the corresponding write
control logic (top or bottom).
FIG. 11E illustrates one bit slice 422 of the data input control
and driver circuit of FIGS. 10A and 11A. This bit slice 422
includes a D-type flip-flop (DFF), a programmable delay unit, a
programmable pulse generator and a bus driver unit 420. The
flip-flop and programmable delay unit receive a corresponding write
clock signal WCLKDn. The D-type flip-flop is illustrated as a
positive edge triggered device that converts a single-sided write
data value at a data input pad to a differential input data value
(at outputs Q and QX), which may represent a rail-to-rail signal.
The programmable delay unit may have fixed and variable delay
elements therein that delay the write clock signal WCLKDn by a
desired delay amount. The programmable pulse generator generates a
driver enable signal DRVDEN as an active high pulse that causes the
bus driver unit 420 to drive a respective pair of lines within the
horizontal DIN BUS 430 with a differential signal that reflects the
value of the differential input data Q and QX. As described more
fully hereinbelow, this differential signal may be a 200 mV
differential signal relative to a precharged positive supply
voltage (e.g., Vdd=2.5 V). Another bit slice (not shown) that is
active during a DDR write operation is essentially equivalent to
the illustrated bit slice 422 of FIG. 11E, however, the D-type
flip-flop is a negative edge triggered device. This additional bit
slice includes a bus driver unit that is configured to drive
another pair of lines within the DIN BUS 430 with differential
signals, as illustrated by the dotted lines in FIG. 11A.
Accordingly, each data input pad is electrically coupled to a pair
of D-type flip-flops that are synchronized with opposite edges of a
write clock signal WCLKDn during DDR write operations. For example,
in a x40 DDR write mode, 40 bits of data will be captured in-sync
with a rising edge of a write clock signal and then 40 additional
bits of data will be captured in-sync with a falling edge of the
write clock signal. After all 80 bits have been captured, then
internal signals are generated to drive all 80 bits onto the
horizontal DIN BUS 430.
Operations to precharge and drive respective pairs of data input
bus lines within the horizontal DIN BUS 430 with differential
signals will now be described more fully with respect to FIGS. 11F
11H. In FIG. 11F, the horizontal DIN BUS 430 is illustrated as
including a plurality of DIN/DINX prechargers 432 that are arranged
at spaced intervals from left to right across the full width of the
DIN BUS. The prechargers 432 that are located relatively near the
center of the integrated circuit substrate are designated by the
reference NEAR and the prechargers 432 located on the far right or
far left of the substrate are designated by the reference FAR.
These designations will signify differences in the timing of the
operations to precharge and equalize the data input bus lines. As
illustrated by FIG. 11G, each precharger 432 includes a "small"
precharger unit 432a, which is operative to compensate for charge
leakage on already precharged data input bus lines, and a "big"
precharger and equalizer unit 432b, which is operative to restore a
pair of data input lines to precharged levels after a write
operation. The small precharger unit 432a is enabled by one active
low precharge signal (shown as PULSEBn) and the big precharger and
equalizer unit 432b is enabled by another active low precharge
signal (shown as PULSEAn). The PMOS transistors within the small
precharger unit 432a are illustrated as being relatively narrow
transistors that can exert a relatively weak pull-up force on a
corresponding pair of the data input bus lines (e.g., DIN and
DINX). In contrast, the PMOS transistors within the big precharger
and equalizer unit 432b are illustrated as being relatively wide
transistors that can exert a strong pull-up force on a pair of data
input bus lines.
The active low precharge signals PULSEAn and PULSEBn (where n=0,1,2
and 3) are generated by a plurality of pulse generators, which are
responsive to respective write clock signals WCLKDn. These pulse
generators are illustrated in FIG. 11F as PULSEGENABn. The pulse
generator that is responsive to the write clock signal WCLKD0
controls precharging operations on DIN BUS<0:9> and DIN
BUS<40:49> and the pulse generator that is responsive to the
write clock signal WCLKD1 controls precharging operations on DIN
BUS<10:19> and DIN BUS<50:59>. Similarly, the pulse
generator that is responsive to the write clock signal WCLKD2
controls precharging operations on DIN BUS<20:29> and DIN
BUS<60:69> and the pulse generator that is responsive to the
write clock signal WCLKD3 controls precharging operations on DIN
BUS<30:39> and DIN BUS<70:79>.
The timing of operations performed by the write data path
components illustrated by FIGS. 11A 11G will now be described more
fully with respect to the timing diagram of FIG. 11H. In
particular, FIG. 11H will now be described in a manner that
highlights the timing of a single bit of write data as it passes
from DIN PAD0 to the write IO control logic associated with a
corresponding FIFO during a write operation. This timing is
controlled by an external write clock signal EXTWCLKn (where n=0)
that is received and used by the first write clock generator
WCLKGEN1 to generate a corresponding internal write clock signal
WCLKDn. A rising edge of the internal write clock signal WCLKDn
causes the D-type flip-flop associated with DIN PAD0 to latch in
new write data and pass this new data as a rail-to-rail
differential signal (Q and QX) to the corresponding data input
driver DINDRV 420 (see, e.g., FIG. 11E). This rising edge of the
internal write clock signal WCLKDn also results in the generation
of an active high driver enable signal DRVDEN by the programmable
pulse generator. In response to a leading edge of the driver enable
signal DRVDEN, the data input driver DINDRV 420 drives a
corresponding pair of data input bus lines (DIN and DINX) with a
differential signal that passes through a selected mux element
within a DIN MUX (see, e.g., FIG. 11D). This differential signal is
a small swing signal that signifies a logic 1 value when DIN=Vdd
and DINX=(Vdd-200 mV) or signifies a logic 0 value when DINX=Vdd
and DIN=(Vdd-200 mV). These logic values are identified by the "1",
"0", "1" sequence for DINX/DIN in FIG. 11H. The use of small swing
signals supports the 200 MHz and higher clock rates.
The timing of the leading edge of the driver enable signal DRVDEN
is preceded by a turn off of the small precharger unit 432a. This
turn off operation is illustrated in FIG. 11H by the low-to-high
transition of the PULSEBn signal, which is illustrated as a "near"
signal that is received by the small precharger units 432a near the
center of the substrate and a "far" signal that is received by the
small precharger units 432a located near the left and right sides
of the substrate.
The write data signals WPROGX/WPROG, which are passed vertically
from a data input multiplexer (DIN MUX) to the write IO control
logic, reflect the value of the data on the corresponding data
input lines DINX/DIN. As illustrated by the dotted lines associated
with the signals WPROGX/WPROG in FIG. 11H, the timing of the
signals WPROGX/WPROG can vary depending on the relative locations
of the corresponding data input driver 420 that is driving the data
input bus DIN BUS and the location of the vertical 8:1 input
multiplexer that is passing the "horizontal" data input signal
DINX/DIN as a "vertical" WPROGX/WPROG signal. After a sufficient
amount of time has passed to enable capture of the WPROGX/WPROG
signals by the corresponding write IO control logic, the
corresponding data input bus lines DINX/DIN are again precharged to
logic 1 levels. This precharging operation is performed in response
to the high-to-low transition of the corresponding PULSEAn signal,
which is accompanied by a high-to-low transition of the
corresponding PULSEBn signal as well. This high-to-low transition
of the PULSEAn signal operates to precharge and equalize
corresponding data input bus lines DINX/DIN to Vdd and prepare
these lines for a subsequent write operation.
Referring again to FIG. 10A, each of the write IO control logic
blocks is responsive to a corresponding write clock signal WCLKNn
that is passed from the center of the substrate to the far right or
far left side of the corresponding write IO control logic. This
clock signal WCLKNn is illustrated at the bottom of FIG. 11H in
order to reflect the timing of when the corresponding write IO
control logic operates to latch in the value of the data reflected
on the corresponding vertical WPROGX/WPROG lines. The dotted lines
associated with this write clock signal WCLKNn reflect the delay in
passing this clock signal across the substrate. The data latching
operation by the write IO control logic is performed in-sync with a
write control clock signal WCTRX, which is generated by a
respective pulse generator (not shown) that receives the write
clock signal WCLKNn as an input.
Referring now to FIG. 12A, a bit slice 440 of the write IO control
logic of FIG. 10A is illustrated as including first and second
precharge units 442 and 446, a latching sense amplifier 444, a
write IO driver 448 and a write IO precharge circuit 450. The first
precharge unit 442 includes a small precharge unit that is
responsive to an active low precharge signal PRGEPX and a big
precharge and equalizing unit that is responsive to an active low
precharge signal PRGEP2X. These precharge units may be similar to
the precharge units 432a and 432b illustrated by FIG. 11G. The
first precharge unit 442 performs the function of precharging a
pair of vertical WPROG and WPROGX lines that extend downward from
the data input muxes (DIN MUX) illustrated by FIGS. 11B 11D. The
timing of these active low precharge signals PRGEPX and PRGEP2X is
illustrated by FIG. 12B. In particular, the precharge signal PRGEPX
is a signal that is frequently low in order to compensate for
charge leakage on the vertical WPROG and WPROGX lines, whereas the
signal PRGEP2X is only low when necessary to reset the vertical
WPROG and WPROGX lines to precharged levels in anticipation of a
subsequent write operation.
The second precharge unit 446 includes a small precharge unit that
is responsive to an active low precharge signal SAEPX and a big
precharge and equalizing unit that is responsive to an active low
precharge signal SAEP2X. The second precharge unit 446 performs the
function of precharging a pair of transfer lines XFER and XFERX
that extend from the latching sense amplifier 444 to the write IO
driver 448. The timing of these active low precharge signals SAEPX
and SAEP2X is illustrated by FIG. 12B. In particular, the precharge
signal SAEPX is a signal that is frequently low in order to
compensate for charge leakage on the transfer lines XFER and XFERX,
whereas the signal SAEP2X is only low when necessary to reset the
transfer lines XFER and XFERX to precharged levels in anticipation
of the latching operation performed by the latching sense amplifier
444.
When enabled in response to the sense amplifier enable signal SAEN,
the latching sense amplifier 444 generates rail-to-rail transfer
signals XFER and XFERX in-sync with a rising edge of the write
control clock signal WCTRX, as illustrated by FIG. 12B. The write
IO driver 448, which is enabled by an active high write IO driver
enable signal WIODRVEN, operates to drive the vertical write IO
lines WIO and WIOX with a small swing differential signal that
matches the value of the transfer signals XFER and XFERX. This
operation is illustrated at the bottom of the timing diagram of
FIG. 12B, where the write IO lines WIO and WIOX are precharged
in-sync with a leading edge of the active low write IO driver
precharge signal WIODREPX. As described above with respect to FIGS.
10A 10B, these write IO lines WIO and WIOX extend vertically over
the memory core to corresponding write/read spine control
logic.
Referring now to FIGS. 13A 13C, a bit slice 414a of the write
portion of the write/read spine control logic 414 of FIG. 10B will
be described. This bit slice 414a is illustrated as including a
precharge and equalize unit 462 that is electrically coupled to a
pair of write IO lines WIO and WIOX. Top and bottom redundancy
multiplexers 464 and 476 are illustrated. These multiplexers 464
and 476 are set by fuses to control which grouping of eight (8)
redundant columns (corresponding to a pair of write IO lines), if
any, will be used to replace a defective group of ormal
columns.
If the write data on WIO/WIOX is destined for a top quadrant within
a FIFOn memory core, then the top IO lines TIO and TIOX receive the
write data as a small swing differential signal. These top IO lines
TIO and TIOX are periodically precharged to Vdd by a precharge and
equalization unit 466. The small swing differential signal on the
top IO lines TIO and TIOX is captured by the write sense amplifier
(top) 468. This write sense amplifier 468 is responsive to a top
sense enable signal TSAEN and a top write control clock signal
TWCTRX. The write sense amplifier 468 generates a pair of
rail-to-rail signals TSA/TSAX during a sense and amplify operation
that is synchronized with a leading edge of the top write control
clock signal TWCTRX. The signal lines TSA/TSAX are periodically
precharged to Vdd by a precharge and equalization unit 470. The
signal lines TSA/TSAX are provided to a write driver 472 that is
configured to support rail-to-rail write bit line driving
operations. The outputs TDOUT/TDOUTX of the write driver 472 are
provided to a top bit line multiplexer 474 that performs a 1:8
selection operation. The top bit line multiplexer 474 is responsive
to an active low bit line precharge signal TBLEPX and a multi-bit
column selection signal TCOL<7:0>. Depending on the value of
the column selection signal TCOL<7:0>, the data provided on
the signal lines TDOUT/TDOUTX is routed to one of eight immediately
adjacent columns within a top quad of a FIFOn. Redundant columns
(not shown) may also be provided to replace one or more defective
columns within a segment of memory elements.
Alternatively, if the write data on WIO/NIOX is destined for bottom
quadrant within a FIFOn memory core, then the bottom IO lines BIO
and BIOX receive the write data as small swing differential signal.
These bottom IO lines BIO and BIOX are periodically precharged to
Vdd by a precharge and equalization unit 478. The small swing
differential signal on the bottom IO lines BIO and BIOX is captured
by the write sense amplifier (bottom) 480. This write sense
amplifier 480 is responsive to a bottom sense enable signal BSAEN
and a bottom write control clock signal BWCTRX. The write sense
amplifier 480 generates a pair of rail-to-rail signals BSA/BSAX
during a sense and amplify operation that is synchronized with a
leading edge of the bottom write control clock signal BWCTRX. The
signal lines BSA/BSAX are periodically precharged to Vdd by a
precharge and equalization unit 482. The signal lines BSA/BSAX are
provided to a write driver 484 that is configured to support
rail-to-rail write bit line driving operations. The outputs
BDOUT/BDOUTX of the write driver 484 are provided to a bottom bit
line multiplexer 486 that performs a 1:8 selection operation. The
bottom bit line multiplexer 486 is responsive to an active low bit
line precharge signal BBLEPX and a multi-bit column selection
signal BCOL<7:0>. Depending on the value of the column
selection signal BCOL<7:0>, the data provided on the signal
lines BDOUT/BDOUTX is routed to one of eight immediately adjacent
columns within a bottom quad of a FIFOn.
Thus, the bit slice 414a of FIG. 13A illustrates one-tenth of one
segment of the write portion of the write/read spine control logic
414 of FIG. 10B that drives write bit lines in both the top and
bottom quadrants of a memory core of a FIFOn. As described above,
each quadrant of memory elements in a FIFOn is associated with 80
pairs of write IO lines (WIO<0:79>/WIOX<0:79>) and each
segment of each quadrant of memory elements is associated with ten
pairs of write IO lines. This relationship is reflected by FIG.
13B, where the routing of ten bits of write data from ten (10) of
the bit slices 414a illustrated by FIG. 13A includes routing data
on each write IO line pair (WIO/WIOX) to one of eight pairs of
write bit lines in the top or bottom quadrants of memory elements.
In FIG. 13C, the routing of 80 bits of write data from 80 of the
bit slices 414a includes routing data on each of the 80 write IO
line pairs to 80 of the 640 pairs of write bit lines in the top or
bottom quadrants of memory elements.
This routing of 80 bits of write data into a selected FIFOn may
correspond to a x40 DEMUX or x40 MULTI-Q write operation at a DDR
write rate, as described above with respect to FIGS. 9A 9F. The
sequence of write operations that fill a selected FIFOn with 80
bits of write data on each write cycle are illustrated more fully
by TABLE 16. In particular, TABLE 16 illustrates how 80 bit words
are routed from the write spine control logic into respective top
and bottom quadrants, in a right-to-left and top-to-bottom
sequence. In the first write cycle (WRITE CYCLE 1), 80 bits of
write data are written into ten columns of memory elements within
each of the eight segments within a quadrant. During this write
cycle, 80 instances of the bit line multiplexer 474 illustrated by
FIG. 13A operate to select column 0 in the top right quadrant of
memory elements.
TABLE 16 also illustrates how after 640 bits of write data have
been written into row 0 of the top right quadrant (TR) of memory
elements during eight consecutive write cycles, a switch is made to
the top left quadrant (TL) of memory elements, which represents a
separate memory array having separate word lines, word line
decoders, etc. After row 0 of the top left quadrant (TL) has been
written to, then row 1 of the top right quadrant (TR) is accessed.
This back and forth switching between the right and left quadrants
continues until the top quadrants are full. Thereafter, write
operations are made in a back and forth sequence between the bottom
quadrants (BR and BL).
TABLE-US-00016 TABLE 16 FIFO WRITE OPERATIONS - 80 BIT WORDS (1.3
MEG) WRITE CYCLE QUAD ROW COLUMNS SEGMENTS 1 TR 0 0 0 7 2 TR 0 1 0
7 3 TR 0 2 0 7 4 TR 0 3 0 7 5 TR 0 4 0 7 6 TR 0 5 0 7 7 TR 0 6 0 7
8 TR 0 7 0 7 9 TL 0 0 8 15 10 TL 0 1 8 15 11 TL 0 2 8 15 12 TL 0 3
8 15 13 TL 0 4 8 15 14 TL 0 5 8 15 15 TL 0 6 8 15 16 TL 0 7 8 15 17
TR 1 0 0 7 18 TR 1 1 0 7 . . . . . . . . . . . . . . . 8191 TL 511
6 8 15 8192 TL 511 7 8 15 8193 BR 0 0 0 7 8194 BR 0 1 0 7 . . . . .
. . . . . . . . . . 16383 BL 511 6 8 15 16384 BL 511 7 8 15
The routing of 40 bits of write data into a selected FIFOn may
correspond to a x20 DUAL mode, x20 DEMUX, or x20 MULTI-Q write
operation at a DDR write rate or a x40 width mode at an SDR rate. A
sequence of write operations that fill a selected FIFOn with 40
bits of write data on each write cycle are illustrated more fully
by TABLE 17. In particular, TABLE 17 illustrates how sixteen 40-bit
write operations are needed to fill a row of memory elements within
a selected quadrant, before the next quadrant is selected. The word
lines associated with each row of memory elements within a
respective quadrant are operated as static word lines that remain
active at high levels during multiple consecutive write cycles. In
TABLE 17, sixteen consecutive write cycles are performed on a
selected row before a transition is made to an adjacent quadrant,
and the word line for the selected row remains high during these
sixteen consecutive write cycles. Moreover, well before the time of
transition from one quadrant to an adjacent quadrant during a
series of write operations, the word line associated with the
adjacent quadrant is precharged high to an active level and remains
high until all write operations into the corresponding row have
been completed. This eliminates the time delay associated with an
operation to drive the word line to an active level from the speed
path during write operations.
TABLE-US-00017 TABLE 17 FIFO WRITE OPERATIONS - 40 BIT WORDS WRITE
CYCLE QUAD ROW COLUMNS SEGMENTS 1 TR 0 0 0 3 2 TR 0 0 4 7 3 TR 0 1
0 3 4 TR 0 1 4 7 5 TR 0 2 0 3 6 TR 0 2 4 7 7 TR 0 3 0 3 8 TR 0 3 4
7 9 TR 0 4 0 3 10 TR 0 4 4 7 11 TR 0 5 0 3 12 TR 0 5 4 7 13 TR 0 6
0 3 14 TR 0 6 4 7 15 TR 0 7 0 3 16 TR 0 7 4 7 17 TL 0 0 8 11 18 TL
0 1 12 15 . . . . . . . . . . . . . . . 32 TL 0 7 12 15 33 TR 1 0 0
3 . . . . . . . . . . . . . . . 32768 BL 511 7 12 15
The routing of 20 bits of write data into a selected FIFOn may
correspond to a x10 QUAD, x10 DUAL, x10 DEMUX, or x10 MULTI-Q write
operation at a DDR write rate or a x20 DUAL, x20 DEMUX, or x20
MULTI-Q write operation at an SDR rate. A sequence of write
operations that fill a selected FIFOn with 20 bits of write data on
each write cycle are illustrated more fully by TABLE 18. In
particular, TABLE 18 illustrates how 32 20-bit write operations are
needed to fill a row of memory elements within a selected quadrant,
before the next quadrant is selected.
TABLE-US-00018 TABLE 18 FIFO WRITE OPERATIONS - 20 BIT WORDS WRITE
CYCLE QUAD ROW COLUMNS SEGMENTS 1 TR 0 0 0 1 2 TR 0 0 2 3 3 TR 0 0
4 5 4 TR 0 0 6 7 5 TR 0 1 0 1 6 TR 0 1 2 3 . . . . . . . . . . . .
. . . 32 TR 0 7 6 7 33 TL 0 0 0 1 34 TL 0 0 2 3 . . . . . . . . . .
. . . . . 64 TL 0 7 6 7 65 TR 1 0 0 1 . . . . . . . . . . . . . .
32769 BR 0 0 0 1 . . . . . . . . . . . . . . . 65536 BL 511 7 14
15
The routing of 10 bits of write data into a selected FIFOn may
correspond to a x10 QUAD, x10 DUAL, x10 DEMUX, or x10 MULTI-Q write
operation at an SDR rate. A sequence of write operations that fill
a selected FIFOn with 10 bits of write data on each write cycle are
illustrated more fully by TABLE 19. In particular, TABLE 18
illustrates how 64 10-bit write operations are needed to fill a row
of memory elements within a selected quadrant, before the next
quadrant is selected.
TABLE-US-00019 TABLE 19 FIFO WRITE OPERATIONS - 10 BIT WORDS WRITE
CYCLE QUAD ROW COLUMNS SEGMENTS 1 TR 0 0 0 2 TR 0 0 1 3 TR 0 0 2 4
TR 0 0 3 5 TR 0 0 4 6 TR 0 0 5 7 TR 0 0 6 8 TR 0 0 7 9 TR 0 1 0 10
TR 0 1 1 . . . . . . . . . . . . . . . 64 TR 0 7 7 65 TL 0 0 8 66
TL 0 0 9 65636 TL 511 7 15 65637 BR 0 0 0 . . . . . . . . . . . . .
. . 131272 BL 511 7 15
FIGS. 11A 11H, 12A 12B and 13A 13C provide a detailed description
of the pipelined write paths associated with the multi-FIFO device
400 of FIGS. 10A 10B. In an analogous manner, these write paths
translate to essentially equivalent read paths that extend
vertically in a pipelined sequence from the read bit lines within
each quadrant of memory elements, to the read spine control logic
between the quadrants of each FIFO, and then to the read IO control
logic, the DOUT multiplexers, the DOUT BUS and the DOUT control and
drivers illustrated by FIG. 10A. This vertical read path 500 is
illustrated by FIG. 14A, which shows the four FIFOs providing read
data to respective read spine control logic 414b. Each of the four
read paths extends downward on read IO lines from the central spine
of each FIFO to the read IO control logic 510 and bus driver
devices. These bus driver devices drive the read data through
respective data output multiplexers (DOUT MUXES) to the data output
bus 520 (DOUT BUS). (See, e.g., FIGS. 11A 11D). From the data
output bus 520, read data is passed to data output control logic
and drivers 530 that drive the output pads at the output port
Q[39:0] (and off-chip loads) with the read data.
As illustrated by the read path bit slice 500a of FIG. 14B, each
bit of read data is double buffered in a read pipeline. The first
buffering occurs within the read spine control logic 414b, when the
read data is latched by a latching sense amplifier that is
responsive to a level 1 read clock signal (RCLK1). From there, the
read data is passed down the read IO lines as a small swing
differential signal (e.g., maximum swing equals 200 mV) to the read
IO control logic and data output bus driver 510. The read IO
control logic senses, amplifies and latches the read data in-sync
with a first level 2 read clock signal RCLKLA1. The read IO control
logic passes the read data as a rail-to-rail signal to a latch that
is responsive to a second level 2 read clock signal RCLKLA2, which
may be a delayed version of the first level 2 read clock signal
RCLKLA1. These clock signals are generated by the second read clock
generator RCLKGEN2 illustrated by FIG. 10A. The data output bus
driver, which is responsive to a read driver clock signal RCLKDRV,
drives the data output multiplexers and data output bus 520 with a
small swing differential signal that is sensed and latched by a
sense amplifier within the data output control logic 530. This
sense amplifier is responsive to a level 3 read clock signal
RCLKLA3. The read data latched by the third latch (LATCH3) is then
passed to an output stage latch (LATCH0) and output pad (DOUT PAD),
in-sync with a read clock signal RCLKQ that is generated by the
first read clock generator RCLKGEN1.
In the drawings and specification, there have been disclosed
typical preferred embodiments of the invention and, although
specific terms are employed, they are used in a generic and
descriptive sense only and not for purposes of limitation, the
scope of the invention being set forth in the following claims.
* * * * *