Au; Mario

Patent Applications and Registrations

Patent applications and USPTO patent grants for Au; Mario.The latest application filed is for "serial buffer supporting virtual queue to physical memory mapping".

Company Profile

0.20.18

Au; Mario - Fremont CA

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system Grant 8,230,174 - Au , et al. July 24, 2	2012-07-24
Serial buffer supporting virtual queue to physical memory mapping Grant 7,945,716 - Wang , et al. May 17, 2	2011-05-17
Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system Grant 7,870,310 - Au , et al. January 11, 2	2011-01-11
Multi-function queue to support data offload, protocol translation and pass-through FIFO Grant 7,805,551 - Wang , et al. September 28, 2	2010-09-28
Partial packet write and write data filtering in a multi-queue first-in first-out memory system Grant 7,805,552 - Au , et al. September 28, 2	2010-09-28
Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system Grant 7,523,232 - Au , et al. April 21, 2	2009-04-21
Serial Buffer Supporting Virtual Queue To Physical Memory Mapping App 20090089532 - Wang; Chi-Lie ; et al.	2009-04-02
Multi-Function Queue To Support Data Offload, Protocol Translation And Pass-Through FIFO App 20090086748 - Wang; Chi-Lie ; et al.	2009-04-02
Multi-queue FIFO memory devices that support a backed-off standard mode of operation and methods of operating same Grant 7,392,354 - Au , et al. June 24, 2	2008-06-24
Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system Grant 7,269,700 - Au , et al. September 11, 2	2007-09-11
Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system Grant 7,257,687 - Au , et al. August 14, 2	2007-08-14
Sequential flow-control and FIFO memory devices having error detection and correction capability with diagnostic bit generation Grant 7,246,300 - Au , et al. July 17, 2	2007-07-17
Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation Grant 7,209,983 - Au , et al. April 24, 2	2007-04-24
Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system Grant 7,154,327 - Mo , et al. December 26, 2	2006-12-26
Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system Grant 7,099,231 - Au , et al. August 29, 2	2006-08-29
Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration Grant 7,093,047 - Au , et al. August 15, 2	2006-08-15
Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes Grant 7,082,071 - Knaack , et al. July 25, 2	2006-07-25
Multi-queue FIFO memory systems that utilize read chip select and device identification codes to control one-at-a-time bus access between selected FIFO memory chips App 20060155940 - Au; Mario ; et al.	2006-07-13
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same Grant 7,076,610 - Au , et al. July 11, 2	2006-07-11
Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays Grant 7,042,792 - Lee , et al. May 9, 2	2006-05-09
Multiple counters to relieve flag restriction in a multi-queue first-in first-out memory system App 20060018177 - Au; Mario ; et al.	2006-01-26
Mark/re-read and mark/re-write operations in a multi-queue first-in first-out memory system App 20060018176 - Au; Mario ; et al.	2006-01-26
Interleaving memory blocks to relieve timing bottleneck in a multi-queue first-in first-out memory system App 20060018170 - Au; Mario ; et al.	2006-01-26
Self-timed multiple blanking for noise suppression during flag generation in a multi-queue first-in first-out memory system App 20060017497 - Mo; Jason Z. ; et al.	2006-01-26
Synchronization of active flag and status bus flags in a multi-queue first-in first-out memory system App 20060020741 - Au; Mario ; et al.	2006-01-26
Multi-queue address generator for start and end addresses in a multi-queue first-in first-out memory system App 20060020743 - Au; Mario ; et al.	2006-01-26
Partial packet read/write and data filtering in a multi-queue first-in first-out memory system App 20060020761 - Au; Mario ; et al.	2006-01-26
Status bus accessing only available quadrants during loop mode operation in a multi-queue first-in first-out memory system App 20060020742 - Au; Mario ; et al.	2006-01-26
Multi-port memory cells for use in FIFO applications that support data transfers between cache and supplemental memory arrays App 20050152204 - Lee, Shih-Ked ; et al.	2005-07-14
FIFO memory devices having multi-port cache and extended capacity memory devices therein with retransmit capability Grant 6,874,064 - Au , et al. March 29, 2	2005-03-29
Integrated DDR/SDR flow control managers that support multiple queues and mux, demux and broadcast operating modes App 20050018514 - Knaack, Roland T. ; et al.	2005-01-27
Sequential flow-control and FIFO memory devices that are depth expandable in standard mode operation App 20050005082 - Au, Mario ; et al.	2005-01-06
Integrated circuit memory devices having clock signal arbitration circuits therein and methods of performing clock signal arbitration App 20050005069 - Au, Mario ; et al.	2005-01-06
Fifo memory devices having multi-port cache and extended capacity memory devices therein with retransmit capability App 20040193805 - Au, Mario ; et al.	2004-09-30
FIFO memory devices and methods of operating FIFO memory devices having multi-port cache memory devices therein Grant 6,754,777 - Au , et al. June 22, 2	2004-06-22
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same App 20040047209 - Lien, Chuen-Der ; et al.	2004-03-11
FIFO memory devices having multi-port cache memory arrays therein that support hidden EDC latency and bus matching and methods of operating same App 20040019743 - Au, Mario ; et al.	2004-01-29
Multi-port cache memory devices and FIFO memory devices having multi-port cache memory devices therein Grant 6,546,461 - Au , et al. April 8, 2	2003-04-08

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