Knaack; Roland T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Knaack; Roland T..The latest application filed is for "dram interface circuits having enhanced skew, slew rate and impedance control".

Company Profile

0.12.2

Knaack; Roland T. - Suwanee GA
Knaack; Roland T. - Duluth GA
Knaack; Roland T. - Starkville MS

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Programmable clock drivers that support CRC error checking of configuration data during program restore operations Grant 7,196,562 - Luis , et al. March 27, 2	2007-03-27
Multi-FIFO integrated circuit devices that support multi-queue operating modes with enhanced write path and read path queue switching Grant 7,120,075 - Gibson , et al. October 10, 2	2006-10-10
Integrated DDR/SDR flow control managers that support multiple queues and MUX, DEMUX and broadcast operating modes Grant 7,082,071 - Knaack , et al. July 25, 2	2006-07-25
DRAM interface circuits having enhanced skew, slew rate and impedance control Grant 7,079,446 - Murtagh , et al. July 18, 2	2006-07-18
DRAM interface circuits having enhanced skew, slew rate and impedance control App 20050259504 - Murtugh, Paul ; et al.	2005-11-24
Integrated DDR/SDR flow control managers that support multiple queues and mux, demux and broadcast operating modes App 20050018514 - Knaack, Roland T. ; et al.	2005-01-27
Methods of testing integrated circuits to include data traversal path identification information and related status information in test data streams Grant 6,173,425 - Knaack , et al. January 9, 2	2001-01-09
Circuit and method for instruction controllable slew rate of bit line driver Grant 6,005,821 - Knaack , et al. December 21, 1	1999-12-21
Integrated circuit memory devices having partitioned multi-port memory arrays therein for increasing data bandwidth and methods of operating same Grant 5,978,307 - Proebsting , et al. November 2, 1	1999-11-02
Parity generation and check circuit and method in read data path Grant 5,872,802 - Knaack , et al. February 16, 1	1999-02-16
Circuit and method for instruction controllable slewrate of bit line driver Grant 5,777,944 - Knaack , et al. July 7, 1	1998-07-07
Multiple frequency memory array clocking scheme for reading and writing multiple width digital words Grant 5,764,967 - Knaack June 9, 1	1998-06-09
Multiple word width memory array clocking scheme for reading words from a memory array Grant 5,682,356 - Knaack October 28, 1	1997-10-28
Testing method for FIFOS Grant 5,642,318 - Knaack , et al. June 24, 1	1997-06-24

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