U.S. patent number 6,093,642 [Application Number 09/354,508] was granted by the patent office on 2000-07-25 for tungsten-nitride for contact barrier application.
This patent grant is currently assigned to Texas Instruments Incorporated. Invention is credited to Chih-Chen Cho, Jiong-Ping Lu, Yoshimitsu Tamura.
United States Patent |
6,093,642 |
Cho , et al. |
July 25, 2000 |
Tungsten-nitride for contact barrier application
Abstract
A contact and method of forming a contact. A layer of titanium
(112) is deposited. Then, a RTP anneal is performed to react the
titanium layer (112) with underlying silicon (112) to form a
silicide layer (114). After the RTP anneal, a layer of
tungsten-nitride (116) is deposited as a barrier layer. The metal
interconnect layer (118) is then formed over the tungsten-nitride
layer (116).
Inventors: |
Cho; Chih-Chen (Richardson,
TX), Tamura; Yoshimitsu (Ibaraki-ken, JP), Lu;
Jiong-Ping (Dallas, TX) |
Assignee: |
Texas Instruments Incorporated
(Dallas, TX)
|
Family
ID: |
22284932 |
Appl.
No.: |
09/354,508 |
Filed: |
July 15, 1999 |
Current U.S.
Class: |
438/643;
257/E21.165; 257/E21.584; 257/E21.585; 257/E23.019; 438/648;
438/653; 438/664 |
Current CPC
Class: |
H01L
21/28518 (20130101); H01L 21/76843 (20130101); H01L
21/76855 (20130101); H01L 21/76856 (20130101); H01L
21/76877 (20130101); H01L 23/485 (20130101); H01L
2924/0002 (20130101); H01L 2924/0002 (20130101); H01L
2924/00 (20130101) |
Current International
Class: |
H01L
21/70 (20060101); H01L 21/768 (20060101); H01L
21/285 (20060101); H01L 21/02 (20060101); H01L
23/48 (20060101); H01L 23/485 (20060101); H01L
021/4763 () |
Field of
Search: |
;438/627,628,629,630,643,649,653,664 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Quach; T. N.
Attorney, Agent or Firm: Garner; Jacqueline J. Brady, III;
W. James Telecky, Jr.; Frederick J.
Parent Case Text
CROSS-REFERENCE TO RELATED APPLICATIONS
This application claims priority under 35 USC .sctn.119(e)(1) of
provisional application number 60/101,492 filed Sep. 23, 1998.
The following co-assigned pending application is related and hereby
incorporated by reference:
Claims
What is claimed is:
1. A method for fabricating a contact in an integrated circuit,
comprising the steps of:
forming a dielectric layer over a semiconductor body;
forming a contact hole in said dielectric layer exposing a portion
of said semiconductor body;
forming a silicide layer in said contact hole by
depositing a layer of titanium (ti) in said contact hole
depositing a layer of titanium-nitride (tin) over said ti layer;
and
then performing a rapid thermal process (RTP) anneal to convert a
portion of said ti layer to said silicide layer,
depositing a tungsten-nitride (WN) layer over said suicide layer
after said RTP step; and
forming a metal interconnect layer over said WN layer.
2. The method of claim 1, wherein said performing a RTP anneal step
occurs at a temperature in the range of 650-700.degree. C. and a
duration on the order of 30 sec.
3. The method of claim 1 wherein said Ti layer has a thickness on
the order of 200 .ANG..
4. The method of claim 1, wherein said TiN layer has a thickness on
the order of 100 .ANG..
5. The method of claim 1, wherein said WN layer has a thickness on
the order of 300 .ANG..
6. The method of claim 1, wherein said metal interconnect layer
comprises tungsten (W).
7. A method for fabricating an integrated circuit, comprising the
steps of:
forming a transistor in a semiconductor body;
forming a dielectric layer over said transistor and said
semiconductor body;
forming a contact hole in said dielectric layer exposing
source/drain region of said transistor;
depositing a layer of titanium (Ti) in said contact hole;
depositing a layer of titanium nitride (TiN) over said Ti
layer;
reacting said Ti layer with a surface of said source/drain region
to form a silicide layer using a rapid thermal process (RTP) anneal
after said step of depositing said layer of TiN;
depositing a tungsten-nitride (WN) layer over said silicide layer;
and
forming a metal interconnect layer over said WN layer.
8. The method of claim 7, wherein said reacting step occurs at a
temperature on the order of 650.degree. C. and a duration on the
order of 30 sec.
9. The method of claim 7, wherein said Ti layer has a thickness on
the order of 200 .ANG..
10. The method of claim 7, wherein said TiN layer has a thickness
on the order of 100 .ANG..
11. The method of claim 7, wherein said WN layer has a thickness on
the order of 500 .ANG..
12. The method of claim 7, wherein said metal interconnect layer
comprises tungsten (W).
Description
FIELD OF THE INVENTION
The invention is generally related to the field of fabricating
contacts in integrated circuits and more specifically to
fabricating contacts with a tungsten-nitride contact barrier.
BACKGROUND OF THE INVENTION
As the density of integrated circuits, such as dynamic random
access memory (DRAM) devices, has increased, the size of the
contact hole for connecting to a metal layer has decreased while
the aspect ratio of the contact hole has increased. As a result,
the fabrication of contact structures for sub-micron complementary
metal oxide semiconductor (CMOS) devices is difficult. Typically, a
contact structure is formed after the formation of the capacitor
elements. However, if the contact structure can be formed before
the formation of the capacitor structure and withstand the high
temperature steps required in the formation of the capacitor
structure(s), the process flow can be simplified and a reduced
aspect ratio for the contact hole(s) can be obtained.
A need has been felt for a technique for forming a contact with a
diffusion barrier which is easy to fabricate, which results in low
contact resistance, and which has sufficient thermal stability to
withstand the process temperature required in the formation of
capacitor elements.
SUMMARY OF THE INVENTION
A contact structure and method comprising a tungsten-nitride
diffusion barrier is disclosed herein. Contact resistance is
reduced by performing a rapid thermal process after refractory
metal deposition to form silicide and then forming the
tungsten-nitride diffusion barrier over the silicide.
An advantage of the invention is providing a contact having good
thermal stability and low contact resistance.
This and other advantages will be apparent to those of ordinary
skill in the art having reference to the specification in
conjunction with the drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
In the drawings:
FIGS. 1A-1D are cross-sectional diagrams of a contact constructed
according to a first embodiment of the invention at various stages
of fabrication; and
FIGS. 2A-2C are cross-sectional diagrams of a contact constructed
according to a second embodiment of the invention at various stages
of fabrication.
DETAILED DESCRIPTION OF THE EMBODIMENTS
The invention will now be described in conjunction with a process
for forming a contact between a metal interconnect layer and a
source/drain region of a transistor. It will be apparent to those
of ordinary skill in the art that the benefits of the invention may
alternatively be applied to contacts to silicon material in
general.
TiN has been the most widely used diffusion barrier material for
contacts in integrated circuits. However, a very thick TiN layer is
needed to prevent contact failure if the device has to endue a high
temperature process after the contact is formed. As discussed in
U.S. patent application Ser. No. 60/067,608 (TI-24164), filed Dec.
5, 1997, and assigned to Texas Instruments Incorporated, WN
(tungsten-nitride) is a good diffusion barrier material that offers
lower sheet resistance and better thermal stability than TiN
barriers. However, in order to make a good contact, the diffusion
barrier must not only prevent intermixing of the layers below
(e.g., TiSi2) and above (e.g., W), but also provide low contact
resistance. Unfortunately, contacts with WN diffusion barriers can
have very high contact resistance. The embodiments of the invention
described below provide a contact having WN diffusion barrier,
better thermal stability than TiN, and low contact resistance.
In a first embodiment of the invention, a semiconductor body 102 is
processed through the formation of transistors, such as transistor
104 and other devices (not shown). Referring to FIG. 1A,
semiconductor body 102 is further processed through the formation
of a poly-metal dielectric (PMD) 106 that has been patterned and
etched to form contact hole 108. Contact hole 108 exposes a portion
of silicon 110 that may, for example, be a source/drain region of
transistor 104.
Referring to FIG. 1B, a layer of refractory metal (preferably
titanium (Ti)) 112 is deposited over semiconductor body 102
including in contact hole 108 over silicon portion 110. Ti 112 may
be deposited, for example, by collimated sputtering, ionized
sputtering, or chemical vapor deposition as are known in the art.
The thickness of Ti layer 112 is on the order of 200 .ANG.. It will
be apparent to those of ordinary skill in the art that other
refractory metals, such as Co or Ni may alternatively be used for
layer 112.
After deposition, the Ti layer 112 is subjected to a rapid thermal
process (RTP) anneal using a nitrogen containing ambient. The RTP
anneal is performed at a temperature on the order of 650.degree. C.
and preferably in the range of 650-700.degree. C. The duration of
the anneal is on the order of 30 sec. The purpose of the anneal is
to react the Ti with silicon to form silicide 114 as shown in FIG.
1C. A thin layer of titanium-nitride (TiN) 115 is also formed.
It should be noted that TiO.sub.x could form on the surface of the
Ti layer 112 if the react step cannot be performed in the same
chamber as the titanium deposition. TiO.sub.x can increase the
contact resistance of the final contact structure.
After the RTP anneal, a layer of tungsten-nitride (WN) 116 is
formed over the structure including over silicide layer 114 as
shown in FIG. 1D. WN layer 116 may be deposited by
chemical-vapor-deposition (CVD) as is known in the art. The
thickness of WN layer 116 is on the order of 300 .ANG., and
preferably in the range of 50-500 .ANG..
Next, a metal interconnect layer 118 is deposited, patterned and
etched. Preferably, metal interconnect layer 118 comprises W. This
is followed by an anneal. The anneal occurs at a temperature on the
order of 800.degree. C. and has a duration on the order of 5
minutes.
In a second embodiment of the invention, a semiconductor body 202
is processed through the formation of transistors, such as
transistor 204 and other devices (not shown). Semiconductor body
202 is further processed through the formation of a poly-metal
dielectric (PMD) 206 that has been patterned and etched to form
contact hole 208. Contact hole 208 exposes a portion of silicon 210
that may, for example, be a source/drain region of transistor
204.
Referring to FIG. 2A, a layer of titanium (Ti) 212 is deposited
over
semiconductor body 202 including in contact hole 208 over silicon
portion 210. Ti 212 maybe deposited, for example, by sputtering or
CVD as is known in the art. The thickness of Ti layer 212 is on the
order of 200 .ANG..
Next, a thin layer of TiN 213 is deposited over Ti layer 212. The
thickness of TiN layer 213 is on the order of 100 .ANG.. The
purpose of TiN layer 213 is to prevent the formation of a TiO layer
on the surface of Ti layer 212. Without TiN layer 213, TiO could
form on Ti layer 212 when transferring the structure between
process chambers (e.g., between deposition and silicide react
chambers or between Ti deposition and WN deposition).
After deposition of TiN layer 213, the Ti layer 212 is subjected to
a rapid thermal process (RTP) anneal. The RTP anneal is performed
at a temperature on the order of 650.degree. C. and preferably in
the range of 650-700.degree. C. The duration of the anneal is on
the order of 30 sec. The purpose of the anneal is to react the Ti
with silicon to form silicide 214 as shown in FIG. 2B, which
decreases contact resistance.
After the RTP anneal, a layer of tungsten-nitride (WN) 216 is
formed over the structure including over silicide layer 214 and TiN
layer 213 as shown in FIG. 2C. WN layer 216 may be deposited by
chemical-vapor-deposition (CVD) as is known in the art. The
thickness of WN layer 216 is on the order of 300 .ANG., and
preferably in the range of 50-500 .ANG.. The use of WN reduces the
sheet resistance of the contact. As a result, a thinner metal layer
for the interconnect can be used for the same total sheet
resistance. This, in turn, results in reduced capacitance. This is
especially useful for bitlines in DRAM memory chips.
Next, a metal interconnect layer 218 is deposited, patterned and
etched. Preferably, metal interconnect layer 218 comprises W. This
is followed by an anneal. The anneal occurs at a temperature on the
order of 800.degree. C. and has a duration on the order of 5
minutes.
TABLE 1
__________________________________________________________________________
Kelvin Contact (ohm/contact) M1 N-channel N-channel P-channel
P-channel Process ohm/sq 0.22 .mu.m 0.30 .mu.m 0.22 .mu.m 0.30
.mu.m
__________________________________________________________________________
Process 1 Ti(400.ANG.)/WN/RTP 0.94 126 61 1436 900 after
800.degree. C. 5 min anneal 0.76 532 551 n/a n/a Process 2
Ti(200.ANG.)/RTP/WN 1.31 129 65 237 151 after 800.degree. C. 5 min
anneal 1.33 349 359 2136 2413 Process 3
Ti(200.ANG.)/TiN(100.ANG.)/RTP/WN 1.25 72 41 240 204 after
800.degree. C. 5 min anneal 1.20 373 366 1711 2013 Process 4
Ti(200.ANG.)/TiN(500.ANG.)/RTP 1.46 135 47 304 186 after
800.degree. C. 5 min anneal 1.36 353 295 1603 1724
__________________________________________________________________________
Table 1 shows the contact and sheet resistances for several
processes and for both n-channel and p-channel transistors. Two
transistor sizes are shown for each type. In all cases, Ti was
deposited by collimated sputtering. The thickness of the WN is 500
.ANG. on the field areas. Each process was subsequently subjected
to a 800.degree. C. 5 min anneal after M1 deposition. Resistance
values are shown both before and after the final anneal.
In Process 1, Ti is deposited on silicon and followed by
tungsten-nitride deposition. The Ti thickness is 400 .ANG. and the
WN thickness is 500 .ANG.. A 725.degree. C., 30 sec. rapid thermal
process for silicide formation follows deposition. The sheet
resistance (M1 ohm/sq) is low. However, this process results in
higher contact resistance, especially for the P-channel
transistors. The n/a in Table 1 refers to a resistance that is so
high that it is out of the measurement range. Even worse contact
resistance is observed when the Ti thickness is reduced to 200
.ANG.A. Leakage current was also found to be high using this
process.
Process 2 relates to the first embodiment of the invention in which
200 .ANG. of Ti is deposited over silicon. The RTP anneal (for
silicide formation) is then performed prior to the deposition of
500 .ANG. of WN. The sheet resistance is increased from that of
Process 1 but lower than that of Process 4. Contact resistance is
significantly reduced for the P-channel transistors from Process 1.
Contact resistance after the 5 min anneal is also reduced.
Process 3 relates to the second embodiment of the invention in
which 200 .ANG. of Ti is deposited followed by 100 .ANG. of TiN.
The RTP anneal (for silicide formation) is then performed followed
by the deposition of 500 .ANG. of WN. Sheet resistance is the
lowest for the 4 processes. In addition, contact resistance is
reduced from Process 1 for both P-channel and N-channel
transistors. Thinner TiN results in lower stress compared to
Process 4 and WN deposited after the RTP silicide react in anneal
prevents punchthrough.
Process 4 is a prior art process in which 200 .ANG. of Ti is
deposited followed by ECVD of 500 .ANG. of TiN. RTP for silicide
formation is then performed. Sheet resistance is higher than in the
other processes that use WN. Contact resistance is similar to that
of Process 3. In addition, there are several process concerns with
the ECVD of 500 .ANG. of TiN. First, the process is slow and has a
high carbon content. Second, 500 .ANG. is a minimum thickness and
this thickness can result in stress problems.
While this invention has been described with reference to
illustrative embodiments, this description is not intended to be
construed in a limiting sense. Various modifications and
combinations of the illustrative embodiments, as well as other
embodiments of the invention, will be apparent to persons skilled
in the art upon reference to the description. It is therefore
intended that the appended claims encompass any such modifications
or embodiments.
* * * * *