U.S. patent number 5,864,499 [Application Number 08/958,487] was granted by the patent office on 1999-01-26 for non-volatile data storage unit and method of controlling same.
This patent grant is currently assigned to Micron Technology, Inc.. Invention is credited to Michael S. Briner, Frankie F. Roohparvar.
United States Patent |
5,864,499 |
Roohparvar , et al. |
January 26, 1999 |
**Please see images for:
( Certificate of Correction ) ** |
Non-volatile data storage unit and method of controlling same
Abstract
A non-volatile data storage unit having a data input and a
volatile memory device for storing data. The volatile memory device
is preferably a latch circuit made up of a pair of cross-coupled
inverter circuits which store the data in complementary form. A
non-volatile memory device, such as a pair of flash memory cells,
is included which also store data in complementary form. Control
circuitry is provided for controlling the operation of the data
storage unit, including circuitry for transferring data from the
data input to the volatile memory device and circuitry for
programming the non-volatile memory device with data from the
volatile memory device. The storage unit also preferably includes
circuitry for transferring data stored in the non-volatile memory
device to the volatile memory device, with such transfer typically
taking place after an interruption of power to the storage
unit.
Inventors: |
Roohparvar; Frankie F.
(Cupertino, CA), Briner; Michael S. (San Jose, CA) |
Assignee: |
Micron Technology, Inc. (Santa
Clara, CA)
|
Family
ID: |
24024394 |
Appl.
No.: |
08/958,487 |
Filed: |
October 24, 1997 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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668398 |
Jun 25, 1996 |
5862345 |
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508864 |
Jul 28, 1995 |
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Current U.S.
Class: |
365/185.08;
365/185.33 |
Current CPC
Class: |
G11C
14/00 (20130101) |
Current International
Class: |
G11C
14/00 (20060101); G11C 014/00 (); G11C
016/04 () |
Field of
Search: |
;365/185.07,185.08,185.22,185.33,185.29,185.04,218,156,228 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Nelms; David
Assistant Examiner: Phan; Trong
Attorney, Agent or Firm: Schwegman, Lundberg, Woessner &
Kluth, P.A.
Parent Case Text
This is a continuation application No. 08/668,398, filed Jun. 25,
1996, now U.S. Pat. No. 5,682,345 which is a continuation of
application No. 08/508,864, filed Jul. 28, 1995, now abandoned.
Claims
We claim:
1. A method of transferring data from one or more non-volatile
memory cells to a volatile storage unit after loss of power to the
volatile storage unit, with each nonvolatile memory cell being
coupled to a word line, a source line, and a bit line, and the
volatile storage unit having a voltage supply node requiring a
nominal supply voltage, the method comprising:
applying a positive voltage to the word line of one or more of the
non-volatile memory cells, while the voltage supply node has a
voltage less than the nominal supply voltage; and
increasing the voltage of the voltage supply node toward the
nominal supply voltage a period of time after initially applying
the positive voltage to the word line of the one or more of the
non-volatile memory cells.
2. The method of claim 1 further comprising:
electrically coupling the bit lines of the one or more non-volatile
memory cells to the volatile storage unit before applying the
positive voltage to the word line of the one or more non-volatile
memory cells; and
applying a ground voltage to the source line of the one or more
non-volatile memory cells, while the voltage supply node has a
voltage less than the nominal supply voltage.
3. The method of claim 1 wherein increasing the voltage of the
voltage supply node toward the nominal supply voltage comprises
linearly increasing the voltage of the supply node from a ground
voltage to nominal supply voltage.
4. The method of claim 1 further comprising detecting a
predetermined increase in a primary power supply voltage before
applying the positive voltage to the word line of one or more of
the non-volatile memory cells.
5. The method of claim 1 wherein the volatile storage unit
comprises a latch circuit having two outputs, and the method
further comprises providing capacitively balanced loads on the two
outputs, before applying the positive voltage to the word line of
the one or more of the nonvolatile memory cells.
6. A method of transferring data from one or more non-volatile
memory cells to a volatile latch circuit after loss of a primary
power supply voltage, with each nonvolatile memory cell being
coupled to a word line, a source line, and a bit line, and the
volatile storage unit having a voltage supply node requiring a
nominal supply voltage, the method comprising:
detecting a predetermined increase in the primary power supply
voltage;. electrically coupling the bit line of the one or more
non-volatile memory cells to the volatile storage unit, after
detecting the predetermined increase;
applying a ground reference voltage to the source line of the one
or more non-volatile memory cells, after detecting the
predetermined increase and while the voltage supply node has a
voltage less than the nominal supply voltage;
applying a positive voltage to the word line of the one or more
non-volatile memory cells, after detecting the predetermined
increase and while the voltage supply node has a voltage less than
the nominal supply voltage; and
increasing the voltage of the voltage supply node toward the
nominal supply voltage a period of time after initially applying
the positive voltage to the word line of the one or more of the
non-volatile memory cells.
7. The method of claim 6 wherein increasing the voltage of the
voltage supply node toward the nominal supply voltage comprises
linearly increasing the voltage of the supply node from a ground
voltage to nominal supply voltage.
8. The method of claim 6 wherein the volatile latch circuit
includes two outputs, and the method further comprises providing
capacitively balanced loads on the two outputs, before applying the
positive voltage to the word line of the one or more of the
non-volatile memory cells.
9. A method of using a non-volatile memory cell with a
predetermined drive capability to drive a volatile latch circuit
normally driven with a drive capability greater than the
predetermined drive capability of the non-volatile memory cell, the
method comprising:
providing a voltage supply node of the volatile latch circuit with
a voltage less than a nominal supply voltage required to maintain
data;
electrically coupling a bit line of the non-volatile memory cell to
the volatile latch circuit;
applying a positive voltage to a word line of the non-volatile
memory cell, while the voltage supply node has a voltage less than
the nominal supply voltage; and
increasing the voltage of the voltage supply node toward the
nominal supply voltage a period of time after initially applying
the positive voltage to the word line of the non-volatile memory
cell.
10. The method of claim 9 wherein increasing the voltage of the
voltage supply node toward the nominal supply voltage comprises
linearly increasing the voltage of the supply node from a ground
voltage to the nominal supply voltage.
11. The method of claim 9 wherein the volatile latch circuit
includes two outputs, and the method further comprises providing
capacitively balanced loads on the two outputs, before applying the
positive voltage to the word line of the non-volatile memory cell.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates generally to data storage and in
particular to a non-volatile data storage unit which may be
programmed to a predetermined value, erased and read and a method
of controlling the data storage unit.
2. Background Art
In many integrated circuit devices, it is desirable to have the
capability of storing certain parameters relating to the operation
of the integrated circuit. By way of example, sometimes an
integrated circuit is implemented so that it can be used in
different operating modes. The circuit can be configured at a
fabrication facility to permanently operate in only one mode,
depending upon the requirements of a particular user. This can be
achieved by modifying the metallization layer of the integrated
circuit so that the desired operating mode is achieved.
This approach has one advantage in that the change in metallization
is permanent and will not be affected by loss of operating power.
However, this advantage is offset by many disadvantages. A major
disadvantage is that further changes in the stored operating
parameters cannot be made once the metallization has been
completed. This is particularly disadvantageous where the value of
the stored parameters is dependent upon the characteristics of the
integrated circuit which frequently cannot be ascertained until the
metallization has been completed. In addition, once the integrated
circuit has been packaged, it is frequently impossible to ascertain
the value of the stored parameter.
The present invention provides the capability of storing operating
parameters in an integrated circuit which can be altered at any
time after the fabrication process. Once a parameter has been
stored, the parameter is retained even in the event of a loss of
power. In addition, the stored parameter can be examined to
determine the state of the parameter. These and other advantages of
the present invention will be obvious to those skilled in the art
upon a reading of the following Detailed Description of the
Invention together with the drawings.
SUMMARY OF THE INVENTION
A non-volatile data storage unit is disclosed having a data input
and a volatile memory device for storing data. Typically, the
volatile memory device is a latch circuit comprising a pair of
cross-coupled inverter circuits which store the data in
complementary form. The data storage unit further includes a
non-volatile memory device such as a pair of flash memory cells
which also store data in complementary form.
Control means is provided for controlling the operation of the data
storage unit. The control means includes load means for
transferring data from the data input to the volatile memory
device. Typically, the load means includes a pair of transistors
coupled between the data inputs and the latch circuit which force
the latch circuit to a state determined by the input data.
The control means further includes program means for programming
the non-volatile memory device with the data stored in the volatile
memory device. In the event the non-volatile memory device is
implemented by a pair of flash memory cells, the current for
programming the cells is preferably provided by output transistors
of the volatile memory device.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a detailed schematic diagram of the subject non-volatile
data storage unit.
FIG. 2 is a timing diagram illustrating the various operating modes
of the subject data storage unit, including the Load Cycle, the
Erase Cycle, the Program Cycle, the Recall Cycle and the Verify
Cycle.
DETAILED DESCRIPTION OF THE INVENTION
Referring to the drawings, FIG. 1 is a detailed schematic diagram
of one embodiment of the present invention. The subject data
storage unit is capable of storing a single bit of parameter data.
Multiple bits can be stored by simply providing a separate storage
unit for each bit. The storage unit includes a non-volatile memory
or Flash section 10, a volatile Latch section 12 and a Comparator
section 14. The flash section includes a pair of flash memory cells
C and C for storing one bit of parameter data in complementary
form. As is well known, a flash cell utilizes a floating gate
transistor having a drain, source, floating gate and control gate.
Data is stored in the cell by adding or removing charge from the
floating gate. Erasure is accomplished by removing charge by way of
Fowler-Nordheim tunneling from the floating gate through a thin
gate oxide disposed intermediate the floating gate and the cell
channel. The flash cells have their common source regions connected
to a common source line which receives signal SL and their control
gates connected to a common word line which receives signal
W.sub.L.
The Latch section 12 includes a pair of cross-coupled inverters
which form a latch circuit. A first inverter 15 includes a P
channel transistor 16 connected in series with an N channel
transistor 18. The common drain connections of transistors 16 and
18 form the output of the inverter and the common gate connection
form the input. The second inverter 19 includes a P channel
transistor 20 connected in series with an N channel transistor 22.
The common drain connection of transistors 20 and 22 form the
output of the second inverter 19 and the common gate connection
forms the input.
As previously noted, the two inverters of the Latch section 12 are
connected to form a latch circuit. In particular, the output of the
first inverter 15, the common drain connection of transistors 16
and 18, is connected to the input of the second inverter 19, the
common gate connection of transistors 20 and 22. The output of the
second inverter 19, the common drain connection of transistors 20
and 22, is connected back to the input of the first inverter 15,
the gates of transistors 16 and 18.
The output of the first inverter 15 of the Latch section 12 is
connected to the drain of flash cell Cby way of a N channel
transistor 26 and the output of the second inverter 19 is connected
to the drain of flash cell C by way of N channel transistor 24. The
gates of the two connect transistors 24 and 26 are connected to a
common control line which carries signal C.sub.N.
Latch section 12 is powered by applying a voltage V.sub.SUP to the
sources of transistors 16 and 20. As will be explained, the
magnitude of the voltage V.sub.SUP can be controlled by
conventional circuitry, the details of which are not described
since they are conventional and form no part of the present
invention.
Data to be loaded into the Latch section 12 is provided in
complementary form A and A by way of N channel transistors 28 and
30. The common gates of the transistors 28 and 30 are connected to
a line which receives a load signal L.sub.D. Transistor 28
functions to couple data input A to the input of the first inverter
15 of Latch section 12 and transistor 30 functions to couple data
input A to the input of the second inverter 19.
The two complementary outputs of the Latch section 12 are coupled
to respective inverters 32 and 34. The outputs of inverters 32 and
34 form the complementary outputs O.sub.T1 and O.sub.T1 of the
subject data storage unit. The outputs of the Latch section 12 are
also coupled to respective inputs of a comparator circuit 14. The
data inputs A and A are also coupled to respective inputs of the
comparator circuit 14. As will be explained, the comparator circuit
14 functions to compare the data stored in the Latch section 12
with the data inputs A and A so that the state of the latch circuit
can be verified. Typically, the output of the Comparator section
14, signal V.sub.ER is wire ORed to other Comparator sections 14
associated with other data storage units so that a single
verification signal V.sub.ER can be used to indicate whether there
is a match between the contents of the Latch section 12 and the
associated data inputs A and A among several of the subject storage
units.
Comparator section 14 includes five N channel transistors 36, 38,
40, 42 and 44. Transistor 36 is coupled between the comparator
output V.sub.ER and the common drain connection of transistors 38
and 42. In addition, the gate of transistor 36 is connected to
receive signal F.sub.v which is active when the state of the
Comparator section 14 is to be sampled. Transistors 38 and 40 are
connected in series, with the gate of transistor 38 connected to
receive data input A and the gate of transistor 40 connected to
receive the output of the first inverter 15 of Latch section 12.
Similarly, transistors 42 and 44 are connected in series, with the
gate of transistor 42 connected to receive data input A and the
gate of transistor 44 connected to receive the output of the second
inverter 19 of Latch section 12. As will be explained, when the
complementary data inputs A and A match the complementary outputs
of the two Latch section inverters, the output of the comparator
circuit 14, V.sub.ER will be high, otherwise the output will be
low.
The present invention provides a high degree of flexibility. There
are a total of five operations which the subject storage unit can
perform, including Load, Erase, Program, Recall and Verify. These
operations will each be described in connection with the timing
diagram of FIG. 2 together with the schematic diagram of FIG. 1. As
will be explained in greater detail, the flash cell C and C are
programmed by first loading the programming data into the Latch
section 12. In addition, the flash cells C and C are read by
transferring the contents of the flash cells to the Latch section
12.
Load The function of the Load cycle is to set the Latch section 12
to a known state based upon the complementary input data A and A.
The Load operation is required prior to the Program operation to
ensure that the Latch circuit 12 is at the desired state.
The beginning of the Load cycle is indicated by time T.sub.0.
Following time To, the input data A and A is applied to the drains
of transistors 28 and 30. Once the input data are stabilized, the
load signal L.sub.D is made active thereby turning on transistors
28 and 30 In addition, the Latch section 12 supply voltage
V.sub.SUP is maintained at its nominal primary supply voltage
V.sub.cc level of +5 volts. Assuming, for example, that A is a high
level, the input of the first inverter 15, the common gates of
transistors 16 and 18 will be pulled up to a high level. At the
same time, complementary signal A will be at a low level and will
tend to pull the input of the second inverter 19, the gates of
transistors 20 and 22, down to a low level by way of load
transistor 30.
This combined opposing action on the inputs of the two inverters
will force the output of the first inverter 15 to a low state and
the output of the second inverter 19 to a high state. The Latch
section 12 will hold or store this data until it is altered by a
subsequent Load operation, until it is changed by a Recall
operation (as will be explained) or until the power is removed from
the system. Load transistors must be of sufficient size so as to be
capable of forcing the Latch section 12 transistors to the desired
state.
Erase The operation for erasing the flash cells C and C commences
at time T.sub.1. This cycle is performed directly on the cells
rather than by way of the Latch section 12. The connect signal
C.sub.N is inactive in this operation so that both connect
transistors 24 and 26 will be non-conductive. Thus, the drains of
cells C and C will be left floating. In addition, signal W.sub.L
connected to the word line of the two cells is grounded and the
signal S.sub.L connected to the sources of the two cells is raised
to a large positive voltage such as +12 volts. As is well known,
under these conditions, the cells C and C will both be erased by
way of Fowler-Nordheim tunneling. The Flash section 10 must then be
appropriately programmed so that the cells C and C will store
complementary data.
Program The Programming cycle commences at time T.sub.2. As
previously noted, the Latch circuit 12 must have been previously
set to the desired programmed state of the Flash section 10. Load
signal L.sub.D is inactive so that transistors 28 and 30 are off.
The supply voltage V.sub.SUP is at a nominal value of +6 volts.
Assume, for example, that the Latch section 12 had previously been
set such that the output of inverter 15 is at a low level and the
output of inverter 19 is at a high level. In that event, the drain
of transistor 24 will be close to the supply voltage V.sub.SUP and
the drain of transistor 26 will be close the circuit common.
The connect signal C.sub.N is made active (high) shortly after time
T.sub.2, thereby turning on transistors 24 and 26 and effectively
connecting the supply voltage V.sub.SUP and circuit common to the
drain of cells C and C, respectively. The connect signal C.sub.N
switches to a high level of +12 volts in the Programming cycle so
that transistors 24 and 26 have a sufficient gate-source voltage to
connect the supply voltage F.sub.SUP of +6 volts to either one of
the drains of cells C and Cdepending upon the data stored in the
latch. In this case, cell C will get the F.sub.SUP on its drain. At
the same time, the control ga of the cells C and C are connected to
word line signal W.sub.L having a magnitude equal to +12 volts. In
fact, in many cases C.sub.N and W.sub.L can be the same signal. The
source line signal S.sub.L is at circuit common and is connected to
the common sources of cells C and C. This combination of voltages
applied to cell C will cause the cell to be programmed whereas
those applied to cell C will not result in programming of the cell.
In order to enable the cells C and C to be programmed to opposite
states, it is necessary to first erase both cells in an Erase cycle
prior to performing the Programming cycle. As previously noted, the
Latch circuit 12 must have also been previously set in order to
carry out a Programming cycle.
Transistor 20 of inverter circuit 19 will provide the programming
current, which is typically 500microamperes, to cell C. If cell C
is being programmed, the programming current is provided by
transistor 16 of inverter circuit 15. Thus, transistors 16 and 20
of the Latch circuit 12 must be of sufficient size to be able to
conduct these programming currents. As previously noted,
transistors 28 and 30 must also be sized so that they have
sufficient strength to force transistors 16 and 20 to a desired
state during the Load cycle. Typically, the programming voltages
will be applied for a relatively long duration ranging from a few
hundred microseconds to a millisecond. Since the data is stored in
cells C and C in complementary form and since, as will be
explained, the cells will be read in a differential manner, there
is a large error tolerance margin. Accordingly, it is not necessary
to perform any type of program verification as is frequently done
in flash memory systems to confirm that the data has been properly
programmed.
Recall The Recall cycle is illustrated in the FIG. 2 diagram
beginning at time T.sub.3. In this operation, the complementary
states of cells C and C are transferred to the Latch section 12.
When power is removed from the data storage unit, the data is not
retained in volatile Latch section 12. Accordingly, when power is
reapplied, initialization circuitry is used to cause the transfer
of the data stored in the non-volatile cells C and C to the Latch
section 12.
Since the flash cells C and C have a limited drive capability and
would not normally have sufficient strength to force the
transistors of the Latch section 12 to a desired state, the supply
voltage V.sub.SUP is momentarily dropped to a low level approaching
ground potential in the initial stage of the Recall operation. In
addition, the connect signal C.sub.N is made active thereby
connecting the Flash section 10 to the Latch section 12 by way of
transistors 24 and 26. The word line of cells C and C is connected
to a signal W.sub.L having a magnitude equal to the primary supply
voltage V.sub.cc of typically +5 volts. Again, signals W.sub.L and
C.sub.N can be the same signal for this operation.
The Recall cycle is preferably initiated by some form of
power-on-reset circuit which will cause the Recall cycle to be
performed at power on and when the primary supply voltage V.sub.cc
drops to some predetermined level which would possibly affect the
state of the Latch circuit 12. The Recall cycle is initiated by the
power-on-reset circuit when the circuit has detected that the
primary supply voltage V.sub.cc has ramped up to about +3 volts
after initial power on or has ramped up to about +3 volts after a
drop in voltage V.sub.cc below that level.
During the Recall cycle, the common source line signal S.sub.L is
also set to ground potential. Assuming that cell C has been
programmed and cell C is in an erased state, cell C will be
non-conductive so that the input of inverter 15 of the Latch
section l2 will not be affected. Cell C will be conductive and tend
to pull the input of inverter 19 of the Latch section 12 down to
ground potential.
Since the Latch section 12 is not powered at this point, cell C is
capable of pulling the input of inverter 19 down to a low level
despite the limited drive capability of the cells. As can be seen
from the FIG. 2 timing diagram, voltage V.sub.SUP is held to a low
value momentarily and then is increased to the normal operating
level. Preferably, the voltage is increased at a slow rate.
As the supply voltage V.sub.sup increases, the cell C will continue
to hold the input of inverter 19 at a low level so that P channel
transistor 20 will proceed to turn on. This will cause the output
of inverter 19 to be high which will, in turn, cause the input of
inverter 15 to also be high. Thus, transistor 18 of inverter 15
will also begin to turn on thereby causing the output of inverter
15 to go low thereby reinforcing cell C in pulling down the input
of inverter 19. Eventually, the supply voltage V.sub.SUP will be at
the normal high voltage of V.sub.cc or typically +5volts and the
Latch circuit 12 will be in the desired state of indicating the
state of the Flash section 10. Even though cell C has a very small
drive capability, by controlling the supply voltage V.sub.SUP as
described, the cell is capable of forcing the Latch section 12 to
the desired state. Programmed cell C will not have much, if any,
tendency to pull the input of inverter 15 down and thus will not
oppose the action of cell C. However, even if the programmed
threshold voltage of cell C approached the erased threshold voltage
of cell C , it can be seen that the cell with the largest cell
current will still be able to control the state of the Latch
circuit 12. This differential action enhances the reliability of
the operation of the subject data storage unit. Note also that the
outputs of inverters 15 and 19 are coupled to respective inverters
32 and 34 so that loading on the Latch section outputs will be
equal. The Latch section will thus remain capacitively balanced so
as to enhance the ability of the flash cells C and C to force the
Latch section to any desired state.
Verify As previously explained, the Verify cycle is used to
determine the state of the Latch section 12. This operation can be
used to determine the state of the Flash section 10 if it preceded
by a Recall cycle. The Verify cycle utilizes the complementary data
inputs A and A and compares them with the state of the Latch
section 12. Comparator section 14 functions essentially as an
exclusive NOR circuit and provides a logic low output V.sub.ER in
the event there is a match between the Latch section 12 and the
data input A and A.
By way of example, assume that a Verify cycle is to take place so
that the verify signal F.sub.v, is made active. This will cause
transistor 36 of the Comparator section 14 to be conductive.
Further assume that data input A is a logic "1" (high) so that A is
a logic "0" (low). Still further assume that inverter 15 output of
the Latch section 12 is a logic "0" so that the inverter 19 output
will be a logic "1" . Since input A is high and since the output of
inverter 15 is low, transistor 38 of the Comparator 14 section will
be conductive and transistor 40 will be off. Similarly, since input
A is low and the output of inverter 19 is high, transistor 42 will
be off and transistor 44 will be on. There is a pull-up device (not
depicted) connected between the output of the Comparator section 14
and voltage V.sub.cc. As a result of transistors 40 and 42 being
off, there will be no conductive path between the source of
transistor 36 and the circuit common. Accordingly, the output
V.sub.ER will remain in a high state ("1") indicating a valid
compare.
If the outputs of inverters 15 and 19 were logic "1"and "0",
respectively, and the data inputs A and Aremain the same,
transistors 38 and 40 will both be conductive. Thus, when
transistor 36 is turned on by signal F.sub.v, the output V.sub.ER
will be pulled down to a logic "0" indicating a no compare
condition.
In the event the data inputs A and A are a logic "0"and "1",
respectively, and the outputs of inverters 15 and 19 are a logic
"1" and "0", respectively, transistors 38 and 44 will be off. Thus,
signal V.sub.ER will be a logic "1" thereby indicating a valid
compare. Continuing, if inputs A and A were a logic "0" and "1",
respectively and inverters 15 and 19 were a logic "0" and "1",
respectively, transistors 42 and 44 will be conductive so that
signal V.sub.ER will be at a logic "0", thereby indicating a no
compare.
Thus, a novel data storage unit has been disclosed. Although one
embodiment has been described in some detail, it is to be
understood that certain changes can be made by those skilled in the
art without departing from the spirit and scope of the invention as
defined by the appended claims. 16
* * * * *