U.S. patent number 5,495,124 [Application Number 08/141,659] was granted by the patent office on 1996-02-27 for semiconductor device with increased breakdown voltage.
This patent grant is currently assigned to Mitsubishi Denki Kabushiki Kaisha. Invention is credited to Tomohide Terashima.
United States Patent |
5,495,124 |
Terashima |
February 27, 1996 |
Semiconductor device with increased breakdown voltage
Abstract
A low concentration impurity region 6 of a second conductivity
type is formed to cover lower portion of a high concentration
impurity region 8 of the second conductivity type. Consequently,
impurity concentration gradient between the high concentration
impurity region 8 of the second conductivity type and the low
concentration impurity layer 2 of a first conductivity type can be
made moderate to relax the electric field, which leads to provision
of higher breakdown voltage of the semiconductor device. Further,
the depth of impurity diffusion of the low concentration impurity
region 6 of the second conductivity type from the main surface of
the low concentration impurity layer 2 of the first conductivity
type is made at least three times the depth of impurity diffusion
of the high concentration impurity region 8 of the second
conductivity type from the main surface of the low concentration
impurity layer 2 of the first conductivity type. Therefore, minimum
dimensions necessary for suppressing the electric field can be set
in the semiconductor device, and therefore the semiconductor device
comes to have higher breakdown voltage efficiently while not
preventing miniaturization.
Inventors: |
Terashima; Tomohide (Hyogo,
JP) |
Assignee: |
Mitsubishi Denki Kabushiki
Kaisha (Tokyo, JP)
|
Family
ID: |
26491929 |
Appl.
No.: |
08/141,659 |
Filed: |
October 26, 1993 |
Foreign Application Priority Data
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Jul 7, 1993 [JP] |
|
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5-168089 |
Oct 8, 1993 [JP] |
|
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5-253407 |
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Current U.S.
Class: |
257/550; 257/369;
257/409; 257/545; 257/E21.537; 257/E27.066; 257/E29.063 |
Current CPC
Class: |
H01L
21/74 (20130101); H01L 27/0927 (20130101); H01L
29/1083 (20130101) |
Current International
Class: |
H01L
21/74 (20060101); H01L 29/10 (20060101); H01L
21/70 (20060101); H01L 27/085 (20060101); H01L
27/092 (20060101); H01L 29/02 (20060101); H01L
029/36 () |
Field of
Search: |
;257/550,545,369,372,409,491,492,370,500 |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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54-11682 |
|
Jan 1979 |
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JP |
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2-170571 |
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Jul 1990 |
|
JP |
|
Other References
Terashima et al., "Development of Structure of 600V HIVC",
published Oct. 29, 1992. .
Proceedings of The 5th International Symposium on Power
Semiconductor Devices and ICs, ISPSD '93, published May 18,
1993..
|
Primary Examiner: Crane; Sara W.
Assistant Examiner: Bowers; Courtney A.
Attorney, Agent or Firm: Lowe, Price, LeBlanc &
Becker
Claims
What is claimed is:
1. A semiconductor device, comprising:
a low concentration impurity layer of a first conductivity type
having a main surface;
a low concentration impurity layer of a second conductivity type
formed on said main surface of said low concentration impurity
layer of the first conductivity type;
a high concentration impurity region of the second conductivity
type formed on a prescribed region of said main surface of said low
concentration impurity layer of the first conductivity type so as
to be enclosed by said low concentration impurity layer of the
first conductivity type and the low concentration impurity layer of
the second conductivity type; and
a low concentration impurity region of the second conductivity type
formed in said low concentration impurity layer of the first
conductivity type so as to cover a lower portion of said high
concentration impurity region of the second conductivity type,
wherein
said low and high concentration impurity regions of the second
conductivity type extend to depths below the main surface of the
low concentration impurity layer of the first conductivity type so
that the depth of the low concentration impurity region of said
second conductivity type is three times the depth of the high
concentration impurity region of the second conductivity type.
2. A semiconductor device according to claim 1, wherein
the depth of impurity diffusion of said low concentration impurity
region of the second conductivity type from said main surface of
said low concentration impurity layer of the first conductivity
type extends from a point where an impurity concentration of said
high concentration impurity region of the second conductivity type
assumes the maximum value to an interface with said low
concentration impurity layer of said first conductivity type, in
accordance with a log scale.
3. The semiconductor device according to claim 1, wherein,
said high concentration impurity region of said second conductivity
type has an impurity concentration profile which extends in depth
from a position where the impurity concentration assumes the
maximum value to a position where a quadratic differential of the
concentration assumes a positive maximum value, in accordance with
a log scale.
4. A semiconductor device, comprising:
a low concentration impurity layer of a first conductivity type
having a main surface;
a low concentration impurity layer of a second conductivity type
formed on said main surface of said low concentration impurity
layer of the first conductivity type;
a high concentration impurity region of the second conductivity
type formed on a prescribed region of said main surface of said low
concentration impurity layer of the first conductivity type so as
to be enclosed by said low concentration impurity layer of the
first conductivity type and the low concentration impurity layer of
the second conductivity type; and
a low concentration impurity region of the second conductivity type
formed in said low concentration impurity layer of the first
conductivity type so as to cover a lower portion of said high
concentration impurity region of the second conductivity type,
wherein
said low and high concentration impurity regions of the second
conductivity type extend to depths below the main surface of the
low concentration impurity layer of the first conductivity type so
that the depth of the low concentration impurity region of said
second conductivity type is at least three times the depth of the
high concentration impurity region of the second conductivity type,
wherein
said high concentration impurity region of the second conductivity
type has a closed planar pattern including ends, each end having an
arch which has a radius of at least three times the depth of the
high concentration impurity region of the second conductivity type
from said main surface of the low concentration impurity layer of
the first conductivity type.
5. A semiconductor device, comprising:
a low concentration impurity layer of a first conductivity type
having a main surface;
a low concentration impurity layer of a second conductivity type
formed on said main surface of said low concentration impurity
layer of the first conductivity type;
a high concentration impurity region of the second conductivity
type formed on a prescribed region of said main surface of said low
concentration impurity layer of the first conductivity type so as
to be enclosed by said low concentration impurity layer of the
first conductivity type and the low concentration impurity layer of
the second conductivity type; and
a low concentration impurity region of the second conductivity type
formed in said low concentration impurity layer of the first
conductivity type so as to cover a lower portion of said high
concentration impurity region of the second conductivity type,
wherein
said low and high concentration impurity regions of the second
conductivity type extend to depths below the main surface of the
low concentration impurity layer of the first conductivity type so
that the depth of the low concentration impurity region of said
second conductivity type is at least three times the depth of the
high concentration impurity region of the second conductivity
type,
wherein said low concentration impurity region of the second
conductivity type has a closed planar pattern including ends, each
end having an arch which has a radius at least three times the
depth of the low concentration impurity region of the second
conductivity type from said main surface of said low concentration
impurity layer of the first conductivity type.
6. A semiconductor device, comprising:
a low concentration impurity layer of a first conductivity type
having a main surface;
a low concentration impurity layer of a second conductivity type
formed on said main surface of said low concentration impurity
layer of the first conductivity type;
a high concentration impurity region of the second conductivity
type formed on a prescribed region of said main surface of said low
concentration impurity layer of the first conductivity type so as
to be enclosed by said low concentration impurity layer of the
first conductivity type and the low concentration impurity layer of
the second conductivity type; and
a low concentration impurity region of the second conductivity type
formed in said low concentration impurity layer of the first
conductivity type so as to cover a lower portion of said high
concentration impurity region of the second conductivity type,
wherein
said low and high concentration impurity regions of the second
conductivity type extend to depths below the main surface of the
low concentration impurity layer of the first conductivity type so
that the depth of the low concentration impurity region of said
second conductivity type is at least three times the depth of the
high concentration impurity region of the second conductivity
type,
wherein said high concentration impurity region of the second
conductivity type and said low concentration impurity region of the
second conductivity type each have a closed planar pattern
including ends, each end have an arch of a prescribed radius
and
difference in radii of the ends of said high concentration impurity
region of the second conductivity type and said low concentration
impurity region of said second conductivity type is made larger
than the difference between the depth of the low concentration
impurity region of the second conductivity type from said main
surface of said low concentration impurity layer of the first
conductivity type and the depth of the high concentration impurity
region of the second conductivity type from said main surface of
said low concentration impurity layer of the first conductivity
type.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
The present invention relates to semiconductor devices and
manufacturing method thereof, and, more specifically, to a
semiconductor device breakdown voltage of which can be increased,
and to the method of manufacturing the same.
2. Description of the Background Art
Recently, high voltage integrated circuits (HVIC) including CMOS
transistors, bipolar transistors, high voltage isolating structure
as well as level shift function by high voltage devices have been
much developed in order to realize lower cost of power control
system, lower power consumption and down sizing while providing
higher performance.
FIG. 37 is a cross section showing a structure of a conventional
CMOS transistor.
Referring to FIG. 37, an n.sup.- epitaxial layer 10 is formed on a
main surface of a p.sup.- semiconductor substrate 2. An n.sup.+
buried impurity region 8 is formed enclosed by p.sup.-
semiconductor substrate 2 and n.sup.- epitaxial layer 10.
A CMOS transistor is formed on the surface of n.sup.- epitaxial
layer 10 above n.sup.+ buried impurity region 8.
The CMOS transistor includes a p channel MOS transistor 28 and an n
channel MOS transistor 38.
The p channel MOS transistor 28 includes a gate electrode 22 formed
on the surface of n.sup.- epitaxial layer 10 with a gate insulating
film 20 interposed, and source/drain regions 24 and 26 of p type
impurity regions formed at positions sandwiching, from left and
right, the gate electrode 22.
The n channel MOS transistor 38 includes a gate electrode 32 formed
on the surface of n.sup.- epitaxial layer 10 with a gate insulating
film 30 interposed therebetween, and source/drain regions 34 and 36
of n type impurity regions formed at positions sandwiching from
left and right, the gate electrode 32 in a p.sup.- impurity region
12 formed in n.sup.- epitaxial layer 10.
At the surface of n.sup.- epitaxial layer 10, the CMOS transistor
is surrounded by an element isolating oxide film 18.
In the n.sup.- epitaxial layer 10, an n.sup.+ collector wall 14 is
provided to surround the CMOS transistor, which is in turn
surrounded by a p type isolating region 16.
FIG. 38 is a schematic view showing a depletion layer generated in
the semiconductor device of FIG. 37.
Referring to FIG. 38, assume that the potential of n.sup.+ buried
impurity region 8 is made higher with respect to the semiconductor
substrate 2.
At this time, a depletion layer is generated from the interface
between p.sup.- semiconductor substrate 2 and n.sup.+ buried
impurity region 8 and from the pn junction between p.sup.-
semiconductor substrate 2 and n.sup.- epitaxial layer 10 over the
hatch region.
The electric field in the semiconductor device with this depletion
layer formed will be described with reference to FIGS. 39 to
41.
FIG. 39 is a perspective view of n.sup.+ buried impurity region 8
which is cut at the interface between p.sup.- semiconductor
substrate 2 and n.sup.- epitaxial layer 10.
It is assumed that the impurity concentration has been sufficiently
lowered to increase the breakdown voltage of the p.sup.-
semiconductor substrate 2.
Referring to FIG. 38, the electric field in the direction (A-A' in
the figure) perpendicular to the bottom surface of n.sup.+ buried
impurity region 8 is constant in the region of p.sup.-
semiconductor substrate 2, as shown by the dotted line in FIG.
40.
Meanwhile, the electric field at the corner portion (the direction
of B-B' in FIG. 39) of n.sup.+ buried impurity region 8 shows the
maximum value at the pn junction portion between n.sup.+ buried
impurity region 8 and p.sup.- semiconductor substrate 2.
The internal electric field and the inclination of the electric
field of n.sup.+ buried impurity region 8 and p.sup.- semiconductor
substrate 2 are represented, in approximation, by the following
equations (5) and (6). ##EQU1##
Here, it is assumed that the electric field at the pn junction
interface at the corner portion of n.sup.+ buried impurity region 8
is constant.
In the above equations, Q represents the total of space charges on
the side of n.sup.+ buried impurity region 8 where electric line of
force passing through the hatch portion of FIG. 39 terminates, l'
represents corner radius of n.sup.+ buried impurity region 8, and
r' represents the depth of diffusion of n.sup.+ impurity region
3.
As can be seen from equations (5) and (6), at the corner portion,
the electric field at the pn junction interface changes, and
provides the maximum electric field at the interface of the pn
junction.
Namely, the breakdown voltage of the semiconductor device as a
whole is determined by this maximum value of the electric
field.
FIG. 41 shows the relation between r' and the electric field.
FIG. 41 shows the change of the electric field E when r' is
multiplied by .alpha. with the value of .beta.', which is
l'/r'=.beta.', being changed to 0, 1 and 3, assuming that the value
of the electric field E (x=r') is 1 when the size of l' in the
perspective view of FIG. 39 is 0.
As can be seen from FIG. 41, when the value of .alpha. is set to 3
or more, the electric field can be suppressed to about 1/10 when
.beta.'=0.
If the value of .alpha. is set to be 3 or more with the value of
.beta.' being 1 or 3, the electric field can be further suppressed.
In other words, by setting the value of .alpha. to 3 or more, that
is, by increasing the depth of diffusion of n.sup.+ buried impurity
region 8, the electric field generated in the semiconductor device
can be suppressed to be small, and therefore a semiconductor device
having high breakdown voltage can be provided.
However, when the depth of diffusion of n.sup.+ buried impurity
region 8 is increased, the diffusion in the lateral direction also
increases.
For example, referring to FIGS. 42 and 43, an isolation region per
one npn transistor of a class having the breakdown voltage of about
30 V requires the area of
When the distance X.sub.j of n.sup.+ buried impurity region 8 is
tripled from 5 .mu.m to 15 .mu.m, it requires expansion of the size
in the lateral direction of 10 .mu.m.
Therefore, the isolation region would be
and therefore the area of the isolating region per one npn
transistor would be increased by about
This increase of the area is against the recent demand of
miniaturizing the semiconductor devices, and therefore the increase
of the depth of diffusion of the n.sup.+ buried impurity region
cannot be adopted as a method of suppressing the electric
field.
SUMMARY OF THE INVENTION
Therefore, an object of the present invention is to provide a
semiconductor device of which breakdown voltage can be
increased.
Another object of the present invention is to provide a
semiconductor device which can be miniaturized.
A further object of the present invention is to provide a method of
manufacturing a semiconductor device of which breakdown voltage can
be increased.
A still further object of the present invention is to provide a
method of manufacturing a semiconductor device which can be
miniaturized.
In order to attain the above described objects, the semiconductor
device in accordance with the present invention includes a low
concentration impurity layer of a first conductivity type having a
main surface; a low concentration impurity layer of a second
conductivity type formed on the main surface of the low
concentration impurity layer of the first conductivity type; a high
concentration impurity region of the second conductivity type
formed on a prescribed region of the main surface of the low
concentration impurity layer of the first conductivity type so as
to be enclosed by the low concentration impurity layer of the first
conductivity type and the low concentration impurity layer of the
second conductivity type; and a low concentration impurity region
of the first conductivity type formed in the low concentration
impurity layer of the first conductivity type so as to cover lower
portion of the high concentration impurity region of the second
conductivity type.
According to the semiconductor device, the low concentration
impurity region of the second conductivity type is formed to cover
the high concentration impurity region of the second conductivity
type.
Therefore, the impurity concentration gradually changes from the
high concentration impurity region of the second conductivity type
to the low concentration impurity region of the first conductivity
type.
Consequently, the extent of the depletion layer formed at the
interface between the high concentration impurity region of the
second conductivity type and the low concentration impurity layer
of the first conductivity type can be suppressed.
In the present invention, preferably, the depth of impurity
diffusion of the low concentration impurity region of the second
conductivity type from the main surface of the low concentration
impurity layer of the first conductivity type is set to be three
times or more than the depth of impurity diffusion of the high
concentration impurity region of the second conductivity type from
the main surface of the low concentration impurity layer of the
first conductivity type.
Consequently, the depth of impurity diffusion of the low
concentration impurity region of the second conductivity type and
the depth of impurity diffusion of the high concentration impurity
region of the second conductivity type can be set to the minimum
values necessary for suppressing the electric field.
As a result, breakdown voltage of the semiconductor device can be
increased efficiently, while not preventing miniaturization of the
device.
Therefore, a semiconductor device having high performance and high
reliability can be provided.
In the present invention, more preferably, the depth of impurity
diffusion of the low concentration impurity region of the second
conductivity type from the main surface of the low concentration
impurity layer of the first conductivity type is, in accordance
with a log scale, the distance from a point at which the
concentration of the high concentration impurity region of the
second conductivity type assumes the maximum value from the
interface of the low concentration impurity layer of the first
conductivity type. Therefore, the depth of impurity diffusion of
the low concentration impurity region of the second conductivity
type and the depth of impurity diffusion of the high concentration
impurity region of the second conductivity type can be set to the
minimum values necessary for suppressing the electric field.
Therefore, breakdown voltage of the semiconductor device can be
increased efficiently, while not preventing miniaturization of the
device.
Therefore, a semiconductor device having high performance and high
reliability can be provided.
More preferably, in the present invention, the depth of impurity
diffusion of the high concentration impurity region of the second
conductivity type from the main surface of the low concentration
impurity layer of the first conductivity type is, in accordance
with a log scale, a distance from a point where the concentration
of the high concentration impurity region of the second
conductivity type assumes the maximum value to the point at which
quadratic differential of the impurity concentration assumes a
positive maximum value.
Therefore, the depth of impurity diffusion of the low concentration
impurity region of the second conductivity type and the depth of
impurity diffusion of the high concentration impurity region of the
second conductivity type can be set to the minimum values necessary
for suppressing the electric field. Consequently, breakdown voltage
of the semiconductor device can be increased efficiently, while not
preventing miniaturization of the device.
Therefore, a semiconductor device having high performance and high
reliability can be provided.
In the present invention, more preferably, the high concentration
impurity region of the second conductivity type has a closed planar
pattern including corners, and the corner is formed to have an arc
of which radius is at least three times the depth of impurity
diffusion of the high concentration impurity region of the second
conductivity type from the main surface of the low concentration
impurity layer of the first conductivity type. Consequently, the
depth of impurity diffusion can be set to the minimum value
necessary for suppressing the electric field at the corner portion
of the high concentration impurity region of the second
conductivity type. Consequently, the corner portion of the high
concentration impurity region of the second conductivity type comes
to have high breakdown voltage, and hence the semiconductor device
as a whole comes to have higher breakdown voltage, while not
preventing the miniaturization of the semiconductor device.
More preferably, in the present invention, the low concentration
impurity region of the second conductivity type has a closed planar
pattern including corners, and the corners are each formed to have
an arc of which radius is at least three times the depth of
impurity diffusion of the low concentration impurity region of the
second conductivity type from the main surface of the low
concentration impurity layer of the first conductivity type.
Consequently, the depth of impurity diffusion can be set to the
minimum value necessary for suppressing the electric field at the
corner portion of the low concentration impurity region of the
second conductivity type.
Consequently, the corner of the low concentration impurity region
of the second conductivity type comes to have higher breakdown
voltage, and hence the semiconductor device as a whole comes to
have higher breakdown voltage, while not preventing miniaturization
of the semiconductor device.
In the present invention, more preferably, the high concentration
impurity region of the second conductivity type and the low
concentration impurity region of the second conductivity type have
closed planar patterns including corners, and the difference
between radii of the arcs of the corners of the high concentration
impurity region of the second conductivity type and the low
concentration impurity region of the second conductivity type is
set such that it is greater than the difference between the depth
of impurity diffusion of the low concentration impurity region of
the second conductivity type from the main surface of the low
concentration impurity layer of the first conductivity type and the
depth of impurity diffusion of the high concentration impurity
region of the second conductivity type from the main surface of the
low concentration impurity layer of the first conductivity
type.
Consequently, the electric field at the corners of the high
concentration impurity region of the second conductivity type and
the low concentration impurity region of the second conductivity
type can be relaxed.
Consequently, the corners of the low concentration impurity region
of the second conductivity type and the high concentration impurity
region of the second conductivity type come to have higher
breakdown voltage, and hence the semiconductor device as a whole
comes to have higher breakdown voltage, while not preventing
miniaturization of the semiconductor device.
In order to attain the above described objects, the method of
manufacturing the semiconductor device in accordance with the
present invention includes the following steps.
At first, an impurity of the second conductivity type is introduced
to a prescribed region of the main surface of the low concentration
impurity layer of the first conductivity type by using a first
photomask having a prescribed pattern, and thus a low concentration
impurity region of the second conductivity type is formed.
Thereafter, an impurity of the second conductivity type is
introduced to a prescribed region of the main surface of the low
concentration impurity layer of the first conductivity type by
using a second mask having a prescribed pattern such that it is
covered by the low concentration impurity region of the second
conductivity type, and thus the high concentration impurity region
of the second conductivity type is formed.
Then, the low concentration impurity region of the second
conductivity type is formed by epitaxial growth on the main surface
of the low concentration impurity layer of the first conductivity
type.
According to this method of manufacturing, the low concentration
impurity region of the second conductivity type is formed to cover
the high concentration impurity region of the second conductivity
type.
Accordingly, the concentration of impurity changes gradually from
the high concentration impurity region of the second conductivity
type to the low concentration impurity layer of the first
conductivity type.
Consequently, the extent of depletion layer formed at the interface
between the high concentration impurity region of the second
conductivity type and the low concentration impurity layer of the
first conductivity type can be suppressed.
In the present invention, more preferably, the position of the
first mark is displaced from the interface of the low concentration
impurity layer of the first conductivity type by a length which is
equal to the depth of impurity diffusion of the low concentration
impurity region of the second conductivity type from the main
surface of the low concentration impurity layer of the first
conductivity type.
Consequently, the depth of diffusion can be set to the minimum
value necessary for suppressing the electric field at the corner
portion of the low concentration impurity region of the second
conductivity type.
Consequently, the corner of the low concentration impurity region
of the second conductivity type comes to have higher breakdown
voltage, and hence the semiconductor device as a whole comes to
have higher breakdown voltage, while not preventing miniaturization
of the semiconductor device.
In the present invention, more preferably, the position of the
second mask is displaced from the position at which the value of
quadratic differential of the impurity concentration assumes a
positive maximum value in accordance with the log scale by a length
which is equal to the depth of impurity diffusion of the high
concentration impurity region of the second conductivity type from
the main surface of the low concentration impurity layer of the
first conductivity type.
Consequently, the depth of diffusion can be set to the minimum
value necessary for suppressing the electric field at the corner
portion of the high concentration impurity region of the second
conductivity type.
Consequently, the corner of the high concentration impurity region
of the second conductivity type comes to have higher breakdown
voltage and hence the semiconductor device as a whole comes to have
a higher breakdown voltage, while not preventing miniaturization of
the semiconductor device.
In the present invention, preferably, the step of forming the low
concentration impurity region of the second conductivity type and
the step of forming the high concentration impurity region of the
second conductivity type include the step of introducing impurities
such that the depth of impurity diffusion of the low concentration
impurity region of the second conductivity type from the main
surface of the low concentration impurity layer of the first
conductivity type is set to be at least three times the depth of
impurity diffusion of the high concentration impurity region of the
second conductivity type from the main surface of the low
concentration impurity layer of the first conductivity type.
Consequently, the depth of impurity diffusion of the low
concentration impurity region of the second conductivity type and
the depth of impurity diffusion of the high concentration impurity
region of the second conductivity type can be set to the minimum
values necessary for suppressing the electric field.
Consequently, breakdown voltage of the semiconductor device can be
increased efficiently, while not preventing miniaturization of the
device.
Still more preferably, in the present invention, the step of
forming the high concentration impurity region of the second
conductivity type includes the step of forming this region to have
a closed planar pattern including corners, each corner having an
arc of which radius is at least three times the depth of impurity
diffusion of the high concentration impurity region of the second
conductivity type from the main surface of the low concentration
impurity layer of the first conductivity type.
Therefore, the depth of diffusion can be set to the minimum value
necessary for suppressing the electric field at the corner of the
high concentration impurity region of the second conductivity
type.
Consequently, the corners of the high concentration impurity
regions of the second conductivity type comes to have high
breakdown voltage, and hence the semiconductor device as a whole
comes to have higher breakdown voltage, and, while not preventing
miniaturization of the semiconductor device.
Still more preferably, in the present invention, the step of
forming the low concentration impurity region of the second
conductivity type includes the steps of forming this region to have
a closed planar pattern including corners, each corner having an
arch of which radius is at least three times the depth of impurity
diffusion of the low concentration impurity region of the second
conductivity type from the main surface of the low concentration
impurity layer of the first conductivity type.
Consequently, the depth of diffusion can be set to the minimum
value necessary for suppressing the electric field at the corner
portion of the low concentration impurity region of the second
conductivity type.
Consequently, the corners of the low concentration impurity region
of the second conductivity type comes to have higher breakdown
voltage, and hence the semiconductor device as a whole comes to
have higher breakdown voltage, while not preventing miniaturization
of the device.
Still more preferably, in the present invention, the step of
forming the high concentration impurity region of the second
conductivity type and the step of forming the low concentration
impurity region of the second conductivity type include the steps
of forming these regions to have closed planar patterns including
corners such that the difference in length between the radii of the
arc at the corners of the high concentration impurity region of the
second conductivity type and the low concentration impurity region
of the second conductivity type is made longer than the difference
between the depth of impurity diffusion of the low concentration
impurity region of the second conductivity type from the main
surface of the low concentration impurity layer of the first
conductivity type and the depth of impurity diffusion of the high
concentration impurity region of the second conductivity type from
the main surface of the low concentration impurity layer of the
first conductivity type.
Accordingly, the electric fields at the corners of the high
concentration impurity region of the second conductivity type and
the low concentration impurity region of the second conductivity
type can be relaxed.
As a result, the corners of the low concentration impurity region
of the second conductivity type and the high concentration impurity
region of the second conductivity type come to have higher
breakdown voltages and hence the semiconductor device as a whole
comes to have higher breakdown voltage, not preventing
miniaturization of the semiconductor device.
The foregoing and other objects, features, aspects and advantages
of the present invention will become more apparent from the
following detailed description of the present invention when taken
in conjunction with the accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a cross section of a semiconductor device in accordance
with a first embodiment of the present invention.
FIG. 2 is a schematic view showing a depletion layer generated in
the semiconductor device.
FIGS. 3 to 10 are cross sections showing first to eighth steps of
manufacturing the semiconductor device.
FIG. 11 is a cross section showing a structure of a semiconductor
device in accordance with a second embodiment of the present
invention.
FIG. 12 is a partial cross section of the semiconductor device in
accordance with the second embodiment of the present invention.
FIG. 13 is a first graph showing the profile of the impurity
concentration.
FIG. 14 is a schematic plan view of the semiconductor device in
accordance with the second embodiment of the present invention.
FIG. 15 is a second graph showing the profile of the impurity
concentration.
FIG. 16 is a partial perspective view of the semiconductor device
in accordance with the second embodiment of the present
invention.
FIG. 17 is a first graph showing the state of electric field in the
semiconductor device in accordance with the second embodiment of
the present invention.
FIG. 18 is a second graph showing the state of the electric field
in the semiconductor device in accordance with the second
embodiment of the present invention.
FIG. 19 is a third graph showing the state of the electric field in
the semiconductor device in accordance with a third embodiment of
the present invention.
FIGS. 20 to 22 are first to third plan views showing other
acceptable shapes of the planar pattern of the buried impurity
region.
FIGS. 23 to 34 are cross sections showing first to twelfth steps of
manufacturing the semiconductor device in accordance with the
present invention.
FIG. 35 is a first graph showing the state of the electric field in
the semiconductor device in accordance with the third embodiment of
the present invention.
FIG. 36 is a graph showing the relation between the breakdown
voltage and the dosage in the n.sup.- buried impurity region of the
semiconductor device in accordance with third embodiment of the
present invention.
FIG. 37 is a cross section showing a structure of a conventional
semiconductor device.
FIG. 38 is a schematic view showing the state of the depletion
layer generated in the semiconductor device of the prior art.
FIG. 39 is a partial perspective view showing the structure of the
conventional semiconductor device.
FIG. 40 is a first graph showing the state of the electric field in
the conventional semiconductor device.
FIG. 41 is a second graph showing the state of the electric field
in the conventional semiconductor device.
FIG. 42 shows the problems of the conventional semiconductor
device.
FIG. 43 is a cross section taken along the line X--X of FIG.
42.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
A first embodiment of the semiconductor device in accordance with
the present invention and the method of manufacturing the same will
be described with reference to the figures.
First, referring to FIG. 1, an n.sup.- epitaxial layer 10 is formed
on a main surface of a p.sup.- semiconductor substrate 2. An
n.sup.+ buried impurity region 8 is formed at a prescribed region
of the main surface of the p.sup.- semiconductor substrate 2,
enclosed by p.sup.- semiconductor substrate 2 and n.sup.- epitaxial
layer 10.
Further, an n.sup.- buried impurity region 6 is provided in p.sup.-
semiconductor substrate 2 to cover lower portion of n.sup.+ buried
impurity region 8.
A CMOS transistor is formed at the surface of n.sup.- epitaxial
layer 10 above n.sup.+ buried impurity region 8. The CMOS
transistors includes a p channel MOS transistor 28 and an n channel
MOS transistor 38.
The p channel MOS transistor 28 includes a gate electrode 22 formed
on the surface of n.sup.- epitaxial layer 10 with a gate insulating
film 20 posed therebetween, and source/drain regions 24, 26 of p
type impurity regions formed sandwiching, from left and right, the
gate electrode 22.
The n channel MOS transistor 38 includes a gate electrode 32 formed
on the surface of n.sup.- epitaxial layer 10 with a gate insulating
film 30 posed therebetween, and source/drain regions 34, 36 of n
type impurity regions formed at positions sandwiching, from left
and right, the gate electrode 32 in a p.sup.- impurity region 12
formed in n.sup.- epitaxial layer 10.
At the surface of n.sup.- epitaxial layer 10, the CMOS transistor
is surrounded by an element isolating oxide film 18.
In n.sup.- epitaxial layer 10, an n.sup.+ collector wall 14 is
provided to surround the CMOS transistor, and a p type insulating
region 16 is formed to surround the collector wall 14.
FIG. 2 is a schematic view showing the state of generation of a
depletion layer in the semiconductor device shown in FIG. 1.
Referring to FIG. 2, assume that the potential at n.sup.+ buried
impurity region 8 becomes higher than that of p.sup.- semiconductor
substrate 2.
In this case, the depletion layer is formed from the interface
between p.sup.- semiconductor substrate 2 and n.sup.+ buried
impurity region 8 and from the pn junction between p.sup.-
semiconductor substrate 2 and n.sup.- epitaxial layer 10 over the
hatch regions.
As compared with the state of the prior art shown in FIG. 29, the
extent of the depletion layer can be suppressed, since there is
provided n.sup.- buried impurity region 6.
The method of manufacturing the semiconductor device shown in FIG.
1 will be described with reference to FIGS. 3 to 10.
FIGS. 3 to 10 are cross sections showing the steps of manufacturing
the semiconductor device shown in FIG. 1.
Referring to FIG. 3, on a surface of a p.sup.- semiconductor
substrate 2 having the substrate impurity concentration of about 30
to about 100 .OMEGA.cm, a thermal oxide film 4 is formed to the
thickness of about 5000 .ANG. to 10000 .ANG.. Thereafter, a
prescribed region of thermal oxide film 4 is patterned so that it
has the thickness in the range of about 500 .ANG. to about 1000
.ANG..
Then, referring to FIG. 4, phosphorus is introduced to the surface
of semiconductor substrate 2. Then, semiconductor substrate 2 is
heated to form n.sup.- buried impurity region 6. Thereafter, by
thermal oxidation, thermal oxide film 4 is made thicker.
Then, referring to FIG. 5, a prescribed region of thermal oxide
film 4 is etched and patterned. Thereafter, antimone is applied to
that region which is enclosed by n.sup.- buried impurity region 6,
heat treatment is effected to diffuse the antimone and thus n.sup.+
buried impurity region 8 is formed.
Thereafter, referring to FIG. 6, thermal oxide film 4 is removed,
and n.sup.- epitaxial layer 10 is formed by epitaxial growth on the
p.sup.- semiconductor substrate 2.
Thereafter, boron is introduced to a prescribed region at the
surface of n.sup.- epitaxial layer 10 and annealing is effected, so
as to form p.sup.- impurity region 12 for forming the n channel MOS
transistor.
Then, referring to FIG. 8, boron is introduced to surround the
prescribed region of n.sup.- epitaxial layer 10, and annealing is
effected so as to form a p type isolating region 16.
Thereafter, phosphorus is introduced to a prescribed region in
n.sup.- epitaxial layer 10 above n.sup.+ buried impurity region 8,
so as to form n.sup.+ collector wall 14.
Referring to FIG. 9, by selective oxidation, a field oxide film 18
is formed on the surface of n.sup.- epitaxial layer. Thereafter, on
the active regions isolated by the field oxide film 18, gate
electrodes 22 and 32 are formed with gate oxide films 20 and 30
interposed therebetween.
Thereafter, by using gate electrode 22 as a mask, boron is
introduced to the surface of n.sup.- epitaxial layer 10 and
annealing is effected, so as to form n type source/drain regions 24
and 26 of the n channel MOS transistor.
Then, referring to FIG. 10, by using gate electrode 32 as a mask,
phosphorus is introduced to the surface of n.sup.- epitaxial layer
10 and annealing is effected, so as to form p type source/drain
regions 34 and 36 of p channel MOS transistor.
Through the above described steps, the semiconductor device having
n.sup.- buried impurity region 6 as shown in FIG. 1 is
completed.
As described above, according to the first embodiment of the
present invention, since there is formed the n.sup.- buried
impurity region 6, the impurity concentration gradient at the pn
junction can be made moderate. Consequently, the concentration of
electric field in the semiconductor device can be relaxed, enabling
higher breakdown voltage.
A second embodiment of the semiconductor device in accordance with
the present invention and the method of manufacturing the same will
be described with reference to the figures.
First, referring to FIG. 11, the structure of the semiconductor
device in accordance with the present embodiment will be
described.
An n.sup.- epitaxial layer 10 is formed on the main surface of a
p.sup.- semiconductor substrate 2. At a prescribed region on the
main surface of p.sup.- semiconductor substrate 2, an n.sup.+
buried impurity region 8 is formed sandwiched by n.sup.- epitaxial
layer 10 and p.sup.- semiconductor substrate 2. Furthermore, an
n.sup.- buried impurity region 6 is provided in p.sup.-
semiconductor substrate 2 so as to cover n.sup.+ buried impurity
region 8.
At the surface of n.sup.- epitaxial layer 10 above n.sup.+ buried
impurity region 8, a CMOS transistor is formed.
The CMOS transistor includes a p channel MOS transistor 28 and an n
channel MOS transistor 38.
The p channel MOS transistor 28 includes a gate electrode 22 formed
on the surface of n.sup.- epitaxial layer 10 with a gate insulating
film 20 posed therebetween, and source/drain regions 24, 26 of p
type impurity regions formed at position sandwiching, from left and
right, the gate electrode 22.
The n channel MOS transistor 38 includes a gate electrode 32 formed
on the surface of n.sup.- epitaxial layer 10 with a gate insulating
film 30 posed therebetween, and source/drain regions 34, 36 of n
type impurity regions formed at positions sandwiching, from left
and right, the gate electrode 32 in a p.sup.- impurity region 12
formed in n.sup.- epitaxial layer 10.
At the surface of n.sup.- epitaxial layer 10, the CMOS transistor
is surrounded by an element isolating oxide film 18. In n.sup.-
epitaxial layer 10, an n.sup.+ collector wall 14 is formed to
surround the CMOS transistor, and a p type isolating region 16 is
formed to surround collector wall 14.
Referring to FIG. 12, the relation between n.sup.+ buried impurity
region 8 and n.sup.- buried impurity region 6 will be
described.
In the present embodiment, the depth of diffusion X.sub.j2 of
n.sup.- buried impurity region 8 and the depth of diffusion
X.sub.j1 of n.sup.- buried impurity region 8 are set to X.sub.j1
=5.mu. and X.sub.j2 =15-20.mu., so that X.sub.j2 is at least three
times the depth X.sub.j1.
The profile of the impurity concentration in the depth direction of
t.sup.- semiconductor substrate 2 of n.sup.+ buried impurity region
and n.sup.- buried impurity region 6 will be described.
Referring to FIG. 13, the depth of X.sub.j1 of n.sup.+ buried
impurity region 8 is the distance between a point (A) where the
concentration of n.sup.+ assumes the maximum value to a point at
which the quadratic differential of the impurity concentration
assumes a positive maximum value (which is plotted as a downward
convex), in accordance with the log scale.
More specifically, the depth X.sub.j1 corresponds to the value x
which provides the maximum value of ##EQU2##
As for the depth X.sub.j2 of n.sup.- impurity region, similarly to
X.sub.j1 it corresponds to the distance from a point (A) at which
the impurity assumes the maximum concentration to a point (the
position of the pn junction) at which the concentration assumes the
minimum value, in accordance with the log scale.
Referring to FIG. 13, the n.sup.- buried impurity region 8 has an
approximately rectangular planar pattern, and as for the radius of
each of the corners thereof, it is in the range of r.sub.2 =45 to
65.mu. so that it is at least three times the depth of diffusion
X.sub.j2 of n.sup.- buried impurity region 8.
Referring to FIG. 14, n.sup.+ impurity region 6 has approximately
rectangular planar pattern, and as for the radius of each of the
corners thereof, it is about r.sub.1 .apprxeq.15.mu., so that it is
at least three times the depth of diffusion X.sub.j1 of n.sup.+
buried impurity region 8.
The profile of the impurity concentration in the direction along
the surface of p.sup.- semiconductor substrate 2 of n.sup.+ buried
impurity region 8 and n.sup.- buried impurity region 6 will be
described.
Referring to FIG. 15, the length of diffusion (X.sub.j) in the
depth direction of p.sup.- semiconductor substrate 2 can be
considered equal to the length of diffusion in the direction along
the surface of p.sup.- semiconductor substrate 2 at the time of
diffusion of impurity for n.sup.+ buried impurity region 8 and
n.sup.- buried impurity region 6.
Therefore, the positions of the mask patterns for n.sup.+ buried
impurity region 8 and n.sup.- buried impurity region 6 can be
determined in the following manner.
First, the position of the mask pattern for forming n.sup.+ buried
impurity region 8 should be a position displaced by X.sub.j1 from
the position at which the value of quadratic differential of the
impurity concentration assumes a positive maximum value in
accordance with the log scale.
As for the position of the mask pattern for forming n.sup.- buried
impurity region 6, it should be positioned at a point displaced by
a X.sub.j2 from a position (the position of pn junction) at which
the impurity concentration assumes the minimum value, in accordance
with the log scale. More detailed description will be given with
reference to FIGS. 16 to 21.
FIG. 16 is a perspective view of n.sup.- buried impurity region 6
cut at the interface between p.sup.- semiconductor substrate 2 and
n.sup.- epitaxial layer 10. Here, n.sup.+ buried impurity region 8
is not shown. Here, it is assumed that impurity concentration is
sufficiently lowered in p.sup.- semiconductor substrate 2 in order
to provide higher breakdown voltage.
Referring to FIG. 17, the electric field in the direction (A-A' of
FIG. 16) perpendicular to the bottom surface of n.sup.- buried
impurity region 6 is constant in the region of p.sup.-
semiconductor substrate 2 as shown by the dotted line.
Meanwhile, the electric field and the direction of the electric
field at the corner (in the direction of B-B' in the figure) of
n.sup.- buried impurity region 6 changes in accordance with the
impurity concentration of n.sup.- buried impurity region 6, and
when the impurity concentration of n.sup.- buried impurity region 6
attains lower than a prescribed value, the peak of the electric
field moves to the interface between n.sup.+ buried impurity region
8 and n.sup.- buried impurity region 6.
In this embodiment, the peak of the electric field is generated at
the pn junction, because the impurity concentration of n.sup.-
buried impurity region 6 is relatively high, as shown by the solid
line in FIG. 16.
The electric field and the inclination of the electric field are
represented, in approximation, by the following equations (1) and
(2). ##EQU3##
Here, it is assumed that the electric field at the pn junction
interface at the corner portions of n.sup.- buried impurity region
6 and n.sup.+ buried impurity region is constant. Q represents the
total of space charges on the side of n.sup.- buried impurity
region 6 where electric line of force passing through the hatch
region of FIG. 16 terminates, l represents the corner radius of
n.sup.- buried impurity region 6, and r represents the depth of
diffusion of n.sup.- buried impurity region 6.
As can be seen from equations (1) and (2), at the corner portion,
the electric field changes and provides the peak of the electric
field at the pn junction, and by this concentration of the electric
field, the breakdown voltage of the semiconductor device as a whole
is determined.
The relation between the depth r of diffusion of n.sup.- buried
impurity region 6 and the electric field is shown in FIG. 18.
FIG. 18 shows the change of electric field E, assuming that the
value of the electric field E (X=r) is is 0, with the value r is
multiplied by .alpha., when the value .beta., which is l/r=.beta.
is 0, 1 and 3, respectively.
The relation shown in FIG. 18 can be represented by the following
equation (3), where l/r=.beta.. ##EQU4##
When l=0 (.beta.=0), the equation (3) is satisfied when .alpha. is
at least about 3. If l>0 (.beta.>0), the value of .alpha. can
be further reduced.
Therefore, the effect of introduction of n.sup.- buried impurity
region 6 can be surely obtained when r is set to at least three
times the depth of diffusion of n.sup.+ buried impurity region
8.
The change of .vertline.E' (X=.alpha.r).vertline. with respect to
.beta. is shown in FIG. 19. Referring to FIG. 19, a case where
.alpha.=1 and .beta.=0 (corresponds to the case when the corner of
the pattern has a right angle) is assumed to be 1 for
normalization, and the value of .alpha. is set to 1, 2 and 3,
respectively. It can be seen that the value E reduces significantly
as the value .beta. increases. In order to stabilize the effect of
lowering the value E when .beta. is increased to some extent from
0, the value .vertline.E' (X=.alpha.r).vertline. should be 1/10 at
the most, when .beta.=0.
The above condition can be represented by the equation (4) below.
##EQU5##
The above requirement can be satisfied if .beta. is .beta..gtoreq.3
when .alpha.=1.
When .alpha.>1, the value of .beta. can be further reduced.
Therefore, in order to meet the above requirement, .beta. should be
at least 3.
As described above, by setting the values r and l appropriately,
the breakdown voltage of the semiconductor device can be increased.
Further, by providing n.sup.- buried impurity region 6 only at
those portions which require higher breakdown voltage, the
structure does not prevent miniaturization of the semiconductor
device.
Though the n.sup.- buried impurity region 8 and n.sup.+ buried
impurity region 6 have approximately rectangular planar pattern
such as shown in FIG. 14, the planar pattern is not limited
thereto. The impurity regions may have an oval planar pattern as
shown in FIG. 20, a circular pattern as shown in FIG. 21 or any
other polygonal shapes provided that the relation between r1 and r2
at the corner of the polygon, as shown in FIG. 22, satisfy the
above-described relation.
The method of manufacturing the semiconductor device shown in FIG.
11 will be described with reference to FIGS. 23 to 34. FIGS. 23 to
34 are cross sections showing the steps of manufacturing the
semiconductor device shown in FIG. 11.
First, referring to FIG. 23, on a surface of p.sup.- semiconductor
substrate 2 having the substrate impurity concentration of about 30
to about 100 .OMEGA.cm, a thermal oxide film 4 is formed to the
thickness of about 5000 .ANG. to about 10000 .ANG.. Thereafter,
referring to FIG. 24, a prescribed region of thermal oxide film 4
is removed by etching. Then, referring to FIG. 25, on p.sup.-
semiconductor substrate 2, a thermal oxide film 4a having the
thickness of about 500 to about 1000 .ANG. is formed.
Referring to FIG. 26, phosphorus is introduced with the
implantation energy of about 120 kV and the dosage of
1.times.10.sup.12 to 1.times.10.sup.13 to the surface of
semiconductor substrate 2.
Thereafter, annealing is effected for about 30 hours at about
1260.degree. C. on p.sup.- semiconductor substrate 2, and thus an
n.sup.- buried impurity region 6 is formed.
Thereafter, referring to FIG. 27, on the surface of p.sup.-
semiconductor substrate 2, thermal oxide film 4b is formed by
thermal oxidation to the thickness of about 5000 .ANG. to about
10000 .ANG.. Then, referring to FIG. 28, a prescribed region of
thermal oxide film 4 is etched to expose the surface of p.sup.-
semiconductor substrate 2.
Thereafter, antimone is applied, or phosphorus, arsenic or the like
is implanted, to that region which is enclosed by n.sup.- buried
impurity region 6, annealing is carried out for about 3 hours at
about 1240.degree. C. so as to diffuse impurities and thus n.sup.+
buried impurity region 8 is formed.
Thereafter, thermal oxide film 4 is removed, and an n.sup.-
epitaxial layer 10 is formed on p.sup.- semiconductor substrate 2
by epitaxial growth. Consequently, the depth of diffusion X.sub.j1
of n.sup.+ buried impurity region 8 attains X.sub.j1 .apprxeq.5.mu.
and it is possible to set the depth of diffusion X.sub.j2 of
n.sup.- buried impurity region 6 to X.sub.j2 .apprxeq.15 to
20.mu..
Referring to FIG. 31, boron is introduced to a prescribed region at
the surface of n.sup.- epitaxial layer 10, annealing is carried
out, and thus p.sup.- impurity region 12 for forming the n channel
MOS transistor is formed.
Referring to FIG. 32, boron is introduced to surround a prescribed
region in n.sup.- epitaxial layer 10 and annealing is effected, so
as to form the p type isolating region 16.
Thereafter, phosphorus is introduced in a prescribed region of
n.sup.- epitaxial layer 10 above the n.sup.+ buried impurity region
and annealing is effected, and thus n.sup.+ collector wall 14 is
provided.
Then, referring to FIG. 33, a field oxide film 18 is formed at the
surface of n.sup.- epitaxial layer 10 by selective oxidation.
Thereafter, in the active region isolated by the field oxide film
18, gate electrodes 22 and 32 are formed with gate oxide films 20
and 30 posed therebetween.
Thereafter, by using gate electrode 22 as a mask, boron is
introduced to the surface of n.sup.- epitaxial layer 10 and
annealing is effected, so that p type source/drain regions 24, 26
of the n channel MOS transistor are formed.
Referring to FIG. 34, phosphorus is introduced to the surface of
n.sup.- epitaxial layer by using gate electrode 32 as a mask,
annealing is effected, and thus n type source/drain regions 34 and
36 of the p channel MOS transistor are formed.
Through the above described steps, the semiconductor device shown
in FIG. 11 is completed.
According to this second embodiment, the depth of diffusion of
n.sup.- buried impurity region is made three times the depth of
diffusion of n.sup.+ buried impurity region, and the radius at the
corner of n.sup.- buried impurity region is made at least three
times the radius of the corner of n.sup.+ buried impurity
region.
Consequently, minimum dimension necessary for suppressing the
electric field can be set, and thus breakdown voltage of the
semiconductor device can be increased while not preventing
miniaturization of the device.
A third embodiment of the present invention will be described in
the following. The structure of the third embodiment is the same as
the second embodiment in its structure. However, the impurity
concentration of n.sup.- buried impurity region 6 is relatively
low, and therefore the peak electric field is at the interface
between n.sup.+ buried impurity region 8 and n.sup.- buried
impurity region 6.
FIG. 35 is a graph corresponding to FIG. 17 of the embodiment
2.
As compared with FIG. 15, assuming that the spatial charges of
n.sup.- buried impurity region 6 is sufficiently smaller than Q of
the second embodiment, the electric field at B-B' and the
inclination of the electric field can be represented by the
equations (5) and (6). The values of r' and l' are the same as r
and l of Embodiment 2.
Since the equations representing the electric field and the
inclination of the electric field are the same as those of the
prior art, seemingly there is no advantage of higher breakdown
voltage. However, since spatial charges in the n.sup.- buried
impurity region 6 serve to suppress the peak of the electric field,
the same effect as in the second embodiment can be obtained.
Referring to FIGS. 36, the result of optimization of the structure
of the semiconductor device will be described.
FIG. 36 shows the difference in the relation between the breakdown
voltage and the value l when r.sub.1 '=5 .mu.m, l'=0 .mu.m and
r.sub.2 '=16 .mu.m with respect to the impurity concentration of
n.sup.- buried impurity region 6.
When the dosage of n.sup.- buried impurity region 6 is
6.times.10.sup.12 cm.sup.-2, the peak of the electric field is at
the pn junction between p.sup.- semiconductor substrate 1 and
n.sup.- buried impurity region 6 (corresponds to Embodiment 1), and
when it is 1.times.10.sup.13 cm.sup.-2, the peak is at the
interface between n.sup.+ buried impurity region 8 and n.sup.-
buried impurity region 6 (corresponds to Embodiment 2).
As can be seen from FIG. 36, when the value of l is set to
l.gtoreq.20 .mu.m, higher breakdown voltage than in the Embodiment
2 can be obtained in Embodiment 3.
This means that the pattern of n.sup.- buried impurity region 6
should be overlapped by at least 20 .mu.m on n.sup.+ buried
impurity region 8, and it can be understood that the breakdown
voltage of a semiconductor device can be increased by forming these
regions overlapped with each other.
Although the present invention has been described and illustrated
in detail, it is clearly understood that the same is by way of
illustration and example only and is not to be taken by way of
limitation, the spirit and scope of the present invention being
limited only by the terms of the appended claims.
* * * * *