U.S. patent number 3,876,208 [Application Number 05/399,333] was granted by the patent office on 1975-04-08 for gaming machine.
Invention is credited to Wolfgang Straszer, Russi Tschernev, Peter Uri, Gunter Wachtler.
United States Patent |
3,876,208 |
Wachtler , et al. |
April 8, 1975 |
Gaming machine
Abstract
An electronically controlled gaming machine having poker-like
rules of play, the machine comprises a matrix of card memory stages
in rows and columns, each memory stage having three conditions and
an output which is energised in one of the conditions. An indicator
device includes a plurality of indicators one connected to each
memory stage for illumination, when the output of the associated
memory stage is energised. A dealing unit provides five sequential
impulses to energise a random selection of five of the memory
stages to represent five cards being dealt. A card return unit
allows up to three of the memory stages so energised to be
de-energised and subsequently blocked from re-energisation and the
dealing unit can then be reoperated randomly to energise different
memory stages until five stages are energised. Control circuits
connected to the rows and columns of the memory stage matrix then
determine the score in accordance with poker-like rules.
Inventors: |
Wachtler; Gunter
(Rottach-Egern, DT), Straszer; Wolfgang (Munich,
DT), Uri; Peter (Munich, DT), Tschernev;
Russi (Neukeferioh, DT) |
Family
ID: |
5856770 |
Appl.
No.: |
05/399,333 |
Filed: |
September 20, 1973 |
Foreign Application Priority Data
|
|
|
|
|
Sep 20, 1972 [DT] |
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2245969 |
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Current U.S.
Class: |
463/13; 273/292;
463/26 |
Current CPC
Class: |
G07F
17/3293 (20130101); A63F 1/00 (20130101); G07F
17/32 (20130101); A63F 2001/008 (20130101) |
Current International
Class: |
G07F
17/32 (20060101); G06F 19/00 (20060101); A63F
1/00 (20060101); A63f 009/00 () |
Field of
Search: |
;273/1E,1R,1M,138A,139,142B,143R,143A,143B,143C,143D,143E |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
Primary Examiner: Shapiro; Paul E.
Attorney, Agent or Firm: Brisebois & Kruger
Claims
We claim:
1. An electronically controlled gaming machine adapted to play card
games with poker-like rules of play, comprising:
an indicating unit having a plurality of selectively operable
card-representing indicator devices, one for each card of a group
of possible cards;
a card memory having a plurality of memory stages one for each
indicator device, each card memory stage having an input thereto
and an output connected to the associated indicator device, and
being operable to assume one of three memory conditions, a
reception condition, a memory condition, and a blocking condition,
each said memory stage operating to produce an output signal when
in said memory condition and no output signal when in said
reception condition or said blocking condition, and switching to
said memory condition on the occurrence of a signal on said input
if it is in said reception condition but not if it is in said
blocking condition,
a dealing unit having a plurality of outputs each connected to the
inputs of a respective card memory stage, said dealing unit
comprising in combination;
a random signal generator,
means connecting said random signal generator to all said outputs
from said dealing unit,
means for cyclically enabling said outputs from said dealing unit
whereby an output signal on one of said output lines is produced if
a random signal occurs when said one of said output lines is
enabled, said output signal operating to switch the card memory
stage connected to said one of said output lines to its memory
condition if it is in its reception condition,
a counter circuit connected to the outputs of all said memory
stages and operable to produce an output pulse when a predetermined
number of memory stages have been switched to their memory
conditions, and
means interconnecting said counter and said random signal generator
to inhibit the generation of further random signals upon the
occurrence of said output signal from said counter indicating that
said predetermined number of memory stages have been switched to
their memory condition to represent the dealing of a predetermined
number of cards,
a card return unit having,
a plurality of operating members each connected to a respective
memory stage and operating, when actuated, to switch the associated
memory stage to its blocking condition from its memory condition,
and
a new deal operating member connected to said dealing unit and
operable to energise said dealing unit, when actuated, to randomly
switch further memory stages to their said memory conditions until
the said predetermined number of memory stages in the memory
condition is re-established,
a stake unit having a coin or token receiving mechanism and means
for producing an output signal when coins or tokens are held in
said stake unit,
inhibit means interconnecting the output of said stake unit and
said dealing unit, operating to inhibit said dealing unit unless
there is an output signal from said stake unit, and
result read-out means connected to said memory stages and operating
to indicate the score obtained in dependence on which of said
memory stages are in said memory condition.
2. The gaming machine of claim 1, wherein said dealing unit
includes a plurality of multiple input AND gates the outputs from
which constitute the outputs of said dealing unit and are connected
to the inputs of corresponding card memory stages, and wherein each
said card memory stage comprises first and second bistable circuits
each having set and reset inputs and set and reset outputs, the set
input of said first bistable circuit being connected to said
dealing unit and the set input of said second bistable circuit
being connected to a corresponding operating member of said card
return unit, said set output of said first bistable circuit being
connected to the corresponding indicating device, said reset
outputs of both said first and said second bistable circuits being
connected to respective inputs of the corresponding multiple input
AND gate, whereby said memory stage is in said reception condition
when both said bistable circuits are in their reset state, in said
memory condition when said first bistable circuit is in its set
state and said second bistable circuit is in its reset state, and
in its blocking condition when said first bistable circuit is in
its reset state and said second bistable circuit is in its set
state.
3. The gaming machine of claim 2, wherein said means for cyclically
enabling said outputs of said dealing unit comprise:
an oscillator producing a train of output pulses,
a counter having a serial input connected to the output from said
oscillator, said counter having a plurality of parallel binary
outputs on which appear, in binary form, signals representing the
number of pulses counted by said counter,
means interconnecting said parallel outputs of said counter and
some of the inputs of each of said multiple input AND gates the
remaining input of said multiple input AND gates being connected to
said random signal generator whereby, when said first and second
bistable circuits of the corresponding card memory stages are both
in a reset state said multiple input AND gates are enabled by said
counter when it has counted a corresponding number of pulses from
said oscillator circuit.
4. The gaming machine of claim 2, wherein said dealing means
additionally comprises a reversible counter having a forward input
and a reverse input, and an output connected to a first decoder
circuit having two outputs, one energised on a forward count of
five signals and the other energised on a forward count of two
signals,
means interconnecting the set output of the first bistable circuit
of each said memory stage of said card memory to said forward input
of said reversible counter, and
means interconnecting said one output of said first decoder circuit
with said inhibit means whereby said dealing unit is stopped after
five memory stages have been switched to their memory condition,
representing five cards dealt.
5. The gaming machine of claim 1 wherein said inhibit means
includes a third bistable circuit having set and reset inputs and
set and reset outputs, means connecting said set input to said one
output of said first decoding circuit, means connecting said reset
input to said other output from said decoding circuit, and
an AND gate having one input connected to said oscillator and an
output connected to said counter, another input of said AND gate
being connected to said reset output of said third bistable circuit
whereby said AND gate is enabled when said third bistable circuit
is in its reset state, and disabled when said third bistable
circuit is switched to its set state upon the occurrence of an
output signal on the said one output of said decoder circuit.
6. The gaming machine of claim 1 wherein said operating members of
said card return unit each comprise a single pole reversing switch
for each memory stage, resilient biasing means biasing each
reversing switch to one position, all said reversing switches being
connected in series in a line when in said one position, and
means applying a card return signal to the movable contact of the
reversing switch at one end of said line of switches for a
predetermined time after the dealing unit has stopped.
7. The gaming machine of claim 1 wherein the memory stages of said
card memory are arranged in a matrix of lines and columns, said
lines corresponding to the suits, and said columns corresponding to
the card values in sequential order, and wherein said result
read-out unit has a flush determining circuit comprising in
combination a column member determining circuit including eight
first OR gates each having four inputs, the inputs of each said
first OR gate being connected to the outputs of the memory stages
of a corresponding column,
an eight stage shift register having a serial input, a serial
output, and a parallel input to each stage, said parallel inputs
being connected to the output of a corresponding first OR gate
whereby a stage is switched to a binary 1 state by an output from
the corresponding first OR gate indicating that one of said memory
stages in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of
said shift register,
a counter connected to said serial output of said shift register,
and
a second decoder circuit connected to the output of said counter
circuit, said second decoder having first, second and third outputs
respectively energised with an output signal, when said counter has
counted the contents of said shift register, if said counter output
indicates 2,3 or 5 stages of said shift register in a binary 1
condition,
a sequence determining circuit comprising six first invertor
circuits, three of which are connected to the outputs of the three
first OR gates connected to the three columns at a first end of
said memory stage matrix and three of which are connected to the
three first OR gates connected to the three columns at a second end
of said memory stage matrix,
four first NAND gates each having three inputs, the outputs of said
first invertor circuits being connected in different groups of
three to said inputs of said first NAND gates whereby each NAND
gate produces an output signal if the corresponding columns of said
memory stage matrix having no memory stage in said memory condition
leave five remaining columns in which it is possible for memory
stages to be in said memory condition to form a sequence of five,
and no signal if the distribution of columns having no memory stage
in said memory condition is such that no sequence of five different
adjacent columns can have memory stages in said memory condition,
and
a first AND gate having five inputs, four of said inputs being
connected to the outputs of said first NAND gates and the fifth
being connected to said third output of said second decoder circuit
whereby said first AND gate produces an output signal when said
memory stages of said matrix in said memory condition all lie in
five different adjacent columns,
a line number determining circuit operating to produce an output
signal when all the memory stages of said matrix in said memory
condition are disposed in a single line, said circuit comprising
eight second OR gates each having eight inputs connected to the
outputs of respective memory stages in a corresponding line,
a threshold circuit having eight inputs connected to the outputs of
the eight second OR circuits and operating to produce an output
signal if there is a signal on two or more inputs thereof, and
a second invertor circuit connected to the output of said threshold
circuit, the output of said second invertor circuit producing an
output signal only when a signal is present on one input only of
said threshold circuit,
a third invertor circuit connected to the output of said first AND
gate,
a fourth invertor circuit connected to the output of said second
invertor circuit, and
a second AND gate having three inputs respectively connected to the
outputs of said second and third invertor circuits and said third
output of said second decoder circuit.
8. The gaming machine of claim 1 wherein the memory stages of said
card memory are arranged in a matrix of lines and columns, said
lines corresponding to the suits, and said columns corresponding to
the card values in sequential order, and wherein said result
read-out unit has a straight flush determining circuit comprising
in combination a column number determining circuit including eight
first OR gates each having four inputs, the inputs of each said
first OR gate being connected to the ouputs of the memory stages of
a corresponding cloumn,
an eight stage shift register having a serial input, a serial
output, and a parallel input to each stage, said parallel inputs
being connected to the output of a corresponding first OR gate
whereby a stage is switched to a binary 1 state by an output from
the corresponding first OR gate indicating that one of said memory
stages in the associated column is in a mamory condition,
means for providing a train of clock pulses to the serial input of
said shift register,
a counter connected to said serial output of said shift register,
and
a second decoder circuit connected to the output of said counter
circuit, said second decoder having first, second and third outputs
respectively energised with an output signal, when said counter has
counted the contents of said shift register, if said counter output
indicates 2, 3 or 5 stages of said shift register in a binary 1
condition,
a sequence determining circuit comprising six first invertor
circuits, three of which are connected to the ouputs of the three
first OR gates connected to the three columns at a first end of
said memory stage matrix and three of which are connected to the
three first OR gates connected to the three columns at a second end
of said memory stage matrix,
four first NAND gates each having three inputs, the outputs of said
first invertor circuits being connected in different groups of
three to said inputs of said first NAND gates whereby each NAND
gate produces an output signal if the corresponding columns of said
memory stage matrix having no memory stage in said memory condition
leave five remaining columns in which it is possible for memory
stages to be in said memory condition to form a sequence of five,
and no signal if the distribution of columns having no memory stage
in said memory condition is such that no sequence of five different
adjacent columns can have memory stages in said memory condition,
and
a first AND gate having five inputs, four of said inputs being
connected to the outputs of said first NAND gates and the fifth
being connected to said third ouput of said second decoder circuit
whereby said first AND gate produces an output signal when said
memory stages of said matrix in said memory condition all lie in
five different adjacent columns,
a fifth invertor circuit connected to the output of that one of
said first OR gates the inputs of which are connected to the column
of said matrix of memory stages representing aces, and
a third AND gate having three inputs respectively connected to said
third output of said second decoder circuit, said output of said
first ANd gate and the output of said fifth invertor circuit.
9. The gaming machine of claim 1 wherein the memory stages of said
card memory are arranged in a matrix of lines and columns, said
lines corresponding to the suits, and said columns corresponding to
the card values in sequential order, and wherein said result
read-out unit has a royal flush determining circuit comprising in
combination a column number determining circuit including eight
first OR gates each having four inputs, the inputs of each said
first OR gate being connected to the outputs of the memory stages
of a corresponding column,
an eight stage shift register having a serial input, a serial
output, and a parallel input to each stage, said parallel inputs
being connected to the output of a corresponding first OR gate
whereby a stage is switched to a binary 1 state by an output from
the corresponding first OR gate indicating that one of said memory
stages in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of
said shift register,
a counter connected to said serial output of said shift register,
and
a second decoder circuit connected to the output of said counter
circuit, said second decoder having first, second and third outputs
respectively energised with an output signal, when said counter has
counted the contents of said shift register, if said counter output
indicates 2, 3 or 5 stages of said shift register in a binary 1
condition,
a sequence determining circuit comprising six first invertor
circuits, three of which are connected to the outputs of the three
first OR gates connected to the three columns at a first end of
said memory stage matrix and three of which are connected to the
three first OR gates connected to the three columns at a second end
of said memory stage matrix,
four first NAND gates each having three inputs, the outputs of said
first invertor circuits being connected in different groups of
three to said inputs of said first NAND gates whereby each NAND
gate produces an output signal if the corresponding columns of said
memory stage matrix having no memory stage in said memory condition
leave five remaining columns in which it is possible for memory
stages to be in said memory condition to form a sequence of five,
and no signal if the distribution of columns having no memory stage
in said memory condition is such that no sequence of five different
adjacent columns can have memory stages in said memory condition,
and
a first AND gate having five inputs, four of said inputs being
connected to the outputs of said first NAND gates and the fifth
being connected to said third output of said second decoder circuit
whereby said first AND gate produces an output signal when said
memory stages of said matrix in said memory condition all lie in
five different adjacent columns, and
a fourth AND gate having three inputs respectively connected to
said third output of said second decoder circuit, said output of
said first AND gate and the output of that one of said first OR
gates the inputs of which are connected to the column of said
matrix of memory stages representing aces.
10. The gaming machine of claim 1 wherein the memory stages of said
card memory are arranged in a matrix of lines and columns, said
lines corresponding to the suits, and said columns corresponding to
the card values in sequential order, and wherein said result
read-out unit has a poker determining circuit comprising in
combination a column number determining circuit including eight
first OR gates each having four inputs, the inputs of each said
first OR gate being connected to the outputs of the memory stages
of a corresponding column,
an eight stage shift register having a serial input, a serial
output, and a parallel input to each stage, said parallel inputs
being connected to the output of a corresponding first OR gate
whereby a stage is switched to a binary 1 state by an output from
the corresponding first OR gate indicating that one of said memory
stges in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of
said shift register,
a counter connected to said serial output of said shift register,
and
a second decoder circuit connected to the output of said counter
circuit, said second decoder having first, second and third outputs
respectively, energised an a output signal, when said counter has
counted the contents of said shift register, if said counter output
indicates 2, 3 or 5 stages of said shift register in a binary 1
condition,
eight fifth AND gates each having four inputs connected to the
outputs of respective memory stages in corresponding columns of
said matrix whereby a fifth AND gate produces an output signal if
all said memory stages in the corresponding column are in said
memory condition, and
a third OR gate having eight inputs connected to the outputs of
said eight fifth AND gates, said third OR gate producing an output
signal when all the memory stages of any column of said matrix are
all in said memory condition,
a sixth AND gate having two inputs connected to the outputs of two
of the memory stages in the column of said memory matrix
representing aces,
a sixth invertor connected to the output of said sixth AND gate,
and
a seventh AND gate having two inputs respectively connected to the
outputs of said sixth invertor circuit and said second OR gate,
said seventh AND gate producing an output signal representing
poker.
11. The gaming machine of claim 1 wherein the memory stages of said
card memory are arranged in a matrix of lines and columns, said
lines corresponding to the suits, and said columns corresponding to
the card values in sequential order, and wherein said result
read-out unit has an ace poker determining circuit comprising in
combination a column number determining circuit including eight
first OR gates each having four inputs, the inputs of each said
first OR gate being connected to the outputs of the memory stages
of a corresponding column,
an eight stage shift register having a serial input, a serial
output, and a parallel input to each stage, said parallel inputs
being connected to the output of a corresponding first OR gate
whereby a stage is switched to a binary 1 state by an output from
the corresponding first OR gate indicating that one of said memory
stages in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of
said shift register,
a counter connected to said serial output of said shift register,
and
a second decoder circuit connected to the output of said counter
circuit, said second decoder having first, second and third outputs
respectively energised with an output signal, when said counter has
counted the contents of said shift register, if said counter output
indicates 2, 3 or 5 stages of said shift register in a binary 1
condition,
eight fifth AND gates each having four inputs connected to the
outputs of respective memory stages in corresponding columns of
said matrix whereby a fifth AND gate produces an output signal if
all said memory stages in the corresponding column are in said
memory condition, and
a third OR gate having eight inputs connected to the outputs of
said eight fifth AND gates, said third OR gate producing an output
signal when all the memory stages of any column of said matrix are
all in said memory condition,
a sixth AND gate having two inputs connected to the outputs of two
of the memory stages in the column representing aces, and
an eighth AND gate having two inputs connected respectively to the
output of said sixth AND gate and to the output of said second OR
gate and producing an output signal representing ace poker.
12. The gaming machine of claim 1 wherein the memory stages of said
card memory are arranged in a matrix of lines and columns, said
lines corresponding to the suits, and said columns corresponding to
the card values in sequential order, and wherein said result
read-out unit has a full house determining circuit comprising in
combination a column number determining circuit including eight
first OR gates each having four inputs, the inputs of each said
first OR gate being connected to the outputs of the memory stages
of a corresponding column,
an eight stage shift register having a serial input a serial
output, and a parallel input to each stage, said parallel inputs
being connected to the output of a corresponding first OR gate
whereby a stage is switched to a binary 1 state by an output from
the corresponding first OR gate indicating that one of said memory
stages in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of
said shift register,
a counter connected to said serial output of said shift register,
and
a second decoder circuit connected to the output of said counter
circuit, said second decoder having first second and third outputs
respectively energised with an output signal, when said counter has
counted the contents of said shift register, if said counter output
indicates 2, 3 or 5 stages of said shift register in a binary 1
condition,
eight fifth AND gates each having four inputs connected to the
outputs of respective memory stages in corresponding columns of
said matrix whereby a fifth AND gate produces an output signal if
all said memory stages in the corresponding column are in said
memory condition, and
a third OR gate having eight inputs connected to the outputs of
said eight fifth AND gates, said third OR gate producing an output
signal when all the memory stages of any column of said matrix are
all in said memory condition, a seventh invertor circuit connected
to the output of said third OR gate,
eight groups of three ninth AND gates each having three inputs, the
inputs of each group being connected to the memory stages of a
corresponding column whereby an output signal from one of said
ninth AND gates of a group is produced if any three of said memory
stages in said corresponding column are in said memory
condition,
a group of eight fourth OR gates connected to the outputs or
respective groups of said ninth AND gates,
a fifth OR gate connected to the outputs of said fourth OR gates,
and
a tenth AND gate having three inputs respectively connected to the
outputs of said seventh inverter circuit, the output of said fourth
OR gate and the first output of said decoder circuit, said tenth
AND gate producing an output signal representing full house.
13. The gaming machine of claim 1 wherein the memory stages of said
card memory are arranged in a matrix of lines and columns, said
lines corresponding to the suits, and said columns corresponding to
the card values in sequential order, and wherein said result
read-out unit has a three-of-a-kind determining circuit comprising
in combination a column number determining circuit including eight
first OR gates each having four inputs, the inputs of each said
first OR gate being connected to the outputs of the memory stages
of a corresponding column,
an eight stage shift register having a serial input, a serial
output, and a parallel input to each stage, said parallel inputs
being connected to the output of a corresponding first OR gate
whereby a stage is switched to a binary 1 state by an output from
the corresponding first OR gate indicating that one of said memory
stages in the associated column is in a memory condition,
means for providing a train of clock pulses to the serial input of
said shift register,
a counter connected to said serial output of said shift register,
and
a second decoder circuit connected to the output of said counter
circuit, said second decoder having first second and third outputs
respectively energised with an output signal, when said counter has
counted the contents of said shift register, if said counter output
indicates 2, 3 or 5 stages of said shift register in a binary 1
condition,
eight groups of three ninth AND gates each having three inputs, the
inputs of each group being connected to the memory stages of a
corresponding column whereby an output signal from one of said
ninth AND gates of a group is produced if any three of said memory
stages in said corresponding column are in said memory
condition,
a group of eight fourth OR gates connected to the outputs of
respective groups of said ninth AND gates,
a fifth OR gate connected to the outputs of said fourth OR gates,
and
an eleventh AND gate having two inputs respectively connected to
said second output of said second decoder circuit and the output of
said fifth OR gate.
14. The gaming machine of claim 1 wherein said stake unit
comprises,
a coin or token checking device having an output which is energised
upon insertion of a valid coin or token into said coin or token
checking device,
a coin or token payout device,
a credit meter having a reversible counter and an indicator showing
the count in the counter, said counter having a forward input
connected to the output of said coin or token checking device and a
backward input connected to said coin or token payout device and to
said card return unit,
a decoder circuit having an output which is energised when the
count in said counter is zero, and
a payout inhibit device connected to said output of said decoder
and operating to inhibit payout when the count in said counter is
zero.
Description
The present invention relates to a gaming machine with poker-like
rules of play, in accordance with which firstly five cards are
dealt, then there is the possibility of returning up to three cards
again and in return buying a corresponding number of new cards and
finally the score is determined in accordance with the final
distribution of the points and suits of the cards which has been
dealt.
One aim of the present invention is to provide a gaming machine
which so imitates the game of poker, the most-played card game of
the World, in a simplified form that each individual player can
play against chance, there is the greatest possible urge to play
further games and cheating is practically impossible,
According to the present invention an electronically controlled
gaming machine adapted to play card games with poker-like rules of
play, comprises an indicating unit having a plurality of
selectively operable card-representing indicator devices, one for
each card of a group of possible cards; a card memory having a
plurality of memory stages one for each indicator device, each card
memory stage having an input thereto and an output connected to the
associated indicator device, and being operable to assume one of
three memory conditions, a reception condition, a memory condition,
and a blocking condition, each said memory stage operating to
produce an output signal when in said memory condition and no
output signal when in said reception condition or said blocking
condition, and switching to said memory condition on the occurrence
of a signal on said input if it is in said reception condition but
not if it is in said blocking condition; a dealing unit having a
plurality of outputs each connected to the inputs of a respective
card memory stage, said dealing unit comprising in combination, a
random signal generator, means connecting said random signal
generator to all said outputs from said dealing unit, means for
cyclically enabling said outputs from said dealing unit whereby an
output signal on one of said output lines is produced if a random
signal occurs when said one of said output lines is enabled, said
output signal operating to switch the card memory stage connected
to said one of said output lines to its memory condition if it is
in its reception condition, a counter circuit connected to the
outputs of all said memory stages and operable to produce an output
pulse when a predetermined number of memory stages have been
switched to their memory conditions, and means interconnecting said
counter and said random signal generator to inhibit the generation
of further random signals upon the occurrence of said output signal
from said counter indicating that said predetermined number of
memory stages have been swtiched to their memory condition to
represent the dealing of a predetermined number of cards, a card
return unit having a plurality of operating members each connected
to a respective memory stage and operating, when actuated, to
switch the associated memory stage to its blocking condition from
its memory condition, and a new deal operating member connected to
said dealing unit and operable to energise said dealing unit, when
actuated, to randomly switch further memory stages to their said
memory conditions until the said predetermined number of memory
stages in the memory condition is re-established, a stake unit
having a coin or token receiving mechanism and means for producing
an output signal when coins or tokens are held in said stake unit,
inhibit means interconnecting the output of said stake unit and
said dealing unit, operating to inhibit said dealing unit, unless
there is an output from said stake unit, and result read-out means
connected to said memory stages and operating to indicate the score
obtained in dependence on which of said memory stages are in said
memory condition.
The stake unit comprises preferably a token input and checking
device, for example a coin checker, and a credit balance memory,
which stores the credit balance and indicates what credit balance
can be made up from the amount placed by the player in the form of
tokens in the gaming machine and also from the winnings.
The gaming machine can furthermore comprise a pay-out unit with an
operating element, which makes it possible for the player to have
paid out the credit balance present or a desired part of it.
The principle of the invention and further advantages, forms and
further developments of it are described in detail in what follows
with reference to an embodiment shown in the drawings.
FIG. 1 shows a block circuit diagram of a gaming machine in
accordance with the invention, comprising a card memory, an
indicating unit, a card return unit, a dealing unit, a result
read-out unit, a controlled unit, and a paying out unit.
FIG. 2 shows a somewhat simplified circuit of the card memory, the
indicating unit and the card return unit.
FIG. 3 is a block circuit diagram of dealing unit.
FIGS. 4a to 4f show circuit diagrams of parts of the result
read-out unit.
FIG. 5 shows a circuit of the control unit.
FIG. 6 shows a diagrammatic representation of the credit balance
unit and the paying out unit.
In the case of the following embodiments of the invention the
player pays his stake by inserting coins of money, which are
checked by a coin checker and which on receipt of the inserted
coins supplies corresponding count signals to a credit balance
memory. It is naturally possible to use other tokens, such as chips
or banknotes and the like. Instead of the coin checker use will
then be made of a suitable token input and checking device, which
can be constructed in a conventional manner.
The gaming machine shown in block form in FIG. 1 comprises a stake
unit 11 with a coin checker 13 and a credit balance register 14,
and furthermore a card memory 15 with a card indicating device 17,
and also a dealing unit 19, a card return unit 21, a result
read-out unit 23, a control unit 25, which controls the course of
the game in as far as it is not to be influenced by the player
himself, and a paying out unit 27, which comprises a coin store 29
and a coin delivery device 31. The coin store 29 preferably accepts
the coins accepted by the coin checker 13.
The indicating unit 17 comprises fields 18, which can be
illuminated, for the 32 cards of a skat game. The card memory 15
correspondingly comprises 32 memory stages and the card return unit
21 comprises 32 card return buttons or switches.
Before giving a detailed description of the construction of the
various units of the gaming machine only shown diagrammatically in
FIG. 1, the rules of play and the general manner of operation of
this gaming machine are to be explained.
Before commencing play all circuit units of the gaming machine are
set in their resting conditions with the exception of the card
memory. The card memory still stores the results of the preceding
game and correspondingly the indicator unit 17 indicates the cards
drawn in the preceding game. In the case of an objection by a
player this makes possible a check of the result of play by the
supervisiing staff.
For playing a game it is necessary for the credit balance memory 14
to have a sufficient credit balance. In the case of the embodiment
described for the initial dealing of five cards one coin unit (for
example 1 DM) is required and a further coin unit is required for
each newly bought card after card return. The necessary credit
balance in the credit balance memory 14 can be built up by
inserting coins 35 into the stake unit 11 or can be drawn from an
earlier win.
The commencement of play takes place by actuating a start button
37, which is coupled with the control unit 25. The actuation of the
start button 37 ensures that all stages of the card memory 15 are
returned to the resting condition and correspondingly all fields 18
of the indicating device are dark, that is to say switched off.
After a certain delay (for example 0.5 seconds) the control unit
then gives a dealing command to the dealing unit 19, which in a
purely statistical manner sets five memory stages of the card
memory 15 in sequence. The cards dealt in this manner in a
completely random fashion are indicated by illuminated fields 18 of
the indicating device 17. The dealing unit will be explained in
more detail presently. Within a certain period (in this case for
example 20 seconds), which is determined by the control unit 25,
the player has the possibility, after issue of the first five
cards, of returning up to three of the cards dealt by actuation of
corresponding return buttons in the card return unit 21. By
operation of the card return button the memory stage associated
with the return card is switched over from the first memory
condition into the second one and the associated field 18 in the
indicating device 17 becomes dark.
After actuation of a new dealing button 39 (on the assumption that
the credit balance in the balance memory 14 is sufficient) the same
number of new cards are dealt as have been returned. The card
memory is so constructed that the return cards cannot be dealt a
second time. Therefore, in any event the player receives cards
different to those which he has surrendered.
If the player does not require to return any cards, he actuates the
new deal button 39 without having previously actuated a card return
button.
When following the actuation of the card return button in the card
memory 15 five memory stages are in the first memory condition, the
result read-out unit 23 is caused to check the memory stages which
are in the first memory condition, that is to say the dealt cards,
to see whether a score has been obtained or not.
In the case of the present embodiment of the invention the
following card combinations win. They are given in the order of
increasing win quotas:
1 Three of a kind (three cards of the same value, that is to say
for example three kings).
2 Full House (respectively three and two cards of the same value,
for example three queens and two nines).
3 Flush (five cards of the same suit, which however do not form a
sequence).
4 Ordinary poker (four cards of the same value, for example four
queens, but not however four aces).
5 Ace poker (four aces).
6 Straight Flush (five sequentially following card values of the
same suit, for example seven of hearts to jack of hearts) without
an ace.
7 Royal Flush (five card values in sequence of the same suit
including the ace).
The means for carrying out the above-mentioned functions and the
course of play described are explained in what follows with
reference to FIGS. 2 to 6.
In the case of the following description of the manner of operation
of the present gaming machine with reference to a typical game it
is to be assumed that the credit balance memory 14 is empty, that
the coin store 29 contains a certain amount of coins, and that in
the card memory the five cards drawn in the preceding game are
stored. The indicating unit 17 therefore shows the views of these
five cards by means of the corresponding illuminated fields 18, and
preferably also any score or winning obtained.
At the beginning of the game the player should preferably insert
several coins 35 into the coin checker 13. The coin checker can be
of a conventional construction (see for example the German Pat. No.
2,029,751) and on accepting a coin passes an electrical pulse to
the coin gate which is normally comprised in a coin checker so that
the accepted coin passes through a receiving channel 41 (FIG. 6)
into the coin store 29, which can consist for example of a
vertically placed tube. The pulse produced on acceptance is also
supplied to a forward count input VZ of a reversible counter 43
contained in the credit balance memory 14 and the counter 43 is
provided with an indicating device 45, which indicates the credit
balance. The credit balance unit 14 furthermore comprises a decoder
connected with the counter 43 which supplies an output signal at an
output line 49 when the counter 43 is at zero. The line 49 leads to
an inverter 51, at whose output, therefore, a credit balance signal
GU is produced when the counter 43 stores a credit balance
different from zero.
After the insertion of one or more coins the player then actuates
the starting button 37 (FIG. 5) which cuases a monostable
multivibrator (referred to below as "monoflop") 53 which on
actuation supplies a pulse of predetermined length at one of two
inputs of an AND-gate 55. At the second input of the AND-gate the
credit balance signal GU is present and, since it was assumed that
the credit balance differed from zero, the pulse from the monoflop
53 can pass through the AND-gate 55. The output pulse of the
AND-gate serves as a resetting pulse RS, which resets the card
memory and the score determining circuit with the associated
indicating means at zero. The output pulse RS furthermore passes
through a delay member 57 and an OR-gate 59 and then passes to the
setting input of the flip-flop 61, which is accordingly set. When
the flip-flop 61 has been set, there appears at its 1-output a
dealing command signal AB, which is supplied to an AND-gate 63
(FIG. 3) in the dealing unit 19. The AND-gate 63 has two further
inputs, of which one receives clock pulses (with the frequency of
for example 10 kHz) from an oscillator 65, while at the third input
a dealing termination signal is present, which vanishes when five
cards have been "dealt." The production of the dealing termination
signal will be described presently in conjunction with FIG. 2.
At the point in time in consideration all three input signals are
present at the AND-gate 63 so that the clock pulses are allowed to
pass through and can pass on the one hand to a random signal
generator 69 and on the other hand to a five stage counter 67.
The five stages of the counter each have a respective 1-output and
a 0-output. At the 1-output the signal L (binary number 1) occurs
when the stage is set, while when the stage is reset an "L" occurs
at the 0-output".
The random signal generator 69 consists of a conventional circuit
arrangement, for example a shift register provided with feed-back
loops, which supplies a quasi-statistical binary sign sequence with
a very large cycle duration (see for example Gernam Pat. Nos.
1,188,123, 1,054,491 and 1,095,876). The quasi-statistical sign
sequence produced by the random signal generator 69 is supplied to
frequency divider 71, which reduces the frequency of the
quasi-statistical pulse sequence to such a degree that the
"dealing" of the cards can be carried out with a sufficiently low
speed in order to be observed. The quasi-statistical pulse sequence
divided as to frequency is shaped in a pulse-shaping and delay
circuit 73 and brought into such a phase position with respect to
the clock pulses TP fed to the counter 67 that the respective
quasi-statistical pulses only occur after the counter 67 has
terminated the switching over operation which was initiated by the
corresponding clock pulse TP. The quasi-statistical pulses
(referred to in what follows as random pulses) Z are supplied from
the output of the pulse-shaping and delay circuit 73 to a
respective input of 32 AND-gates, which are arranged so as to
correspond to a respective stage of the card memory (FIG. 2). FIGS.
2 and 3 show only one such respective AND-gate 75, which is
associated with the memory stage for the card T7 (seven of clubs).
THe AND-gates each have 8 inputs, of which five are connected with
corresponding outputs of the stages of the counter 67, as is
indicated in the table contained in FIG. 3. The relevant five
inputs of the AND-gate 75 of a first memory stage (that is to say
in this case the memory stage T7) are connected therefore with the
1-output of the counter-stage 1 and with the 0-outputs of the
counter-stages 2 to 5. At the relevant five inputs of the AND-gate
75 signals only of the value L are present when the counter 67 is
at (decimal) 1. On switching on the counter 67 further by the clock
pulses CP therefore the five inputs of the 32 AND-gates 75 are
switched first into the enabled condition.
The remaining inputs of the AND-gate 75 are connected with the
0-outputs of two flip-flops FF1a and FF1b (FIG. 2) which together
form the memory stage T7. The card memory 15 comprises 32 memory
stages, which are arranged in four lines and eight columns, as
shown in the following table and which respectively comprise two
flip-flops corresponding to the flip-flops FF1a and FF1b.
Table 1 ______________________________________ Column 7 2 3 4 5 6 7
8 ______________________________________ Line 1 T7 T8 T9 T10 TB TD
TK TA 2 P7 P8 PA 3 C7 CA 4 K7 KA
______________________________________ The following examples shown
the designations which apply for the table: T7 = seven of clubs TB
= jack of clubs TA = ace of clubs P7 = seven of spades C7 = seven
of hearts K7 = seven of diamonds
______________________________________
It is therefore a question of abbreviations of the designations of
a pack of 32 cards.
Since the 32 memory stages of the card memory 15 are identical in
construction, it is sufficient to explain the memory stage T7.
The setting input S of the flip-flop FF1a is connected with the
output of the associated AND-gate 75. The flip-flop FF1a is thus
set if
1 the counter 67 is at the number coordinated with the relevant
memory stage,
2 a random pulse Z occurs, and
3 both flip-flops of the respective memory stage are reset.
Owing to the setting of the flip-flop 1a the signal L occurs at its
1-output, while the signal at the 0-output becomes zero and the
AND-member 75 is in the blocking condition. The signal from the
1-output of the flip-flop FF1a firstly switches an indicating
device 79, for example an incandescent lamp of the corresponding
field 18 of the indicatinig unit 17, which then indicates that the
card in question has been dealt. Furthermore, the signal passes
from the 1-output of the flip-flop 1a to one of 32 inputs of an
OR-gate 81, whose output is connected with the forward counting
input VZ of a reversible counter 83. The counter 83 can count to 5
and then always switches on one step it counts, one each time one
of the first flip-flops of a memory stage is set (that is to say
one of the flip-flops corresponding to the flip-flop FF1a).
In the above-mentioned manner in sequence five random cards are
"dealt" from the store or magazine of 32 cards in a statistical
sequence in accordance with the random pulses Z one after the
other. When the five cards have been dealt, that is to say when the
first flip-flops of five memory stages have been set, the counter
83 is at 5. The counter 83 is connected with a decoder 85, which in
the case of the counter condition 5 provides a signal 5k ("five
cards"), which passes via an OR-gate 87 to the set input of the
flip-flop 77 and sets the latter. When the flip-flop 77 has been
set, the signal AS vanishes and the card dealing is terminated by
blocking of the AND-gate 63.
The signal AS can control an indicating means in a manner which is
not shown. The indicating means informs the player that he can
return three of the dealt five cards and buy new cards in exchange.
For this he is allowed a certain period of time, which in the case
of the present example amounts to 20 seconds. If within 20 seconds
the player does not return any card, the reading out of the result
is started, as will be described presently.
In the present case it is, however, assumed for the present time
that the player desires to return cards. The return of cards
assumes that at least a credit balance of one coin unit is
contained or stored in the credit balance memory.
Card return is carried out by actuating card return buttons 91 in
the card return unit 21 (bottom of FIG. 2). The card return buttons
91 respectively drive or control a single-pole reversing switch 93,
which are so connected in series in the manner shown in FIG. 2 that
a simultaneous return of two cards is impossible. By actuation of
the return card switch 93 associated with the card which is to be
returned (for example T7) the settng operation S of the second
flip-flop of the relevant memory stage, that is to say of the
flip-flop 1b of the memory stage T7, a card return signal KRS is
supplied, which sets the relevant second flip-flop. If therefore
the reversing switch 93 associated with the memory stage T7, is
actuated, the flip-flop 1b is set and at its 1-output a signal
ocurs, which via an OR-gate 95 passes to the resetting input R of
the first flip-flop FF1a of the corresponding stage and resets this
flip-flop. Accordingly the indicating device 79 in the indicating
unit becomes dark. Owing to the setting of the flip-flop FF1b the
signal L now vanishes at its 0-output and the associated AND-gate
75 can therefore still not allow the passage of any pulse for
setting the first flip-flop FF1a, if the relevant memory stage is
selected by the counter 67 and simultaneously a random pulse Z is
produced during the new deal stage of operation which follows.
The lines (for example line 97) leading from the reversing switches
93 to the setting inputs S of the second flip-flops of the memory
stages are connected with the inputs of an OR-gate 99, which for
each returned card supplies an output pulse. This putput pulse is
supplied after shaping by a pulse shaping circuit 101 to the
reverse count input of the counter 83 as a reverse count signal
RZS. The counter 83 therefore makes one backward count for each
returned card amounting to one step. The return of more than three
cards is prevented by the fact that the decoder 85 supplies a
signal 2K ("two cards") in the case of the count 2 and this signal
switches off the card return signal KRS from the card return unit
21. The signal KRS is produced by the circuit shown in FIG. 5.
After card return the player actuates the new deal button 39 (FIG.
5), which sets a flip-flop 103. The signal occurring at the
1-output of the flip-flop when the latter is set is differentiated
in a differentiating circuit 105 and supplied via the OR-gate 59 to
the setting input of the flip-flop 61, which has previously been
reset by the signal 5K. Owing to the setting of the flip-flop 61
the dealing command signal AB again occurs and since furthermore
the flip-flop 77 is again in the reset state (due to the 2K signal
from decoder 85), the clock pulses TP from the oscillator 65 are
allowed to pass by the AND-gate 63 and the above-described dealing
operation begins again. When again the number of cards dealt equals
the number which has been returned, that is to say when in all five
cards have been dealt, the flip-flop 77 is set by the signal 5K
again and the dealing operation is again terminated.
The determination of the score by means of the score determining
circuit shown in FIGS. 4a to 4f can now begin.
The determination of the score is carried out on the basis of the
criteria given in the following table:
Three Number of the Poker Number of Sequ- kind in in 1 ace 2 of
columns ence column column aces lines + +
__________________________________________________________________________
Three of the kind 3 no yes no -- -- -- Full House 2 no yes no -- --
-- Flush 5 no no no -- -- 1 Poker 2 no yes yes -- no -- Ace Poker 2
no yes yes -- yes -- Straight Flush 5 yes no no no -- 1 Royal Flush
5 yes no no yes -- 1
__________________________________________________________________________
For determining the number of lines and the presence of a sequence
(five sequentially following values) use is made of the circuit
arrangement shown in FIG. 4a. It comprises an AND-gate 105 at whose
output the signal NAS from the 1-output of the flip-flop 103 the
signal 5K of the decoder 85 and the clock pulses TP of the
oscillator 65 are present. The clock pulses are therefore only
allowed to pass when the flip-flop 103 is set and five cards have
been dealt.
The clock pulses allowed to pass by the AND-gate 105 are passed to
the setting input of a flip-flop 107, which is set by the first
clock pulse allowed to pass. The leading edge of the pulse
occurring at its 1-output triggers a monostable multivibrator 108
or monoflop, which supplies a memory signal to all eight stages of
an eight-stage shift register 109. The inputs of the eight stages
of the shift register 109 are respectively connected with the
output of an OR-gate 111a to 111h. The inputs of each OR-gate are
coupled with the 1-outputs of the first flip-flops of the memory
stages of a column (see table 1). The input, denoted T7, of the
OR-gate 111a is thus connected with the 1-output of the flip-flop
FF1a (FIG. 2). At the output of the OR-gate 111a a column signal
SP1 therefore occurs when a card which has been dealt is found in
the first column (see table 1), that is to say when a seven has
been dealt. The same applies for the other OR-gates, that is to say
the column signal SP8 thus occurs when an ace has been dealt.
The column signals SP1 to SP8 are stored by the memory signal
produced by the monoflop 108, in parallel in the eight stages of
the shift register 109.
The clock pulses from the output of the AND-gate 105 are
furthermore supplied via a delay member 113 to shift inputs of the
eight stages of the shift register 109. The delay member is so
dimensioned that the first clock pulse only occurs at the shift
inputs when the storing operation of the column signals SP1 to SP8
is terminated. The clock pulses then shift the content of the shift
register into a counter 115, which can count to 5 and is provided
with a decoder 117, which has three outputs, at which a respective
signal 2S, 3S and 5S occurs when the cards dealt are in two, three
and five columns respectively.
The column signals SP1, SP2, SP3, SP6, SP7 and SP8 are futhermore
inverted by an inverter 119 and supplied in groups of three to the
four NAND-gates 121 to 124 shown in FIG. 4a and these gates then
only all supply an output signal L to an AND-gate 125, if the
unoccupied columns are so distributed that a sequence is possible.
The AND-gate 125 has furthermore the signal 5S supplied to it as a
fifth input signal; it therefore only supplies a sequence signal SQ
when a sequence (independent of the suit of the cards), is
present.
The circuit arrangement shown in FIG. 4b serves for determining
poker, that is to say four cards of the same value (corresponding
to a full column). The output signals of the first flip-flop of the
memory stages are supplied respectively in accordance with the
columns to eight AND-gates 127a to 127h. The AND-gate 127a
therefore only supplies a signal VS1 (column 1 full), when all four
sevens have been dealt. The outputs of the AND-gates 127a to 127h
are connected with corresponding outputs of an OR-gate 129, at
whose output a poker signal PS only occurs when a full column is
present.
The circuit shown in FIG. 4C consists of an AND-gate 131 and
supplies a signal 2A (two aces signal) when the ace of clubs and
the ace of spades have been dealt. The inputs of the AND-gate 131
could be connected with any two ace memory stages, since the
circuit in accordance with FIG. 4c only serves for determining the
ace poker.
The circuit in accordance with FIG. 4d serves for determining
whether the cards dealt are distributed in one or more lines. This
circuit supplies a signal 1 ZS (1 line) only when all cards dealt
are to be found in a single line. The circuit in accordance with
FIG. 4d comprises for each line of the memory stage matrix (see
table 1) an OR-gate with eight inputs, of which only the upper gate
133 for the first line is shown. The inputs of the OR-gate 133 have
the signals of the 1-output of the first flip-flop of all memory
stages of the first line supplied to them. A line signal Z1 is
always supplied when the first line (clubs) comprises a dealt card.
For the other OR-gates which are not shown much the same
applies.
The line signals Z1 to Z4 are supplied to corresponding inputs of a
threshold gate 135, which supplies an output signal when two or
more line signals are present at its outputs. The output signal of
the threshold gate 135 is inverted by an inverter 137. At the
output of the inverter 137 a signal of the value L is therefore
only present when all drawn cards are located in a single line.
The circuit in accordance with FIG. 4e serves for determining
whether three of a kind have been dealt. In this case the four
signals of each column in groups of three are supplied to three
respective AND-gates 139, 140, 141, as is shown in FIG. 4e. The
outputs of the AND-members 139 to 141 are connected with the inputs
of an OR-gate 143, which always supplies a signal D1 (three of a
kind in column 1) when the first column comprises a three of a
kind, that is to say when three sevens have been drawn.
For each of the eight columns a circuit in accordance with the
AND-gates 139 to 141 and the OR-gate 143 is provided. These
circuits are, however, only hinted at in FIG. 4e. There are
therefore in all eight OR-gates which are connected in accordance
with the OR-gate 143 and these OR-gates supply signals D1 to D8.
The signals D1 to D8 are supplied to the eight inputs of an OR-gate
145, at whose output a three of a kind signal DR occurs when a
three of a kind hand is to be found in any column.
The evaluation of the score criteria signals produced in the
above-described manner is carried out by means of the circuit shown
in FIG. 4f, which consists of inverters and AND-gates. The
construction and the manner of operation of these circuits is
obvious, and they supply the following score signals:
Gdr = three of a Kind winning score
Gfh = full House winning score
Gfl = flush winning score
Gph = poker winning score (single)
Gap = ace poker winning score
Gsf = straight Flush winning score
Grf = royal Flush winning score
The winning scores can be indicated.
Preferably, however, besides or instead of the indication there is
a winning score payment or winning score credit in the credit
balance memory 14. For this purpose the score signals can be
respectively supplied for example to a coder 147 (FIG. 6), which
comprises a counter 149 with respect to a number corresponding to
the win quota. The count of the counter is then transferred into
the counter 43 of the credit balance unit 14, as is indicated by
the connection x--x. In the case of very large winning scores there
is preferably no payment or crediting but instead an optical or
acoustic indication is provided by means of an alarm device 151
(FIG. 4f ), since very large sums are difficult to pay out using
coin.
In the case of the present gaming machine the player can cause his
credit balance registered in the counter 43 to be paid out
completely or partly at any time. For this purpose he actuates a
paying out button 153, by means of which a circuit 155 is closed
and a voltage U is supplied to an input of the AND-gate 157. At the
other input of the AND-gate the credit balance signal GU is
present. When a credit balance is present, the voltage U passes to
a paying out device 159, which for example can comprise a
reciprocating slight 161, which ejects the coins 35 stored in the
coin stored 29 one after the other into a delivery pan. The ejected
coins are detected by a photoelectric light beam device 165 and
pulses produced as a result pass through a pulse shaping circuit
167 and an OR-gate 169 to the reverse count input of the counter
43. Therefore for each coin delivered the counter 43 is set back by
one step. When the count reaches zero, the credit balance signal GU
vanishes and the AND-gate 157 blocks and further delivery of coins
is thus prevented.
The delayed signal from the output of the delay member 113 is
supplied to a further delay member 170, which delivers a end of
game reset signal RSS for the resetting circuit units of the gaming
machine (with the exception of the card memory and the score
indication means, which on resetting of the counter 115 is put out
by the signal RS). The duration of the delay is so selected that
the above-described determination of the winning score is
terminated before the signal RSS occurs.
If the player does not return any cards, the win or score is
determined after the expiry of 20 seconds, after the card return
signal KRS (FIG. 5) has disappeared. The signal KRS is then
supplied for this purpose via an inverter 172 and an OR-gate 174 to
the AND-gate 105 and starts the same operation as after card return
by the NAS-signal (which is supplied via the second input of the
OR-gate 175 to the AND-gate 105).
* * * * *