U.S. patent number 3,849,773 [Application Number 05/340,103] was granted by the patent office on 1974-11-19 for apparatus for displaying characters and/or limited graphs.
This patent grant is currently assigned to Matsushita Electric Industrial Co. Ltd.. Invention is credited to Hiroshi Izumi, Toshiaki Katahira, Masao Tokonami.
United States Patent |
3,849,773 |
Katahira , et al. |
November 19, 1974 |
APPARATUS FOR DISPLAYING CHARACTERS AND/OR LIMITED GRAPHS
Abstract
Character codes of plural lines from an input-output circuit are
entered into a refresh memory circulating at a clock frequency. One
of these lines of character codes is then transferred to a shift
register during a time period necessary for scanning a space
between two adjacent lines. The shift register circulates at a rate
higher by an integer number times the clock frequency and is equal
to a horizontal scanning time of a standard television system. The
integer number corresponds to the number of scanning lines existing
in the space. A pattern generator is driven by the output signals
of the shift register to convert such signals into video signals
which produce one line of a character pattern on the cathode ray
tube of the standard television system.
Inventors: |
Katahira; Toshiaki (Osaka,
JA), Izumi; Hiroshi (Osaka, JA), Tokonami;
Masao (Osaka, JA) |
Assignee: |
Matsushita Electric Industrial Co.
Ltd. (Kadoma, Osaka, JA)
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Family
ID: |
27456043 |
Appl.
No.: |
05/340,103 |
Filed: |
March 12, 1973 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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112201 |
Jan 22, 1971 |
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Foreign Application Priority Data
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Feb 16, 1970 [JA] |
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45-13638 |
Feb 27, 1970 [JA] |
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45-17299 |
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Current U.S.
Class: |
345/23 |
Current CPC
Class: |
G09G
5/24 (20130101); G09G 5/222 (20130101) |
Current International
Class: |
G09G
5/22 (20060101); G09G 5/24 (20060101); G06f
003/14 () |
Field of
Search: |
;340/324AD,324A,168SR |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Caldwell; John W.
Assistant Examiner: Curtis; Marshall M.
Attorney, Agent or Firm: Wenderoth, Lind & Ponack
Parent Case Text
This application is a Division of parent application Ser. No.
112,201 filed Jan. 22, 1971, now abandoned.
Claims
What is claimed is:
1. An apparatus for displaying characters and limited graphs on a
cathode ray tube of a standard television system, each character
being displayed at a character area on said cathode ray tube, which
character area is divided into (S-1) blocks for picture element
display, the apparatus comprising:
an input-output circuit;
a refresh memory circulating at a clock frequency;
a character generator;
a picture element generator;
means coupled to said input-output circuit and said refresh memory
for entering character codes of plural lines from said input-output
circuit into said refresh memory, each character code being formed
by S bits, one of which is a discrimination bit for discriminating
whether to drive said character generator or to drive said picture
element generator and the others of which correspond to said (S-1)
blocks of each character area;
a shift register operatively coupled to said character generator
and said picture element generator; and
means coupled to said shift register and said refresh memory for
transferring said character codes to said shift register from said
refresh memory, said character generator being driven in accordance
with the value of said discrimination bit of the output signals
produced by said shift register for converting said output signals
into video signals which produce character patterns on said cathode
ray tube, said picture element generator being driven in accordance
with the value of said discrimination bit of the output signals
produced at said shift register for converting said output signals
produced at said shift register into video signals which produce
picture element patterns on said cathode ray tube, whereby when it
is determined in accordance with the discrimination bit in each of
some predetermined character codes to drive said picture element
generator, said picture element generator is driven by the output
signals produced at said shift register and generates picture
elements in some blocks of predetermined character areas in
accordance with the value of each of said (S-1) bits of said some
predetermined character codes so as to enable a display of a
limited graph on said cathode ray tube, so that characters and
limited graphs in a predetermined pattern can be displayed on said
cathode ray tube.
Description
This invention relates to an apparatus for displaying characters
and/or limited graphs on a cathode ray tube (CRT) by using standard
television raster scanning and more particularly, the apparatus is
characterized by a simultaneous display of characters and
graphs.
The CRT display devise is used very effectively in general for
peripheral equipment and on-line remote terminals, as the medium of
man-machine communication on a digital computer. The CRT display
device is superior to the ordinary teletypewriter due to its high
display speed, noiseless operation because it has no printing
mechanism, and capability of editing and formating functions of an
off-line operation.
Although the CRT display device is well recognized and is much
requested for use in man-machine communication, its wide use is not
at present possible due to its high cost.
The conventional CRT display device using refresh memory (buffered
CRT display) comprises two main parts, a controller and a console.
The controller includes an interface circuit, an input-output
circuit, a temporary memory (refresh memory), a character
generation circuit and a control circuit. The console comprises a
CRT, a CRT peripheral circuit and a keyboard.
An interface circuit is used to connect the display device with a
digital computor and communication line. The control circuit
controls operation of the interface circuit, the I/O circuit, the
temporary memory, and the character generation circuit. A temporary
memory stores character codes for displaying which are transmitted
from the computer and keyboard. The character generation circuit
produces a character pattern on the CRT face plate by using the
codes stored in the temporary memory. The CRT peripheral circuit
comprises a deflection circuit for deflecting an electron beam, a
high voltage source and an intensity modulation circuit. The
keyboard is used for providing input data, controlling transmission
of the data and editing of the display contents.
As for the method for generating a pattern, there are four known
methods: that is the charactron method, the monoscope method, the
dots method and the strokes method.
When the CRT display device uses a normal television receiver, the
dots method is widely used adopting raster scanning. According to
the dots method, a character pattern is displayed in an ixj dots
matrix. Because a character space is necessary in order to discern
the characters from those on the next line, the scanning skip
method is used. However, there are defects in this method, in that
the usual television scanning system cannot be used and that dotted
sequence curves are displayed.
In order to display characters and the limited graph with the ixj
dots matrix pattern by using a delay line, for example by using a
low cost magnetostrictive delay line, two registers are required,
that is a refresh memory (temporary memory) and a shift register. A
refresh memory can store any character codes corresponding to
information to be displayed on the face plate, that is M lines of N
characters. After being stored in the refresh memory, the
characters of one line (N characters) are transferred to the shift
register therefrom. By circulating the shift register J times, one
line is displayed on the CRT.
The number N of the characters to be displayed per line according
to the conventional method is determined in accordance with the
following equation;
N = T.sub.D.sup.. C/K
where
N = characters per line for screen format.
T.sub.D = effective scanning time per line.
C = clock frequency (Hz) of the refresh memory.
K = bit length of the binary character code.
For example, when T.sub.D is 50 .mu.sec, C is 1 MHz and K is 6
bits, the number N of the characters is nearly 8 characters per
line.
In order to increase the number of the characters to be displayed
per line for a screen format, it is necessary to make the clock
frequency of the refresh memory higher or to make the effective
scanning time longer. Further, a higher clock frequency of the
refresh memory requires that the refresh memory have a short access
time. This makes the memory system expensive. On the other hand,
making a longer effective scanning time makes it impossible to use
a standard television system and requires a special television
system. This also increases the cost of the display device.
Also, it is very difficult to display a limited graph on the CRT
face plate of the ordinary character CRT display. In order to
display limited graphs on the character CRT display it is necessary
to divide the picture plate of CRT into picture elements so that a
graph is formed by appointing one character area to picture element
positions. However, the quantity of information for addressing to
display a graph is increased. Therefore, the display control
circuit becomes complex and further software used for displaying
also becomes very complex. Accordingly, the display device of this
method becomes substantially more expensive.
The object of the present invention is to provide a low-cost novel
CRT display device capable of using a character mode and a graphic
mode together and of providing terminals of an on-line control
system. Therefore, the device according to the invention can be
used suitably for the terminals of a mini-computer and on-line
remote terminals. The cost of the device can be decreased due to
the simplified control circuit. Further the commercial television
receiver is readily used for the CRT monitor in accordance with the
invention.
These and other objects of the invention will become apparent upon
consideration of the following description taken together with
accompanying drawings in which:
FIG. 1 is a block diagram for illustrating the method of the
invention;
FIG. 2 shows a character code to be located in the refresh
memory;
FIGS. 3A-3D show a raster scanning pattern, a character pattern,
picture element patterns and character and picture codes,
respectively;
FIG. 4 is a block diagram for illustrating the method for
displaying a limited graph and a character together;
FIG. 5 is a logic circuit diagram for producing the limited graph
shown in FIG. 4; and
FIGS. 6A-6C show the codes, the picture element pattern and the
limited graphic curve displayed in accordance with the system shown
in FIG. 4.
Referring to FIG. 1, an input-output circuit 12 treats plural lines
of character codes from a terminal of computer (not shown). A
refresh memory 1 (a magnetostrictive delay line) is connected to
said input-output circuit 12 and receives said character codes, and
circulates at a clock frequency. A shift register 2 to receive one
line of said character codes circulates at a circulating rate which
is higher by an integer number times than said clock frequency of
said refresh memory 1 and which is equal to a horizontal scanning
time of a standard television system (not shown). Said integer
number corresponds to a number of scanning lines at a line space
between two adjacent lines of said character codes. A control
circuit 5 is connected to a transfer exchange gate 6 to control the
operation of said shift register 2. A serial to parallel conversion
gate 3 is connected to said shift register 2 and to said control
circuit 5. A character pattern generator 4 is connected to said
control circuit 5 and to said serial to parallel conversion gate 3.
Output signals produced at said serial to parallel conversion gate
3 are converted into video signals which are to be reproduced as
one line of a character pattern on a cathode ray tube of said
standard television system.
When the character codes are transmitted from the refresh memory 1
to said shift register 2 during a time period necessary for
scanning a line space between two adjacent lines, the refresh
memory 1 produces a clock pulse C1 to operate said shift register
2. Upon transmission of said character codes from said refresh
memory 1 to said shift register 2, said pattern generation circuit
4 starts to display character codes (l scanning lines). As a
result, the shift clock of said shift register 2 is changed to
C2.
C1 and C2 are related by the following equation:
C2 = l .sup.. C1 (1)
After the change of the clock from C1 to C2, the shift register 2
circulates at a rate higher by l times than said clock frequency at
C1. During the circulation, output serial pulses of the shift
register 2 are converted into parallel pulses in a character code
by the serial to parallel conversion gate 3. The parallel character
codes enter the character pattern generator 4. A video signal from
said pattern generator 4 is displayed as a one line dotted pattern
on the CRT.
A repeat of this operation i times causes a one line character
pattern to be displayed on the CRT. In the space interval between
the one line character pattern and the next line (l scanning
lines), character codes of the next line are transferred from the
refresh memory 1 to the shift register 2. When these operations are
repeated M times a picture is displayed fully on the CRT. The
refresh memory 1 when synchronized with a standard television
system circulates to reveal 60 frames per second. When a character
display of one line is finished, the refresh memory 1 transfers the
next line character codes to the shift register 2. In order to
cause the character code to address to the refresh memory 1, the
character codes in the refresh memory 1 are arranged as shown in
FIG. 2.
Referring to FIG. 2 reference character A designates character
codes in the refresh memory 1, and m.sub.1 and m.sub.2 are code
sequences of one display line. The enlargement of m.sub.1 is shown
by B which is further enlarged to C. The character codes of one
line (1, 2, . . . , n) are stored in order in the refresh memory 1
and synchronous codes H succeed the character codes as shown in B.
These codes form the line block m.sub.1. The line block m.sub.2 of
the characters to be displayed at the following line is arranged
after the i/l blocks as shown at A in FIG. 2. Each block of the
character codes to be displayed in order is arranged with an i/l
block interval from each other. Such arrangement is controlled by
the control circuit 5 when the input of these character codes is
supplied to the refresh memory from the circuit 12.
In this method, the number N1 of characters which can be displayed
in one line is calculated by the following equations
N1 = D.sup. . C2/K (2)
= D.sup.. lC1/K (3)
= lN (4)
Therefore, it is necessary to make the capacity of the refresh
memory 1 and the shift register 2 larger l times than that of an
ordinary refresh memory. An ordinary display system has more than
two scanning lines at the interval space between the line of the
characters and the succeeding line. A combination of the novel
display system according to the present invention and the ordinary
display system makes it possible to display characters in a number
more by two times than that displayed only by the ordinary display
system.
The above description is directed to horizontal raster scanning,
but vertical raster scanning is achieved in a manner exactly
similar to that of horizontal raster scanning. In case of the
latter, the codes are transferred from the refresh memory 1 to the
shift register 2 during a time period corresponding to the interval
space between the rows of the character.
Accordingly, the display method of the present invention provides a
CRT display system in which characters can be displayed by means of
raster scanning adaptable for standard television system. The
method of the invention has the advantages of being able to employ
a commercial television receiver and a low speed magnetostrictive
delay line and to be able to increase the number of characters to
be displayed at one line.
Now, the following description will explain a method for displaying
a limited graph by using a CRT character display system at a low
cost in accordance with the present invention.
Referring to FIG. 3, a character pattern shown in FIG. 3A is
displayed by dot points for horizontal raster scanning. Any
character pattern can be displayed on this display system by using
an ixj matrix such as shown n FIG. 3B. In addition, a limited
graphic pattern also can be displayed as shown in FIG. 3C in which
each picture element forms one block to be divided by an nxm dots
matrix in one character area. The block of each picture element in
the character area corresponds to each character code bit, and each
of the picture element blocks is displayed independently. Now when
the number of blocks is d, the graphs in number of 2.sup.d
combinations can be displayed in one character display area. The
character pattern and graphic pattern are discriminated from each
other by noting a given bit 7 of one character code, as shown in
FIG. 3D. The remaining bits of the code are used as a pattern
code.
The following will describe in more detail the operation of
displaying limited graphs. Referring to FIG. 4, wherein similar
reference characters designate networks similar to those of FIG. 1,
an input-output circuit 12 treats plural lines of character codes
from the terminal of a computer (not shown). A refresh memory 1 (a
magnetostrictive delay line) is connected to said input-output
circuit 12 and receives said character codes, and circulates at a
clock frequency. A shift register 2 to receive one line of said
character codes circulates at a circulating rate which is higher by
an integer number times than said clock frequency of said refresh
memory 1 and which is equal to a horizontal scanning time of a
standard television system. Said integer number corresponds to the
number of scanning lines at a line space between two adjacent lines
of said character codes. A transfer control circuit 7 is connected
to a transfer exchange gate 6 to control the operation of said
shift register.
A display gate 8 is connected to said shift register 2. A
discrimination gate 9 is connected to said shift register 2 and
receives an output code from said refresh memory 1 so as to control
said display gate 8. Said display gate 8 is switched to G or C
depending upon the output signals of a picture code or a character
code from said discrimination gate 9. Display gate 8 is connected
to G and C to a picture elements generator 31 and a character
generator 32, respectively. A display shift register 10 is
connected to said picture elements generator 31 and to said
character generator 32 and has an output signal controlled by said
transfer control circuit 7 to form a video signal for the CRT
11.
At first, the transfer control exchange gate 6 is synchronized with
a first scanning line of the displaying lines so as to couple with
a b side thereof and then the character codes are transferred from
the refresh memory 1 to the shift register 2. Just after the codes
are transferred to the shift register 2, the transfer exchange gate
6 is reset to the a side. Then, the shift register 2 operates as a
circulating register. The character codes are circulated in the
shift register corresponding to the horizontal scanning lines.
The transfer of the character codes is controlled by the transfer
control circuit 7. At first, the transfer control circuit 7 picks
up a character code, 6, a bit 0 or 1, which defines the codes as
character codes or graphic codes. The use of the bit 0 or 1 causes
the display gate 8 to be switched to C or G by the control circuit
9. When the gate 8 is set at C, the character codes from the shift
register 2 are supplied to the character generator 32. Then, the
character generator 32 produces character patterns and the
characters are displayed on the CRT face plate. The character
generator 32 comprises a well known diode matrix or a pulse trans
type magnetic core matrix, or the like, and generates the dot
patterns in sequence by scanning lines as shown in FIG. 3D. The
output signals from the character generator 32 are parallel j dots
signals and are converted into serial j bits through the display
shift register 10 so as to be sent to the CRT 11.
In case of graphic codes, the transfer control circuit 7 controls
the display gate 8 to be set to G and the graphic codes from the
shift register 2 are supplied to the picture elements generator 31,
which generates a picture elements pattern corresponding to each
code bit of the graphic codes. The output signals of the picture
elements pattern generator 31 are supplied to the display shift
register 10, and displayed in a manner similar to that of the
character display.
The picture elements generator 31 is shown in more detail in FIG.
5, in which similar numerical characters 2, 7, 8, 9, 10, 11 and 31
designate networks similar to those of FIG. 4.
As an example of an embodiment of the invention, it is considered
that one character code in FIG. 3D consists of seven bits and the
picture elements pattern in FIG. 3C is expressed by i = 12, j = 8
and m = n = 3. In this case, one character code has a maximum of
six (2 .times. 3) picture elements and one picture element is
defined by 3 .times. 3 dots which correspond to three horizontal
scanning lines and three vertical dots. A picture element is spaced
from an adjoining picture element by one horizontal scanning line
and one vertical dot. The picture element bits A, B, C, D, E and F
in FIG. 3D are positioned in one character area as shown in FIG.
3C.
Referring to FIG. 5, a shift register 2 is in operation for one
character code and has a parallel code output supplied to a display
gate 8 and to a discrimination gate 9. Input signals to said
discrimination gate 9 through a refresh memory are in the form of
the special fixed bit of FIG. 3D. Input signals to said display
gate 8 through said refresh memory are composed of the picture
elements code of FIG. 3D and the output signals of said
discrimination gate 9. Output signals A, B, C, D, E and F of
display gate 8 correspond to codes A, B, C, D, E and F of FIG. 3C,
respectively. These output signals of said display gate 8 enter a
picture generation gate 311 and produce a pattern of picture
elements. A scanning signal also enters a scanning signal gate 310
which has output signals supplied to said picture generation gate
311 to produce picture elements pattern corresponding to every
scanning line. Output signals (a, b, c, d, e and f) of said picture
generation gate 311 enter, for generation of a picture element
block, a picture element block gate 312 which has an output signal
thereof supplied to a display shift register 10. Output signals of
said display shift register 10 are controlled by a transfer control
circuit 7 and are supplied to a CRT 11 for display of the
pattern.
The picture element generator 31 of FIG. 4 is composed of scanning
signal gate 310, picture element generator gate 311 and picture
element block gate 312.
The operation of the pattern generation of picture elements is
described in the following. When the discrimination bit of the code
"7" in FIG. 3D is 1 (namely the code is a graphic code), all bits
(A, B, C, D, E and F) of the graphic code are switched on by the
discrimination gate 9 upon transfer of one character code to the
shift register 2. In order to first display the picture elements C
and F shown in the FIG. 3C by the picture elements generation gate
310 of the picture elements generator 31, the picture elements
generation gate 310 in FIG. 5 is switched on by a first scanning
signal and the code output signal C of the display gate 8.
Similarly, the gate output f of the picture element generation gate
311 is gated out by the first scanning signal and the output signal
F of the display gate 8. As the shift register 2 is in
synchronization with the shift clock, the transfer control circuit
7 generates a set pulse only when a character code is fully
supplied to the shift register 2. This means that the set pulse is
synchronized with the end bit of the character code. By this set
pulse, a set gate of the display gate 8 is opened and the signals
of the picture element generator 31 are supplied to the display
shift register 10. Then, the output signal of the display shift
register 10 is displayed on the display CRT scanning spots of
intensity modulation signal. As the discrimination gate 9
discriminates whether the code is character or graphic, the graphic
character patterns can be displayed on the CRT face plate
simultaneously.
This operation is repeated for every character code, and one dot
pattern of the scanning line is fully displayed. One circulation of
the shift registers 2 and 10 terminates the display of the first
scanning line. This operation is repeated in scanning order and the
picture elements C and F are displayed. Similarly by scanning the
5th, 6th and 7th scanning lines or 9th, 10th and 11th scanning
lines, the picture elements B and E or A and D are displayed in
order. A circulation of the shift register 2 for twelve times
complete the display of one line pattern. Upon the completion, the
transfer exchange gate 6 of FIG. 4 is set to the b side, and then
each code of the next line is transferred from the refresh memory 1
to the shift register 20 so as to be displayed as a character or
graphic pattern on the CRT. A repeat of this operation completes
one display on the whole CRT. During this operation, the transfer
control circuit 7 controls line synchronization, line exchange and
the shift clock.
The character patterns are generated by the character generator 32,
while a graphic pattern is formed by each of picture element
patterns corresponding to each bit of the code. When one character
is, for example, of six bits, 2.sup.6 (=64) kinds of graphic
elements can be formed by the code including the six bits. Such
graphic elements make it easier to display any kind of limited
graph. For instance when the number of the characters to be
displayed on the whole CRT is MN (M lines of N characters) and one
character area is constructed by six picture elements as in FIG.
3C, the resolution of the display face on the CRT is 2 .times. N
horizontal and 3 .times. N vertical picture elements.
The display of y = f(x) is explained with reference to FIG. 6. The
code and picture elements are defined as shown in FIGS. 6A and 6B,
and lines and rows are defined as in FIG. 6C. In connection with a
code of DKl corresponding to the display pattern the the lth row of
kth line, the matrix position of Pxy is defined by the following
equations:
l = (x/2) + 1 (5) k = (Y/3) (6)
where
x = 0, 1, 2, . . . , (l-1)
(x) is integer part of x,
and a code of position Pxy is defined by the following
equations:
.alpha. = x - 2(l-1)
= 0
1 (7) .beta. = y - 3(k-1) = 0 1 2 (8)
Accordingly, a code D to display a point Pxy is defined as
follows:
D = 2.sup.3.sup..alpha. .sup.+.sup..beta. (9)
Then the display character position of this code is the lth
character of the kth line. By the above equations, a code of any
point Pxy is obtained easily. In addition, such display system can
be used as graphical input equipment because a drawing of a graph
on the CRT face plate results in the formation of codes in the
refresh memory, and the formed codes can be converted into matrix
positions by the above equations.
As described hereinbefore, according to a method of this invention,
both the character pattern and limited graphs can be displayed
simultaneously. The refresh memory can store both character codes
of graphs and character codes of characters similar to each other.
The display system of the invention has great advantages compared
with the ordinary CRT character display system, so that it can be
widely used as a graphical input machine and a simple input-output
terminal machine.
While the invention has been particularly shown and described with
reference to a preferred embodiment thereof, it will be understood
by those skilled in the art that various changes in form and
details may be made therein without departing from the spirit and
scope of the invention.
* * * * *