Mixed Alphameric-graphic Display

Abstract

An apparatus for providing a mixed alphanumerical and graphical display of coded data. The coded data is stored in a memory. Those data characters to be displayed graphically have an additional control bit stored with them. As the data is read from the memory for display, those characters accompanied by such a control bit are directed to a graphics logic unit, while those characters lacking the control bit are directed to a read-only memory. The outputs of these two components control a video signal generator which generates the necessary video signal for application to a display device such as a commercial television receiver.

Description

The present invention pertains to a data display device. More particularly, the present invention pertains to apparatus capable of providing a video display including both graphical and alphanumeric display of data.

In numerous data processing operations it is desirable to be able to provide a visable display of various data. It is frequently desired to display data generated by automatic data processing systems. Automated accounting systems, for example, frequently process voluminous accounting information of large companies. In numerous operations it may be desired to display such information rapidly to permit analysis and evaluation of the operation of the business. In many other applications of automatic data processing systems it is likewise desirable to be able to rapidly display data stored within the processing system. While much data can be adequately displayed in an alphanumerical display in which alphabetical and numerical characters are displayed, meaningful interpretation of some kinds of data can best be achieved if the data is displayed in graphical form. Mere graphs are not sufficient for such displays, of course; alphanumerical legends must be provided with the graphical displays to make such displays meaningful. Thus, optimum display of data requires mixed displays including both alphanumerical and graphical presentation of data, and in the following specification such displays are described as mixed displays.

The use of various cathode-ray tube devices and other such display mechanisms permits the rapid and economical display of data. Commercial television monitors have recently come into use as output display devices for data processing systems. Using such a television monitor, data can be simultaneously displayed in numerous widely separated locations. In the past systems for display of data by means of such display devices have been limited to alphanumerical displays, although there have recently been developed techniques for the graphical display of data on television-type display devices. These graphical display techniques, however, have been limited solely to the graphical displays. To display data alphanumerically with such techniques, it has been necessary to form the alphanumerical display by graphical methods. This is a complex method for the development of alphanumerical displays and so is expensive and thus undesirable.

The present invention is a system by means of which data can be displayed on a video display device in a mixed alphanumerical and graphical display. The alphanumerical display is generated in fixed patterns permitting optimum economical alphanumerical pattern generation, while the graphical display is formed by a versital graphical technique adapted to permit the rapid formation of any desired graphical or pictorial display. Utilizing the present invention it is not necessary to form the alphanumerical display by graphical techniques. Thus, more uniform alphanumerical displays are created while making optimum use of alphanumerical pattern generation techniques, thereby permitting optimum and economical generation of such displays.

Data to be displayed in a mixed alphanumerical and graphical display is applied to the apparatus of the present invention in coded form. A code interpreter determines whether particular data is to be displayed alphanumerically or graphically. Data to be displayed alphanumerically is applied to a translator such as a read-only memory which converts the data to alphanumerical control signals. Data to be displayed graphically is applied to a logic circuit which transforms it into graphical control signals. The two sets of control signals are applied to a video signal generator which converts them into the necessary video signal for application to the output display device.

These and other aspects and advantages of the present invention are more apparent in the following detailed description and claims, particularly when considered in conjunction with the accompanying drawings. In the drawings:

FIG. 1 is a block diagram of a data display system in accordance with the present invention;

FIG. 2 is a diagram of an output display monitor suited for use in the present invention;

FIG. 3 is a representation of an alphanumerical display of a character which might be provided on the display device of FIG. 2.

FIG. 4 is an enlarged view of one character space of the output display monitor of FIG. 2.

In the apparatus of FIG. 1 data from a source 10 is provided in coded form to the system of the present invention on line 11 which applies the data to code interpreter 12. Data source 10 might be any source of coded data character signals. In addition to the coded data character signals, source 10 applies to code interpreter 12 coded control character signals indicating whether particular data is to be displayed alphanumerically or graphically. Code interpreter 12 interprets the coded character signals applied to it and transmits the coded data character signals to memory 14 in which they are stored. When data source 10 applies a coded control character signal to code interpreter 12, the code interpreter transmits a control signal to an appropriate control circuit. While numerous control signals might be utilized in the present invention to control various features of the display of data, only those necessary to determine whether data is to be displayed alphanumerically or graphically are considered here. If a particular set of data is to be presented in a purely alphanumerical display, then data source 10 sends to code interpreter 12 a signal indicating that the system is to operate in an alphanumerical mode. In response to this signal, code interpreter 12 applies a signal to the reset input of bistable multivibrator or flip-flop 16. All subsequently displayed data is then displayed alphanumerically. If data is to be presented in a mixed alphanumerical and graphical display, data source 10 sends to code interpreter 12 a signal indicating that the system is to operate in a mixed mode, and in response thereto code interpreter 12 applies a signal to the set input of flip-flop 16. While the system is operating in this mixed mode, data to be displayed graphically is preceded from data source 10 by a graphical control command which causes code interpreter 12 to apply a signal to the set input of flip-flop 18, and data to be displayed alphanumerically is preceded from data source 10 by an alphanumerical control command which causes code interpreter 12 to apply a signal to the reset input of flip-flop 18. If desired the system could be constructed to operate only in the mixed mode, with flip-flop 16 and related circuitry omitted and with flip-flop 18 reset during what would be alphanumerical mode operation.

The ONE output of flip-flop 16 is connected to the first input of AND-gate 20, while the zero output of flip-flop 16 is connected to the first input of AND-gate 22. The data output from memory 14 is connected to the second inputs of both AND-gate 20 and AND-gate 22, and thus when the system is operating in a mixed mode to provide mixed alphanumerical and graphical displays, the ONE output of flip-flop 16 enables AND-gate 20 to pass the data from memory 14, and when the system is operating in an alphanumerical mode to provide only alphanumerical displays, the ZERO output of flip-flop 16 enables AND-gate 22 to pass the data from memory 14. In the mixed mode, when data is to be displayed graphically, flip-flop 18 is set, and its ONE output applies a signal to memory 14. As a consequence of this, each multibit data character subsequently stored in memory 14 has stored with it an additional bit which is a control bit, to indicate that the associated data character is to be displayed graphically. Conversely, when data is to be displayed alphanumerically, flip-flop 18 is reset, and so no such control bit is stored with the associated multibit data characters subsequently stored in memory 14. When the system is in the graphical mode of operation with AND-gate 20 enabled, the data characters from memory 14 are applied through gate 20 to the first input of AND-gate 24 and to the noninhibiting input of INHIBITED-AND-gate 26. The control bits stored in memory 14 with those data characters which are to be displayed graphically are applied from memory 14 to the second input of AND-gate 24 and to the inhibiting input of INHIBITED-AND-gate 26. Thus, in the mixed mode, data which is to be displayed graphically passes from AND-gate 20 through AND-gate 24 to graphics logic unit 28, while data which is to be displayed alphanumerically passes from AND-gate 20 through INHIBITED-AND-gate 26 and OR-gate 30 to read-only memory (ROM) 32. In the alphanumerical mode with flip-flop 16 reset, all data passes through AND-gate 22 and OR-gate 30 to ROM 32.

Graphics logic unit 28 interprets the data signals applied to it and in response thereto generates the graphical pattern signals which form the basis of the graphical output display. In like manner ROM 32 interprets the alphanumerical data signals and generates the alphanumerical pattern signals which form the basis of the alphanumerical output display. These pattern signals from graphics logic unit 28 and from ROM 32 are applied through OR-gate 34 to video signal generator 36 in which they are mixed with the necessary synchronization and other signals to form the appropriate video signal that is applied by output line 38 to display device 40. Video signal generator 36 in addition generates the necessary timing signals which not only are required by its output video signal but which also are applied to code interpreter 12, memory 14, graphics logic unit 28 and ROM 32 to synchronize operation of the system.

As a specific illustration of one preferred embodiment of the present invention, consider that output display device 40 is a commercial television receiver operating. As depicted in FIG. 2, when such a receiver is operating in a noninterlaced mode, there are on its display screen 41 a total of 2621/2 raster scan lines in its output display. To ensure against distortion of data on the output display, the 23 uppermost and the 23 lowermost raster scan lines are not used, and so 216 scan lines are available for data. These 216 scan lines can be divided into 24 data lines, each having nine scan lines. Each scan line is made up of 80 character positions, each of which is divided into six dot positions.

Assume that the data from data source 10 is in the ASCII code which is a widely accepted data code utilizing seven data bits for the encoding of each data character. Details of the ASCII code can be found in numerous publications such as United States of America Standards Institute publication USAS X3.4-1968, entitled Standard Code for Information Exchange, published in 1968. The following table presents the ASCII code: ##SPC1##

Columns 0 and 1 of the ASCII code are nonprinting control characters rather than data characters. These control characters can be utilized for the control commands from data source 10 to code interpreter 12. Thus, for example, the command to shift the system to the mixed mode might be the SO control character 0001110, while the command to shift the system to the alphanumerical mode might be the SI control character 0001111. In the ASCII code these control characters are the "shift out" and the "shift in" control commands, respectively. In accordance with the ASCII definitions the "shift out" control character 0001110 indicates that the coded characters which follow it are to be interpreted as not being from the ASCII code. Thus, usage of this coded character to indicate that the data characters following it is to be presented graphically is in agreement with this ASCII definition. Likewise, by the ASCII definition the "shift in" control character 0001111 indicates that coded characters following it are to be interpreted according to the ASCII code, and so use of this ASCII control command to indicate that data characters following it are to be presented alphanumerically in accordance with the ASCII code is in agreement with this ASCII definition. With the system operating in the mixed alphanumerical and graphical mode, any ASCII control character not required for another specific function can be used to indicate which data characters are to be displayed alphanumerically and which are to be displayed graphically. Thus, for example, two of the ASCII code information separators GS, RS, and US might be used for these control commands. Likewise, any other unused control characters could be utilized for this purpose. Code interpreter 12 senses the control commands and in response thereto applies the necessary signals to the different inputs of flip-flops 16 and 18. Data characters are likewise sensed by code interpreter 12 and are applied to the data input of memory 14. Video signal generator 36 applies the data line number and the character number to memory 14. Code interpreter 12 can be any set of gates capable of properly sensing the signals applied to it from data source 10. It is to be noted that in accordance with the ASCII code, each character having a zero for both bits six and seven is a control character which thus is applied by code interpreter 12 to either flip-flop 16 or flip-flop 18 or to some other control device should additional control features be provided.

Columns 2, 3, 4 and 5 of the above ASCII code table are referred to as the dense ASCII subset. These columns include all of the upper case alphabet, the numerals 0 through 9, and the most used punctuation and other symbols. Thus, while the present invention can be utilized to provide an alphanumerical display of the full ASCII code, a savings can be achieved without undue loss by limiting the display to the dense ASCII subset. Note that in every coded character in the dense ASCII subset the sixth bit is the opposite of the seventh bit; i.e., in those coded characters from the dense ASCII subset which have a zero for the sixth bit, the seventh bit is a one, and vice-versa. Hence, within the dense ASCII subset, each data character is uniquely defined by a six-bit coded character. Consequently, if the system is limited to display of the dense ASCII subset, code interpreter 12 needs to transmit to memory 14 only bits one through six of each coded character received from data source 10.

With the system operating in the mixed mode, when data from source 10 has been preceded by a control character indicating that the data is to be displayed alphanumerically, code interpreter 12 causes flip-flop 18 to be reset so that the data is stored in memory 14 without the extra control bit. Consequently, when that data is read from memory 14, AND-gate 24 is blocked, and INHIBITED-AND-gate 26 is not inhibited. The data from memory 14 therefore passes through gates 20, 26 and 30 to ROM 32 which interprets the data in accordance with the dense ASCII subset. ROM 32 receives the scan line number and the dot position number from counters within video signal generator 36, and from these numbers and from the data character, ROM 32 generates alphanumerical pattern signals that are transmitted through OR-gate 34 to video signal generator 36.

Video signal generator 36 generates a video signal including the six-bit position signals for the designated scan line of the designated data character. Thus, for example, if it is desired to display the alphanumerical character A depicted in FIG. 3, ROM 32 generates for the first scan line of that data character the alphanumerical pattern signal 001000, and in response to that signal and to the synchronization signals generated within video signal generator 36, the video signal generator applies to output line 38 a video signal to cause display device 40 to produce the first scan line of the alphanumerical character A as shown in FIG. 3. Generally, the video display will consist of totally blanked and totally unblanked areas, and so the video signal output from video signal generator 36 includes two-state blank and unblank signals mixed with the necessary vertical and horizontal synchronization signals. Thus, in response to this alphanumerical pattern signal 001000, video signal generator 38 generates a video signal for the first scan line of the designated character location on display screen 41 which causes dot positions one, two, four, five and six to be blanked while dot position three is unblanked. Should the reverse background be desired on display screen 41, then the video signal causes dot positions one, two, four, five and six to be unblanked while dot position three is blanked. If, of course, a representation of the alphanumerical character A different from that depicted in FIG. 3 is desired, the appropriate alphanumerical pattern signal is generated by ROM 32. It will be noted that the display of FIG. 3 utilizes seven raster lines and five dot positions of the nine raster lines and six dot positions in the character space. The remaining two raster lines and one dot position provide interline and intercharacter spacing.

When a control character from data source 10 has placed the system in the alphanumerical mode so that data read from memory 14 passes through gates 22 and 30 to ROM 32, the data is treated in the same manner by ROM 32 and video signal generator 36. Thus, the coded data characters are interpreted by ROM 32 in accordance with the dense ASCII subset to generate an alphanumerical pattern signal which is applied to video signal generator 36 to generate the appropriate video signal for application by system output line 38 to display device 40.

In the mixed mode, when data source 10 has applied to code interpreter 12 a control character indicating that subsequent data characters are to be displayed graphically, code interpreter 12 sets flip-flop 18 and each of those subsequent data characters is stored in memory 14 together with an extra control bit which indicates that those data characters are to be displayed graphically. When those data characters are read from memory 14, the control bit inhibits INHIBITED-AND-gate 26 and enables AND-gate 24. Consequently, those data characters pass from memory 14 through gates 20 and 24 to graphics logic unit 28 which in response thereto generates a graphical pattern signal. The coded data characters from data source 10 which result in graphical displays are in a six-bit code, just as are the coded data characters which result in alphanumerical displays of the dense ASCII subset. FIG. 4 depicts a typical character position on the display screen 41 made up on nine horizontal raster scan lines, each including six dot positions. As depicted in FIG. 4, each character position is divided into six bit spaces, b1 through b6. Each of the bit spaces b1-b6 is three scan lines high and three dot position wide. Rather than interpreting the coded characters in accordance with the dense ASCII subset, the coded characters are interpreted to indicate whether the respective six-bit spaces b1 through b6, depicted in FIG. 4, of the corresponding character position are to be blanked or unblanked on output display device 40. Thus, for example, the six-bit code can be interpreted by graphics logic unit 28 in accordance with the following graphics subset: ##SPC2##

The data characters from memory 14 which are to be displayed graphically are interpreted by graphics logic unit 28 in accordance with this graphics subset, and so graphics logic unit 28 applies a graphical pattern signal through OR-gate 34 to video signal generator 36 to cause the video signal generator to apply to output line 38 a video signal including two-state blank and unblank signals mixed with the necessary vertical and horizontal synchronization signals to generate the patterns of the above graphical subset. Graphics logic unit 28 receives from video signal generator 36 the raster line number and the dot position number to synchronize generation of the graphical pattern signals. Note that, as shown in FIG. 4, each bit position b1-b6 of the character position includes three dot positions on each of three raster lines. Thus, for example, if a display is to have blanked alphanumerical and graphical characters on an unblanked background, the coded character 110101 would graphically generate an L-shaped pattern having blanked dot positions one, two and three on each of raster lines one through six and dot positions one through six on each of raster lines seven through nine, with dot positions four, five and six on each of raster lines one through six unblanked. As can be seen from the above graphical subset, the blanked areas are contiguous. Thus, using the above graphical subset, continuous, unbroken graphical lines can be generated in accordance with the present invention, and so a flexible graphical display capability is achieved. If desired for a particular application, a bit space which is to be blanked can have fewer than all nine dot positions blanked in response to the data characters from memory 14. Thus, for example, in the three raster line by three dot position bit position, only centermost the dot space might be blanked. Alternatively, the four dot spaces defined by the intersection of the top two raster lines and left two dot positions of each bit position (e.g. dot positions one, two, four and five of raster lines one, two, four five, seven and eight) might be blanked. Numerous other such patterns, of course, could be utilized.

Memory 14 can be any memory having nondestructive read out and having sufficient capacity to hold the maximum number of data characters which it is desired to display. Thus, if the display is to have a maximum capability of 24 display lines, each with 80 character positions, the memory 14 must have a capacity of 1,920 seven-bit characters (six data bits and a control bit per character). The data characters stored within the memory 14 are then sequentially read out to gates 20 and 22, while the control bits are sequentially applied to gates 24 and 26.

The data bits in the data characters applied from data source 10 to code interpreter 12 can be applied either serially or in parallel. If the data is applied serially, code interpreter 12 preferably converts the data to parallel for application to memory 14.

Although the above description of one preferred embodiment of the present invention has been with reference to the normal commercial television raster pattern in which the display is raster scanned horizontally one raster line at a time, other scanning techniques could be utilized. Thus, for example, a subraster scanning technique might be used in which each display line is raster scanned by a horizontal scanning signal modulated with a sinesoidal sweep signal to sweep the scan vertically over the full character height during each display line raster scan. As other alternatives, a vertical raster scan could be utilized or a vertical subraster scan in which each vertical character location is raster scanned by a signal that is modulated by a sinesoidal sweep signal to horizontally sweep the scan over the full character width. Likewise, while a nine raster line by six dot position character space has been described, other sizes could be utilized. It is to be noted that once the coded data characters have been applied from data source 10 to memory 14, signals are no longer required from data source 10, and the system continues to display the static data within memory 14. Should a change in that data be made, data source 10 simply applies the new data characters through code interpreter 12 to memory 14, thus giving a dynamic capability. Accordingly display line numbers and character numbers are provided to code interpreter 12 from video signal generator 36 to synchronize this data input function.

Any of numerous display mechanisms could be utilized as a display device 40. Thus, for example, instead of a commercial television receiver, a standard cathode-ray tube could be utilized with both X and Y deflection voltages applied to it. Likewise, a stored image cathode-ray tube, not requiring frequent image refreshing, could be utilized, in which event memory (14) need not have a nondestructive readout. Other possible display devices include plasma screens, light-emitting diodes, and tungsten light bulb patterns. These various display devices are thus referred to as video display devices. It is thus seen that although the present invention has described with reference to preferred embodiments, numerous modifications and rearrangements could be made, and still the result would be within the scope of the invention.

Claims

What is claimed is:

1. Apparatus for generating from a plurality of coded input character signals, including coded input data character signals and coded input control character signals, a video output signal for application to a video display device to provide a mixed alphanumerical and graphical display of the input data characters encoded in the coded input data character signals, said apparatus comprising:

a. memory means for storing coded input data character signals;

b. first generating means for generating from said coded input data character signals a graphical pattern signal;

c. second generating means for generating from said coded input data character signals an alphanumerical pattern signal;

d. first control means coupled to said memory means, to said first generating means and to said second generating means and capable alternatively of assuming a first state in which coded input data character signals from said memory means pass through said first control means to said first generating means and of assuming a second state in which coded input data character signals from said memory means pass through said first control means to said second generating means;

e. input code interpreting means for receiving from a data source coded input character signals including coded input data character signals and coded input control character signals and for directing coded input data character signals to said memory means for storage wherein and directing coded input control character signals to said first control means to cause said first control means to assume one of its two states in response thereto; and

f. video signal generator means coupled to said first generating means and to said second generating means for generating a video signal, in response to the graphical pattern signal and the alphanumerical pattern signal, the video signal including synchronization components, said video signal generator means applying the video signal to an output line for application to a video display device, said video signal generator further generating timing signals for application within the apparatus to synchronize operation thereof.

2. Apparatus as claimed in claim 1 in which the coded input data character signals are multibit binary coded signals and in which said first control means includes:

means for applying to said memory means in one of the first and second states a control bit for storage in conjunction with an associated input data character signal; and

gate means responsive to presence of a control bit in association with an input data character signal stored within said memory means for applying that input data character signal to a first one of said first and second generating means, said gate means further responsive to absence of a control bit in association with another input data character signal stored within said memory means for applying that other input data character signal to the other one of said first and second generating means.

3. Apparatus as claimed in claim 2 further comprising second control means coupled to said input code interpreter means, to said memory means, to said first control means and to said second generating means, said second control means capable alternatively of assuming a first state in which coded input data character signals from said memory means pass through said second control means to said first control means and of assuming a second state in which coded input data character signals from said memory means pass through said second control means to said second generating means, said input code interpreter means directing selected coded input control character signals to said second control means to cause said second control means to assume one of its two states in response thereof.

4. Apparatus as claimed in claim 1 further comprising a video display device connected to said video signal generator output line for providing a video display of video signals applied thereto.

5. Apparatus as claimed in claim 4 in which said video display device is a television receiver.

6. Apparatus as claimed in claim 1 further comprising a source of coded input character signals.

7. Apparatus as claimed in claim 1 in which one of said first and second generating means is a read-only memory.