U.S. patent number 3,837,459 [Application Number 05/311,451] was granted by the patent office on 1974-09-24 for word processor with means for programming indented paragraph format.
This patent grant is currently assigned to Arthur D. Little, Inc.. Invention is credited to Peter G. Martin.
United States Patent |
3,837,459 |
Martin |
September 24, 1974 |
**Please see images for:
( Certificate of Correction ) ** |
WORD PROCESSOR WITH MEANS FOR PROGRAMMING INDENTED PARAGRAPH
FORMAT
Abstract
The invention relates to a word processor of the type utilizing
a typewriter as an input/output printer, and comprises indented
paragraph typewriter programming and control means for causing the
typewriter to establish and maintain a desired indented paragraph
format.
Inventors: |
Martin; Peter G. (Arlington,
MA) |
Assignee: |
Arthur D. Little, Inc.
(Cambridge, MA)
|
Family
ID: |
23206919 |
Appl.
No.: |
05/311,451 |
Filed: |
December 4, 1972 |
Current U.S.
Class: |
400/63; 400/64;
400/62; 400/280; 715/272; 715/202; 715/273 |
Current CPC
Class: |
B41J
5/42 (20130101) |
Current International
Class: |
B41J
5/31 (20060101); B41J 5/42 (20060101); B41j
005/30 () |
Field of
Search: |
;197/1,19,20
;340/172.5,174.1 ;179/1 ;235/61.9 |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Pulfrey; Robert E.
Assistant Examiner: Radar; R. T.
Attorney, Agent or Firm: Schiller & Pandiscio
Claims
What is claimed is:
1. Word processing and printing apparatus comprising: a printer, a
recording apparatus, data transfer means for controlling the
transfer of data between said printer and said recording apparatus,
and indented paragraph programming and control means for
establishing and maintaining an indented paragraph format;
said printer comprising a holder for a record medium; printing
means for printing characters on said record medium; said holder
and printing means being adapted for relative movement, printer
advancing means slectively operable to produce (a) bidirectional
relative movement of said holder and printing means along a first
axis so as to permit said printing means to print characters on
said record as a line of characters extending along said first axis
and (b) relative movement of said holder and printing means along a
second axis so as to permit said printing means to print characters
on said record in a line by line format; a plurality of
informational character and function keys; character operator means
responsive to operation of said character keys for operating said
printing means and said printer advancing means so as to cause said
printing means to print selected characters as a line of characters
along said first axis; function operator means responsive to
operation of said function keys for causing said printer to execute
selected functions according to the function key that is operated,
said function keys including a Return key, a Tab key and a Shift
key; said function operator means including first means responsive
to operation of said Return key for operating said printer
advancing means so as to position said printing means and said
holder relative to one another at a predetermined left hand margin
position along said first axis and also to produce an increment of
relative movement of said printing means and said holder along said
second axis whereby said printer is ready to print a new line of
characters, and second means responsive to operation of said Tab
key for operating said printer advancing means so as to relatively
reposition said printing means and said holder a preselected
distance along said first axis away from said left hand margin
position each time said Tab key is operated; code generating means
responsive to operation of any of said keys for generating codes
representative of the characters or functions corresponding to the
keys that are operated, including a Return code, a Tab code and a
Shift code; means responsive to operation of said Shift key for
enabling said code generating means to generate a Required Return
code and a Required Tab code on operation of said Return and Tab
keys respectively; and playback printer operating means including
means responsive to previously generated character and function
codes for operating said printer so as to print the characters and
perform the functions represented by said previously generated
codes;
said recording apparatus comprising storage means for storing a
plurality of said character and function codes, said storage means
having input and output means;
said data transfer means comprising selectively operable means for
applying codes generated by said printer code generating means to
said storage means, and selectively operable means for applying the
codes appearing at the output means of said storage means to said
playback printer operating means;
said indented paragraph programming and control means comprising
means for generating a Required Tab sensing signal each time a
Required Tab code is generated responsively to operation of said
Tab key, a Required Tab counter adapted to be incremented
responsively to each Required Tab sensing signal, means for
generating a Return sensing signal and a Required Return sensing
signal each time a Return code and a Required Return code
respectively is generated responsively to operation of said Return
key, means for clearing said Required Tab counter responsively to a
Required Return sensing signal, and means responsive to said Return
sensing signal for producing and applying tab-forcing signals to
said playback printer operating means to cause said printer
advancing means to relatively reposition said printing means and
said holder responsively to each such tab-forcing signal until the
number of tab-forcing signals so produced and applied equals the
count in said counter.
2. Apparatus according to claim 1 wherein said indented paragraph
programming and control means comprises means for incrementing said
Required Tab counter each time a Required Tab code appears at the
output means of said storage means and is applied to said playback
printer operating means, said means for generating a Return sensing
signal being adapted to provide a Return sensing signal each time a
Return code is coupled from the output means of said storage means
to said playback printer operating means, means responsive to each
said Return sensing signal produced responsively to a Return code
appearing at the output means of said storage means for producing
and applying tab forcing signals to said playback printer operating
means until the number of tab forcing signals so produced and
applied equals the count in said Required Tab counter, and means
for clearing said Required Tab counter responsively to a Required
Return code appearing at the output of said storage means and
applied to said playback printer operating means.
3. Word processing and printing apparatus comprising: a printer, a
recording apparatus, data transfer means for controlling the
transfer of data between said printer and said recording apparatus,
and indented paragraph programming and control means for
establishing and maintaining an indented paragraph format;
said printer comprising a holder for a record medium; printing
means for printing characters on said record medium; said holder
and printing means being adapted for relative movement, printer
advancing means selectively operable to produce (a) bidirectional
relative movement of said holder and printing means along a first
axis so as to permit said printing means to print characters on
said record as a line of characters extending along said first axis
and (b) relative movement of said holder and printing means along a
second axis so as to permit said printing means to print characters
on said record in a line by line format; a plurality of
informational character and function keys; character operator means
responsive to operation of said character keys for operating said
printing means and said printer advancing means so as to cause said
printing means to print selected characters as a line of characters
along said first axis; function operator means responsive to
operation of said function keys for causing said printer to execute
selected functions according to the function key that is operated,
said function keys including a Return key and a Tab key; said
function operator means including first means responsive to
operation of said Return key for operating said printer advancing
means so as to position said printing means and said holder
relative to one another at a predetermined left hand margin
position along said first axis and also to produce an increment of
relative moemvement of said printing means and said holder along
said second axis whereby said printer is ready to print a new line
of characters, and second means responsive to operation of said Tab
key for operating said printer advancing means so as to relatively
reposition said printing means and said holder a preselected
distance along said first axis away from said left hand margin
position each time said Tab key is operated; code generating means
responsive to operation of any of said keys for generating codes
representative of the characters or functions corresponding to the
keys that are operated, including a Return code and a Tab code;
selectively operable means for enabling said code generating means
to generate a Required Return code and a Required Tab code on
operation of aid Return and Tab keys respectively; and playback
printer operating means including means responsive to previously
generated character and function codes for operating said prnter so
as to print the characters and perform the functions represented by
said previously generated codes;
said recording apparatus comprising storage means for storing a
plurality of said character and function codes, said storage means
having input and output means;
said data transfer means comprising selectively operable means for
applying codes generated by said printer code generating means to
said storage means, and selectively operable means for applying the
codes appearing at the output means of said storage means to said
playback printer operating means;
said indented paragraph programming and control means comprising
means for generating a Required Tab sensing signal each time a
Required Tab code is generated responsively to operation of said
Tab key, a Required Tab counter adapted to be incremented once
responsively to each Required Tab sensing signal, means for
generating a Return sensing signal and a Required Return sensing
signal each time a Return code and a Required Return code
respectively is generated responsively to operating of said Return
key, means for clearing said Required Tab counter responsively to a
Required Return sensing signal, means responsive to said Return
sensing signal for producing and applying tab forcing signals to
said playback printer operating means to cause said printer
advancing means to relatively reposition said printing means and
said holder responsively to each said tab-forcing signal until the
number of tab-forcing signals so produced and applied equals the
count in said counter, means for incrementing said Required Tab
counter each time a Required Tab code appears at the output means
of said storage means and is applied to said playback printer
operating means, means responsive to positioning of said holder and
printing means at said left hand margin position for producing and
applying tab-forcing signals to said playback printer operating
means until the number of tab-forcing signals so produced and
applied equals the count in said Required Tab counter, and means
responsive to a Required Return code appearing at the output of
said storage means and applied to said playback printer operating
means for clearing said Required Tab counter.
4. Apparatus according to claim 3 wherein said indented paragraph
programming and control means comprises means for producing a Tab
sensing signal each time a Tab code or a tab-forcing signal is
applied to said playback printer operating means, a second counter
adapted to be incremented once responsively to each Tab sensing
signal, and means for clearing said second counter responsively to
relative positioning of said printing means and said holder at said
left-hand margin position, and further wherein said means for
producing and applying tab-forcing signals to said playback printer
operating means comprises comparator means for comparing the count
in said Required Tab and second counters, and means for
incrementing said second counter each time a tab-forcing signal is
applied to said playback printer operating means until the count in
said second counter equals the count in said Required Tab
counter.
5. Apparatus according to claim 4 wherein said means for producing
said forcing signal comprises a flip-flop, means for toggling said
flip-flop to a first state responsively to relative positioning of
said printing means and said holder at said left-hand margin
position, and means for clearing said flip-flop when the count of
said second counter is at least equal to the count of said Required
Tab counter.
6. Apparatus according to claim 3 wherein said selectively operable
means for enabling said code generating means to generate a
Required Tab code comprises a Shift key.
7. Apparatus according to claim 3 wherein said printer is an
electric typewriter.
8. Apparatus according to claim 7 wherein said printing means is
moveable along said first axis relative to said holder.
9. Apparatus according to claim 7 wherein said holder comprises a
roller platen.
10. A word processing system comprising a typewriter, a recording
apparatus, data transfer means including a buffer memory for
controlling the transfer of data between said typewriter and said
recording apparatus, and means for automatically programming said
typewriter for tabbing so as to provide a predetermined indented
paragraph format;
said typewriter including a holder for a record medium, printing
means moveable relative to said holder, means for indexing said
holder, a plurality of informational character and function keys
including a Return key and a Tab key, character operator means
responsive to operation of said informational character keys for
operating said printing means to print selected characters in a
line extending transversely of said record medium, function
operator means responsive to operation of said function keys for
performing functions corresponding to the function keys that are
operated, said function keys including a Return key and a Tab key,
and said function operator means including (a) means responsive to
operation of said Return key for returning said printing means to a
predetermined left hand margin position and operating said indexing
means so that subsequent operation of said informational character
keys will cause said printing means to print a new line of
characters and (b) means responsive to operation of said Tab key
for causing said printing means to shift transversely of said
holder away from said left hand margin position a predetermined
distance each time said Tab key is operated, means responsive to
operation of said keys for generating digital codes representative
of characters and functions corresponding to the keys that are
operated, and playback typewriter operating means including means
responsive to digital informational character and function codes
applied thereto for causing said typewriter to print characters and
perform functions responsively to said applied digital codes;
said recording apparatus comprising storage means for storing a
plurality of information character and function codes;
said buffer memory comprising a multi-cell storage register for
storing a plurality of said digital codes, first code transferring
means for transferring digital codes in either direction between
said typewriter and said register, second code transferring means
for transferring digital codes in either direction between said
recording apparatus and said register;
said data transfer means also including data transfer operating
means for operating said buffer memory and said code transferring
means in a first mode enabling transfer of codes generated in
response to operation of said keys from said printer to said
recording apparatus via said register or a second mode enabling
transfer of codes from said recording apparatus to said playback
typewriter operating means via said register, and mode control
means for selectively enabling said data transfer operating means
to operate said buffer memory and said code transferring means in
either of said modes;
said automatic programming means comprising counter means for
counting the number of digital codes generated by operation of said
Tab key at the beginning of the first line of an indented paragraph
that is being typed and for holding said count during the typing of
subsequent lines of said indented paragraph, means responsive to
operation of said Return key while said data transfer operating
means is enabled to operate said buffer memory and said data
transfer means in said first mode for generating tab-forcing
signals and applying said tab-forcing signals to said playback
typewriter operating means so as to cause said printing means to be
shifted a selected distance away from said left-hand margin
position responsively to each such tab-forcing signal until the
number of said tab-forcing signals so produced and applied equals
the count in said counter, and means for clearing said counter
means responsively to operation of said Return key at the
conclusion of said indented paragraph.
11. Apparatus according to claim 10 wherein said automatic
programming means comprises means operative when said data transfer
operating means is enabled to operate said buffer memory and said
code transferring means in said second mode for incrementing said
counter means responsively to application of digital tab codes to
said playback typewriter operating means, means for causing said
counter to hold said count, means responsive to application of
digital return code to said typewriter playback means from said
recording apparatus via said buffer memory for generating
tab-forcing signals equal in number to the count stored in said
counter means and for applying said same tab-forcing signals to
said playback typewriter operating means, and means operative to
clear said counter means when the last digital code of said
indented paragraph has been transferred from said recording
apparatus to said playback typewriter operating means via said
buffer memory.
12. Apparatus according to claim 10 further including selectively
operable means for causing said code generating means to generate a
Required Return code when said Return key is operated, and further
wherein said means for clearing said counter means is operative
responsively only to the generation of a Required Return code.
13. Apparatus according to claim 11 further including selectively
operable means for causing said coe generating means to generate a
Required Return code when said Return key is operated, and further
wherein said means for clearing said counter means when said data
transfer means is enabled to operate said buffer memory and said
code transferring means in either of said modes comprises means
operative responsively to the generation of a Required Return code
by operation of said Return key or the transfer of a Required
Return code to said playback typewriter operating means from said
recording apparatus via said buffer memory.
14. Apparatus according to claim 13 wherein said selectively
operable means for causing said code generating means to generate a
Required Return code comprises a Shift key on said typewriter and
means operable responsively to operation of said Shift key for
generating a code modifying signal.
15. Apparatus according to claim 12 wherein said counter means is
adapted to count only Required Tab codes and said automatic
programming means comprises selectively operable means for causing
said code generating means to generate a Required Tab code when
said Tab key is operated.
16. Apparatus according to claim 10 including selectively operable
skip means for preventing transfer of tab codes from said storage
means to said playback typewriter operating means when said data
transfer operating means is enabled to operate said buffer memory
and said code transferring means in said second mode.
17. Apparatus according to claim 16 further including means for
inhibiting generation of tab-forcing signals when said skip means
is operated.
18. Apparatus according to claim 16 further including means for
inhibiting clearing of said counter means when said skip means is
operated.
19. Apparatus according to claim 11 further including selectively
operable means for inhibiting application of a Tab code to said
storage means when said tab key is operated.
20. Apparatus according to claim 19 wherein said means for
inhibiting application of a Tab code to said storage means is
operative only when said data transferring means is enabled to
operate said buffer memory and said code transferring means in said
second mode.
21. A word processing system comprising a typewriter, a recording
apparatus, data transfer means including a buffer memory for
controlling the transfer of data between said typewriter and said
recording apparatus, and means for automatically programming said
typewriter for tabbing so as to provide a predetermined indented
paragraph format;
said typewriter including a holder for a record medium, printing
means moveable relative to said holder, means for indexing said
holder, a plurality of informational character and function keys
including a Return key and a Tab key, character operator means
responsive to operation of said informational character keys for
operating said printing means to print selected characters in a
line extending transversely of said printing medium, function
operator means responsive to operation of said function keys for
performing functions corresponding to the function keys that are
operated, said function keys including a Return key and a Tab key,
and said function operator means including (a) return function
means responsive to operation of said Return key for returning said
printing means to a predetermined left hand margin position and
operating said indexing means so that subsequent operation of said
informational character keys will cause said printing means to
print a new line of characters and (b) tabfunction means responsive
to operation of said Tab key for causing said printing means to
shift transversely of said holder away from said left hand margin
position a preselected distance each time said Tab key is operated,
means responsive to operation of said keys for generating codes
representative of characters and functions corresponding to the
keys that are operated, and playback typewriter operating means
responsive to informational character and function codes applied
thereto for causing said typewriter to print characters and perform
functions according to said applied codes;
said recording apparatus comprising storage means for storing a
plurality of informational character and function codes;
said buffer memory comprising a multi-cell storage register for
storing a plurality of said codes, first code transferring means
for transferring codes in either direction between said typewriter
and said register, second code transferring means for transferring
codes in either direction between said recording apparatus and said
register;
said data transfer means also including data transfer operating
means for operating said buffer memory and said code transferring
means in a first mode enabling transfer of codes generated in
response to operation of said keys from said printer to said
recording apparatus via said register or a second mode enabling
transfer of codes from said recording apparatus to said playback
typewriter operating means via said register, mode control means
for selectively enabling said data transfer operating means to
operate said buffer memory and said code transferring means in
either of said modes, and means for recycling said buffer memory so
that the beginning of a recorded line of characters is advanced to
the output of said buffer memory;
said automatic programming means comprising counter means for
counting the number of codes generated by operation of said Tab key
at the beginning of the first line of an indented paragraph that is
being typed and for holding said count during the typing of
subsequent lines of said indented paragraph, means responsive to
operation of said Return key while said data transfer operating
means is enabled to operate said buffer memory and said data
transfer means in said first mode for generating tab-forcing
signals equal in number to the count stored in said counter means
and for applying said tab-forcing signals to said playback
typewriter operating means so as to cause said printing means to be
shifted a selected distance away from said left hand margin
position responsively to each such tab-forcing signal, means for
clearing said counter means responsively to operation of said
Return key at the conclusion of said indented paragraph, means
operative when said data transfer operating means is enabled to
operate said buffer memory and said code transferring means in said
second mode for incrementing said counter means responsively to
application of tab function codes to said playback typewriter
operating means, means for causing said counter to hold said count,
means responsive to application of a return function code to said
typewriter playback means from said recording apparatus via said
buffer memory for generating tab-forcing signals equal in number to
the count stored in said counter means and for applying said same
tab-forcing signals to said playback typewriter operating means so
as to cause said printing means to shift away from said left-hand
margin position a selected distance responsively to each such
tab-forcing signal, means operative to clear said counter when the
last code of said indented paragraph has been transferred from said
recording apparatus to said playback typewriter operating means via
said buffer memory, and means for clearing said counter when said
buffer memory is recycled to the beginning of a recorded line.
22. Apparatus according to claim 21 further including means for
searching said storage means to find a desired recorded line of
characters, and means for clearing said counter whenever said
storage means is being searched.
23. Apparatus according to claim 3 including selectively operable
skip means for preventing transfer of tab codes from said storage
means to said playback typewriter operating means when said data
transfer means is enabled to apply codes from said storage means to
said playback typewriter operating means, and means for inhibiting
incrementing of said Required Tab counter whenever a tab code is
skipped.
24. Apparatus according to claim 3 including means for searching
said storage means to find a desired recorded line of characters,
and means for clearing said counter whenever said storage means is
being searched.
25. Apparatus according to claim 1 wherein the said means in said
playback printer operating means which is responsive to previously
generated character and function codes comprises a decoder for
decoding character and function codes transferred from said storage
means to said playback printer operating means, and further wherein
said tab-forcing signals applied to said playback printer operator
means bypass said decoder.
26. Apparatus according to claim 1 wherein said indented paragraph
programming and control means comprises a second tab counter
adapted to be incremented responsively to execution of a tab
function by said printer, means for clearing said second counter
responsively to execution of a return function by said printer, and
means for comparing the count in said Required Tab counter and said
second counter and for producing an output signal so long as the
count in said required tab counter exceeds the count in said second
counter, said means for producing and applying tab-forcing signals
to said playback priner operating means being responsive to the
output signal produced by said comparing means.
Description
This invention relates to word processors, and more particularly to
electronically-controlled data recording and printing systems
employing a typewriter as an input/output terminal.
PRIOR ART
A large number of systems are known in which data entered on a
keyboard-operated printer such as a typewriter are encoded and
stored on a record storage medium, the process being reversible so
that the information stored on the record medium can be decoded and
printed by the printer. It is also known to record the coded data
on a wide variety of recording media such as magnetic tape or
cards, punched tape and the like. One system enjoying wide use is
the type described for example in U.S. Pat. Nos. 3,297,124,
3,260,340 and 2,271,150, among many others. The system described in
these patents is particularly adapted for use with printers of the
type disclosed in U.S. Pat. No. 2,919,002 issued to L.E.
Palmer.
The typical word processor is capable of operating in at least two
modes. One mode, often called the Record mode, enables data typed
on the input/output printer to be recorded in the record storage
medium. In the second mode, frequently called the Play mode, data
stored in the record storage medium is read out and fed to the
printer which provides a printout having the same line and
paragraph format as was originally typed in. Typically, additional
data may be typed by manually operating the printer during playback
in the Play mode without affecting the data stored in the record
storage medium. A number of such systems also provide a mode of
operation, often designated "Adjust Mode," wherein the data stored
in the record medium is printed out by the typewriter with
automatic adjustment of line length according to the setting of the
right hand margin control on the typewriter by the operator.
A problem attendant to prior art word processors embodying an
Adjust mode of operation is maintaining the desired format when
printing out a record characterized by intended paragraphs. With
reference to certain typical prior art word processors using the
Palmer variety of typewriter, in recording data a line is
terminated on the typewriter by striking a carrier return (CR) key
which serves not only to terminate the line and return the
printhead to a preset left hand margin position but also to
generate a CR code signal which is stored in the record medium. On
playback in the Play mode the stored CR signal is transferred back
to the typewriter to cause the latter to perform precisely the same
functions as when the signal was originally generated. To
compensate for the operator making a change in the right-hand
margin between recording and playback or for insertion, deletion or
skipping of one or more characters, the right-hand margin control
logic is adapted on playback in the Adjust mode to skip over any
recorded CR signal that may be read out when the printhead is
outside of the so-called "return zone" and to force the typewriter
to execute a space in place of the sensed CR signals. The "return
zone" is a region (encompassing a predetermined number of character
positions immediately preceding the position at which the right
hand margin sensor of the typewriter is set during operation in the
Adjust mode) in which the right-hand margin control logic is
capable of forcing execution of a carrier return operation even
though no CR signal is present in the recorded data at positions
that fall within the return zone.
In these same prior art word processors, the termination of a
paragraph is commonly indicated by recording a CR signal
immediately followed by a signal indicating a typewriter tab
function (TAB). On playback, whether or not in the Adjust mode of
operation, the processor is required to recognize that the
combination of a CR signal followed by a TAB signal requires the
formation of a new paragraph regardless of the setting of the right
hand margin control on the typewriter, so that the data
constituting the new paragraph is not typed out as a continuation
of the preceding paragraph.
This requirement that the system recognize that a sequence
comprising a CR signal followed by a TAB signal denotes a new
paragraph presents a problem when the desired format includes
indented paragraphs where the indention of each line is indicated
by the presence of a CR signal followed by at least one TAB signal.
The problem is exemplified by assuming that an indented paragraph
has been typed on the typewriter and recorded in the recording
medium and that before playback the right-hand margin setting is
moved substantially closer to the left-hand margin setting. If now
the recorded data is played back in the Adjust mode, carrier return
signals followed by tab signals may result in sub-paragraphs in
some instances although such sub-paragraphs are not desired.
In the aforementioned prior word processors, this problem of
identifying and maintaining a predetermined indented paragraph
format is overcome by recording at the beginning of the first line
of the indented paragraph one or more special tab codes known as
Required Tabs (RTAB) and by employing means which remembers now
many RTAB codes are recorded and, each time a line of the intended
paragraph is completed with a CR, causes the succeeding line to be
preceded by a number of tabs equal to that recorded for the first
line. The tabs for the second, third, and subsequent lines of the
indented paragraph are executed on the typewriter automatically but
are not recorded. This automatic generation of tabs relieves the
typist from having to manually enter them and also serves to remind
the typist that the indented format of what is being typed is an
indented paragraph. When recording of an indented paragraph is
completed, the automatic tabbing function is cancelled by typing a
special CR code that usually is identified as a Required CR (RCR)
and is generated by simultaneously pressing a special code button
and striking the carrier return key.
If now the recorded data is played back as entered, i.e., without
operating in the Adjust Mode, the RTAB codes for the first line of
the indented section are executed in the typewriter as recorded
and, with respect to succeeding lines, are remembered and executed
as if they have actually been recorded for each such line. Thus
each time a line is completed by playing a CR, printing of the
succeeding line is delayed while the typewriter automatically
executes a number of tabs equal to that executed for the first
line. This automatic tabbing function ceases when the RCR code
designating the end of the indented section is played out.
In the Adjust mode of playback there is normally little correlation
between the lines as recorded and the lines as printed out.
Nevertheless, the automatic tabbing feature is adapted to maintain
the required indented format. This is achieved by executing the
RTAB codes played out at the beginning of the indented section so
that the first line is indented as originally recorded and
thereafter, whenever a CR is forced on the typewriter under the
control of the right-hand margin adjust logic, the same number of
tabs are automatically executed for each succeeding line. Again
automatic tabbing on playback is terminated when an RCR code is
played out.
Prior word processors embodying means for maintaining a
predetermined indented paragraph or left margin format during
printout have a number of limitations, the most notable of which
are (a) the necessity of providing an additional "code" key to
enter "required" codes, (b) the inability to reduce the amount of
indentation when playing out a record and especially the inability
to reduce indentation without affecting the recorded data and (c)
the inability to increase the amount of indentation when playing
out a record, and again without affecting the stored data. Still
other limitations may be known to persons skilled in the art.
SUMMARY OF THE INVENTION
The primary object of this invention is to provide an improved
indented paragraph handling feature for word processors.
Another object is to provide a word processor having improved means
for maintaining a desired indented paragraph format when printing
out a record with or without automatic adjustment of line length,
i.e., right-hand margin adjustment.
A further object is to provide an indented left-hand margin feature
for word processors that does not require the input/output device
to have a special "code" key that must be used with the TAB and CR
keys to enter "required" TAB and CR code signals.
Still another object is to provide a word processor having means
for increasing, decreasing or completely eliminating during
playback the indentation of the left-hand margin of an indented
paragraph of recorded data, without changing the recording of said
data in the recording medium.
Another specific object is to provide in a word processor of the
character described the capability of reducing the indentation of a
recorded paragraph or section of data when playing out a record
with or without automatic right-hand margin adjustment.
The foregoing and still other objects that are described or
rendered obvious hereinafter are achieved by a system that in its
preferred embodiment comprises two counters and a comparator. One
counter (TABR counter) remembers how many tabs are needed at the
beginning of each line while the other remembers how many tabs have
been automatically generated on each line (TABX counter). The
comparator indicates whether the TABR count is greater than the
TABX count, in which case further tabs must be generated, or
whether the TABR and TABX counts are equal, in which case no
further tabs are needed. The TABR counter is incremented whenever
an RTAB is typed (whether or not recorded) or an RTAB is read out
and played. The same counter is cleared whenever an RCR is typed
(whether or not recorded) or read out and played or skipped over.
The TABX counter is incremented whenever a TAB or RTAB signal is
typed or is played out or forced. It is cleared whenever any CR or
RCR is typed or is played out or forced. The ability to reduce the
amount of indentation of a paragraph when played out in the Adjust
mode or Final mode involves provision of means for skipping RTAB
codes manually so that they are not counted in the TABR counter and
so that the recording is not disturbed. The ability to reduce or
completely eliminate the indentation of a paragraph when playing
out in the Final mode involves typing an RCR after reading and
playing out some or all of the RTAB codes at the beginning of the
indented paragraph. The system also has the capability to increase
the indentation of a paragraph when playing in the Final mode by
typing one or more RTAB codes into the TABR counter. The ability to
decrease the indentation of other lines of the same paragraph is
exercised by typing RCR or RTAB codes at appropriate times during
playback. Typing an RCR clears the TABR counter while typing an
RTAB increments the TABR counter.
In a preferred form of word processor hereinafter described which
employs a buffer memory for temporarily storing, examining and
transferring data in either direction between the input/output
printer and a magnetic tape record storage medium, two additional
features may be provided. One feature involves resetting the TABR
counter during any tape search operation so that moving from an
indented paragraph to a non-indented paragraph does not result in
unwanted tabs. A second feature is operative when stepping the
contents of the buffer memory left and involves resetting the TABR
counter when stepping left over a TAB or RTAB. As this cycles the
buffer to the beginning of the line of data stored therein, any
RTAB codes recorded in that line will be played out but RTAB codes
are not automatically generated. Implementation of these two
additional features requires the TABR counter to be cleared
whenever stepping left over a TAB occurs or whenever any tape
search is executed. Other features and specific details of the
invention are described or rendered obvious hereinafter.
For a fuller understanding of the nature, objects and features of
the present invention, reference should be had to the following
detailed disclosure of a preferred embodiment which is to be
considered together with the accompanying drawings wherein:
FIG. 1 is a perspective illustration of a typewriter and coupled
console embodying the principles of the present invention;
FIG. 2 is an enlarged view of the console of FIG. 1 showing various
control buttons, displays and other elements;
FIG. 2A is a perspective view of a standard tape cassette
illustrating in phantom, the organization of information on the
tape according to the principles of the present invention;
FIG. 3 is a block diagram illustrating the organization of the
invention;
FIG. 4 is a block diagram showing details of the keyboard interface
logic of FIG. 3;
FIG. 5 is a block diagram showing details of the buffer memory of
FIG. 3;
FIG. 6 is a logic diagram partly in block form illustrating a
clocking control system forming part of the buffer control of FIG.
3;
FIGS. 6A to 6D illustrate, as timing diagrams on a common time
base, operation of the clocking control system of FIG. 6;
FIG. 7 is a logic diagram partly in block form illustrating output
multiplex, input demultiplex and read and write circuits shown in
FIG. 3;
FIG. 8 is a timing diagram illustrating the operation of elements
of FIG. 7;
FIG. 9 is a logic diagram partly in block form, showing the print
control logic system of FIG. 3;
FIG. 10 is a diagram illustrating some logic employed in the main
control of FIG. 3 for controlling clocking of the buffer
memory;
FIG. 11 is a diagram, partly in block form showing address display
logic coupled with the control console;
FIG. 12 is a diagram illustrating logic in the main control of FIG.
3;
FIG. 13 is an additional logic diagram illustrating the main
control of FIG. 3;
FIG. 14 shows additional logic cooperating with that of FIG. 13 to
control the step-left operation of the system;
FIG. 15 is a logic diagram, partly in block form, showing the
margin adjust logic of FIG. 3; and
FIG. 16 illustrates the logic for establishing and maintaining an
indented paragraph format.
Referring now to the drawings, there is shown in FIG. 1 a preferred
arrangement of equipment in which the invention is incorporated.
The apparatus of the invention includes an input/output printer 20
interconnected by an electrically conductive cable 21 to a control
console unit 22 for controlling recording, reproducing, and
editing. Printer 20 typically includes a manually operable keyboard
23 for controlling a single head printer of the Palmer-type which
has been adapted (for example by being emplaced on a baseplate 24
which is capable of detecting the condition of the latch and cycle
shaft switches in the printer and also having solenoids capable of
driving the latches and cycle shaft of the printer) for producing
an output indicative of the condition of those switches. Such a
baseplate is described in U.S. Pat. Nos. 3,452,851 and 3,453,379
issued to L. Holmes, Jr. In printers of the Palmer type each
character is automatically encoded when typed. When such a printer
is combined with a Holmes type baseplate the combination will be
capable of translating or interconverting formation of typed
characters and performance of printing functions with corresponding
coded character and function signals.
Unit 22 has a control panel 26 shown in more detail in FIG. 2, the
panel including a spring-loaded, normally closed cassette door 27
which is moveable so that a magnetic tape cassette 240 (shown in
more detail in FIG. 2A) can be loaded into a tape transport
mechanism located behind the door. Adjacent door 27 is a display 28
for indicating a record number corresponding to the position of a
data location on the tape 18 in a cassette 240 which may be loaded
into the machine. On control panel 26 are also a number of keys or
buttons and display lights associated with data entry, editing and
playback. The system of the invention is intended to have three
basic operating modes, a draft mode, a final mode and an insert
mode. To provide for selection of the mode of operation of this
sysyem there are provided a Draft button 30, a Final button 31, and
an Insert button 32. To provide for control of printing out onto
the printer of a character, word, or line from storage, either
while the system is in draft or final mode, there are included a
Character button 33, a Word button 34, and a Line button 35, plus
an Automatic button 36 for allowing the system to print
continuously. An On button 37 is also provided for starting the
system. Stop button 38 is included for stopping any printing
operation by the machine. The deleting or skipping of characters,
words and lines respectively is provided by manipulation of
Character, Word and Line buttons 45, 39 and 40.
A brief description of the functional consequences of the operation
of the various buttons on control panel 26 will be helpful in
understanding the detailed structural description of the device. It
is intended that the system be capable of both recording data onto
a cassette 240 or playing data from a cassette 240 onto printer 20
when operating in the draft mode. Specifically, it is intended
during draft mode operation that any data entered by manipulation
of keyboard 23 of printer 20 should be stored in a magnetic storage
or record in the system with any previously recorded characters
being overwritten by new data being stored at the same data
locations. In order to accomplish this end one need merely start
the system, select the record location, press Draft button 30 and
proceed to type in data on the keyboard. To cause the data thus
stored to actuate printer 30 and therefore to be typed out, it is
only necessary to return to the beginning of the stored data to
push Character button 33 to obtain print out of a single character,
to push Word button 34 to obtain a single word, to push Line button
35 to obtain a single line, or to push Automatic button 36 to
permit the entire stored data to be reproduced on printer 20.
If one should now press Final button 31, the system is conditioned
so that no storage of data manually typed or entered on printer 20
can occur, but that only the data stored in the machine can be
played out on printer 20. When playing in the Final mode it will be
later seen that an automatic right margin control system operates.
The Draft and Final modes of operation are mutually exclusive and
the system provides that if either the Draft or Final buttons are
pushed, the machine is switched from the one to the other mode of
operation.
Depression of Insert button 32 while the system is in the Final
mode will be ineffective, i.e., will not in any sense allow the
machine to operate other than in normal Final Mode operation. On
the other hand, if the Insert button 32 is depressed while the
system is in the Draft mode, the system switches to an Insert Mode
of operation, and if desired, visual indication can be given that
the machine is in an Insert Mode, as by lighting Insert button 32
or the like. The Insert Mode is intended to provide an operation
such that data entered on printer 20 by manual operation of the
keyboard 23 will be inserted into storage, up to a limit, without
overwriting or otherwise destroying previously stored data. Only
typing and recording can take place while in the Insert Mode since
pushing any other buttons (except the Draft or Final buttons) on
the control panel will cause the machine to trip out of the Insert
mode and revert to the Draft mode. If Insert button 32 is pushed
again, the system will switch out of the Insert Mode back to the
Draft Mode and, of course, any visual indication of Insert Mode
operation will terminate. If Final button 31 is pressed, the system
will switch to Final mode operation.
The play or print buttons 33, 34, 35, 36 or 38 control the extent
to which data will be read out of storage, either in draft or final
mode operation, and displayed on printer 20. Each time Character
button 33 is pushed, the next character in storage will be read out
on printer 20. Similarly, depression of Word button 34 or Line
button 35 will cause the next word or line in storage to be read
out on the printer. When the Automatic button 36 is pushed, the
system will cause the printer 20 to type out the data in storage
continuously until some stopping command occurs. The latter can be
obtained by pressing Stop button 38, or by certain special
conditions which will be described hereinafter.
Step Right and Step Left buttons 41 and 42 control the shifting of
data in storage. Each time either is pushed the data in storage is
shifted by one character in the appropriate direction and the
single print head 16 or carrier on the printer 20 similarly steps.
In this respect buttons 41 and 42 actuate the print head 16 to move
in the same manner as the space bar and backspace key on the
printer keyboard 23, with certain exceptions as will be explained
later. Preferably, if one of the buttons 41 and 42 is held down,
repetitive action is initiated so that the system steps
sequentially character by character.
As described, there are three delete/skip buttons 45, 39 and 40.
When the system is in Draft mode depression of these buttons will
serve to delete a recorded character, word or line from storage.
When the system instead is in the Final mode, these buttons act as
skip buttons which cause the system to skip the appropriate
character, word or line in storage without overwriting or otherwise
destroying the skipped data. Because the functioning of these
buttons to cause either deletion or skipping depends upon the mode
in which the system is then operating, means are provided in the
form of visual indicating lights 43 and 44 which respectively light
up to indicate the nature of the function of the buttons, i.e.,
delete or skip as the case may be.
There are two buttons for controlling tape motion, a Tape Forward
button 46 and a Tape Back button 47. These are preferably of the
spring-loaded type and each has a first or up position and a second
or down position. Pushing either of the tape buttons 46 or 47 to
its down position causes the system to move the tape 18 either back
or forward (as the case may be) to the beginning of the next of a
number of predetermined data blocks 19 or stations on the tape 18.
This motion from predetermined station to predetermined station on
the tape 18 will continue as a smooth sequence until the
appropriate button is released. After release of the button, the
motion of the tape 18 in the cassette 240 will continue until the
next predetermined station on the tape 18 is reached, at which time
the motion of the tape 18 is stopped. Similarly pushing either
buttons 46 or 47 to their up position causes the system to shift to
a fast forward or fast rewind movement (as the case may be) during
which the tape winds continuously. Fast winding due to pushing the
Tape Back button 47 to its up position will continue until the
button 47 is released, at which point the system then shifts to
slow forward speed and continues to move the tape until the next
predetermined station on the tape is located. A similar operation
in the opposite direction is effected by manipulation of the Tape
Forward button.
In the preferred embodiment the cassette tape is at least a two
track (25 and 29) tape, and two read/write heads, one for each of
tracks 25 and 29, (or a single two-channel head such as head 238)
are incorporated into the system. One of the tracks, 25, of the
tape is for the data to be stored. The other tape track 29 is
intended to contain data addresses 48, preferably in the form of
coded conversions of sequentially numbered three decimal digits,
each data address 48 being physically located substantially
adjacent the beginning of a data block 19 on track 25. Thus, when
the tape is moved either forward or back in the cassette, circuitry
associated with the address read/write head and the record number
display 28 will cause the latter to be appropriately indexed each
time an address corresponding to a data block 19 or record moves
past the read head. If desired, one can provide an erase mechanism
associated with the tape transport mechanism and the control panel
so as to erase selectively all data from the tape 18, and also if
desired to regenerate the addresses on the tape 18.
Also in the preferred embodiment, associated with the control panel
are a number of visual indicators or special lights 49 in addition
to the delete/skip light and insert indicator light discussed
earlier. These additional lights will be described later
hereinafter. Similarly, a number of audio signal devices to
indicate certain conditions of the apparatus can also be provided
and will be described hereinafter.
The operation of the device thus described can be advantageously
described in connection with a typewriter as an example of the
printer. There are three basic situations to be described:
1. Basic entering of data through the typewriter keyboard, i.e.,
recording an initial draft;
2. Insertion, deletion and other operations on data after entry of
the latter, i.e., editing; and
3. Data retrieval, i.e., typing of final copy.
In order to record data initially, the operator will first activate
the typewriter and also will depress button 37 to turn on the
remainder of the system. The operator should first set margins and
tabs on the typewriter as desired although one or more embodiments
of the invention may include the ability to set and clear tabs on
the basis of prior stored information. Then a magnetic tape
cassette 240 is placed in the carrier behind door 27 and the
operator then depresses button 30 to place the system in the draft
mode of operation. The position of the tape 18 in the cassette 240
will be indicated by the address displayed at display 28. If the
cassette 240 is not rewound and it is desired to start from the
beginning of the cassette, the latter can be rewound by pushing
Tape Back button 47 to its up position and waiting until rewind is
completed. If the operator wishes to start beyond previously
recorded material that is to be preserved, the tape 18 can be moved
with buttons 46 and 47 until the appropriate address is noticed at
display 28.
Hereafter, recording in the draft mode is accomplished
automatically merely by typing the desired information on the
typewriter keyboard 23. Each time the operator types a Carrier
Return, the data associated with the preceding typed line is then
transferred from the buffer memory of the system onto magnetic tape
18. If the operator observes that a wrong key has been struck,
correction can be made by depressing the Step Left button 42 which
causes the typewriter to automatically backspace. When the
typewriter has been backspaced to the error, the operator can
strike over the error with the correct character key. To get back
to the point where recording had been interrupted, the Step Right
button 41 can be depressed, or as will appear later, one can play
out the intervening material which has been recorded, or lastly one
can retype the intervening material and rerecord it.
If the operator wishes to underscore a word upon entry, the word
can be typed and then, using the regular backspace key on the
typewriter keyboard which will provide a recorded backspace, the
typewriter should be backed up to the beginning of the word. The
word can then be underscored, the underscoring being recorded
also.
When the operator has completed the draft, a Stop Code should be
entered. The Stop Code is generated by depressing the shift key and
striking Stop button 38 on the control panel.
Editing of a draft can be done in three basic ways:
1. a new draft can be generated in the draft mode of operation,
combining the desired parts of the old draft with typed and
recorded corrections;
2. Only specific lines requiring editing can be modified; or
3. A final copy can be generated in the final mode of operation
with correction being entered on the copy as the letter is typed,
without recording the corrections.
Normally, the first approach would be used especially if further
author revisions are anticipated. The third approach is appropriate
if only final, minor corrections are to be made and a final copy is
desired.
In generating a new draft, the following situations are likely to
be encountered. First, one can edit simple typographical errors by
playing back the tape 18 in the Draft mode, by first striking any
one of buttons 33, 34, 35 or 36. This will cause the material
recorded on the cassette to be played back on the typewriter,
assuming of course that the cassette 240 has been rewound to the
appropriate starting position. The material is then played up to
but not through the error and the error is corrected by
overstriking. Overstriking using the keyboard 23 will automatically
erase the erroneous material from the system and insert the
corrected material in the appropriate place.
If the error in the draft is surplusage of material such as an
extra letter or the like, it can be corrected by playing the
material out on the printer 20 up to but not through the extra
matter. The latter can now be deleted by simply pressing the
appropriately selected one of Delete/Skip buttons 38, 39 or 40
inasmuch as these buttons generate to place the system in condition
to delete the material when the system is also in the Draft
mode.
If the error in the Draft mode is due to missing material, the
latter can be added by playing out the recorded material (in the
draft mode) up to the appropriate position, pushing Insert Button
32 and typing on keyboard 23 the missing characters or words. The
machine can then be taken out of the Insert mode simply by pushing
any of the buttons 33 to 36 inclusive, all of which when actuated
switch the system back to the Draft mode of operation.
Final copy can be typed in either the Draft of Final mode. In
typing out copy, the basic difference in operation between the two
modes is simply that in the draft mode the system will execute each
carrier return signal that has been recorded whereas, in the final
mode the carrier returns may or may not be executed depending upon
the operation of an automatic right margin control feature.
If no further editing is required, the operator merely inserts
paper into the printer 20, sets the tabs and margins of the latter,
puts the cassette 240 into the machine, and moves it to the
beginning of the record with buttons 46 and 47. The machine then is
placed in automatic play by striking Automatic button 36. The
material or text stored in the machine will now be played out on
the printer 20 on a substantially continuous basis until the
printing is stopped by either striking Stop button 38 or because
the operator has preferably recorded an appropriate Stop Code at
the end of each page of text. If manual entry of certain material
such as the name and address of the person to whom a letter is to
be sent is to be inserted on the final copy, a Stop Code should
have been recorded when the original draft was recorded so that
automatic printing stops at the point where the special material is
to be manually entered. In order to prevent a recording of the
manually entered material if the system is not operating in the
final mode, the system should then be switched temporarily to that
mode of operation by depressing button 31.
If the final copy is being printed out in the Final mode of
operation, the system will stop printing whenever it detects that
it cannot automatically find a carrier return opportunity such as a
recorded Carrier Return or Space or Hyphen signal in a
predetermined return zone adjacent the right margin of the printed
text. When this occurs, the operator may use key 33 to cause
automatic printing, character by character, up to the point where a
Hyphen and a Carrier Return can be manually entered on the keyboard
23 after which automatic typing can then be reinitiated, e.g., by
again depressing the Automatic key 36. Normally, this manually
entered Hyphen and Carrier Return will not be recorded so that any
reruns from the same tape will encounter the same stopping
conditions. If, however, the operator wishes to record the Hyphen
and Carrier Return, this may be done by pressing Draft button 30
and Insert button 32, typing the Hyphen and Carrier Return, then
pushing Final button 31 to switch the system operation back to
Final mode, and finally pushing one of the buttons 33-36 inclusive
to resume printing. As long as no further changes are made in the
paragraph up to this point, subsequent reruns will always find the
Carrier Return and hyphen when needed and will continue playing
without automatically stopping.
In typing final copy, it may be necessary to make some minor
corrections in the recorded material. As long as these changes need
not be recorded on the tape, the procedure is simple while
operating in the final mode. Simply by depressing any of the
Delete/Skip buttons, 39, 40 and 45, one may cause the system to
skip over unwanted characters, words, or lines in the material
being played back and additional material may be manually typed
in.
Before describing some of the more complex editing operations, it
will be advantageous to describe briefly the general organization
of the system embodying printer 20, baseplate 24 and control
console unit 22. With reference particularly to FIG. 3, there is
shown a block diagram of the organization of a system in simplified
form. In order to clarify the diagram, all of the control
connections are shown as solid lines whereas all of the data
carrying lines are shown as dashed lines. The embodiment of FIG. 3
includes input/output printer 20 which, as previously described, is
connected via base plate 24 to the control console. Data flow from
the printer 20, in the form of electrical signals, is applied to
keyboard interface logic 50. The latter primarily serves to encode
electrical signals from the printer 20. The output of the interface
logic 50 is then fed along an appropriate connection to the input
of a buffer memory 52. As will be described later, the buffer
memory 52 is preferably in the form of a shift register capable of
storing, for example, 200 characters each of eight bits.
It will be appreciated that one may however employ a random access
type memory such as a core array as memory 52, but because a random
access memory might involve complex addressing logic, a shift
register type of memory is preferred. The output of the buffer
memory 52 in turn is connected to means such as a multiplexer 54
for converting the eight parallel bit per character format of the
data organization in the buffer memory 52 to a serial train of data
bits. The output of multiplexer 54 is then in turn fed to the input
of write-data circuitry 56 which conditions the data and places it
in single-channel format for storage, such as on the tape 18 in a
cassette mounted in a magnetic recording apparatus indicated as
data storage 58.
Alternatively, if one employs an eight-track tape with
corresponding read-write channels, data need not be multiplexed but
can be read out directly from buffer storage to tape.
The organization shown in FIG. 3 also includes a return path for
reading data out of data storage 58 so that it can be printed out
by printer 20. To this end, data storage 58 is connected to
read-data circuits 60 and to read-address circuits 63. The latter
is intended to read the address track 29 on the two-channel tape 18
and provides an output which is connected to address-display logic
64 which serves to actuate address-display 28. Read-data circuits
60 are intended to read the data stored in serial form on the other
track 25 of the tape 18. The output of read-data circuits 60 is fed
to means, such as input demultiplexer 62, for converting the serial
form of the data into an eight parallel bit per character code,
suitable for injection into the buffer memory. To that end the
output of demultiplexer 62 is coupled to the input of buffer memory
52. The output of buffer memory 52 is also connected as an input to
both margin-adjust logic 66 and print-control logic 68.
Margin-adjust logic 66 serves to examine the contents of buffer
memory 52 so as to decide if, within a predetermined printing zone
along the right hand margin of the carrier travel set on printer
20, a Hyphen, Space or Carrier Return code will occur, thereby
providing the basis for a right hand margin adjustment system.
Print-control logic 68 is primarily employed to control printer 20
in accordance with the character and functional signals received
from the buffer memory and the signals received from margin-adjust
logic 66. Additionally, print-control logic 68 is intended to
decode the contents of buffer memory 52 into a form suitable for
actuating printer 20.
Console unit 22 and the controls contained therein are shown as
main control block 22A which is connected for controlling the
operation of printer 20. Main control block 22A is interconnected
with the keyboard interface logic for controlling the sum of the
encoding functions of the latter and is also in turn connected to
receive signals from the keyboard interface logic for use elsewhere
in the system. Similarly, control block 22A is connected so as to
view the data flowing both into buffer memory 52 and out of buffer
memory 52. Print-control logic 68 includes preferably a parity
check system whereby it examines data flowing out of buffer memory
52 for odd parity and provides a control signal to main control
block 22A to indicate if parity is or is not correct. Buffer memory
52 is connected so as to be controlled by a buffer control system
70 which in turn is under the control of main control block 22A.
The system also includes write-control logic 72 which is connected
so as to be responsive to main control block 22A and is also
coupled to control write-data circuits 56. Similarly, the system
includes read-control logic 74 which is connected to be responsive
to main control block 22A and serves to control both read-data
circuits 60 and read-address circuits 63. The system also includes
tape control circuits 75 which are responsive to main control block
22A and serve to control operation of mechanisms for transporting
the data storage record or tape.
For convenience, the form of encoding employed in the system of the
invention is based to a large extent upon the nature of the basic
structure of a printer of the Palmer-type and a base plate of the
Holmes-type. Thus, the print or informational characters can be
defined in binary form according to the following Table I, wherein
the eight data lines carrying each bit are respectively identified
as R1, R2, R2A, R5, T1, T2, P (parity) and S (case), all
collectively referred to hereafter as the data lines.
TABLE I
__________________________________________________________________________
1 2 3 4 5 6 BIT POSITION R1 R2 R2a R5 T1 T2 PARITY CASE
__________________________________________________________________________
Character: a 1 1 0 1 0 1 1 0 b 1 1 1 0 1 0 1 0 c 1 1 0 1 1 0 1 0 d
0 1 0 1 1 0 0 0 e 0 1 0 0 1 0 1 0 f 1 0 0 1 1 1 1 0 g 0 0 0 1 1 1 0
0 h 0 1 1 0 1 0 0 0 i 1 1 0 0 0 1 0 0 j 0 0 0 0 1 1 1 0 k 1 1 0 0 1
0 0 0 l 0 1 1 1 1 0 1 0 m 0 0 0 1 0 1 1 0 n 1 0 0 0 1 0 1 0 o 0 1 1
1 0 1 1 0 p 0 1 0 0 1 1 0 0 q 1 1 0 0 1 1 1 0 r 0 1 0 1 0 1 0 0 s 0
1 1 0 0 1 0 0 t 0 0 0 0 1 0 0 0 u 1 0 0 1 1 0 0 0 v 1 0 0 1 1 0 0 0
w 1 1 1 0 0 1 1 0 x 0 0 0 1 1 0 1 0 y 0 1 1 0 1 1 1 0 z 0 0 0 0 0 0
1 0 1 0 0 0 1 0 0 0 0 2 1 0 0 0 0 0 0 0 3 1 0 0 1 0 0 1 0 4 0 1 1 1
0 0 0 0 5 0 1 0 0 0 0 0 0 6 1 1 0 0 0 0 1 0 7 0 1 0 1 0 0 1 0 8 1 1
0 1 0 0 0 0 9 1 1 1 0 0 0 0 0 0 0 1 1 0 0 0 1 0 ; 0 1 0 1 1 1 1 0 ,
1 1 0 1 1 1 0 0 . 1 0 0 0 0 1 1 0 ' 0 1 0 0 0 1 1 0 / 0 1 1 1 1 1 0
0 = 1 0 0 0 1 1 0 0 .+-. 1 1 1 1 1 1 1 0 Hyphen 0 0 0 0 0 0 1 0
__________________________________________________________________________
Upper case characters, of course, use a 1 bit in place of the case
bit in each instance, and also for upper case characters the parity
bit is the complement of the parity bit for the lower case
character, in order to maintain odd parity. It will be appreciated
that other encoding systems can be used, but the foregoing is the
more convenient.
As known, base plate 24 has six output data lines on which appear
information character signals identified as R1, R2, R2a, R5, T1,
and T2 (see FIG. 4). Each information character generated by the
printer in response to operation of the keyboard is partially
encoded in the form of combination of bits represented by these
information character signals. These signals are direct outputs of
the base plate.
Note that these information character signals are barred, (e.g.,
R2) to indicate for purposes of this disclosure that they are
actually of negative (as opposed to positive) polarity.
Additionally, other signals representing operation of the
functional keys of the printer are produced by the base plate as
uncoded or simple signals. These signals are, in inverted form, Tab
(TAB), Tab Set (TABS), Tab Clear (TABC), Backspace (BS), Carrier
Index or Line Feed (CI), Space (SP), Shift (SH) and Carrier Return
(CR). Still another output obtained directly from the baseplate 24
is a printer head in motion signal (PIM). These signals, except CR,
are all fed as inputs to the keyboard interface logic 50 (FIGS. 3
and 4). In addition to the foregoing signals received directly from
the baseplate, other simple signals may be supplied as inputs to
the keyboard interface logic 50. Included are such signals as a
Stop Code signal generated by depressing the shift key on the
keyboard 23 of the printer and concurrently depressing Stop button
38 on the control console. The shift and stop signals produced are
then gated in known manner to produce the Stop Code signal which is
then encoded by keyboard interface logic 50 as shown in Table
III.
Referring now to FIG. 4, the logic 50 includes an encoder which
comprises a plurality of encoder gates 76 having input lines which
carry the foregoing keyboard logic input signals. The keyboard
interface logic 50 also includes a plurality of enable gates 78, a
parity generator 80, and an enable line 82 connected to provide an
enabling signal to enable input terminals of gates 78. Encoder
gates 76 have data output lines connected to the input terminals of
enable gates 78 and parity generator 80 has a plurality of input
terminals connected to receive the signals being carried by the
data output lines of encoder gates 76. The output of parity
generator 80 is also connected as an input to enable gates 78.
To the extent shown in FIG. 4, the keyboard logic 50 performs a
number of related functions. A basic function is to
TABLE II
__________________________________________________________________________
1 2 3 4 5 6 BIT POSITION R1 R2 R2a R5 T1 T2 PARITY CASE
__________________________________________________________________________
Functions: Tab Set 0 1 0 0 0 0 0 0 Tab Clear 0 1 0 0 0 1 1 0 Tab 0
1 0 1 0 1 0 0 Space 0 1 0 1 1 1 1 0 Backspace 0 1 0 1 0 0 1 0
Carrier Index 1 1 0 1 0 1 1 0 Carrier Return 1 1 0 1 1 0 1 0
__________________________________________________________________________
TABLE III
__________________________________________________________________________
1 2 3 4 5 6 BIT POSITION R1 R2 R2a R5 T1 T2 PARITY CASE
__________________________________________________________________________
Functions: Stop Code 1 1 0 0 0 0 1 0 Blank Cell 0 0 0 0 0 0 0 0
__________________________________________________________________________
complete the encoding of characters generated by operation of the
keyboard so that each informational character is now coded as a
unique combination of eight bits as earlier identified in Table I.
This is accomplished by adding a parity bit and a case bit to the
partial code produced by the informational character signals
appearing on the six output data lines of the base plate. Another
function is to encode as other unique combinations of eight bits,
as identified in Table II, the various machine keyboard controlled
functions that appear as direct base plate outputs -- namely, Tab,
Tab Set, Tab Clear, Space, Backspace, Carrier Return and Carrier
Index (i.e., Line Feed).
A third function is to encode as still other unique combinations of
eight bits other logic inputs that do not arise directly or solely
from that baseplate -- namely, the Stop Code, and certain special
or required functions. The preferred coding for the Stop Code is
shown in Table III together with the coding for Blank Cell.
A fourth function is to provide three other outputs, an SH signal,
A PIM signal and a signal identified, for convenience, as Function
from Keyboard. This latter signal appears whenever any one of
several signals indicative of keyboard function (specifically Tab,
Tab Set, Tab Clear, Space, Backspace and Carrier Index) appear at
the inputs to gates 76. It should be noted that the Carrier Return
input to gates 76 does not produce a Function from Keyboard signal.
These encoding functions are performed by encoder gates 76 and
parity generator 80, with the case (S), parity bit signal (P) and
information character signals appearing as outputs of enable gates
78. Enable gates 78 produce outputs in response to signals
appearing in the output data lines of encoder gates 76 and parity
generator 80 only when an enable signal appears on enable line 82.
Parity generator 80 is of a known type which generates a 1 bit
along an output line to provide a parity signal P according to
whether the parity of the signals appearing on its seven output
lines is even or odd. The system herein disclosed uses odd parity
so that a 1 bit is generated by parity generator 80 only when it
determines that its input data signals have even parity. Parity
signal P is passed to an appropriate output terminal of gates 78
when the latter are enabled.
The encoder output shown in FIG. 4 from enable gates 78 and from
encoder gates 76, as previously indicated in FIG. 3, are applied to
buffer memory 52. The latter is shown in FIG. 5 as comprising eight
input OR gates 84, 85, 86, 87, 88, 89, 90, and 91. The outputs from
enable gates 78 are respectively connected to gates 84 through 91
inclusive. The latter are also connected to eight other input
terminals, each identified by the corresponding code bit, to which
are applied information character, case and parity signal inputs
derived from the Read Data Circuits or other sources. the output
from gates 84-91 inclusive are fed to a blank cell detector in the
form of gate 92 which forms part of main control block 22A and are
also fed in to the respective inputs of a main storage memory,
preferably in the form of a static shift register 94 capable of
storing 200 eight bit characters. Clock line 95 is provided for
introducing a clocking signal X.sub.2 for initiating storage or
buffer shifting. The outputs of shift register 94, again eight
lines which correspond to the inputs from enable gates 78 are
connected to corresponding output terminals each identified by the
appropriate corresponding code in the drawing. The eight output
lines are also connected to the corresponding inputs of a first
subsidiary storage register or device 96 which is preferably an
eight-bit single character register having an input clock line 97
at which clocking X1 is intended to be applied. First subsidiary
storage device 96 has eight output lines, each corresponding of
course to one of the eight input lines thereto and each connected
to a corresponding input of a second eight-bit single character
register 98 which is clocked by a signal X.sub.3 over line 99 and
can be cleared by a reset-signal C.sub.3 over a line 100. Register
98 again has eight output lines each corresponding to a respective
input line to the register, the output lines from register 98 each
being connected to a corresponding one of input gates 84-91
inclusive so that, for example, gate 91 which has an input
connected to the parity bit line from parity generator 80 also has
an input connected to the corresponding parity bit line from
register 98. Similarly, all of the other input lines to the various
OR gates 84-91 are matched. The path thus defined from the
respective input OR gates through the main buffer storage register
94, through register 96 and 98 and back to the output OR gate, will
be seen to constitute a complete feed back path around the main
register 94. In the embodiment shown, two subsidiary storage
registers 96 and 98 are employed to minimize problems arising from
possible differences in the operating speed of the main and
subsidiary storages. Hence the feedback loop may comprise but one
single-character register if the latter is closely matched in terms
of operating speed to the main register 94.
It is not important for an understanding of the invention to
appreciate how data is passed through the buffer memory during the
various operating modes heretofore described.
As previously noted, the main store is static shift register.
Assuming that it is an eight-line 200 bit register 94, i.e., can
store 200 eight bit characters, each time a clocking signal X.sub.2
is applied over line 95, a new character will be entered at the
left hand end of the register via gates 84-91 and whatever
characters are already stored in the register will shift one cell,
i.e., one bit position to the right. If a character is already
stored in the 200th cell, it will be ejected from the right hand of
the cell when the register shifts in response to an X.sub.2
clocking signal. The subsidiary stores also are static shift
registers 96 and 98. Accordingly, occurrence of a clocking signal
X.sub.1 on line 96 will cause the first subsidiary storage register
96 to respond to and store the data signals that appear on the
output lines of register 94. Occurrence of a clocking signal
X.sub.3 on line 99 will cause the second subsidiary storage
register 98 to respond to and store the data signals appearing on
the output lines of the first subsidiary storage register 96.
Occurrence of a C.sub.3 reset pulse on clear line 100 clears the
second subsidiary storage register 98 to prevent a character
previously stored therein from being circulated back to the
register 94 via OR gates 84-91. Clearing the second subsidiary
storage register 98 is performed when it is desired to clear the
main register or to enter new data into the main register.
The clocking pulses for the buffer memory are derived from a
four-phase clock pulse generator. As described hereinafter, the
clock generator is gated to provide a series of four clock pulses
or tetrads occurring at times .phi..sub.1, .phi..sub.2,
.phi..sub.3, .phi..sub.4. The generator also is adapted to generate
such tetrads as in four different clusters or groups characterized
by a quantifier depending upon the operating mode of the system.
The clock pulse generator is gated to provide a train of clock
pulses each time a printer key is depressed or the printer prints a
character or executes a function in response to an output from the
buffer memory 52 or each time the system is caused to delete or
skip a character as a result of depressing one of the delete/skip
buttons 38, 39 and 40. The reason for slaving the clock pulse
generator (and thus the buffer memory) to the printer when the
system is set so that the typewriter will print out in accordance
with the output from the buffer memory, is that the printer takes
longer to execute some operations than others. Similar reasoning is
the basis for adapting the clock pulse generator to generate pulses
groups according to one of four different quantifiers depending
upon the operating mode of the system. As will be seen, the
quantifiers in the preferred embodiment are 1, 199, 200 and
201.
As hereinafter described, provision is made for clocking the buffer
memory so that it can be made to undergo a single shift cycle or a
201 shift cycle (assuming a 200 character main buffer memory). In
the single shift cycle the main register 94 is shifted as a result
of an X.sub.2 clocking signal and the second subsidiary register 98
is held clear during the main register 94 shift to prevent
circulation of old data from the second subsidiary register 98 back
to the main register 94. When typing in a character from the
keyboard in the draft mode, there is no need to clock the
subsidiary register in order to effect a single shift cycle whereby
the typed character is entered into the left hand end of the main
storage register 94; in practice, however, all three registers 94,
96 and 98 are clocked according to a "X.sub.1 X.sub.3 X.sub.2 "
sequence (i.e., clocking signals X.sub.1, X.sub.3, and X.sub.2
occur in the order named at times .phi..sub.1, .phi..sub.2, and
.phi..sub.3 respectively). In a 201 shift cycle, the main register
94 is shifted 201 times, with all three registers 94, 96 and 98
being clocked according to the normal sequence "X.sub.1 X.sub.3
X.sub.2," or a second special "X.sub.1 X.sub.2 X.sub.3 " sequence.
In this latter sequence, the clocking signals X.sub.1, X.sub.2, and
X.sub.3 occur in the order named at times .phi..sub.1, .phi..sub.2,
and .phi..sub.3 respectively. Provision is also made for clocking
the buffer memory so that it can undergo a 199 or 200 shift cycle
(again assuming a 200 character main register 94). The 199 shift
cycle is used to shift the contents of the main storage register to
the left (backward) one cell while the 200 shift cycle is used to
clear the main register and for other actions.
A large number of buffer memory clocking modes are employed in
operation of the system. Some of these modes are described as
follows:
Typing data into store in the Draft Mode
In this case a single or a 201 shift cycle is used, with the
clocking occurring in the X.sub.1 X.sub.3 X.sub.2 sequence and the
second subsidiary storage 98 being held clear during the single
shift cycle and during the first of the 201 shifts to prevent
circulation of old data and to enable a new character to be entered
into the main register 94. No reset signal is applied to clear line
100 during the remaining 200 shifts to that the contents of the
main register 94 can be circulated and so that the new character
sits at the left hand end of the main register 94 just as if a
single shift cycle had been executed. The advantage of using the
201 shift cycle rather than the simple shift cycle for this purpose
is because the 201 shift cycle permits one to examine the buffer
contents to detect a full buffer condition.
Printing out from the buffer memory
Single shifts are used in this mode, with the X.sub.1 X.sub.3
X.sub.2 sequence providing normal circulation of data through the
main and subsidiary storage registers 94, 96 and 98. Data signals
from the typewriter sensors in the base plate 24 during the time
that the typewriter is printing out are prevented from appearing on
the input lines to OR gates 84-91.
Inserting data into store in the insert mode
This mode can be utilized when the machine has been set for Draft
Mode operation. It involves a 201 shift cycle. The clocking order
is initially X.sub.1 X.sub.2 X.sub.3, but is caused to revert to
X.sub.1 X.sub.3 X.sub.2 at a point in the 201 shift cycle when a
blank cell is detected at a selected point in the buffer memory.
Two variations are provided. In one case the clocking order will
change to X.sub.1 X.sub.3 X.sub.2 when a blank cell is first seen
at the output of the second subsidiary register 98 (i.e., at the
input of the main register 94) in .phi..sub.4 time, i.e.,
immediately after completion of an X.sub.1 X.sub.2 X.sub.3 clocking
sequence. The second variation is when the system includes an
insert overflow feature to be described hereinafter. If 199 cells
of the available 200 in the main buffer register 94 are filled with
stored characters, a potential insert overflow situation arises.
Accordingly, any further insertions are made with the buffer memory
52 clocking order reverting to the X.sub.1 X.sub.3 X.sub.2
sequence, when a blank cell is detected at the output of the main
storage register 94 immediately after completion of an X.sub.1
X.sub.2 X.sub.3 clocking sequence. A second blank cell detector,
similar to gate 92, is connected to the output lines of the main
storage register 92 when the insert overflow feature is included in
the system.
Delete Mode
This mode can be utilized only when the machine has been set for
Draft Mode Operation. Deletion of a character is accomplished by a
201 shift cycle, initially in the normal X.sub.1 X.sub.3 X.sub.2
clocking sequence but switching to the X.sub.1 X.sub.2 X.sub.3
sequence when a blank cell is first detected at the output of the
second subsidiary register 98 in .phi..sub.4 time. Deletion of a
group of characters is achieved by repetitive cycles of 201
shifts.
Skip Mode
This mode can be used only when the system has been set for Final
Mode operation. It involves single shifts with the X.sub.1 X.sub.3
X.sub.2 clocking sequence. The behavior of the system is the same
as when printing out from the buffer memory, except that the
printer 20 is prevented from typing out the skipped character.
Clearing Buffer
This mode involves a 200 shift cycle and may be conducted according
to either clocking sequence. Preferably, however, it is conducted
with the X.sub.1 X.sub.3 X.sub.2 clocking sequence.
Examining the Buffer Memory Contents for Any Purpose
This mode involves a 200 shift cycle and may be conducted in the
X.sub.1 X.sub.3 X.sub.2 clocking sequence.
The effect of the clocking sequence on the buffer memory will now
be described. In the normal X.sub.1 X.sub.3 X.sub.2 clocking
sequence, the first subsidiary register 96 is clocked first
(.phi..sub.1 time) to store the data signals appearing at the
output of the main register 94, i.e., it assumes the state of the
last cell of the main register 94. Then the second subsidiary
register 98 is clocked (.phi..sub.2 time) so that it will assume
the state of the first subsidiary register 96. When this occurs the
second subsidiary register 98 will have steady state output signals
indicative of its new state and these output signals appear at the
inputs of OR gates 84-91. Next the main register 94 is clocked
(.phi..sub.3 time) so that its contents will undergo a single shift
to the right (forward) and its first cell will assume the state of
the signals appearing at the input terminals of OR gates 84-91.
However, if a C.sub.3 reset signal is applied to clear line 100 at
the time that the second subsidiary register 98 is clocked (or
afterward) and before the main register 94 is clocked, the first
cell of the main register will assume a clear state when the main
register is clocked by the X.sub.2 clock pulse. If however OR gates
84-91 have inputs from the keyboard 23 or other sources, then when
clocked by the X.sub.2 clock pulse the first cell assumes a state
determined by such inputs. This procedure of using an X.sub.1
X.sub.3 X.sub.2 clocking sequence accompanied by a C.sub.3 reset
signal is called the "non-circulate mode" and is used when entering
characters from the keyboard 23. The procedure of using the X.sub.1
X.sub.3 X.sub.2 clocking sequence without a C.sub.3 reset signal is
called the "normal circulate mode" and is used when it is desired
merely to circulate data from one end to the other of the main
register 94.
In the X.sub.1 X.sub.2 X.sub.3 sequence, the first subsidiary
register 96 again assumes the state of the last cell in the main
register 94 when the X.sub.1 clock pulse occurs. Then the main
register 94 is clocked to execute a single step shift. When this
occurs the first cell of the main register 94 assumes the state of
the second subsidiary register 98. Next the second subsidiary
register 98 is clocked to store the signals appearing at the output
of the first subsidiary register 96. As just described, this
X.sub.1 X.sub.2 X.sub.3 clocking sequence permits circulation of
data from one end to the other of the main storage register 94. If
a C.sub.3 reset signal is applied to the second subsidiary register
98 before the main store is clocked (.phi..sub.2 time), the first
cell of the main register 94 will not be able to assume the state
of the second subsidiary register 98 when it shifts, and thus will
be blank or will assume a state determined by whatever other
signals are present at the inputs of OR gates 84-91. However, when
the second subsidiary register 98 is clocked at .phi..sub.3 time,
it will assume the state of the first subsidiary register 96. This
procedure of using an X.sub.1 X.sub.2 X.sub.3 clocking sequence is
called the "enhanced circulation mode" since its not result is to
increase the buffer memory capacity by one character. More
explicitly, it permits circulation of a group of stored characters
without loss while permitting a new character to be inserted into
that group. Essentially this enhanced circulation mode delays
transfer of a character from the output of the main register 94
back to the input of the main register 94 so as to permit a
character to be inserted from the keyboard 23 during an insert
cycle. In other words, it serves to increase temporarily the
effective size of the main register 94 by a single character. It
also permits a character to be deleted during a delete cycle, as
explained hereinafter.
FIG. 6 illustrates the four-phase clock generator and the
associated logic circuit for changing the clocking order. FIG. 6
and other logic diagrams hereinafter will be described in terms of
positive logic for clarity in exposition, but it is to be
understood that negative logic can also be used. Essentially the
four phase clock generator is a self-correcting twisted ring
counter comprising four JK master-slave flip-flops 102, 104, 106
and 108 interconnected so that the Q and Q output terminals of
flip-flop 102 are connected to the K and J terminals of flip-flop
104, while the Q and Q terminals of flip-flop 104 are connected to
the J and K terminals of flip-flop 106 and the Q and Q terminals of
the latter are connected to the J and K terminals of flip-flop 108.
The Q terminals of flip-flop 102 and the Q terminals of flip-flops
104 and 106 are connected to the input terminal of AND gate 112
whose output terminal is coupled directly to the K terminal of
flip-flop 102 and also to the input of inverter 114. The output of
inverter 114 is applied to the J terminal of flip-flop 102. The
generator also includes clock 116 whose output is applied e.g., at
455 KHz, on line 120 to one input terminal of AND gate 122. The
latter is enabled by an enable generator signal that is applied to
gate 122 on line 124. This enable generator signal also is applied
on line 126 to the clear terminals of flip-flops 102 to 108
inclusive. The output terminal of AND gate 122 is connected to the
clocking input terminal C of all four flip-flops 102 to 108
inclusive. As hereinafter described, the four flip-flops operate
sequentially to produce corresponding output clock signals denoted
.phi..sub.1, .phi..sub.2, .phi..sub.3 and .phi..sub.4. These latter
signals are derived from the Q terminal of flip-flop 102 and the
respective Q terminal of each of flip-flops 104, 106 and 108 and
are applied to the input terminals of four AND gates 128, 130, 132
and 134. These latter gates have second input terminals that are
each connected to the output terminal of AND gate 122. The Q
terminal of flip-flop 108 is connected, as will be shown later, to
control the duration of the enable generator signal so that the
four phase clock generator can operate for 1, 199, 200 or 201
cycles of tetrads as required.
Typically, the clock signals from clock 116 and enable generator
signals on line 124 are positive pulses. The leading edge of the
enable generator signal is immediately preceded by the trailing
edge of a clock pulse.
Assume for purposes of discussion that gate 122 is enabled with an
enable generator signal so that the gate will pass clock pulses
from clock 116. The enable generator signal appearing also on line
126 will enable the four flip-flops 102 to 108 to be clocked. As a
consequence, the output of gate 112 will initially be low, so that
the J and K terminals of flip-flop 102 will be high and low
respectively. At the same time the J and K terminals of flip-flop
104 will be high and low respectively while the J and K terminals
of each of flip-flops 106 and 108 will be low and high
respectively. The first flip-flop clocking pulse produced by gate
122 willcause the Q and Q terminals of flip-flops 102 and 104 to go
high and low respectively but will not cause any change in the
signal level appearing at the Q terminals of flip-flops 106 and
108. The second or next flip-flop clocking pulse will cause the Q
terminals of flip-flops 104 and 106 to go high and low respectively
but will not cause any change in the signal level appearing at the
Q and Q terminals of flip-flops 102 and 108 respectively. On the
third flip-flop clocking pulse, the Q terminals of flip-flops 106
and 108 will become high and low respectively while no change in
signal level will occur at the Q and Q terminals of flip-flops 102
and 104. The fourth flip-flop clocking pulse will cause the signals
appearing at the Q and Q terminals of flip-flops 102 and 108 to go
low and high respectively, while the signal levels at the Q
terminal of flip-flops 104 and 106 remain unchanged. At this point
the four flip-flops are in the same state as when held clear by the
absence of the enable generator signal appearing on line 126. A
fifth flip-flop clocking pulse will cause the signals appearing at
the Q and Q of flip-flops 102 and 104 to change as on the first
clocking pulse, while leaving the output at the Q terminals of
flip-flops 106 and 108 unchanged. At the end of this fifth clocking
pulse, the four flip-flops have the same states as after the first
clock pulse. The next three flip-flop clocking pulses will cause
the flip-flops to assume successively the same states produced by
the second, third and fourth clocking pulses. This mode will
continue to be repeated so long as clocking pulses are applied to
the four flip-flops.
As previously noted, the clock signal from gate 122 is applied to
gates 128 to 134 inclusive. The timing arrangement is such that (a)
when the first clock signal arrives at gates 128 to 134, the Q
terminal of flip-flop 102 is high and the Q terminals of flip-flops
104, 106 and 108 are low, with the result that only gate 128
produces an output pulse; (b) when the next clock signal arrives at
gates 128 to 134, the Q terminal of flip-flop 102 and the Q
terminals of flip-flops 106 and 108 are low and the Q terminal of
flip-flop 102 is high so that only gate 130 produces an output
pulse; (c) on the third clock signal, the Q terminal of flip-flop
106 is high and the Q terminal of flip-flop 102 and the Q terminals
of flip-flops 104 and 108 are low, so that only gate 132 produces
an output pulse; (d) on the fourth clock signal, the Q terminal of
flip-flop 102 and the Q terminal of flip-flops 102 and 106 are low
while the Q terminal of flip-flop 108 is high, so that only gate
134 produces an output signal; and (e) on the fifth clock signal
the Q terminal of flip-flop 102 is high and the Q terminals of
flip-flops 104, 106 and 108 are low so that only gate 128 produces
an output signal. The next three clock pulses will cause gates 130,
132 and 134 to pass pulses sequentially as occurred on the second,
third and fourth clock pulses. Essentially flip-flops 102 to 108
inclusive act as a commutator so that pulses are passed
sequentially by gates 128 to 134 inclusive repetitively as long as
these gates are enabled and clock 116 operates. The sequential
outputs from gates 128, 130 132 and 134 identified as .phi..sub.1,
.phi..sub.2, .phi..sub.3 and .phi..sub.4 respectively obviously
will occur at the same repetition rate as the clock pulses.
Resetting of the flip-flops by the absence of an enable generator
signal on line 126 assures that the flip-flops will always be in
the correct state when the clock generator is required to produce
one or more tetrads of .phi..sub.1 - .phi..sub.4 clocking
pulses.
The enable generator signal is provided by another portion of the
circuit shown in FIG. 6. This latter portion of the circuit
comprises four JK flip-flops 136, 138, 140 and 142 whose reset
terminals are all connected to input terminal 143 at which a
negative reset signal is applied when the machine is turned on.
Each J terminal of flip-flops 136 to 142 is connected to a
respective corresponding input terminal 144, 145, 146 and 147 at
which are applied different signals identified as "1 shift," "199
Shift," "200 Shift," and "201 Shift" respectively. The C or
clocking terminals of all four flip-flops are connected by common
line 148 to the output of clock 116. The Q terminals of all of
flip-flops 136, 138, 140 and 142 are connected to separate input
terminals of OR gate 150 whose output is connected by line 124 to
input AND gate 122 of the 4-phase clock generator. The K terminal
of flip-flop 136 is connected by line 152 from the Q terminal of of
the fourth flip-flop 108 of the 4-phase clock generator, and is
also connected to one input terminal of AND gate 154. The latter
has a second input terminal to which is applied, by line 156, a
Terminate Shift signal or pulse derived from counter 190 of the
circuit hereinafter described for counting the number of times the
buffer shifts or is clocked. The output of AND gate 154 is applied
to the K terminals of flip-flops 138, 140 and 142.
Operation of the above described circuit for controlling the clock
generator control signal will now be described. The "1 Shift," "199
Shift," "200 Shift," and "201 Shift" signals are positive pulses
which are respectively and selectively applied to the corresponding
J input of flip-flops 136, 138, 140 and 142 coincidentally with a
clock pulse on line 148. The four flip-flops 136 to 142 are cleared
by the reset signal at terminal 143 and are clocked by the pulses
on line 148. In the cleared condition the Q terminals of the four
flip-flops are all low. Assuming that one of the flip-flops has a
shift signal applied to its J terminal, when a clock pulse is
applied on common line 148 the flip-flop will change states so that
its Q terminal goes high. Because of other logic in the system only
one shift signal can be present at any one time. Thus only one
flip-flop can change state when a clock pulse occurs. For example,
if the "1 Shift" signal is present, the Q terminal of flip-flop 136
will go high and the corresponding Q terminals of the other three
flip-flops will remain low. Assuming for purposes of discussion
that the "199 Shift" signal is applied at terminal 145, OR gate 150
will have one high and three low inputs; accordingly its output
will be a generator enable signal which will cause the clock
generator to produce tetrads of .phi..sub.1 - .phi..sub.4 timing
pulses as above described. The generator enable signal will
continue until coincidence of the terminate shift signal on line
156 and of the input signal on line 152 applied through gate 154
cause the K terminal of flip-flop 138 to go high whereupon the Q
terminal of that flip-flop will go low on the next clock pulse on
line 148. With all four inputs to gate 150 then low, the latter
will now produce a low output, thus terminating the enable
generator pulse on line 126.
Similarly, it will be seen that the application of any of the shift
signals to its corresponding flip-flop will initiate a generator
enable signal at the output of gate 150, and that the 4-phase
generator will continue to run until the generator enable signal
terminates due to coincidence of signals on lines 152 and 156.
FIG. 6 also includes the logic for changing the clocking order of
the buffer memory, which logic comprises JK flip-flop 158 whose J
terminal is connected to the output of OR gate 159 from which is
provided a Change Order signal hereinafter described. The C or
clocking terminal of flip-flop 158 is connected to the output
terminal of gate 134. The reset terminal of flip-flop 158 is
connected to a line 160 on which may be applied a reset signal from
the Q output terminal of flip-flop 142. The Q terminal of flip-flop
158 is connected to one input terminal of an exclusive OR gate 162.
Gate 162 has a second input terminal which is connected to the
output of OR gate 163 which provides an Insert signal derived as
hereinafter described. The output terminal of gate 162 is connected
through inverter 164 to input terminals of two AND gates 165 and
166. The output terminal of gate 162 is also connected to input
terminals of two more AND gates 167 and 168. A second input
terminals of each of gates 165 and 168 are connected to the output
terminal of gate 130, while the second input terminals of each of
gates 166 and 167 are connected to the output terminal of gate 132.
The output terminals of gates 134 and 128 are simply connected
respectively to output line 169 and terminal 170. The output
terminals of gates 165 and 167 are connected to respective input
terminals of OR gate 172 and the output terminals of gates 166 and
168 are connected to different input terminals of OR gate 174. The
output terminals of gates 172 and 174 are connected to output lines
176 and 178 respectively.
Gate 163 has a pair of input terminals respectively connected to
terminal 182 and 187 to which are applied respectively an Overflow
Insert Cycle signal and a Normal Insert Cycle signal.
Gate 159 has a pair of inputs respectively connected to the outputs
of AND gates 180 and 181. AND gate 180 has a pair of inputs
connected to terminals 182 and 183. Terminal 183 is intended to
have applied thereto a Blank Cell Detected at Main Buffer Output
signal. The latter signal typically is derived from gating which is
preferably connected to the output of main register 94 of FIG. 5.
AND gate 181 has a pair of input terminals one of which is
connected to input terminal 184 at which may appear a Blank Cell at
Buffer Input signal from gate 92 shown in FIG. 5. The other input
terminal of AND gate 181 is connected to the output of OR gate 185
which also has two input terminals 186 and 187. Terminal 186 has
applied thereto respectively a Delete Cycle Signal.
Operation of the logic circuit for changing the clocking order of
the buffer memory will now be described. The Change Order signal
applied to the J terminal of flip-flop 158 will occur by operation
of gates 159, 180, 181 and 185 whenever (1) a blank cell is
detected at the output of the second subsidiary storage register 98
of the buffer memory and the machine is ordered to insert a
character into the buffer memory without an overflow, or to delete
a character, or (2) a blank cell is detected at the output of the
main storage register 94 and the machine is ordered to insert with
overflow a character into the buffer. The Insert signal applied to
one of the inputs of exclusive OR gate 162 will occur, by operation
of OR gate 163 whenever the machine is ordered to insert a
character into the buffer memory, with or without overflow.
According to the logical operation of gate 162, the latter will
provide a high output when either input signal is high but not when
both input signals are simultaneously high or simultaneously
low.
Flip-flop 158 is clocked by the .phi..sub.4 output signal from gate
134. If a Change Order Signal is present on the J terminal of
flip-flop 158 when the .phi..sub.4 signal occurs, the Q terminal of
that flip-flop will go high. If a high Insert signal from gate 163
is applied to gate 162, the latter will provide an output signal
only when the Q terminal of flip-flop 158 is low. As noted, a
Change Order signal can occur only during an Insert Cycle or a
Delete cycle in accordance with the buffer memory Insert and Delete
Clocking modes previously described.
If the output of gate 162 is high, it enables AND gates 167 and
168; if it is low, it enables AND gates 165 and 166. Accordingly,
if for example it is .phi..sub.2 time and the output of gate 162 is
high, gate 168 will pass the .phi..sub.2 signal to OR gate 174.
Since at that time both inputs of AND gate 166 are low, the other
input to OR gate 174 will be low, the .phi..sub.2 signal will
appear on line 178. At the same time the output of gates 167 and
165 will also be low because .phi..sub.3 is a low input to gate 167
and the output of inverter 164 is a low input to gate 165.
Accordingly, the output of OR gate 172 will also be low. If now the
output of gate 162 goes low, the .phi..sub.2 signal will appear
instead at the output of OR gate 172 and the other OR gate 174 will
have a logical zero at its output. It is to be noted that lines
170, 178, 176, 169 are connected to terminals identified as
X.sub.1, X.sub.2, X.sub.3, and .phi..sub.4. The signals appearing
at terminals X.sub.1, X.sub.2, and X.sub.3 are the clocking signals
for the buffer memory. Hence the buffer will be clocked in the
X.sub.1 X.sub.3 X.sub.2 mode if the output of gate 162 is low and
in the X.sub.1 X.sub.2 X.sub.3 mode if the output of gate 162 is
high. That is, the .phi..sub.2 and .phi..sub.3 signals appear at
the X.sub.3 and X.sub.2 terminals only when both the Insert signals
and Change Order signal are either present together or absent
together, and the .phi..sub.2 and .phi..sub.3 signals appear
respectively at the X.sub.2 and X.sub.3 terminals only when one of
the Insert and Change Order signals is present and the other
absent. In essence, the gating scheme of gates 162, 165, 166, 167,
168, 172 and 174 together with inverter 164 is the equivalent of a
double-pole, double-throw switch automatically actuated by a set of
circumstances.
The circuit of FIG. 6 includes means for counting the number of
times the buffer is clocked, and to this end the circuit of FIG. 6
includes a counter 190 for generating an output signal after
counting 200 pulses, and input logic for adding or deleting a pulse
as will be hereinafter explained. The logic here includes OR gate
192 having a pair of input terminals connected to the Q terminals
of flip-flops 138 and 140. The output of gate 192 is connected to
an input of OR gate 194 and also to an input of OR gate 195. The Q
terminal of flip-flop 142 is connected to the other input of OR
gate 194. A three-input AND gate 196 has two of its inputs
connected respectively to the output of gate 128 and the Q terminal
of flip-flop 138. Another J-K flip-flop 198 is provided, having its
J and Q terminals tied together and connected to the third input of
AND gate 196. Flip-flop 198 has its clock terminal connected to the
output of gate 132 so as to be clocked by the .phi..sub.3 pulses
from the latter. The clear terminal of flip-flop 198 is connected
to the output of gate 194.
The Q terminal of flip-flop 198 and the Q terminal of flip-flop 142
are connected as inputs to AND gate 199. The output of gate 199 is
connected as an input to gate 195. The output of gate 195 and the
output of gate 130 are connected as inputs to AND gate 200. The
outputs of AND gate 200 and of AND gate 196 are connected as inputs
to OR gate 202 and the output of the latter is connected as the
count input to counter 190. Counter 190 is preferably any of a
large number of digital counters well known in the art having a
clear terminal at which application of a low signal will reset or
clear the counter to its initial state, and, in a preferred
embodiment will provide an output signal when it has counted two
hundred input pulses. The clear terminal of counter 190 is
connected also to the output of gate 194. The output terminal of
counter 190 is connected as the terminate shift line input to gate
154 and to terminate shift terminal 193.
In operation, it will be seen that when the signal from gate 194
goes high, it serves to enable both flip-flop 198 and counter 190
so that both can be clocked. This will occur when according to
gates 192 and 194 any of the 199 shift, 200 shift or 201 shift
signals are applied to the J terminals of flip-flops 138, 140 and
142 respectively. Counter 190 will count .phi..sub.2 pulses passed
by gates 200 and 202 when gate 200 is enabled. Gate 200 is enabled
immediately if the Q terminal of either of flip-flops 138 and 140
goes high. However, gate 196 when enabled provides an alternative
pulse source, being connected to gate 128 which provides
.phi..sub.1 pulses. This enablement only occurs when flip-flop 198
is off, i.e., its Q terminal is high and when the 199 shift signal
has turned flip-flop 138 on, i.e., its Q terminal is high. But, if
the Q terminal of flip-flop 198 is high because it is connected to
the J terminal, when a .phi..sub.3 clock pulse clocks flip-flop
198, the latter turns on and its Q terminal goes low. This
operation thus provides a single pulse to counter 190 prior to any
counting of .phi..sub.2 pulses by the latter. Because gate 200 is
enabled by the output of flip-flop 138 counter 190 will then count
.phi..sub.2 pulses. When the counter has counted a single
.phi..sub.1 pulse and 199 .phi..sub.2 pulses, it yields a terminate
shift signal on line 156. Effectively then it has counted only 199
shifts in the buffer.
When the Q terminal of flip-flop 142 goes high due to the 201 shift
signal, flip-flop 158, flip-flop 198 and counter 190 are eabnled
and the first .phi..sub.2 pulse is not counted by counter 190
because gate 200 is disabled by the absence of a high signal at the
output of gate 195. However the first .phi..sub.3 pulse clocks
flip-flop 198 so that its Q terminal goes high, gate 199 is enabled
and gate 195 passes the signal from gate 195 to enable gate 200.
Counter 190 then counts the next 200 .phi..sub.2 pulses and yields
the output signal on line 156. Effectively however, because it was
forced to skip counting an initial .phi..sub.2 pulse, the counter
190 has counted through 201 shifts of the buffer.
Obviously when flip-flop 140 is triggered, counter 190 will simply
count up to the full 200 shifts and then will provide a Terminate
Shift signal on line 156 to gate 154.
Lastly, the remainder of FIG. 6 includes logic for generating the
C.sub.3 signal which is to be applied to line 100 (FIG. 5) and also
for generating the Enable Keyboard to Storage signal which is to be
applied to line 82 (FIG. 4). To this end, the circuit of FIG. 6
includes NOR gate 204 having one input connected to the output from
OR gate 163, and another input connected to terminal 186. The
output of NOR gate 204 is connected as one input to OR gate 204.
Another input to OR gate 205 is connected to the output of gate
128.
Yet another OR gate 206 is provided, having one input connected to
the 6 Q output terminal of flip-flop 142 and another input
connected to terminal 207. The output of OR gate 206 is connected
to the one input of AND gate 208. A second input to AND gate 208 is
connected to the Q terminal of flip-flop 198. The output of AND
gate 208 is shown connected to line 82, inasmuch as the signal from
gate 208 is the desired Enable Keyboard to Storage signal. The
output of gate 205 and line 82 are also connected as respective
inputs to AND gate 209. The output of the latter is shown as line
100 along which the requisite C.sub.3 signal can be provided.
Gates 209 and 205 define the length of the C.sub.3 pulse. As
indicated, a relatively long C.sub.3 pulse is used when overwriting
a character in the buffer and a relatively short C.sub.3 pulse is
employed when inserting or deleting a character. If the output of
gate 204 is low, the only high input signal to gate 205 will be the
.phi..sub.1 pulse from gate 128 so the output signal from gate 205
will be quite short. The output of gate 204 will be low if there is
an insert or delete signal present at any of terminals 182, 186, or
187. The output from gate 205 will then enable gate 205 only for
the duration of the .phi..sub.1 pulse.
On the other hand, if the system is not in a Delete or Insert mode,
the output from gate 205 will stay high and the duration of any
high output from gate 209 will depend on the output from gate 208.
Gate 202 will provide a high output when the buffer is undergoing a
201 shift (i.e., the Q output from flip-flop 142 is high) or a Dead
Time One Shift signal, derived as hereinafter noted, is present at
terminal 207. Gate 603 will be enabled by the "off" condition of
flip-flop 198 wherein the Q output of the latter is high. It will
be remembered that the Q output goes low after the .phi..sub.3
pulse from gate 132 clocks flip-flop 198, so that gate 208 is
enabled for the time from the beginning of a .phi..sub.1 pulse (or
when flip-flop 198 is enabled) to the end of the following
.phi..sub.3 pulse. This "long" output pulse from gate 208 is
applied on line 82 to provide the Enable Keyboard to Storage Signal
described in conjunction with FIG. 4, and is also applied to gate
209.
When the output pulse from gate 205 is the "short" pulse, the
output from gate 209 will be similarly "short." When there are no
insert or delete commands to gate 204, the output from gate 205
will be "long," hence the C.sub.3 output pulse from gate 209 will
then also be "long."
The use of long and short C.sub.3 pulses in cycling the buffer can
be readily seen with reference to the timing diagrams of FIGS. 6A,
6B, 6C and 6D. As shown on a common time axis in these Figures,
there are several idealized pulse trains identified as CLOCK,
X.sub.1, X.sub.2, X.sub.3, and C.sub.3. The CLOCK, X.sub.1, X.sub.2
and X.sub.3 trains respectively represent the output from clock 116
(FIG. 6) and the inputs to lines 97, 95 and 99 respectively (FIG.
5). The C.sub.3 train represents the output of gate 209 in FIG.
6.
In interpreting the timing diagrams, one can for the sake of
simplicity, assume a six-character main register and two
single-character subsidiary registers. Hence, shown below the pulse
trains on the same time scale are the states of the input and
output cells of the main register and of the two subsidiary
buffers, with appropriate legends. When it is desired to type data
into the buffer in the Draft mode, as noted a 201 shift cycle is
used. The clocking is in the normal X.sub.1 X.sub.3 X.sub.2
sequence with the second subsidiary storage being held clear during
the first of the 201 shifts. As noted also, the 201 shift
condition, in the absence of any insert or delete command, results
in a long C.sub.3 pulse.
To overwrite when typing in, as shown in FIG. 6A, there are
initially data, denoted A, at the main buffer output. On the
trailing edge of first .phi..sub.1 pulse on the X.sub.1 line, the
data Z are transferred to the first subsidiary buffer as shown.
However, on the trailing edge of the .phi..sub.2 pulse which is
applied to clock the second subsidiary buffer, data Z are not
transferred from the first subsidiary buffer to the second
subsidiary buffer because the C.sub.3 pulse holds the second
subsidiary buffer clear for the entire duration of a single cycle
of successive .phi..sub.1, .phi..sub.2 and .phi..sub.3 pulses.
Thus, at the end of the first .phi..sub.3 pulse, the main register
shifts and the buffer input accepts, for example, new data Y from
the keyboard instead of data from the second subsidiary buffer. At
that time too, the remainder of the data in the main buffer are
shifted toward the buffer output by one cell, bringing for example
the data A to the buffer output. On the next successive cycle, the
.phi..sub.1 pulse shifts the data A then from the buffer output to
the first subsidiary register and the .phi..sub.2 pulse shifts the
data A from the first to the second subsidiary register. When, on
the following .phi..sub.3 pulse, the main register is clocked, the
data A are shifted from the second subsidiary register to the
buffer input because the C.sub.3 pulse now no longer holds the
second subsidiary storage clear. By this technique, the data Y has
been used to overwrite or replace data Z.
A similar type of diagram in FIG. 6B shows the use of a series of
shift cycles to insert characters into the main buffer. Here, as
noted, the C.sub.3 pulse has the same duration and phase as the
.phi..sub.1 pulse. To effect insertion, the clocking order is
initially X.sub.1 X.sub.2 X.sub.3 at the end of the second shift
cycle. One can assume initially data denoted Z at the main buffer
output and blank cells in both subsidiary storages. On the trailing
edge of first .phi..sub.1 pulse of the first cycle, those data Z
are shifted to the first subsidiary buffer. Simultaneously, the
short C.sub.3 pulse, in phase with the first .phi..sub.1, makes
certain that the second subsidiary buffer is clear so that it
contains a blank cell. On the ensuing .phi..sub.2 pulse which is
applied according to the special clocking sequence to clock the
main register, the latter shifts and the data Y, presented for
insertion by the keyboard, are shifted into the first cell of the
main buffer. When the .phi..sub.3 pulse occurs, it now shifts the
data Z from the first to the second subsidiary buffer. For
convenience here, it can be assumed that at this point the first of
a number of successive blank cells has been shifted on the
.phi..sub.2 pulse to the main buffer output.
On the next cycle, the .phi..sub.1 pulse causes the blank cell at
the buffer output to be shifted into the first subsidiary storage.
The .phi..sub.2 pulse causes the main register to shift, bringing
the output data Z from the second subsidiary buffer to the main
register input cell. On the .phi..sub.3 pulse, the blank cell in
the first subsidiary buffer is shifted to the second subsidiary
buffer. At this point, a blank cell being detected at .phi..sub.4
time (not shown as a separate train) at the output of the second
subsidiary storage, the clocking order reverts to the normal
X.sub.1 X.sub.3 X.sub.2 sequence. Hence the next .phi..sub.1 pulse
clocks the first subsidiary storage and transfer thereto the blank
cell from the main buffer output. The next .phi..sub.2 pulse clocks
the second subsidiary buffer, transferring thereto the blank cell
from the first subsidiary storage. The .phi..sub.3 pulse then
clocks the main register transferring the blank cell from the
second store to the input cell of the main register. It can readily
be seen that the operation allows the memory to accept data and
insert it into a sequence of data without causing the loss of
stored data, and without otherwise changing the order of the stored
data. Simply, the insertion shifts all of the ensuing information
until the last of the stored data are shifted into a blank
cell.
Examination of FIG. 6C will show the sequence of events for
insertion of a character with overflow. Here, the operation is
quite similar to that described in conjunction with FIG. 6B except
that there are no blank cells left into which the last of the
stored data can be shifted. In such case only one, unavailable
blank cell remains in the combined storage of the registers. As
previously noted, the change in clocking sequence occurs herewith
detection of the blank cell at .phi..sub.4 time at the output of
the main register. The operation will result in insertion of a
character with attendant dropping of the last character (identified
as data A in FIG. 6C) in the sequence in the full register.
To delete, one employs the normal clocking sequence X.sub.1 X.sub.3
X.sub.2 and changes to the special sequence on detection at
.phi..sub.4 time of a blank cell at the output of the second
subsidiary buffer as previously noted. This is shown graphically in
FIG. 6D. Here the shift sequence results in the data (Z) in the
last cell in the main buffer, being dropped or deleted from the
sequence. As shown, a blank cell is inserted and at the end of a
complete shift cycle it will be seen that the blank cell has taken
the place of data Z.
A Carrier Return signal provided from the baseplate 24 will
ordinarily cause the buffer memory to empty into magnetic storage
through repetitive one-shift cycles as heretofore noted. The
emptying process for a completely full 200 character buffer memory
requires about the amount of time needed for the print head 16 on
the printer 20 to return from its extreme right margin position to
its left extreme margin position. However, if the data stored in
the buffer is only a portion of a line, the print head 16 would be
expected to return to its left margin position well before the
entire buffer memory could be emptied of meaningful and blank or
empty characters. Hence, the invention includes means for making
the buffer memory available for input thereto of new data
immediately after the meaningful data has been transferred out.
Thus, as shown in FIG. 7 the invention includes means for
transferring the contents of the buffer memory into magnetic
storage and for releasing the buffer memory for further entry
therein immediately following transfer of the meaningful contents
into magnetic storage. The foregoing means preferably comprises
multiplexer 210 (shown earlier at block 54 in FIG. 3) having a
plurality of parallel inputs respectively connected to the eight
output lines of shift register 94 (FIG. 5). Multiplexer 210 is an
eight-input channel digital multiplexer well known in the art for
coverting eight parallel input bits to a serial chain on a single
output channel.
Lastly, the remainder of FIG. 6 includes logic for generating the
C.sub.3 signal which is to be applied to line 100 (FIG. 5) and also
for generating the Enable Keyboard to Storage signal which is to be
applied to line 82 (FIG. 4). To this end, the circuit of FIG. 6
includes NOR gate 204 having one input connected to the output from
OR gate 163, and another input connected to terminal 186. The
output of NOR gate 204 is connected as one input to OR gate 205.
Another input to OR gate 205 is connected to the output of gate
128.
Yet another OR gate 206 is provided, having one input connected to
the Q output terminal of flip-flop 142 and another input connected
to terminal 207. The output of OR gate 206 is connected to the one
input of AND gate 208. A second input to AND gate 208 is connected
to the Q terminal of flip-flop 198. The output of AND gate 208 is
shown connected to line 82, inasmuch as the signal from gate 208 is
the desired Enable Keyboard to Storage signal. The output of gate
205 and line 82 are also connected as respective inputs to AND gate
209. The output of the latter is shown as line 100 along which the
requisite C.sub.3 signal can be provided.
Gates 209 and 205 define the length of the C.sub.3 pulse. As
indicated, a relatively long C.sub.3 pulse is used when overwriting
a character in the buffer and a relatively short C.sub.3 pulse is
employed when inserting or deleting a character. If the output of
gate 204 is low, the only high input signal to gate 205 will be the
.phi..sub.1 pulse from gate 128 so the output signal from gate 205
will be quite short. The output of gate 204 will be low if there is
an insert or delete signal present at any of terminals 182, 186 or
187. The output from gate 205 will then enable gate 209 only for
the duration of the .phi..sub.1 pulse.
On the other hand, if the system is not in a Delete or Insert Mode,
the output from gate 205 will stay high and the duration of any
high output from gate 209 will depend on the output from gate 208.
Gate 206 will provide a high output where the buffer register is
undergoing a 201 shift (i.e., the Q output from flip-flop 142 is
high) or where an appropriate signal is present at terminal 207.
Gate 208 will be enabled by the "off" condition of flip-flop 198
wherein the Q output of the latter is high. It will be remembered
that the Q output goes low after the .phi..sub.3 pulse from gate
132 clocks flip-flop 198, so that gate 208 is enabled for the time
from the beginning of a .phi..sub.1 pulse (or when flip-flop 198 is
enabled) to the end of the following .phi..sub.3 pulse. This "long"
output pulse from gate 208 is applied on line 82 to provide the
Enable Keyboard to Storage Signal described in conjunction with
FIG. 4, and is also applied to gate 209.
When the output pulse from gate 205 is the "short" pulse, the
output from gate 209 will be similarly "short." When there are no
insert or delete commands to gate 204, the output from gate 205
will be "long," hence the C.sub.3 output pulse from gate 209 will
then also be "long."
A decade counter 212 is provided for counting pulses in modulo ten
and having an input terminal connected to a source of timing pulses
(such as divider 264 which in turn has an input from line 211 to
clock 116 (FIG. 6). Counter 212 is of the type having an inverting
disable terminal 213 so that an appropriate signal at terminal 213
will hold the counter to an initial state, usually zero. Counter
212 typically is an arrangement of interconnected bistable stages
such as flip-flops having output lines 214, 215, 216 and 217, as
from the Q terminals of the flip-flops, for providing signals
corresponding to counts of 1, 2, 4 and 8. Only the first three
output lines 214, 215 and 216 from counter 212 need be connected to
multiplexer 210 in known manner for controlling the sequencing of
the signals on the input lines from register 94 into a serial
signal at the multiplexer output. In order, for reasons adduced
hereinafter, to determine each time a count of 8 is reached by
counter 212, a "state 8" detector is provided and comprises AND
gate 218 having one input connected to the count of 8 line 217 and
another input connected through inverter 219 to the count of 1 line
214.
Means, such as AND gate 220, is provided for determining if a blank
cell is present at the output of the buffer memory or register 94.
Gate 220 as shown, has eight inverting inputs respectively
connected to the eight output lines from register 94.
It is preferred to phase encode the output of the multiplexer and
to this end there is provided a control flip-flop 222 which is
preferably a J-K type device having its clock input connected by
line 223 to the output of gate 134 (FIG. 6), its J input connected
to the output of blank cell detector or AND gate 220, and its K
input grounded. The Q output of flip-flop 222 is connected as one
input to AND gate 224. The other input of AND gate 224 is connected
to the output of multiplexer 210. The outputs of AND gate 224 and
clock line 221 from divider 264 are connected as inputs to
exclusive OR gate 226.
The output of exclusive OR gate 226 is connected as one input to
AND gate 228. Another input to AND gate 228 is connected through
inverter 229 to line 217 from counter 212. Counter output lines
214, 217 and clock line 221 are connected as inputs to AND gate
232. The outputs of the latter and from gate 228 are connected as
respective inputs to OR gate 234. The output from the latter is
connected through amplifier 236 to magnetic read/write head
238.
The system shown in FIG. 7 as thus described, functions as follows:
A Carrier Return signal starts a series of one shifts in the buffer
memory. As the bits representing each character are shifted onto
the eight output lines of the memory multiplexer 210 converts the
eight parallel bits to eight serial bits in sequence and with a
timing determined by the output from decade counter 212. The latter
starts counting clock pulses on line 221 from a count of nine as
soon as an enable write signal at terminal 213 enables the
counter.
From the zero to seventh count by decade counter 212, the eight
input lines are sequenced to provide a serial input to gate 224.
Because in the absence of a high signal at the J input to flip-flop
222, the Q terminal of the latter is high, gate 224 is enabled to
pass the serial bits of each character thus multiplexed. Exclusive
OR gate 226, clocked by the signals on line 221 converts the output
of multiplexer 210 into Ferranti coded signals wherein the value of
a bit is indicated by its transition direction as explained
hereinafter. When counter 212 provides the eighth and ninth counts
by high signals on line 217 and line 214, no corresponding bits are
provided at that time by the encoding logic. Instead, on the eighth
count, the high signal on line 217, being inverted by inverter 229,
disables gate 228. On the ninth count, the high signals on lines
214 and 217 together with the clock pulse on line 211 enable gate
232 which provides a regular pulse or bit to gate 234. Thus the
eighth and ninth counts by decade counter 212 yield respectively no
signal at all and one regular clock pulse at the input to amplifier
236. The eighth count space or lack of signal (hereinafter referred
to as an inter-character gap or ICG) is intended to provide spacing
between serially recorded sets of character bits, whilst the ninth
count pulse is intended to indicate the beginning of a character
and is hereinafter referred to as the start bit. The output of
amplifier 236 is applied to read/write head 238 so that as a
magnetic storage medium such as a tape 18 in cassette 240 is
transported past head 238 as by tape-transport motor 242, the
serial phase-encoded characters, the ICG and the start bit are all
recorded on the tape 18.
The output from gate 218 is applied as hereinafter described to
cause the buffer memory to execute another one shift. The foregoing
will continue until a blank cell (which as noted in Table III is
characterized as a sequence of eight zero bits) appears at the
output of register 94. The blank cell will be detected by AND gate
220 which causes the J terminal of flip-flop 222 to go high and the
Q terminal to go low. Thus, as soon as the meaningful data in
register 94 has been transferred, the output of flip-flop 222
disables gate 224, effectively freeing the register, i.e., making
it available for further entry of data from encoder gates 76.
The output of gate 218 is also preferably connected as through
another input to OR gate 202, to counter 190 (FIG. 6) so that each
shift performed by register 94 is counted by counter 190. If
register 94 is initially full, at the 200th count of 8, as recorded
by counter 190, the latter will provide a signal on line 156 which
stops the shifting of register 94.
As noted below, the same signal, directed along control line 244,
serves as an Enable Write signal to stop motor 242. Line 244 is
also connected to terminal 213 of counter 212 and to the clear
terminal of flip-flop 222 to stop or disable counter 212 and to
clear flip-flop 222 so that gate 224 is no longer disabled.
In the event, however, that for example register 94 only had ten
characters recorded therein, upon depression of the Carrier Return
key by the operator, the print head 16 would quickly return to its
left hand margin position. By the time the print head 16 so
returned, gate 220 would have detected the blank cell on the
eleventh shift and inasmuch as register 94 would then have been
cleared, gate 224 would have been disabled. However, counter 190
would only have recorded eleven shifts, hence decade counter would
continue to operate and clock pulses along line 221 would be phase
encoded by gate 226 as simply all zero bits. Of course, every
eighth and ninth count would be recorded as proper ICG and start
bits by operation of gates 232, 228 and 234. In this manner, null
characters or sequences of eight bits will continue to be generated
and recorded, until counter 190 reaches the count of two hundred,
whereupon counter 212 and motor 242 will become disabled and the
zero character generation and recording ceases.
The recording or data storage system 58 exemplified by motor 242,
read/write head 238 and cassette 240, is preferably a dual capstan,
bidirectional machine with a read and write tape speed typically of
10 inches per second. Such recording system, well known in the art,
is capable of driving a tape 18 in a cassette 240 at its writing
and reading speed and also at some higher rate of speed for search
purposes. Read/write head 238 is preferably a known two-track
digital type as heretofore noted.
The data are recorded on tape 18 in blocks 19 of 200 characters
each block corresponding then to a complete buffer load, each
character, as noted before, having eight bits corresponding to the
bits of a character stored in the main register 94, an additional
start bit and an ICG. These bits are Ferranti or phase-encoded
which is a known system of encoding wherein the first half of each
bit is recorded as the true sense of the bit (i.e., either a high
or low level) and the second half is recorded as the bit
complement. Thus, as noted, the direction of the transition from
first to second half identifies the bit.
An example of a character which might appear at the output of
register 94 is shown in FIG. 8A wherein the sequence of signals as
shown is S, R.sub.1, R.sub.2, R.sub.2 A, R.sub.5, T.sub.1, T.sub.2
and P. The foregoing signals then form a character with the
sequence of bits 11010010. It is recognized that this character has
even parity but is merely used in this description for the sake of
simplicity. A sequence of clock pulses, shown in FIG. 8B,
synchronize the operation of multiplexer 210 and gate 226 to
produce the phase encoded signals shown in FIG. 8C. It should be
noted in FIG. 8C that in accordance with the logical exclusive OR
function of gate 226, the signal is high if and only if either the
signal in FIG. 8A is high or the signal in FIG. 8B is high but not
when both the signals in FIG. 8A and FIG. 8B are high. It will also
be recognized as noted that the first transition of the signal in
FIG. 8C constitutes a "start" bit or transition and, corresponding
to the last "bit" of the signal is a low level or ICG.
As shown in FIG. 3 and FIG. 7 the system also includes read data
circuits 60 for reading the phase-encoded data from tape 18 and for
converting or demultiplexing in demultiplexer 62 the decoded data
back into eight parallel bit characters suitable for insertion into
the buffer memory for ultimate writing out by the printer 20 or for
editing or revision. The remainder of the circuit of FIG. 7 thus
includes read amplifier 246 connected to the output from read/write
head 238. The output of amplifier 246 is connected to means such as
rectifier/shaper 248 for half-wave rectifying the signal from
amplifier 246 to provide an output train of, for example, positive
rectangular pulses representing only the positive signal in the
output of amplifier 246. Similarly the output of amplifier 246 is
connected through inverting amplifier 249 to means, such as
rectifier/shaper 250 for half-wave rectifying the signal from
amplifier 246 to provide another output train, of, for example,
positive rectangular pulses which however represent only the
negative signals in the output of amplifier 246. The output of
rectifier/shaper 248 is connected as one input to AND gate 252, as
one input also to OR gate 254 and is connected to the set (S)
terminal of RS type flip-flop called Control flip-flop 256.
Similarly the output of rectifier/shaper 250 is connected as one
input to AND gate 258 and also as another input to OR gate 254. The
outputs of gates 252 and 258 respectively are connected to the set
(S) and reset (R) inputs of another RS type flip-flop called data
flip-flop 260. The Q output terminal of data flip-flop 260 is
connected to the data input terminal of demultiplexer 62 which is
shown preferably as an eight-bit shift register demultiplexer
262.
Means are provided for clocking the decoding of the signals from
head 248, and to this end clock line 211 is connected to digital
scaler or divider 264 which has an output pulse train which is a
sub-multiple of the input clock frequency. An output of digital
divider 264 (at a frequency four times greater than is provided to
counter 212) is connected to counter 265, which is typically a
simple binary counter formed of three cascaded flip-flop stages.
The three outputs from counter 265, typically the Q terminals of
the respective flip-flop stages, are connected as inputs to a
binary-to-octal converter 266. The latter is a known system of
gates which simply converts the binary output of counter 264 (which
runs from zero to 7) to individual signals appearing in eight
output lines each representing respectively the zero to seventh
count or state of counter 265. Thus, for example, the first output
line from converter 256 will be high if and only if the counter has
counted a first input pulse and has not counted the next pulse. The
zero, third and fourth state output lines from converter 266 are
all connected as inputs to OR gate 267. The output of the latter in
turn is connected to input terminals of AND gates 252 and 258. The
second state or count output line of converter 266 is connected to
the clocking input terminal of shift register 262. The fifth state
or count line from converter 266 is connected to output line 268
and also as one input to AND gate 269. Clock line 211 is also
connected as input to AND gate 269. The output of AND gate 269 is
connected to the reset (R) terminal of control flip-flop 256.
The output of OR gate 254 is connected to the input of a data block
monostable multivibrator 270, the enable input terminal of
multivibrator 270 being connected to the output of OR gate 267. The
output of monostable multivibrator 270 is connected through
inverter 271 as one input terminal to AND gate 272. The Q terminal
of flip-flop 256 is connected as the other input to AND gate 272.
The output of AND gate 272 is connected to the clear input terminal
of counter 265 and to an input of OR gate 273. Another input to
gate 273 is connected to line 244. The output of gate 273 is
connected to the clear input terminal of divider 264. Lastly, there
is provided an Enable Read Data line 274 over which an enabling
signal can be propagated to initiate reading and phase decoding a
record. Line 274 is connected to inverting Clear terminals of
flip-flop 256 and demultiplexer 262.
In operation of the phase decoding portion of FIG. 7, reference
should be had also to the timing diagram of FIG. 8. When it is
desired to read data which has been stored in the tape 18 in
cassette 240, an Enable Read signal on line 274 starts motor 242 so
that the tape in cassette 240 is moved past read/write head 238.
This produces a bipolar output shown typically at FIG. 8D, where
each pulse or peak represents the location and sense of a
transition in the phase-encoded signal stored on tape and shown in
FIG. 8C.
The read-write head output is amplified in amplifier 246 and is
rectified and shaped by rectifier/shaper 248 to produce a train,
typically of positive, shaped output pulses, as shown in FIG. 8E.
By inversion of the output of read/write head 238 in inverter 249
and by operation of rectifier/shaper 250, a similar train of
positive, shaped pulses, such as are shown in FIG. 8F, is produced
representing however only the negative peaks of the original output
train of FIG. 8D. It will be apparent then that the two trains of
pulses applied as inputs respectively to gates 252 and 258
represent respectively all of the positive-going transitions in the
original phase encoded signal of FIG. 8C and all of the negative
going transitions of FIG. 8C, and that some of these transitions
are "midbit" while some are "interbit." The phase decoder system,
designated generally as 251 in FIGS. 7 and 11, is intended to
reconstruct the original sequence of bits (as shown in FIG. 8A)
from the information provided by the midbit transitions only. Thus
it is intended to reject the signals corresponding to the interbit
transitions and this is accomplished by establishing a gating
signal or time "window" after each detected midbit transition and
during an interval when the next midbit transition can be expected
to occur. This window, shown as the pulse train of FIG. 8G is
produced as the output signal from gate 267 which is applied as an
enabling or window signal to gates 252 and 258 and monostable
multivibrator 270.
Divider 264 is arranged so that counter 265 counts four pulses
during each bit time of the original signal of FIG. 8A. Thus, when
the counter sequences to count the first pulse, the count zero
output line from converter 266 goes down and the first count output
line, which is not used here, goes high. Thus, gate 267 has no
output and there is no enabling window present at AND gates 252 and
258. Any pulse appearing during that time in the inputs of AND
gates 252 and 258 from the shapers will be discarded. This is also
true when the counter sequences to the next or second count.
However, the leading edge of the pulse appearing on the second
count line from converter 266 is used to clock shift register 262
and shifts the data in the latter along one bit. When the third
pulse from divider 264 is counted by counter 265 the third count
line from converter 266 brings the output of gate 267 high and
enables gates 252 and 258. As will be seen, the window provided by
gate 267 continues high during the fourth count and then goes low
at the beginning of the fifth count.
Although converter 266 is an octal converter, only five of the
eight output lines are used. It should be noted that all pulses in
the outputs of both rectifier/shapers 248 and 250 are applied as
inputs to gate 254, and that monostable multivibrator 270 is
enabled by each window because the output of gate 267 is connected
to the enable input of the multivibrator. Thus, if a pulse appears
at either input to gate 254 at any other time than during a window,
that pulse will neither trigger multivibrator 270 nor be passed by
gates 252 or 258. On the other hand, when a pulse does appear
during the third and fourth count in counter 265, that input pulse
to gate 254 will also be passed by either gate 252 or 258, and
because multivibrator 270 is enabled during that time, that pulse
will also trigger the multivibrator. The output of the latter, then
serves to disable gate 272 so that counter 265 is reset and held in
its reset state until the pulse from multivibrator 270 disappears,
whereupon the counter resumes counting. Thus, as soon as a
transition from gate 254 appears during the third or fourth count,
counter 265 is reset and the zero count line then goes up and the
window signal in the output of gate 267 stays up. In this manner
all of the interbit transitions are effectively rejected because
they cannot pass AND gates 252 and 258 and the counter is reset
after each detection of a midbit to thereby provide another window
signal. For each of the eight data bits in the original signal
there will be a corresponding mid pulse transition which will
appear either at the input of gate 252 or at the input of gate 258.
All of the midbit transitions appearing at the input of gate 252,
as shown in FIG. 8J of course are applied to the set terminal of
flip-flop 260 and all of the midbit transitions pulses appearing at
the input of gate 258, as shown in FIG. 8H will similarly be
applied to the reset terminal of flip-flop 260. Thus the output of
flip-flop 260 at its Q terminal will be a rectangular wave form
which has positive-going transitions corresponding to the negative
polarity midbit signals in the read/write head output, and will
have negative-going transitions corresponding to the polarity
midbit transitions in the read/write head output. This provides a
wave form shown in FIG. 8K which is a reconstruction of the
original wave form shown in FIG. 8A, phase-displaced ideally by one
half of a bit.
If during the window time no midbit transition is detected, it is
apparent that an intercharacter gap (ICG) instead has been found.
At that point multivibrator 270 is enabled, but there will be no
output frm the latter to reset counter 265 back to zero because
gate 254 has provided no triggering pulse. Instead, counter 265
will count a fifth count and consequently a signal will appear on
the fifth count line of converter 266. This latter signal,
indicative of the detection of an ICG, enables gate 269 so that the
next clock pulse can be applied to the reset terminal of control
flip-flop 256. The Q terminal of the latter then goes low, the
output of gate 272 goes low and counter 265 is thus reset and held
in its zero count state. Also, when an ICG appears, the signal on
line 268 is also applied to terminal 144 (FIG. 6) to actuate
flip-flop 136 and sequence the main register 94 by a single shift,
transferring the output signals at the eight outputs of
demultiplexer 262 to the main register 94.
Because the counter is then at zero count state, the zero count
line from converter 266 is high and the output of gate 267 is high
and thus enables gates 252 and 258. The midbit transition then seen
by the gates is the start transition corresponding to the
positive-going transition in the original clock pulse used in the
phase-encoding of the next character of the original signal. The
pulse corresponding to that start transition is applied to the S
terminal of flip-flop 260 through gate 252 so that the Q terminal
of the latter goes low if it is not already low. Also, the output
of gate 267, being high, sets control flip-flop 256 so that the
latter provides a high input signal to gate 272. This output of
gate 267 also triggers multivibrator 270 which thus keeps gate 272
disabled despite the setting of flip-flop 256, but gate 272 is
disabled only until the signal from multivibrator 270 subsides. At
that point gate 272 enables counter 265 which starts to count from
zero again, so that on the first count, gate 267 is disabled and
the sequence described above reoccurs.
It is apparent from the nature of phase-encoding and the details of
the read logic used that data can be decoded reliably despite
considerable timing errors such as might be due to tape speed
variation and the like.
The decoded signals, appearing at respective lines on the output of
demultiplexer 262 are then the respective R1, R2, R2A, R5, T1, T2,
S and P signals. These output lines from demultiplexer 262 are
connected to the respective terminals identified as Inputs From
Read Data Circuits shown in FIG. 5 and thereby can be introduced
back into the main memory register 94.
All 8 lines at the output of the main memory register are also
connected as inputs to print control logic 68 as noted in FIG. 3.
As shown particularly in FIG. 9, the R1, R2, R2A, R5, T1, and T2
lines from register 94 are connected to respective input terminals
of a like plurality of enable gates 280. All of the output lines
from register 94 are also connected to respective input terminals
of parity checking circuit 282.
In order to decode the characters which represent operator
functions, there is provided operator decoding circuit or decoder
284 having six input terminals respectively connected to the R1,
R2, R2A, R5, T1, and T2 outputs from register 94. The decoder, well
known in the art, is merely a group of gates connected so as to
decode the operator function signals shown in Table II and provide
an output signal on a corresponding operator line when the
requisite input operator signal has been detected or decoded. Thus,
decoder 284 has output lines respectively identified as SP (Space),
CR (Carrier Return), BSP (Back Space), CI (Carrier Index), TAB,
TABS (Tab Set) and TABCL (Tab Clear). These latter output lines are
connected as inputs to a plurality of enable gates 286. Decoder 284
also includes gating which will provide an output on line 287
whenever the encoder determines it has decoded an operator code,
i.e., whenever an output signal appears on any other line from
decoder 284. Typically a simple OR gate will serve this function.
If the signal at the input to decoder 284 is not an operator
function signal but instead is an information character signal then
decoder 284 provides an output signal on line 288. In addition
decoder 284 includes gating for detecting the presence of a hyphen
code (Table I) at the output of register 94 and for providing
responsively thereto an output signal on line H to terminal
289.
It is desirable to inhibit transfer of information from the print
control logic to the printer when the latter is performing a
function or is otherwise busy. To this end, there is provided
Print-Busy OR gate 290 having a plurality of inputs thereto. One of
the inputs is a Print Mode signal simply derived as the inverse of
a signal generated by depression of Print Buttons 33,34,35 or 36
indicating that the device is not in the Print Mode and that the
printer 20 is therefore available for operation of the keyboard by
the operator. Another of the inputs to OR gate 290 is a CIM
(carrier-in-motion) signal indicating that the print head 16 of the
output printer 20 is being transported from right to left; such
signal is derived from a carrier-in-motion sensor in baseplate 24.
Yet another input line to OR gate 290 is a PIM line for carrying a
signal indicating that the print head 16 is in motion or that some
character is being printed out by the print head 16 and the latter
is not ready to print another character. The PIM signal also is
provided by an appropriate sensor in baseplate 24. Another input
line to OR gate 290 identified as Function From Keyboard from
encoder gates 76 in FIG. 4, is intended to carry signals from any
sensor in baseplate 24 which provides a signal that an operator
function such as space, carrier index or the like, is occurring.
Yet another input to gate 290 is a line for carrying a CR or
carrier return signal from an appropriate sensor in baseplate 24.
An additional line to OR gate 290 is intended to carry, in a
preferred embodiment of the invention, delay pulses which are
related to typewriter dynamics and which are intended to adjust the
operation of the print control logic to match the timing
peculiarities or other operating idiosyncracies of the type of
printer 20 being used with the system. The output of OR gate 290 is
connected as one input to NOR gate 292, another input to gate 292
being the output of parity checking circuit 282. The output of NOR
gate 292 is applied as an input to both AND gate 294 and AND gate
293. Another input to gate 294 is line 288, and the output of gate
294 is connected to the enabling input terminal of enabling gates
280.
The output of gate 294 is also connected to provide a signal (CC)
to enable a cycle clutch in the printer 20, in known manner, to
permit the print mechanism to be driven. Similarly, the other input
to gate 293 is line 287 and the output of gate 293 is connected to
the enabling input terminal of enable gates 286. The outputs of
enable gates 286 are thus four lines, each connected to appropriate
mechanisms in baseplate 24, for carrying signals representing the
functions CI, TABS, TABCL and TAB, and three other lines for
respectively carrying signals representing the functions SP, BSP
and CR.
The outputs of enable gates 280 are the six lines R1, R2, R2A, T5,
T1 and T2, connected to the baseplate 24 through a data selector or
switching mechanism that will permit selectively the print out of
data from the buffer or addresses in one embodiment.
The schematic of FIG. 9 also includes three more input terminals,
one marked Force SP, one marked Force BSP and the last marked Force
CR. The input signals at Force SP and Force BSP terminals are
derived from operation of the Step Right and Step Left Buttons 41
and 42 and are intended to provide a compulsory Space signal and a
compulsory Backspace signal to the baseplate. Similarly, the input
signal at Force CR terminal is derived from logic used for
Right-Hand Margin Adjust and is intended to provide a compulsory
Carrier Return signal to the baseplate. Force CR, Force BSP and
Force SP terminals are thus connected to appropriate input
terminals of enable gates 295, the latter having an inverting
enabling material connected to the output of gate 290. Gates 295
thus have three output lines 296, 283 and 297 respectively
connectable to the Force SP, Force BSP, and Force CR inputs
according as gates 295 are enabled or disabled. Line 296 and the SP
output line of gates 286 are connected as inputs to OR gate 298,
the output of the latter then being connected as the SP input line
to baseplate 24. Line 283 and the BSP output line of gates 286 are
inputs to OR gate 285 which has its output connected as the BSP
input to the baseplate. Similarly line 297 and the CR output line
from gates 286 are connected as inputs to OR gate 299, the output
from gate 299 in turn being connected as the CR input line to
baseplate 24. Input Force SP, Force BSP and Force CR lines are all
connected as inputs to OR gate 300. The output of the latter is
connected as an additional input of NOR gate 292.
In operation of the system shown in FIG. 9, as register 94 shifts,
the 8-bit parallel signals appear in sequence at the register
output and all eight bits are applied to parity check logic 282.
The latter, in known manner, sums the bits. Because the present
system requires odd parity. logic 282 provides a high output signal
to gate 292 only if the sum of the bits is even. If any of the
signals at the input of gate 290 are high then a high output signal
is also applied to gate 292. Because the latter inverts, a high
input signal to gate 292 disables gates 293 and 294. Similarly the
output of gate 290 when high serves to disable gates 295. Lastly,
the output of gate 300, when high, is applied as an input to gate
292. Thus, in the event that (1) a "wrong" or even parity signal is
at the output of register 94, or (2) signals indicate that the
Printer is busy, i.e., PIM, CIM, CR or Function from Keyboard, or
(3) delay pulses are at the input of gate 290, or (4) the system is
not in the Print Mode of operation, or (5) a Force SP, Force BSP or
Force CR signal is present, gates 280 and 286 will be disabled and
thereby prevent initiation of any action of the printer 20 by any
output of register 94.
When the operator depresses Step Right button 41, data in storage
is shifted by one character and it is then necessary to command a
corresponding step of one space by the carrier or print head 16 in
the printer 20. Hence, Force SP signal is generated by depression
of button 41 and is coupled through gates 295 and 298 to the
appropriate input terminal of baseplate 24 ti initiate such print
head stepping.
In certain instances when printing out the register contents, it
will be necessary for the system to initiate a Carrier Return
signal to the printer although no CR signal is recorded in the
register at that point. Hence, the system includes a source of the
Force CR signal. Such source is typically a flip-flop activated
responsively to appropriate logic covering a number of situations
where a CR signal must be initiated. The Force CR signal is coupled
through gates 295 and 299 to the proper input terminal of the
baseplate to compel a Carrier Return function by the print carrier
or head. In case of either a Force SP, Force BSP or Force CR signal
being produced, these signals will serve to disable gates 286 and
280 so that the contents of register 94 cannot be used to activate
the baseplate.
As previously noted, when typing data into the register when the
system is in the Draft Mode, a single or a 201 shift cycle is used
and the clocking of register 94 and the subsidiary registers occurs
in the X.sub.1 X.sub.3 X.sub.2 sequence. Similarly, inserting data
from the keyboard into the memory when the system is in the Insert
Mode involves a 201 shift cycle where the clocking order is
initially X.sub.1 X.sub.2 X.sub.3 but changes to X.sub.1 X.sub.3
X.sub.2 during the 201 shift cycle if a blank cell is detected in
the memory. Similarly, the operation of deletion of a character is
accomplished by a 201 shift cycle. As noted single shifts of
register 94 are used along with the X.sub.1 X.sub.3 X.sub.2
clocking sequence when in the Print Mode, i.e., to print out from
the memory.
To effect the foregoing operations, the system includes logic in
buffer control originally shown in block in FIG. 3 at 70 which, in
a simplified version is illustrated in FIG. 10 and includes four
D-type flip-flops 301, 302, 303 and 304. Flip-flop 304 is intended
to provide signals controlling the single shifts when in the Print
Mode. Thus, the D input terminal of flip-flop 304 is connected to
terminal 305 at which a Print Mode signal, derived by operation of
any of the print buttons 33, 34, 35, or 36 is intended to be
applied. The Q terminal of flip-flop 304 is connected to terminal
144 of flip-flop 136 (FIG. 6). The C or clock input terminal of
flip-flop 304 is connected to the output of OR gate 306. The latter
has a pair of input terminals, which are respectively connected to
the outputs from encoder gates 76 shown in FIG. 4 as PIM and
Function from Keyboard. The output of gate 306 is also connected to
the C input terminals respectively of flip-flops 301, 302, 303 and
304.
The logic diagram of FIG. 10 also includes input terminal 169 which
is at the output of gate 134 (FIG. 6). Terminal 169 is connected to
the clear input terminal 307 of flip-flop 304. Terminal 169 is also
connected as an input to AND gate 308, the other input to which is
terminal 310 which is connected to output line 156 of counter 190
(FIG. 6). The output of gate 308 is connected to clear input
terminals 311, 312 and 313 of flip-flops 310, 302, and 303
respectively. A group of logic gates are provided for operating
flip-flops 301, 302 and 303, and include AND gate 314 having its
output connected to the D input terminal of flip-flop 301 and
having four input terminals, one of which is connected to terminal
305 through inverter 315. Another of the input terminals to gate
314 is connected through inverter 316 to terminal 317 which is the
CR line output of decoder 284 (FIG. 9). A third input to gate 314
is through inverter 318 from input terminal 319. The last input
terminal of gate 314 is connected to the output terminal of NAND
gate 320. The inputs to gate 320 are respectively connected to
terminal 322 and line 324 from RS flip-flop 344.
The D input terminal of flip-flop 302 is connected to the output of
second AND gate 326 which has three input terminals, one of which
is connected to the output of inverter 315, a second of which is
connected through inverter 327 to line 324 and the last of which is
connected to the output of OR gate 328. OR gate 328 has one input
connected to terminal 319 and the other input connected to terminal
317.
The third AND gate 329 has its output connected to the D input
terminal of flip-flop 303. Gate 329 has four input terminals, one
connected to the output of gate 328, another connected to the
output of inverter 315, a third connected to line 324 and a fourth
connected through inverter 330 to terminal 322. Lastly, the Q
output terminals of flip-flops 301, 302 and 303 are all connected
as inputs to OR gate 332, the output of the latter being connected
in turn to terminal 147 (FIG. 6).
The buffer control logic shown in FIG. 10 controls the buffer in
accordance with the following operation. As previously noted, the
signal intended to be applied at terminal 305 is derived from
operation of any of the four print buttons. The Q terminal of
flip-flop 304, as is typical of D-type flip-flops, will go high
when simultaneously both the signal at input D is high and the
signal at C terminal goes high. Thus, when the signal at terminal
305 is high and there is PIM or Function from K/B signal, then the
Q terminal of flip-flop 304 will go high. When signal at terminal
144 goes high, as previously described in connection with FIG. 6,
the Q terminal of flip-flop 136 goes high and the data in register
94 is shifted one cell. The first .phi..sub.4 pulse at terminal 169
will clear flip-flop 304 so that its Q terminal goes low. Thus each
time a character is printed or a function is executed on the
printer, the buffer is shifted one place so that the next stored
character is available.
If however, the device is not in the Print Mode and the signal at
terminal 305 is therefore not high, the output of inverter 315 will
however apply a high signal to each of AND gates 314, 326 and 329.
As noted, terminal 317 is connected to the CR output line from
decoder 284 in FIG. 9 and therefore is intended to carry a signal
indicative that a carrier return function signal has been noted at
the buffer memory output. Similarly, terminal 322 is connected to
the output of gate 220 (FIG. 7) and thus is intended to provide a
signal indicative of detection of blank cell at the buffer memory
output. Line 324 is intended to have applied thereto a signal
derived as hereinafter explained indicating that the buffer is
full. Lastly, at terminal 319 there is intended to be applied a
signal indicating that insert button 32 has been depressed and that
the system is therefore to operate in the Insert Mode. It will be
seen then that the output signal from the gate 314 goes high only
when (1) the system is not in the Print Mode, (2) there is no
carrier return signal at the buffer output, (3) the device is not
in the Insert Mode and (4) the buffer is not full with a blank cell
at the buffer output. All of these negative requirements therefore
indicate that the device is to operate in its "normal mode." Hence,
flip-flop 301 provides at its Q output a normal shift signal for
typing in data from the keyboard when the output of gate 314 is
high and if either a PIM or Function from K/B signal is
present.
Similarly, there will be high output from gate 326 when (1) the
system is in an Insert Mode or a carrier return signal appears at
the buffer output, (2) the system is not in the Print Mode and (3)
the buffer memory is not full. This output from gate 326 causes
flip-flop 302 to also provide an output signal which indicates that
a Normal Insert Cycle is to operate and which is fed both as in
input to gate 332 and to terminal 187 (FIG. 6).
Gate 329 will provide a high output only when (1) the system is
either in an Insert Mode or a carrier return signal appears at the
buffer output, (2) a blank cell is not at the buffer output (3) the
buffer is full and (4) the system is not in the Print Mode. In such
case, the resulting output signal from flip-flop 303, applied as an
input to gate 332, also is applied at terminal 182 to control
buffer clocking for the Insert Cycle with Overflow operation.
Resetting of flip-flops 301, 302 and 303 occurs when both a
terminate shift signal is present at the output of counter 190
(FIG. 6) and a .phi..sub.4 signal is present at terminal 169. The
output of gate 332 is applied to terminal 147 to bring the J input
of flip-flop 142 (FIG. 6) high and therefore initiate a 201 shift
as previously described. It should be noted that D type flip-flops
are used particularly because it is desired to do a 201 shift on
the leading edge of the pulse from gate 306.
Included in the circuit of FIG. 10 are means for detecting when its
memory is "full." The foregoing means comprises AND gate 336 having
one input connected to terminal 322 and the other input connected
to terminal 338. The latter is preferably connected to X.sub.1 line
97 (FIG. 5) so that normal .phi..sub.1 clocking signals applied to
single-bit register 96, will also be applied at terminal 338. The
output of gate 336 is connected to the input of counter 339. The
latter has an enable input terminal which is connected to terminal
147. Counter 339 is a counter, which after being enabled, counts
the first three input pulses from gate 336 and then provides a high
output signal indicating that three pulses have been counted,
whereupon the counter stops counting. Such counter can be readily
formed of a pair of flip-flops as is well known in the art. The
output of counter 339 is connected through inverter 340 as one
input to AND gate 341. Gate 341 also has as inputs thereto a line
connected to terminal 310, another line connected to terminal 147,
and a fourth input connected to terminal 342. Terminal 342 is
connected to X.sub.2 line 95 (FIG. 5) so that any signals applied
for clocking shift register 94 (FIG. 5) will also be applied at
terminal 342.
The output of gate 341 is connected to the S input terminal of an
RS type flip-flop 344. The Q output terminal of the latter is
connected to line 324. Lastly, OR gate 345 is provided, having its
output connected to the R terminal of flip-flop 344 and having a
pair of input lines respectively connected to terminals 346 and
347. At terminal 346, there is intended to be applied a signal
indicating that a Delete function is being performed, which signal
is derived hereinafter described. The signal to be applied at
terminal 347 is a signal which will cause a clearing of the buffer
memory and for example may be derived from Enable Write line 244
(FIG. 7).
The portion of FIG. 10 just described detects the "full" buffer in
accordance with the following operation. A signal at the output of
gate 332 will, as previously noted, initiate a 201 shift by being
applied at terminal 147. The same signal enables counter 339.
During the 201 shift, every .phi..sub.1 pulse, being applied at
terminal 338, will serve to enable gate 336. However, the output of
the latter goes high only when a blank cell is detected at the
output of register 94 and a corresponding pulse is therefore
applied at terminal 322. Counter 339 then counts, for example, the
first three blank cells detected during that 201 shift, then stops
counting as the output of the counter goes high. Simultaneously,
the input to gate 341 from gate 332 will remain high during the 201
shift, as will the periodic timing signals applied to gate 341 from
terminal 342. When the terminate shift input signal, indicating
that the 201 shift has been completed, is applied at terminal 310,
gate 341 is then interrogated to see if less than three blank cells
were counted.
If counter 339 has counted at least three blank cells, its output
signal will be high and thus inverter 340 will apply a low signal
to gate 341, disabling the latter. If however, counter 339 has
counted less than three blank cells, gate 341 then, when
interrogated by the signal at terminal 310 and if all of its other
inputs are high, will provide a set pulse to the S terminal of
flip-flop 344 at X.sub.2 time.
In other words, flip-flop 344 will be set when a 201 shift has been
executed and less than three blank cells have been seen at the
output in .phi..sub.1 time during that shift. Setting of flip-flop
344 provides an output signal on the Q terminal thereof which is
applied to line 324 and which indicates that the buffer memory is
full. Flip-flop 344 will be reset by the output of gate 345 if
anything is deleted from the buffer as indicated by a Delete signal
at terminal 346 or if a record is written on to tape 18 as
indicated as by a Write Enable signal which will clear register 94
and which is applied to terminal 347.
It should be noted that if less than three blank cells are seen one
may infer that only two or less are seen by counter 339. This
implies that if only two cells are seen, only one will be left when
the 201 shift cycle is complete. Because for proper operation of
the system at least one blank cell must be left at all times, it is
apparent that a "full" buffer can be defined as one in which,
during the 201 shift, counter 339 counts less than three blank
cells at the output.
As shown in FIG. 11, which is a simplified version of the tape
control circuitry, the address display logic and read address
circuits include shift register demultiplexer 262 (FIG. ). The
inputs shown to the latter are the same as in FIG. 7: line 274
along which an Enable Read signal can be sent, line 350 which is
the data line coupled to the Q output of flip-flop 260, and line
352 which connects the second count output line of converter 266 to
the clocking input terminal of shift register demultiplexer 262.
The decoded signals, appearing at respective lines at the output of
demultiplexer 262 are of course the respective R1, R2, R2A, R5, T1,
T2, S and P lines. Four of these lines are connected to the present
inputs of counter 354.
Counter 354 is preferably an up-down, presettable, clocked counter,
well known in the art, capable of counting in a binary coded
decimal mode. The counter has a load pin or terminal 356 which is
preferably connected to line 268 (FIG. 7) so that the
inter-character gap (ICG) signal can be applied to preset counter
354. Counter 354 also includes an input decrement line 358 and an
input increment line 359. The output of counter 354 is connected to
code converter 360 which is adapted to convert the count in counter
354 to a proper format for display in address display unit 28.
Counter 354, converter 360 and display 28 are all shown, for the
sake of simplicity as a single decimal digit unit, but it is to be
understood that these elements are preferably multi-digit
devices.
FIG. 11 also includes, in schematic form, Tape Forward button 46
and Tape Back button 47, connected to respective double-poled
switches 362 and 364, the switch armature in each case being
centrally spring-biased and coupled to a source of voltage +V. The
up or fast forward terminal 365 of switch 362 is connected as an
input to both motor drive circuits 366 and to AND gate 368. The
down or slow forward terminal 370 of switch 362 is also connected
as an input to motor drive circuits 366. Both the up or fast
reverse terminal 372 and the down or slow reverse terminal 373 of
switch 364 are connected as respective inputs to motor drive
circuits 366 and also as inputs to OR gate 374. The output of OR
gate 374 is connected as input to AND gate 376.
Motor drive circuits 366 are connected in known manner for
controlling the direction and speed of motor or motors 242. Motor
242 is mechanically coupled to control the movement of tape 18 in
casette 240 past read/write head 238, and the output of the latter
is amplified in amplifier 377. The output of amplifier 377 is
connected an an input to data-block monostable multivibrator or
one-shot 378. The output of the latter is connected to respective
inputs to AND gates 368 and 376. The output of AND gate 376 is
connected to input decrement line 358, and the output of AND gate
368 is connected to increment line 359.
The operation of the device of FIG. 11 to identify and display the
address of a block of data on tape in casette 240 can be described
as follows. It will be appreciated that, as previously noted in
connection with FIG. 2A, the data addresses 48 are typically
prerecorded on a second track 29 on the casette tape 18 and are
read from the tape preferably by one of the dual read/write heads
238. The output of both heads will however be applied through the
decoding circuitry of FIG. 7, so that both the data on track 25 of
the tape and the address information on track 29 will appear on
line 350 to shift register demultiplexer 262. To avoid the
simultaneous appearance of information from both tracks 25 and 29,
it is of course necessary to insure that the data recorded on track
25 is not positioned adjacent an address, so that the two tracks
can only be read out in a mutually exclusive fashion.
Alternatively, one can record addresses and other data in sequence
on a single track. The addresses are preferably read out into
demultiplexer 262 in binary coded decimal form to appear on the
four output lines of the demultiplexer that are connected as the
BCD preset inputs of counter 354. The latter is preset at each
intercharacter gap associated with the recorded addresses so that
no data can be transferred from the shift register demultiplexer
262 to counter 354, except address information.
The output of counter 354 is converted in converter 360 to a form
suitable for display in display device 28. The nature of converter
360 is dictated by the type of display desired. For example, if
each display device 28 is a seven-segment display then the
converter 360 will be a BCD-to- seven-segment converter. Similarly,
if display device 28 is a Nixie tube display, then converter 360
would be a BCD-to-decimal converter. Such converters are, of
course, well known in the art and need be described no further
here.
If button 46 is displaced so that the armature of switch 362
contacts slow forward terminal 370, motor drive circuits 366 will
control motor 242 to drive the tape 18 in cassette 240 at a slow
speed. As the address is then read from the tape 18, it is
demultiplexed and sets the state of counter 354. The state of the
counter is converted by converter 360 to a visible display in
device 28.
If however, button 46 is manipulated so that the armature of switch
362 contacts fast forward terminal 365, the resulting signal is
applied both to gate 368 and to motor circuits 366 which then
control motor 242 so that the tape in cassette 240 is driven at
comparatively high speed past read/write head 238, and ordinarily
at a speed which is too fast for the circuit of FIG. 7 to decode
the address. In such case, the output of amplifier 246, while it
may be indecipherable, nevertheless is used to trigger the
monostable multivibrator 378 so that its output is a pulse
representing the envelope of the address signals read from the tape
18. Each such pulse, when applied to the then enabled gate 368,
will be transferred to increment line 359 of counter 354 and hence
change or increment the state of the counter by one added
count.
In a similar fashion, it will be recognized that in neither the
fast reverse nor slow reverse modes of movement of the tape in
cassette 240, can a readily decipherable signal be obtained by
demultiplexer 262. Hence signal from both the fast reverse and slow
reverse terminals 372 and 373 of switch 364 are used to cause the
counter to be decremented and are applied through OR gate 374 to
enable gate 376. When the tape is moving in reverse, detection of
an address will trigger one-shot 378 and the resulting pulse is fed
through gate 376 to line 358 to reduce the state of counter 354 by
one count.
It will be appreciated that one-shot 378 will provide a pulse
corresponding to every address seen, whether in the slow or fast,
forward or backward motion of the tape. However, the output of the
one-shot will not be passed by either gate 368 or 376 unless those
gates are enabled by appropriate signals indicating appropriate
positions of the tape move buttons 46 and 47.
Communication between the operator of the device and the system, to
control the operation of the latter is effected, of course, through
both the printer keyboard and control unit 22. The schematics
showing the details of the control unit connected with the
operation of the various control buttons, are shown particularly in
FIGS. 12 and 13. Referring particularly to FIG. 12, there will be
seen eight of the control buttons identified by name and
specifically shown as switch 380 which is connected to be
controlled by Draft Mode button 30, switch 382 which is connected
to be controlled by Final Mode button 31, and switch 384 which is
connected to be controlled by Insert Mode button 32. All of
switches 380, 382 and 384 have armatures which are each connected
to the common source of voltage, such as +V, and which are moveable
between a corresponding pair of positions.
The armature of switch 380 is moveable between a first position at
which the switch is inoperative or has no effect, and a second
position wherein the armature contacts a terminal connected to the
S input terminal of RS type flip-flop 386. Similarly, switch 382
has a first or inoperative position and a second position wherein
the armature is in contact with a terminal which is connected
directly to the R or reset terminal of flip-flop 386. The Q output
terminal of flip-flop 386 is connected to terminal 387 and the Q
output terminal of flip-flop 386 is connected to output terminal
388.
Switch 384 has a first position wherein the armature thereof
contacts the S input terminal of RS type flip-flop 390. In the
second position of switch 384, the armature of the latter is
connected to the R input terminal of flip-flop 390. The Q output
terminal of flip-flop 390 is in turn connected to the C input
terminal of J-K type flip-flop 392. The Q output terminal of the
latter is connected to the J input terminal and the Q output
terminal is connected to the K input terminal. The Q output
terminal of flip-flop 392 is also connected to output terminal 394.
The reset input terminal of flip-flop 392 is connected to the
output line of NOR gate 395. One input of the latter is connected
to terminal 388 and another input is connected to the output of OR
gate 396.
It will be appreciated that switches 380, 382 and 384 respectively
constitute the Draft, Final and Insert button control switches.
Upon operation of button 30, flip-flop 386, being set, provides a
high signal at its Q terminal and therefore at terminal 387. This
high signal then indicates that the device is to operate in the
Draft mode. Similarly, when button 31 is pressed, it serves to
reset flip-flop 386 and produce a high output signal at terminal
388. This latter high output signal is of course indicative that
the operation of the device is to be in the Final mode. It should
be noted that the signals at terminals 387 and 388 are mutually
exclusive signals so that the system can only operate in either the
Draft or the Final mode, but not in both.
Similarly, Insert button 32 controls the operation of switch 384.
The armature of switch 384 is normally spring biased into the
position whereby flip-flop 390 is held in a reset state. When
insert button 32 is depressed, an input signal is applied to the S
input terminal of flip-flop 390 and serves to provide a high signal
at the Q output terminal of the latter. When the insert button is
released, the armature of switch 384 will return to the reset
position and the signal at the Q output terminal of flip-flop 390
will then again go low. It will be recognized that because
flip-flop 392 is wired so that its input and output terminals are
cross-coupled to one another, flip-flop 392 essentially constitutes
a divide-by-two device. Thus, as the Q terminal of flip-flop 390
goes high, assuming that the Q terminal of flip-flop 392 is
initially high, upon the trailing edge of the signal from flip-flop
390 due to the resetting of the latter, the Q output terminal of
flip-flop 392 will go high, and provide an Insert Mode signal at
terminal 394. This signal will persist until Insert button 32 is
again depressed and an input signal is provided to the clock input
terminal of flip-flop 392. On the trailing edge of such signal,
terminal 394 will then go low.
Gate 395 provides an output which will automatically reset
flip-flop 392 so that if terminal 394 has a high signal, that
signal will then go low. It will be seen that one of the signals
which will serve to reset flip-flop 392 is a high signal at
terminal 388 indicating that the system is in the Final Mode of
operation and that no inserts can be made. Other resetting signals
to flip-flop 392 are derived from gate 396. Gate 396 has a
plurality of inputs thereto. Typically, one input to gate 396 is a
Delete signal, which is derived as hereinafter explained in
connection with FIG. 13. Another input signal to gate 396 is a Tape
Move signal indicating that one of the Tape Forward or Tape Back
buttons are being operated, as for example, a signal on one of the
input lines to motor drive circuits 366 in FIG. 11.
Yet another input to gate 396 can be a line carrying a Step Right
or Step Left signal derived from operation of buttons 41 or 42 as
hereinafter described. Probably the most common signal which will
serve to reset flip-flop 392 is an indication that the device is in
the Print Mode and the derivation of that signal will be described
hereinafter. It will be appreciated that the inputs shown to OR
gate 396 are merely exemplary and that many other inputs from
elsewhere in the system can be applied at corresponding inputs to
either gate 396 or 395 when it is desirable to take the system out
of the Insert Mode of operation. It will also be seen that
flip-flop 390 essentially serves to debounce switch 384 and that
flip-flop 392 serves as a memory to remember when the system is or
is not in the Insert Mode.
FIG. 12 also includes a number of the other buttons of the system
and their associated switches. For example, there is shown Print
Character button 33, Print Word button 34, Print Line button 35,
Automatic Print button 36 and Stop button 38 respectively
associated with switches 398, 399, 400, 401, and 402 so that the
armature of each switch is operated by manipulation of the
respective button. The armature of each of these switches is
connected to a source of potential such as +V, and is moveable
between one of two positions. In each case, the armature is
normally biased to be in contact with the R or reset terminal of a
respective R-S type debouncing flip-flop, and is moveable to the
second position wherein the armature applies the potential +V to
the S or Set terminal of the corresponding flip-flop. Thus,
switches 398-402 inclusive have associated therewith flip-flops
404, 405, 406, 407 and 408 respectively. The Q output terminals of
flip-flops 404, 405, 406 and 407 are respectively connected to the
C input terminals of D type flip-flops 410, 411, 412, and 413. All
of the D terminals of flip-flops 410, 411, 412 and 413 are
respectively connected to Enable Print input terminal 414. All of
the Q output terminals of flip-flops 410-413 inclusive are
connected as respective inputs to OR gate 416. The output of the
latter is connected to terminal 418 and also, as previously
described, as an input to gate 396. The reset terminals of
flip-flops 410, 411, 412 and 413 are connected to the respective
outputs of NOR gates 422, 424, 426 and 420. The Q output terminal
of flip-flop 408 is connected as an input to each of gates 420,
422, 424 and 426. Depending on the complexity of the system, the
latter NOR gates will have many other inputs. Typically, for
example, one of the inputs to NOR gate 420 is connected to input
terminal 428 at which there is intended to be applied a signal
indicating that anticipatory margin control logic has determined
that the printing should stop because no return opportunity has
been found upon examination of a particular part of the buffer
contents, as will be described hereinafter. Any other condition
determined by logic in the system which requires that automatic
printing be arrested, such as the appearance of a stop code signal
at the output of the buffer memory during printing, or some like
condition, can be applied as an input to gate 420 to reset
flip-flop 413 and therefore arrest automatic printing.
Similarly, terminal 429 of gate 426 is preferably connected to the
output of gate 299 (FIG. 9) so that a signal indicating that a
carrier return signal has been detected at the output of the buffer
memory can be applied to gate 426. Again clearly, one can provide
additional inputs to gate 426 as shown by the unmarked terminal,
from logic which determines that a condition exists in the system
whereby it is desired to arrest the printing of a line.
Terminal 430 of gate 424 therefore is connected to the output of
gate 298 (FIG. 9) so that an input signal indicating that a space
signal has been detected at the output of the buffer can be applied
to gate 424 and therefore that a word has terminated. As with OR
gates 420 and 426, other inputs can be provided to gate 424 from
logic which determines when it is desirable to arrest the printing
of the word.
Lastly, as an input to terminal 431 of gate 422, there is provided
a connection to the Q terminal of flip-flop 304 (FIG. 10) so that
flip-flop 410 can be reset on a condition indicating that a
one-shift has been completed by the buffer and therefore a
character has been printed out. Similarly other inputs can be
provided to gate 422 which indicate that it is desirable to stop a
print condition where the system has been ordered to print out but
one character.
In operation, when it is desired to place the system in a Print
Mode of operation, it is only necessary to depress any of Print
buttons 33-36 inclusive to effect printing respectively of a
character, word, line or to effect automatic continual printing as
earlier described. The depression of one of the Print buttons will
provide an appropriate signal at the input of gate 416 and
therefore a Print Mode signal at the terminal 418. It will be
remembered that terminal 418, is connected to terminal 305 (FIG.
10) so that flip-flop 304 thereby provides a signal which triggers
the one-shift flip-flop 136 (FIG. 6) to clock the buffer memory so
that the latter shifts only a single cell. As soon as the shift is
initiated, the Q terminal of flip-flop 304 goes high, and the
latter signal will then, being applied through gate 422, reset
flip-flop 410 terminating the Print Character mode. In like manner,
the output of flip-flop 411, being applied through gate 416, will
cause flip-flop 136 to be triggered through a series of single
shifts until a Space signal is detected at the output of the buffer
memory and flip-flop 411 is reset, thereby terminating that
printing operation. Similarly, signals provided at terminal 418
from flip-flops 412 or 413 will insure that a series of single
shift operations of the buffer memory will occur until terminated
by conditions which indicated that a line has been completed (such
as the occurrence of a carrier return signal at the output of the
buffer memory) or, when it is desired to terminate automatic
printing, (as by the occurrence of a stop code at the output of the
buffer memory).
Referring now to FIG. 13, there will be shown the remainder of the
control buttons from the control console, together with the
switching and logic immediately associated therewith. As shown in
FIG. 13, there are Step Right button 41 and Step Left button 42
each coupled for controlling the armature of a respective one of a
pair of two-position switches 434 and 435. The two terminals of
switch 435 are respectively connected to the set and reset input
terminals of RS type flip-flop 436. Similarly, the S and R
terminals respectively of flip-flop 437 are connected to the output
terminals of switch 434. The Q output terminal of flip-flop 436 is
connected to the C input terminal of D type flip-flop 438. In like
manner, the Q output terminal of flip-flop 437 is connected to the
C input terminal of flip-flop 439. Both D input terminals of
flip-flops 438 and 439 are connected to a source of voltage
V.sub.cc at terminal 440. The Q output terminal of flip-flop 438 is
connected to output terminal 442.
The Q output terminal of flip-flop 439 is connected to the S input
terminal of RS type flip-flop 448. The R input terminal of
flip-flop 448 is connected to input terminal 449 at which there is
intended to be a signal SP/S applied which has been derived from a
sensor in the baseplate indicating that a spacing operation has
been executed in the printer. The Q output terminal of flip-flop
448 is connected to output terminal 450. The clear input terminal
of flip-flop 439 is also connected to terminal 169. Lastly, the
armature of switches 434 and 435 are connected to some voltage
sources such as +V at terminal 454.
It will be appreciated that in the Draft mode, operation of the
backspace key on the typewriter keyboard will cause the typewriter
to backspace and will simultaneously cause the BSP code to be
recorded in the buffer memory. Because it may be necessary to
backspace to a point in the text at which the operator wishes to
insert a correction or overstrike the text without adding the
consequent BSP codes to the buffer, but instead simply move the
contents of the buffer memory in correspondence with the backspace
motion, the present invention includes Step Left button 42 and
control logic for governing the operation of the system when button
42 is operated.
Generally, as earlier noted, when button 42 is depressed, the
contents of the buffer are effectively shifted backward as the
typewriter is backspaced. The buffer contents and typewriter
backspacing are coordinated so that the typewriter carrier is in a
position it would have had prior to execution of the recorded
characters over which backspacing has occurred. Over ordinary text,
backspacing and backward shifting in the buffer will be coincident.
However, if backspacing is used with certain types of characters
recorded in the buffer, the buffer contents and typewriter carrier
will no longer be properly spatially coordinated. For example, if
the character over which backspacing occurs (using the Step Left
button) is a recorded backspace BSP, if then the text is played
out, the next operation of the typewriter will be to carry out the
recorded backspace but with the carrier not in the correct position
with respect to the typed text.
Generally, the logic for controlling coordination of typewriter and
backspacing in response to operation of the Step Left button 42
follows the basic rule that first the buffer contents are
effectively shifted backward by one cell (through a 199 Shift
sequence), the buffer output signal is examined to determine what
signal was just oved over, and if
1. the signal is a normal print character or space then the
typewriter is backspaced one space;
2. if the signal is a "no-move" operator (CI, TABS, TABCL, or a
Stop Code) then the typewriter is not spaced either forward or
backward but the buffer is shifted by one more 199 Shift to move
back another cell;
3. if the signal is a backspace (BSP) then the typewriter is spaced
forward one space;
4. if the signal is a blank cell, then it implies that the system
is at the beginning of a line, hence the buffer is shifted forward
by one cell (1 shift sequence) to place the buffer back where it
was first prior to the previous 199 Shift and the typewriter is not
spaced forward or backward; and
5. if the signal is a TAB, when a Force Carrier Return signal is
provided to cause the typewriter to index and return to the
beginning of a line while at the same time, a series of 199 Shifts
are performed on the buffer until a blank cell appears at the
buffer output. These are followed by a single 1-Shift as in (4)
above. These actions force both the typewriter and buffer contents
to go back to the beginning of the line of text being drafted or
edited.
Referring now to FIG. 14 there is shown an exemplary circuit for
controlling the step left operation of the printer or typewriter
and of the buffer memory. The circuit of FIG. 14 includes input
terminal 442 which is coupled to the Q output of flip-flop 438
(FIG. 12) and to the D input terminal of D type flip-flop 443. The
Q output terminal of flip-flop 443 and terminal 442 are connected
as inputs to OR gate 444, the output of the latter being connected
to terminal 145 at the J input of 199-Shift flip-flop 138 (FIG. 6).
Terminal 442 is also connected to one input of OR gate 445, the
other input to the latter being connected to the Q output terminal
of flip-flop 443. The output of gate 445 is connected to the D
input terminal of D type flip-flop 446. The Q and Q output
terminals of flip-flop 446 are connected respectively to terminal
144 at the J input of 1-Shift flip-flop 136 (FIG. 6) and to an
inverting clear terminal of flip-flop 443. The Q output terminals
of flip-flop flop 443 and 445 are connected as inputs to OR gate
447. The output of the latter is connected to reset terminal 451 of
flip-flop 438 (FIG. 13).
The circuit of FIG. 14 also includes a number of other input
terminals including Terminate Shift terminal 193 connected to the
output from counter 190 (FIG. 6); terminal 322 which is connected
to the output of gate 220 (FIG. 7) and thus intended to provide a
signal indicative of detection of a blank cell at the output of the
buffer memory; terminal 170 at which the .phi..sub.1 pulses are
provided from gate 128 (FIG. 6); a number of terminals identified
by the reference numerals 452, 453 and 455 and connected to
corresponding outputs of decoder 284 (FIG. 9) at which the signals
respectively appear indicative of TAB, BSP and SP signals at the
buffer output, termianl 459 which is connected to output line 288
from decoder 284 (FIG. 9) indicative that an information or print
character signal (PR) is at the output of the buffer; and lastly a
pair of terminals 499 and 463 at which respectively there are
intended to be the signals SP/S as heretofore described, and the
signal BSP/S derived from a sensor in the baseplate indicating that
a backspacing operation has been executed in the printer.
Terminals 169 and 193 are connected as inputs to AND gate 465, the
output of which in turn is connected as an input to AND gate 472
and as an input to AND gate 473. Terminal 322 is also connected as
an input to gate 473, the output of the latter being connected to
the C input terminal of flip-flop 446. Terminal 170 is connected
through inverter 475 to the inverting reset terminal of flip-flop
446.
Terminal 442 is also connected as an input to AND gate 472. The
output of the latter is connected as an input to each of three
different AND gates 530, 531 and 532. Terminal 452 is connected as
another input to gate 530 and the output of gate 530 in turn is
connected to the C input terminal of flip-flop 443. Terminal 453 is
connected as another input to gate 531. Terminals 459 and 455 are
connected as inputs to OR gate 534, the output of the latter being
connected as another input to gate 532.
The circuit of FIG. 14 includes two additional RS type flip-flops,
534 and 536. The S and R terminals of flip-flop 536 are
respectively connected to the output from gate 531 and to terminal
449. The S and R terminals of flip-flop 534 are respectively
connected to the output from gate 532 and to terminal 463. The Q
terminals of flip-flops 534 and 536 are respectively connected to
terminals 538 and 540 and are also both connected as additional
inputs to gate 447.
In the operation of buttons 41 and 42, it will be seen that the
following sequence of events will typically occur. For example, if
button 41 is manually manipulated, it applies a positive voltage at
the set input terminal of flip-flop 437 bringing the Q output
terminal of the latter high. This triggers flip-flop 439 so as to
apply a high signal at the set input terminal of flip-flop 448 and
produces a high signal on the Q output terminal of the latter at
terminal 450. This latter signal is then a Force Space signal
which, as previously noted in connection with FIG. 9, is applied to
Enable Gates 295 and forces the carrier or print head 16 in the
printer 20 to space forward one unit in spatial synchronism with
the shift of data in the buffer memory due to the one-shift.
To effect the latter operation, the Q output of flip-flop 439 is
also used, as will be described hereinafter, as an input signal to
flip-flop 136 (FIG. 6) to initiate the one-shift in the buffer
memory. Flip-flop 439, of course, is cleared by the first
.phi..sub.4 pulse applied at terminal 169 and flip-flop 448 is
reset immediately upon the execution of a Space operation by the
printer as determined by the sensor in the baseplate which provides
a corresponding signal SP/S at terminal 449.
The operation of button 42 and its associated logic can be
described with reference to both FIGS. 13 and 14. Manipulation of
button 42 applied the voltage at terminal 454 to the S terminal of
flip-flop 436 bringing the Q terminal of the latter high thereby
triggering flip-flop 438 to produce a high signal at terminal 442.
Thus, flip-flop 436 (as does flip-flop 437) essentially serves to
debounce the input signal from the switch and clocks flip-flop 438
each time switch 42 is operated. As shown in FIG. 14, the high
signal at terminal 442 is applied simultaneously at the inputs to
gates 444 and 445 and to the D input terminal of flip-flop 443. The
signal thus applied to gate 444 triggers flip-flop 138 (FIG. 6) and
initiates repetitive 199-shift cycles (normally only one), until
flip-flop 438 is reset by a signal from NOR gate 447 at terminal
451. Normally, such a reset signal is achieved when a print or
information character signal or a space signal being at the buffer
output provides a signal (PR/O or SP as the case may be) either at
terminal 459 or 455 in ".phi..sub.4. terminal shift" time, thereby
providing an output from gate 532 and setting flip-flop 534 "on."
Thus, the Q terminal of flip-flop 534 goes high and this signal is
applied at terminal 538 which, being connected to the appropriately
indicated input of gates 295 (FIG. 9) forces the printer to
backspace one unit. The Q output from flip-flop 534 also provides
the desired input to gate 447 to cause resetting of flip-flop 438.
When a sensor signal (BSP/S) occurs at terminal 463 indicating that
the backspace has been performed, flip-flop 534 is then reset so
that the Q output of the latter goes low.
If, however, a backspace signal appears at the buffer output and
hence at terminal 453 at ".phi..sub.4. terminate shift" time, gate
531 provides an output which sets flip-flop 536 so that its Q
output terminal goes high. The signal then from flip-flop 536
appearing at terminal 540 which is connected to the Force SP input
to gates 295 (FIG. 9), so that the printer is forced to execute a
space function. The output from flip-flop 536 also is applied
through OR gate 447 to terminal 451 to reset flip-flop 438.
Flip-flop 536 is reset by the signal (SP/S) received at terminal
499 indicating that the space function has been executed by the
printer.
In the event that the signal at the buffer memory output at
".phi..sub.4. Terminate shift" time is a blank cell as indicated by
a signal at terminal 332, gate 473 is enabled to provide a signal
to C input terminal of flip-flop 446. At the same time, the signal
at terminal 442 is applied through gate 445 to the D input terminal
of flip-flop 446. These two inputs to flip-flop 446 turn the latter
"on" bringing its Q output terminal high and applying the high
signal to terminal 144. Flip-flop 136 (FIG. 6) therefore initiates
a one-shift sequence of data through the buffer memory as
heretofore described. It should be noted that there is no
corresponding operation of the printer accompanies the execution of
this one-shift. The high signal at terminal 144 is also applied
through gate 447 to reset flip-flop 438.
It is quite difficult to coordinate the operation of the printer
and buffer memory with respect to TAB entries, because the tabs
executed by the printer may be of any arbitrary length. Usually the
printer contains no sensors which provide signals indicative of tab
length. Hence, in the present invention, if the signal at the
output of the buffer memory at ".phi..sub.4. terminate shift" time
is a TAB, as indicated by a high signal at terminal 452 and the
requisite signals at terminal 169 and 193, gate 530 is enabled and
provides a signal which, in conjunction with the signal at terminal
442 sets flip-flop 443 "on" causing a series of 199-Shifts to be
executed. The buffer thereby is shifted backward until such time as
a blank cell is detected at the output of a buffer memory as
indicated by a signal at terminal 322. This latter signal then sets
flip-flop 446 which serves both to clear flip-flop 443 and initiate
one compensating 1-shift cycle.
Lastly, if none of the foregoing signals have been detected at the
output of the buffer memory (TAB, Blank Cell, BSP, SP, any
information character) then the implication is that the signal at
the output of the buffer is one of the remaining "no-move"
functions TABS, TABCL, CI and STOP. In such cases, flip-flop 438 is
not reset after only one 199-Shift cycle through the buffer,
because there is no reset output from gate 447. Hence, successive
199-Shifts will occur until the signal examined at the buffer
output is some other code which will initiate a different train of
events as hitherto described.
Gate 472 insures that flip-flops 443, 534, and 536 can only be
triggered during 199-shift cycles initiated by flip-flop 438 and
during ".phi..sub.4. terminate shift" time.
It will be apparent than that the operation of either of the Step
buttons will result in either the buffer contents alternatively
being shifted forward or in effect backward, with a synchronized
attendant movement of the print carrier. The logic for controlling
the buffer can be made considerably more complex to cover a number
of special relations between the buffer contents and printer
opertion that may occur while stepping the print head either as a
series of spaces or as a series of backspaces.
Also included in FIG. 13 are three additional switches 456 457 and
458 respectively associated with and operated by the Skip/Delete
buttons 45, 39 and 40 which are intended respectively to control
the skipping or deleting, as the case may be, or characters, words
and lines. Each of the switches 456, 457 and 458 are two-position
switches wherein the armature is normally spring biased into one
position. The respective contacts of each switch are connected to a
corresponding pair of sets and reset terminals of one of RS type
flip-flops 460, 462 and 464. The Q output terminal of flip-flop 460
is connected to the C input terminals of first and second D type
flip-flops 466 and 467. Similarly, the Q output terminal of
flip-flop 462 is connected as an input to the C input terminals of
both flip-flops 468 and 469, and the Q output terminal of flip-flop
464 is connected to the C input terminals of flip-flops 470 and
471. The D input terminals of flip-flops 466, 468 and 470 are
connected to terminal 388. The D input terminals of flip-flops 467,
469 and 471 are connected to input terminal 387. The Q output
terminals of flip-flops 466, 468 and 470 are all connected together
with the Q output terminal of flip-flop 439 as inputs to OR gate
474. The output of the latter is connected to input terminal 144
(FIG. 6). The Q output terminals of flip-flops 467, 469 and 471 are
all connected as inputs or OR gate 476. The output of the latter is
in turn connected to terminal 147 (FIG. 6) and also to terminal
478. Lastly, the armatures of switches 456, 457 and 458 are all
connected to terminal 454.
In operation of the Skip/Delete buttons of FIG. 13, the operation
of Word button 39 will be described as being exemplary of the
others. Manipulation of button 39 will apply the voltage at
terminal 454 to the S input terminal of flip-flop 462 so that the Q
output terminal of the latter then goes high. This high signal is
then applied to the C input terminals of flip-flops 468 and 469.
One of the two latter flip-flops will then be triggered, depending
upon which of the flip-flops has a high signal applied to its D
input terminal. It will be appreciated that the signal applied at
terminal 388 is indicative that the system is in the Final mode of
operation because terminal 388 is connected the Q output of
flip-flop 386 (FIG. 12). Similarly, if the signal at terminal 387
is high, it is indicative of that the system is in the Draft Mode
of operation because terminal 387 is connected of course to the Q
output of flip-flop 386 (FIG. 12). Thus, depending upon whether the
system is in the Final Mode or Draft Mode (as determined by the
state of flip-flop 386) either flip-flop 468 or 469 will provide an
output. If the Q output of flip-flop 468 goes high because the
system is in Final Mode then the signal is applied to terminal 144
and will initiate a one-shift cycle in the buffer memory. If on the
other hand the system is in the Draft Mode of operation, flip-flop
469 will be triggered and a signal will be applied at terminal 147
to initiate a 210 shift, and the same signal is applied at terminal
478 to provide a Delete signal which, among other things, is
applied as an input to OR gate 396 (FIG. 12), at terminal 346 (FIG.
10) and at terminal 186 (FIG. 6). In similar manner, the operation
of line button 40 will trigger either flip-flop 470 or 471
depending upon whether the system is in the Final or Draft modes of
operation and provides similar output signals either to terminals
144 or 147. A similar situation would also be created by operation
of character button 45.
In any case, the various signals, either at terminal 144 which
serves to initiate one-shift cycles or at terminal 147 which serves
to initiate 201 shift cycles, will persist for variable lengths of
time depending upon the resetting or clearing of the particular
operative one of flip-flops 466-471 inclusive. The various
flip-flops are reset by a number of signals which are derived
through flip-flop reset gating logic shown only generally at 479.
Logic 479 is quite similar to the reset logic shown in FIG. 12, for
example as gates 420, 422, 424 and 426 and have a plurality of
inputs thereto, only a few of which are shown as exemplary as, for
example, terminal 428 at which a signal indicative that there has
been no Return Opportunity detected, or terminal 429 which
indicates that a Carrier Return has been detected and therefore the
line has terminated, or terminal 430 at which a Space signal is
indicated as having been detected at the buffer output. The simple
logic needed to reset flip-flops 466-471 according as character,
word or line termination condition have been detected, is not shown
insasmuch as it would unduly serve to complicate the drawing
without enlarging the understanding of the operation of the
system.
A better understanding of the capability of the system thus
described can perhaps be better appreciate. by contemplating the
operation of the device where inserting a character in an existing
line. As previously noted, this involves a 210 shift cycle where
the change in clocking order fromX.sub.1 X.sub.2 X.sub.3 to X.sub.1
X.sub.3 X.sub.2 is seen to give an insert capability. The order is
changed when a blank cell is seen in the buffer input at
.phi..sub.4 time. Thus, when the insert button 32 is depressed,
flip-flop 392 is triggered to produce an output at terminal 394.
The signal is then applied at input terminal 319 (FIG. 10) to the
change order gating, and starts the cycle of operation described in
connection with the logic of FIG. 10 which provides that the
clocking order will shift during the 201 shift cycle if and when a
blank cell is detected in the memory. During the first part of the
cycle the buffer size is effectively increased by one character and
changing the clocking order returns the buffer to its original size
and causes the blank cell to be lost from the buffer contents.
The procedure for deleting a character is similar to that for
inserting except that as previously noted, the clocking order is
initially X.sub.1 X.sub.3 X.sub.2 and switches to X.sub.1 X.sub.2
X.sub.3. Again, the order is changed when a blank cell is seen at
the buffer input in .phi..sub.4 time. In this way a blank cell is
added to the buffer contents at the expense of the deleted
character. It will also be apparent that whether a delete or skip
function occurs, depends on whether the system is respectively in
Draft or Final mode.
Referring now to FIG. 15, there will be seen a schematic diagram
detailing elements of right-hand margin adjust logic 66. As shown,
the schematic of FIG. 14 includes a plurality of input terminals,
at least three of which, 481, 482 and 484, are respectively
connected to the SP (space) output line from decoder 284, the H
(Hyphen) line from decoder 284 and the CR (Carrier Return) output
line from decoder 284 all shown in FIG. 9. To provide clocking for
the system of FIG. 14, there are three input terminals, 485, 486,
and 487 which are respectively connected to the outputs of gates
128, 130 and 134 (FIG. 6). Input terminal 488 is connected to a
sensor on the baseplate which provides a signal when the carrier or
print head has arrived at the beginning of a return zone, i.e., a
predetermined distance from whatever righthand margin as may have
been set by an operator of the printer. Similarly, terminal 490 is
connected to a sensor in the baseplate which indicates that a
Carrier Return is being executed. Lastly, there are two additional
input terminals, terminal 492 which is connected to the output of
counter 190 (FIG. 6) and terminal 494 which is typically connected
to a source of an inverted signal, indicating that the system is
not in the Draft Mode of operation, such as terminal 387 (FIG.
12).
Terminals 488 and 487 are respectively connected to the J and clock
terminals of J-K type flip-flop 496. The Q output terminal of
flip-flop 496 is connected to the C input terminal of D-type
flip-flop 498. The D terminal of the latter is clamped at some high
voltage V.sub.cc. The Q output terminal of flip-flop 498 is
connected to output terminal 146 (FIG. 6). Terminals 492 and 487
are connected as inputs to AND gate 500. The output of the latter
is connected as one input to OR gate 501. Another input to OR gate
501 is connected to terminal 494. The output of gate 501 is
connected to a disabling input terminal of flip-flop 498.
Terminal 494 is also connected as an input to OR gate 502, and
another input to Or gate 502 is connected to terminal 490. The
output of OR gate 502 is connected to a disabling input terminal of
flip-flop 496.
Terminals 480 and 482 are connected as inputs to OR gate 504. The
output of the latter and terminal 484 are both connected as
respective inputs to OR gate 506. The output of gate 506 and
terminal 485 are both connected as inputs to AND gate 507. Terminal
485 is also connected, together with the Q output of flip-flop as
inputs to AND gates 508. The output of gate 508 is connected to the
C input terminal of D-type flip-flop 510. The D input terminal of
flip-flop 510 is connected to the output of gate 504.
The output of gate 507 is connected to the C input terminal of
another D-type flip-flop 512. The D terminal of the latter is
clamped at voltage V.sub.cc. A disabling input terminal of
flip-flop 510 is connected to the Q output terminal of flip-flop
496. Similarly, an inverting enabling input terminal of flip-flop
512 is connected to the Q output terminal of flip-flop 498. The Q
terminal of flip-flop 510, the Q terminal of flip-flop 496 and the
Q terminal of flip-flop 498 are all connected as inputs to AND gate
514. The output of the latter is connected to the S input terminal
of a RS type flip-flop 516. The R input terminal of flip-flop 516
is connected to terminal 490. The Q output terminal of flip-flop
516 is connected to terminal 517.
A second RS type flip-flop 518 is provided, and its R terminal is
connected to the Q terminal of flip-flop 496. An in-modulo-8
counter 520 is also included and has its input connected to
terminal 486. A reset input terminal of counter 520 connected to
the Q output terminal of flip-flop 498. The output of counter 520
is connected as one input to AND gate 522. The Q terminal of
flip-flop 512 and the Q terminal of flip-flop 498 are also
connected as inputs to gate 522. The output of gate 522 is
connected both terminals 524 and the S input terminal of flip-flop
518.
The operation of the circuit shown in FIG. 15 is intended primarily
to provide an anticipatory margin control i.e., to sense when the
return zone has been entered and to return the print carrier or
print head to the lefthand margin if and when an opportunity to do
so exists, or if no such opportunity exists then to indicate that
hyphenation is going to be required. In order to do so, the circuit
takes advantage of the fact that cycling the buffer memory through
a 200-shift by triggering flip-flop 140 (FIG. 6), can be done in an
extremely short period of time and will permit a search through the
buffer memory contents to indicate whether an opportunity exists to
return the carrier or printhead before printing the first character
in the return zone. These opportunities to return the print carrier
or printhead exist when a space, a carrier return, or a hyphen is
found to occur among data stored in the buffer memory corresponding
to characters to be printed or operations to be carried out while
the carrier or printhead is in the return zone. If no return
opportunity is found, then the system is intended to stop printing
and provide some indication, visually, or audibly or otherwise,
that the operator must intervene and hyphenate. It has been found
that the optimum return zone, at least for ordinary text in the
English language, should be between about six to about ten spaced,
and preferably is eight spaces long to afford a reasonable minimim
of intervention by the operator. Thus the right margin sensor in
the baseplate is positioned so that it will provide a signal when
the carrier or printhead is at the beginning of or entering the
return zone. In the example shown in FIG. 14, the return zone is
intended to be eight spaces long.
Flip-flops 496 and 498 are not enabled unless the system is in the
Final Mode, because of the signal applied at terminal 494 and
passed by gates 501 and 502. When so enabled, and when the
beginning of return zone is reached so that the baseplate sensor
provides a signal at terminal 488, flip-flop 496 will be triggered
by the next .phi..sub.4 clock pulse at terminal 487, and the Q and
Q terminals of flip-flop 496 respectively go high and low. The Q
output of terminal 496 then triggers flip-flop 498 so that its Q
terminal goes high and a signal is therefore applied at terminal
146 to initiate a 200 shift in the buffer memory. The same signal
from flip-flop 498 enables counter 520 which starts counting
.phi..sub.2 pulses at terminal 486. The capacity of counter 520
should be matched to the number of spaces in the return zone, and
therefore, in the example shown, counter 520 is an in-modulo-8
counter. When counter 520 has counted eight input .phi..sub.2
pulses, it provides an output signal to gate 522. The Q terminal of
flip-flop 498 which of course remains high during the execution of
the 200 shift, is also connected as an input to gate 522.
Gates 504 and 506, together constitute a three input OR gate which
examines the signals at terminals 480, 482, and 484, so that as the
buffer memory is shifted, at least during the first eight shifts
counted by the counter 520, the buffer contents are monitored for
the three return opportunities of carrier return, hyphen or space.
If no return opportunity is seen, the output of gate 507 remains
low and the Q output of flip-flop 512 therefore stays high. Thus if
counter 520 has completed its count, gate 522 will provide an
output signal only if no return opportunity existed within the time
period during which counter 520 was counting. This output signal
from gate 522, then applied to terminal 524, is used to reset at
least print mode flip-flop 413 so that the printing operation of
the printer is stopped. Simultaneously, the same output of gate
522, being applied to the set input terminal of flip-flop 518
brings the Q output terminal of the latter up. The Q output
terminal of flip-flop 518 is connected to some indicator such as a
light, buzzer or the like which is identified by the operator as
indicating that the printing has stopped, and that the operator
should then continue to print out one character at a time until an
opportunity to hyphenate occurs, whereupon the operator should add
a hyphen by striking the hyphen key on the keyboard. Then, by
striking the carrier return key, which of course will not be
recorded, the printhead or carrier will be brought back to the left
margin and the carriage indexed.
If however, while counter 520 is counting, gate 504 detects either
the presence of a Hyphen, a Carrier Return, or a Space signal at
the output of the buffer memory, flip-flop 512 will be triggered on
the next .phi..sub.4 pulse. The output of the Q terminal of
flip-flop 512 will then be driven low. Thus, no high signal will
appear at terminal 524 to stop the printing operation, nor will
flip-flop 518 be triggered to indicate that a need for hyphenation
exists.
As soon as the 200-shift has been completed, a Terminate Shift
signal from counter 190 is applied to gate 500, and on the ensuing
.phi..sub.4 pulse flip-flop 498 is reset, bringing the Q terminal
of the latter high. The high signal at the Q terminal of flip-flop
498 serves to enable gate 508 and also provides a Q input to gate
514.
Because the system is still in the Final Mode of operation, the
buffer memory will continue being shifted one shift at a time to
bring up at its output the successive characters or operators
stored in the memory. Ultimately, the return opportunity (or the
first of several) earlier detected will be present at the output of
the buffer memory. If that return opportunity is a Carrier Return
signal then it will simply be executed by the printer, and its
execution will cause a signal at terminal 410 to reset flip-flop
496. The Q terminal of the latter then goes high and forces the Q
terminal of flip-flops 516 and 518 to go low, essentially resetting
the latter.
If however the return opportunity takes the form of a Space or
Hyphen signal, then flip-flop 510 will be triggered on the
.phi..sub.1 pulse associated with printing the Space or Hyphen. The
Q terminal of flip-flop 510 then goes high and is applied to gate
514. Because gate 514 now will have all of its inputs high, the Q
terminal of flip-flop 516 goes high. The high signal on terminal
516 is intended to force a Carrier Return by being applied as the
Force CR input to gate 295, (FIG. 9). Thus, the occurrence of a
Space or Hyphen signal in the return zone will result in such a
signal being executed, and immediately thereafter a Carrier Return
signal being created to force the printer to return to the lefthand
margin and index. It will be seen (referring particularly to FIG.
9) that a high signal at terminal 517 will constitute an input to
gates 295 and thus be applied through gates 300 and 292 to disable
gates 280 and 286. This serves to prevent printing of any operator
of character then at the buffer memory output until the forced
Carrier Return function has been completed.
While counter 520 preferably counts the same number of spaces as
the return zone contains, the counter need not be so limited and
may be provided as an adjustable counter which can be set to count
any arbitrary number. Thus, by simply adjusting the counter, one
can effectively change the length of the return zone for any given
system, without mechanical alteration of the printer.
FIG. 16 illustrates schematically the logic for maintaining and
adjusting an indented paragraph format. It comprises an OR gate 570
having two input lines, one connected to terminal 418 (FIG. 12) so
as to receive the Print Mode signal and the other connected to a
terminal 572 so as to receive a so-called SKIP signal. As seen in
FIG. 13, terminal 572 is connected to the output line of an OR gate
574 which has three input lines which are connected to the Q
terminals of flip-flops 466, 468 and 470. The output line of OR
gate 574 goes high to generate the skip signal whenever any one of
the Q terminals of flip-flops 466, 468 and 470 goes high, which can
occur only when the apparatus is operating in the FINAL Mode and
one of the character, word, and line buttons 45, 39 and 40 is
depressed. The output line of OR gate 570 is connected to one of
the input lines of an AND gate 576. The latter has three other
input lines; one is connected to terminal 170 (FIG. 6) so as to
receive the X.sub.1 timing signal, another is connected to a
terminal 578 which is connected to the carrier return (CR) output
line of the operator decoder 284 (FIG. 9) so as to receive the
carrier return output signal (CR/O) of the buffer, and the last is
connected to a terminal 580 which is connected to the S output line
of buffer 94 (FIG. 5) so as to receive a signal indicative of the
presence of an S-bit at the output of the buffer. The output line
of AND gate 576 is connected to one of the input lines of an OR
gate 582. The latter has three other input lines, one connected to
a terminal 584 (FIG. 14) on which is applied a Step Left Over A Tab
signal which appears on the output line 584 of AND gate 530 (FIG.
14), another connected to a terminal 486 on which is applied a
signal when any tape search is being conducted, and the last
connected to the output line of an AND gate 590. Terminal 586 is
connected to the motor drive circuits 366 (FIG. 11) so that a
signal appears at that terminal whenever any one of the motor
circuits is energized to effect a tape search action. AND gate 590
has three input lines, one connected via an inverter 600 to the
Print Mode signal terminal 418, another connected to a terminal 602
at which is applied a carrier return signal CR/S which is derived
from the carrier return sensor of the baseplate (hence, terminal
602 is connected to the CR input line of encoder gates 76 of FIG.
4), and the last connected to the output line of an AND gate 604.
The latter's output line also is connected to one of the input
lines of an AND gate 606 that has a second input line connected to
the output line of inverter 600 and a third input line connected to
a terminal 608 on which appears a TAB/S signal which is derived
from the tab sensor of the base plate (hence, terminal 608 is
connected to the TAB input line of encoder gates 76 of FIG. 4).
The output line of AND gate 606 is connected to an input line of an
OR gate 612. A second input line of the same OR gate is connected
to the output line of an AND gate 614 that has four input lines.
One of these four input lines is connected to a terminal 616 on
which appears a TAB/O signal. The latter signal is the signal which
appears on the TAB output line of the Operator Decoder 284 (FIG.
9). A second input line is connected to terminal 418 so as to
receive the PRINT MODE signal. A third input line is connected to
terminal 580 so as to receive the S-Bit at buffer output signal.
The fourth input line is connected to terminal 170 so as to receive
the X.sub.1 timing signal.
The output line of OR gate 612 is connected to the increment input
line of a 4-bit counter 620 which is designated the TABR counter.
The Clear input line of TABR counter 612 is connected to the output
line of OR gate 582 while its four output lines are connected to
input lines of a 4-bit comparator 622. A second 4-bit counter 624
also has its four output lines connected to comparator 622, while
its increment input line is connected to terminal 608 so as to
receive the TAB/S signal and its Clear line is connected to
terminal 602 so as to receive the CR/S signal. Counter 624 is
designated the TABX counter. Comparator 622 is adapted to produce
an output signal (its output line goes high) whenever the count of
TABR counter 620 exceeds the count of TABX counter 624. The
comparator's output line is connected to the Reset terminal of a JK
flip-flop 626 whose K terminal is grounded and whose J terminal is
coupled to its Q terminal. The C or Clock terminal of flip-flop 626
is connected to terminal 602 so as to receive the CR/S signal. The
Q terminal of flip-flop 626 is connected to an output terminal 628.
The signal appearing at that terminal is designated TAB/F to
designate a TAB forcing function. Terminal 628 is connected to an
input line of enable gates 295 (FIG. 9) and also to an input line
of OR gate 300. Additionally, enable gates 295 have an output line
which is connected to an input line of an OR gate 630 (FIG. 9)
which has a second input line connected to the TAB output line of
Enable Gates 286. The output of OR gate 630 is designated TAB and
is applied to the base plate.
The AND gate 604 has two input lines. One is connected to a
terminal 632 at which appears the Shift to Upper Case signal SH/S,
which is the signal from the baseplate appearing on the Shift line
of encoder gates 76 (FIG. 4). The other input line is connected to
the Q terminal of a D type flip-flop 634. The D terminal of
flip-flop 634 is connected to a positive voltage source while its Q
terminal is unused. Its C terminal is connected to the terminal 632
so as to receive the Shift to Upper Case signal SH/S. Its Clear
line is connected to a terminal 636 which is connected so as to
receive a Printer in Motion signal PIM/S (terminal 636 is connected
to the PIM input line of encoder gates 76 -- FIG. 4) which is
produced only when the print head undergoes a printing motion. The
output line of AND gate 604 is connected to an output terminal 640
which in turn is connected to the SF input line of encoder gates 76
(see FIG. 4). The signal appearing at terminal 640, designated SF,
is used to cause a required function, i.e., to cause the S-bit in a
function code to be a 1.
The above-described system for handling indented paragraphs behaves
in detail as follows:
Consider first the matter of typing a draft having one (or more)
indented paragraphs. The system is placed in the Draft or Record
mode so that operation of the keyboard will not only cause the
printing head to print but at the same time codes corresponding to
the characters printed and functions executed by the typewriter are
recorded in the mass storage medium. Assume that the operator
desires to make an indented paragraph and that the desired degree
of indentation can be achieved by striking the tab key three times.
Accordingly, at the beginning of the first line of an indented
paragraph, the operator causes the typewriter to execute three
tabbing operations and simultaneously to generate three RTAB codes.
The RTAB codes are generated by depressing the shift key on the
typewriter keyboard and, while the shift key is held down, striking
the tab key three times. Each time a TABR code is generated, the
TABR counter 620 is incremented. The incrementing of the counter is
achieved by operation of AND gate 606 and OR gate 612. In this
connection it is to be noted that the print mode signal appearing
at the terminal 418 is low since the system is not in the Print
mode. Accordingly, the input line of gate 606 which is connected to
the output line of inverter 600 is high. The input line of gate 606
which is connected to terminal 608 also goes high when the tab key
is depressed by the operator. Simultaneously the third input line
of gate 606, connected to the output line of AND gate 604, also is
high since both inputs to AND gate 604 are high. The signal SH/S
appearing at terminal 632 is high because the shift key has been
depressed. The input line of AND gate 604 connected to the Q
terminal of flip-flop 634 also is high since the flip-flop has been
toggled by the SH/S signal appearing at terminal 632 (note that the
Clear terminal of flip-flop 634 is low during tabbing since the
print head is not undergoing a printing motion). Since all three
input lines of gate 606 are high, its output line goes high.
Consequently, the output line of OR gate 612 goes high and the TABR
counter 620 is incremented. The SF terminal 640 (and thus the SF
input line of encoder gates 76) goes high with the output line of
AND gate 604. The TABX counter also is incremented each time the
tab key is operated due to terminal 608 going high.
Typing the second and third tabs while the shift key is held down
will cause the TABR counter 620 to increment in the same way once
for each additional tab. Clearing of the TABR counter 620 while
RTAB codes are being generated is prevented since all of the inputs
to OR gate 582 are low.
After recording the three required tabs, the operator proceeds to
type out the first line of the indented paragraph in the usual
manner. As soon as (a) the typewriter is downshifted or (b) a
character is printed, the SF signal appearing at terminal 640 will
go low. The SF signal will go low when the typewriter is down
shifted since the input line of gate 604 connected to terminal 632
will be low while the other input line will be high. If the
required tabs are followed by the printing of a character (with out
without downshifting), the SF signal at terminal 640 will go low
due to flip-flop 634 being cleared so that its Q terminal is caused
to go low. Flip-flop 634 is cleared by the occurrence of a PIM/S
signal that causes terminal 636 to go high.
On reaching the end of the first line of the indented paragraph,
the operator returns the print head to the left hand margin by
typing a carrier return. This causes the input line of AND gate 590
connected to the CR/S terminal 602 to go high. Simultaneously the
input line connected to inverter 600 is high since the system is
not in the Print mode. However, the third input line which is
connected to the output line of AND gate 604 will remain low since
flip-flop 634 is not toggled when an ordinary carrier return is
typed. Accordingly, the output line of AND gate 590 will remain
low. Consequently, the TABR counter 620 will not be cleared but
rather will retain its accumulated count on execution of the
carrier return. Since the SF terminal remains low during execution
of this carrier return, the S-bit of the carrier return code
entered in the buffer will be zero. Because its Clear line is
connected to terminal 602, the TABX counter 624 is cleared when the
CR/S signal is generated. As a consequence of the count in the TABR
counter now exceeding the count in the TABX counter 624, the output
line of comparator 622 will go high. This in turn enables flip-flop
626. Generation of the CR/S signal clocks the flip-flop 626,
causing the latter's Q terminal and hence the TAB/F terminal 628 to
go high. As a result, the typewriter is forced to execute tabs.
These tabs executed by the typewriter are not recorded, but their
automatic generation relieves the typist from having to enter them
and also serves as a reminder that an indented paragraph is being
typed.
The typewriter will continue to be forced to execute tabs until the
TAB/F terminal 628 goes low. This occurs when the output of the
TABR counter 620 no longer exceeds the output of the TABX counter
624. Hence it is essential that the TABX counter 624 record each
forced tab that is executed. This is achieved by action of the tab
sensor in the baseplate. Each time a tab is executed by the
typewriter, the TAB/S terminal 608 goes high and this causes the
TABX counter to increment. After the required number of tabs have
been generated, the TABX counter 624 will retain its count through
successive printing operations until the typist strikes the carrier
return key. When this occurs, the CR/S terminal 602 goes high,
causing the TABX counter to be cleared. The TABR counter will hold
its count while the second line is being typed and, if the second
line ends in a regular carrier return, three tabs will again be
forced at the beginning of the third line.
The above-described operation of counters 620 and 624 will be
repeated until the operator comes to the end of the indented
section. The end of the indented section is designated by typing a
required carrier return (RCR) which, as described above, involves
striking the carrier return key while the shift key is depressed.
As a consequence of depressing the shift key, an SH/S signal will
appear at terminal 632 and this will cause flip-flop 634 to be
clocked. Since its two input lines are both high, AND gate 604
produces an output signal which causes AND gate 590 and OR gate 582
to operate to clear the TABR counter 620. In this connection it is
to be noted that the output line of AND gate 590 will go high at
this time since all three of its inputs will be high (the input
line connected to inverter 600 will be high since the system is not
in the print mode and the input line connected to terminal 602 will
be high since a CR/S signal is generated each time the carrier
return key is depressed). Clearing of the TABR counter 620 causes
the output line of comparator 622 to go low, with the result that
the flip-flop 626 is cleared and the TAB/F terminal 628 goes low.
When the latter occurs, the system is no longer capable of forcing
execution of tabs and the print head will remain at the normal left
hand margin position. Subsequent typing by the operator will cause
the print head to return to the left hand margin each time a
carrier return is executed.
Consider now how the system operates when playing out without
Adjust, i.e., playing out in the Draft mode. During playback in the
Draft mode, the RTAB codes at the beginning of the indented section
are executed on the typewriter during printing and are also counted
and remembered as if they had been typed. Consequently, each time a
line is completed by playing a carrier return, printing of the
following line is delayed until an equal number of tabs have been
automatically generated. When the required carrier return RCR is
played at the end of the paragraph, the TABR counter 620 is reset
just as if the required carrier return has been typed by the
operator. When the first RTAB code of the indented section is
played out, the TAB/O terminal 616 of gate 614 goes high.
Simultaneously, the X.sub.1 terminal 170 of the same gate goes
high. Since the TAB/O signal appearing at terminal 616 is a
required tab, the S-bit at the buffer output terminal 580 will go
high. Also, since the system is playing the Print mode, the signal
at terminal 418 will go high. Hence all four inputs of gates 614
are high and consequently its output line will also go high. Gate
612 thus supplies a clock pulse input to the TABR counter 620,
causing the latter to increment. Counter 620 will increment in the
same manner on each succeeding RTAB code played out of the buffer.
When the last RTAB code has been played out of the buffer, the
input terminal 616 of gate 614 will go low. Consequently, the
output of gate 614 will also go low and the TABR counter will stop
incrementing. While the RTAB codes are being played out of the
buffer, the clear line of the TABR counter 620 will remain low
since the input terminals 578 and 602 of gates 576 and 590 will be
low and thus prevent the output lines of gates 576 and 590 from
going high.
During playback of the RTAB codes, the TABX counter 624 increments
at the same time as the TABR counter 620 as a result of the TAB/S
terminal 608 going high due to the typewriter executing a TAB
function. Both counters will hold their count while the remainder
of the first line of the indented paragraph is being played out.
When the end of the line occurs, a CR/O signal will appear at the
output of the huffer. Consequently, the terminal 578 will go high.
Since the carrier return at the end of the first line of the
indented paragraph is a regular carrier return, the terminal 580
will be low. Consequently, the gate 576 will be unable to cause the
gate 582 to clear the TABR counter 620. Similarly the gate 590 will
be unable to cause the gate 582 to clear the TABR counter 620 since
its input from inverter 600 will be low. However, the ordinary
carrier return signal appearing at the end of the first line of the
indented paragraph will cause the TABX counter 624 to be cleared.
This is because when the carrier return signal is played out, the
baseplate sensor for the carrier return function will cause the
terminal 602 and hence the Clear line of the TABX counter 624 to go
high. Since the TABX counter is cleared, and since the TABR counter
620 retains a count of three equal to the three tabbing operations
at the beginning of the first line of the indented paragraph, the
output line of the comparator 622 will go high and thus cause the
Clear terminal of flip-flop 626 to go low. This prevents the
flip-flop from being cleared and permits its Q terminal to remain
high (the Q terminal of flip-flop 626 will be high at this point
due to clocking of the flip-flop by the CR/S input appearing at
terminal 602). Since the Q terminal of flip-flop 626 is high, the
system is forced to execute additional tabs during the playback of
the second line. The forced tabbing will continue until the count
registered by the TABX counter equals the count registered by the
TABR counter 620, whereupon the Clear terminal of flip-flop 626 is
driven low, clearing the latter and causing the TAB/F terminal 628
to go low to stop forced tabbing. The forced tabbing operation will
be repeated at the beginning of each line of the indented paragraph
and the TABR counter, which will increment with each executed tab,
will be cleared at the end of each line of the indented
paragraph.
When the end of the indented section is reached, the RCR code
appearing at the end of the indented section will be played out. At
this point since the terminals 170, 418, 578, and 580 will all be
high, the output line of AND gate 576 will go high, causing the OR
gate 582 to drive the clear line of the TABR counter high,
whereupon the TABR counter is cleared.
If playback is conducted with Adjust, i.e., in the Final mode, the
operation is substantially the same. When RTAB codes are played at
the beginning of an indented section, they are counted as before.
Although there is no longer much correlation between recorded lines
and played lines, the required indented format is maintained by
generating the required number of tabs automatically after each
carrier return function is executed. However, it is to be noted
that when playing back in the adjust mode, the right-hand margin
control logic controls operation of the print head. With the
right-hand margin control logic in operation, a recorded ordinary
carrier return may or may not be executed on playback, depending
upon its location in the printed line. If a recorded carrier return
is skipped, the right hand margin control logic causes a space to
be substituted in its place. Accordingly, when an indented
paragraph is being played back, it is essential that the required
number of tabs not be automatically generated immediately after the
occurrence on playback of a recorded carrier return if that carrier
return is skipped and a space substituted in its place. If a
recorded carrier return is executed, the system of FIG. 15
functions in the same manner as when playback is being accomplished
in the Draft mode, i.e., without Adjust.
If a recorded carrier return is skipped, the input to terminal 572
will go high. So also will the input at the X.sub.1 terminal 170
and the CR/O terminal 578. However, the AND gate 576 will not be
enabled since the terminal 580 will be low due to the absence of an
S-bit at the buffer output. Consequently, AND gate 576 will be
unable to cause the OR gate 582 to clear the TABR counter 620.
Since when a recorded carrier return signal is skipped, the
typewriter does not execute a carrier return function, the input
terminal 602 will be low at the time that the skipping occurs.
Consequently, the TABX counter 624 is not cleared when a recorded
carrier return is skipped. The TABX counter 624 will already have a
count equal to that of the TABR counter 620 when a carrier return
is skipped by operation of the right hand margin control logic and
so the TAB/F terminal 628 will remain low so that further tabbing
cannot be forced. However, when the right hand margin control logic
terminates operation of the printer at the end of a printed line
and causes it to execute a carrier return, the terminal 602 will go
high, thereby clearing the TABX counter 624 and simultaneously
toggling the flip-flop 626 so that the TAB/F terminal 628 goes
high. The latter action forces the system to execute a number of
tabs equal to the count in the TABR counter 620 in the manner above
described. The automatic tabbling will desist when the required
carrier return (RCR) code is played out at the end of the indented
section. AND gate 576 is caused to provide a signal to the OR gate
582 and this in turn causes the Clear line of the TABR counter to
go high so that the TABR counter is cleared.
The system of FIG. 16 is also adapted to reset the TABR counter by
any tape search, so that moving from an indented paragraph to an
unindented paragraph does not result in the executed of unwanted
tabs. In this connection it is to be noted that whenever a tape
search is being conducted, the input terminal 586 will go high. As
a result, the OR gate 582 will cause the TABR counter 620 to be
cleared.
The TABR counter also is cleared whenever the buffer is stepped
left over a tab of any sort. As described earlier in the
specification, this action causes the buffer to be recycled to the
beginning of the recorded line. Accordingly, it is essential when
stepping left that any RTAB codes recorded in the line will be
played and should not also be automatically generated. On stepping
left over a tab, the terminal 584 is caused to go high, and this in
turn causes the gate 582 to operate so as to clear the TABR counter
620. The clearing of counter 620 prevents automatic generation of
additional tabs but does not prevent the system from playing out
any RTAB codes recorded in the line.
The system of FIG. 16 is also designed to distinguish between a
required function code and an ordinary shift code. This
discrimination ability is required in order to permit recording an
unrequired function immediately after a required function and also
to prevent accidental recording of required functions when typing a
text in upper case characters. As previously noted, required
functions are entered by shifting to upper case immediately before
typing the functions. This shifting to upper case toggles the
flip-flop 634 so that the output of gate 604 goes high. The output
of gate 604, appearing at S/F terminal 640, conditions the keyboard
interface logic so that required functions are recorded with the
S-bit equal to one. If an unrequired function is recorded
immediately after a required function, the SF output from the AND
gate 604 will be low since the terminal 632 will also be low when
an unrequired function is recorded. If the operator is typing text
in the upper case characters, the input terminal 632 of flip-flop
634 will be high. However, the flip-flop will be cleared by a high
input on its Clear resulting from movement of the printer head.
Consequently, the SF signal appearing at terminal 640 will be low
and hence the system will be prevented from recording any functions
as required functions when typing text in the upper case
characters.
By way partial summary, the AND gate 576 provides a Clear signal
for TABR counter 620 whenever a required carrier return has been
played or skipped. The AND gate 590 provides a Clear signal for the
same counter whenever a required carrier return is typed but not
played. The AND gate 606 generates an Increment or Clock signal for
counter 620 whenever a required tab has been typed but not played.
AND gate 614 generates an Increment or Clock signal for counter 620
whenever a required tab is printed but not skipped.
The system hereinabove described with reference to FIG. 16 offers a
number of advantages. For one thing, it is possible to enter
necessary "required codes" without the use of an additional "code
key." A second advantage is the ability to reduce the amount of
indentation of a paragraph when playing a document in the Adjust or
Final mode by skipping RTAB codes manually so that they are not
counted in the TABR counter, all of this being achieved without
affecting the recording in the mass storage medium. A third
advantage is the ability to increase the indentation of a paragraph
when playing in the Final mode by typing one or more RTAB codes
into the counter. Again, the recording in the mass storage medium
is not affected. The aforesaid second and third advantages combined
permit the ability to vary the degree of indentation of a paragraph
in one direction or the other. In this connection it is to be noted
that typing an RCR clears the TABR counter, while typing an RTAB
increments the TABR counter.
With respect to reducing the amount of indentation by skipping RTAB
codes manually as by striking the skip key, it is to be noted that
a skipped RTAB code will result in the signal at the TAB/S terminal
608 staying low since no tab function is then executed by the
typewriter. Accordingly AND gate 606 is incapable of producing a
signal to increment TABR counter 620. At the same time, AND gate
614 is inhibited from producing a signal to increment counter 620
since the signal at Print Mode terminal 418 is low (the latter
signal does not go high when a skipping operation is being
executed). Hence if, for example, the first line of the recorded
indented paragraph begins with three RTAB codes and one of said
codes is intentionally skipped on playback, the first line will be
printed out with only two RTAB codes being executed and TABR
counter 620 will increment only twice. The counter will hold this
count during playback of the succeeding lines of the indented
paragraph, with the result that two rather than three tab-forcing
signals will be generated and applied to the typewriter/base-plate
at the beginning of each succeeding line. Thus indentation of all
of the lines of the printed paragraph is reduced uniformly.
It is also possible fully to eliminate the indentation of a
paragraph or to reduce the amount of indentation when operating in
the Final or Adjust Modes by playing out some or all of the
Required Tab codes at the beginning of the indented section,
stopping the playing out, and then typing a Required Carrier Return
while still in the Final or Adjust Mode. The Required Carrier
Return that is typed in is not entered in the buffer memory, but it
does act to reset TABR counter 620. If then the typewriter platen
is reverse indexed so as to return the paper sheet on which
playback printing is to be recorded, back to the line position it
occupied when the Required Tab codes were being played out, and
playback printing is then resumed, the remainder of the first line
of the recorded indented paragraph will be printed out. This
printed first line of the recorded indented paragraph will have
lesser or no indentation according to how many of the recorded
Required Tab codes had been played out before the Required Carrier
Return was typed. If the latter action occurred after all of the
RTAB codes had been played out, the TABR counter will remain in the
Clear condition, and hence not only the first line but all
following lines of the same paragraph will be played out with no
indentation. If less than all of the RTAB codes had been played
before the required carrier section was typed, the TABR counter
will be incremented when the remaining TABR codes are played out,
and all subsequent lines will have the same amount of indentations
as the first line as a result of tab-forcing signals equal in
number to the count in the TABR counter being generated at the
beginning of each succeeding line.
When one increases the extent of indentation by typing a number of
Required Tabs in the Final or Adjust Modes, no RTAB codes are
entered into the buffer. However, the execution of each Required
Tab causes TAB/S terminal 608 to go high, and AND gate 606 will
cause TABR counter 620 to increment once for each Required Tab that
is typed. The counter will retain its increased count while the
remainder of the paragraph is being played out with the result that
each succeeding line of that paragraph will be indented to the same
extent as the line at which the RTAB codes were originally
added.
Since certain changes may be made in the above apparatus without
departing from the scope of the invention herein involved it is
intended that all matter contained in the above description or
shown in the accompanying drawing shall be interpreted in an
illustrative and not in a limiting sense.
* * * * *