Editing And Revision System

Abstract

An electronic system for editing and controlling the format of information reproduced on a sheet of paper or other recording device from an automatic input system. The edit control system may be divided into two of the parts, the first of which is the edit control portion and the second is the margin control portion. The edit control portion enables the user to automatically stop the input device after a plurality of preselected information groups have been sensed, as for example a character, a word, a line, a sentence, or a paragraph. The particular group to stop the system is selected by actuating the desired mode switch. This portion of the system may be operated in any one of the print, nonprint or skip modes and the operator may manually enter information onto the recording device after the the automatic input system has been stopped by the edit control. In this way corrections may be easily entered onto the recording device and the information input device may be corrected. The margin control provides different degrees of control, designated herein as the margin control, the automatic edit control and the tab control modes of operation. The margin control mode of operation controls the right-hand margin of the output printer according to the preset margin stop to insure that information is not printed on the paper beyond a preselected extension of the margin stop, irrespective of the length of the information group being recorded. This preselected extension is designated the right-hand margin zone and is adapted to cause preselected automatic operations of the automatic input device. The automatic edit mode is utilized to specifically control the data printed in the right-hand margin zone to permit the operator to manually control the amount of data printed in the right-hand margin zone. The tab control mode controls the left side margin or the number of tabs starting from the left-hand margin for a given data group. With the system in the margin and tab control modes, the system counts and stores the number of tabs on the first line of the data group, and generates the same number of tabs after a carrier return is acted upon. This stored number of tabs is skipped from the reader after the first line in the data group.

Description

The purpose of the foregoing abstract is to enable the Patent Office and the public generally, and especially the scientists, engineers or practitioners in the art who are not familiar with patent or legal terms or phraseology, to determine quickly from a cursory inspection the nature and essence of the technical disclosure of the application. The abstract is neither intended to define the invention of the application, which is measured by the claims, nor is it intended to be limiting as to the scope of the invention in any way.

BACKGROUND AND SUMMARY OF THE INVENTION

This invention relates to business machines and more particularly to business machines of the type comprising printer means operable manually and automatically through use of data storage control devices such as punch paper tapes and cards, magnetic tapes and discs, etc.

The invention, as disclosed, may be utilized in connection with an automatic writing system of the type disclosed in copending application Ser. No. 227,767 filed Oct. 2, 1962 for Writing System. In preparing documents utilizing a writing system of the type disclosed in the copending application, a tape is normally concurrently prepared with the preparation of a draft of the document. Upon subsequent review of the document, it frequently occurs that errors, omissions or duplications are present and it is desired to correct these errors without completely retyping the document.

Also, it often occurs that a document prepared in one format may be desired to be changed to a different format, that is, by either compressing or extending the lines of type. Obviously, to change the format of the document manually would involve a great deal of time and effort on the part of the user.

The edit control portion of the system of the present invention includes provisions for sensing the occurrence of various data groups including the sensing of an occurrence of a character, a word, a sentence, or to stop the data input system after each character or space or other data group when the system is in the automatic edit mode of operation. In this way, additional information may be inserted into the output data storage devices including a printed page or a recording tape.

In the margin control subsystem, various operation or function codes are either translated to other function or operation codes or are eliminated from the output system. For example, carrier return operations which do not occur in the right-hand margin zone are translated into a single-space operation unless the carrier operation is preceded by a punctuation. In this latter case, two spaces are generated in the control system. Also, space or tab operations which occur in the right-hand margin zone are converted into a carrier return operation to insure that data is not recorded in the same line after a logical break in the line is sensed. It is to be understood that consecutive space or tab operations which occur in the right-hand margin zone are converted into a single carrier return operation by eliminating subsequent carrier returns.

A hyphen may be sensed either in the right-hand margin zone or outside the right-hand margin zone. In the former situation, the hyphen is printed or transmitted to the output device and a carrier return is generated after the hyphen to start a new line in the output device. However, if a hyphen is sensed outside the right-hand margin zone, the hyphen is skipped and any carrier return following the hyphen is also skipped. Provision has been made in the system for printing a hyphen irrespective of where that hyphen is sensed. In providing this feature, a precedence code is generated before the hyphen to signify that the hyphen will be outputted no matter whether it occurs in or out of the right-hand margin zone. If the precedence code hyphen appears out of the right-hand margin zone and is followed by a carrier return, the carrier return is skipped.

Similarly, if the precedence code hyphen is read in the right-hand margin zone, a carrier return operation is generated whether there is a carrier return in the data input device or not. Also, the carrier return operation code is transmitted to the output device even though it occurs outside of the right-hand margin zone when it has been preceded by a precedence code condition.

Accordingly, it is one object of the present invention to provide an improved edit control system.

Another object of the present invention is to provide an improved system for stopping the input of data from a data storage device upon the occurrence of a preselected data event to permit the manual control of data output.

It is another object of the present invention to provide an improved system for detecting the occurrence of a preselected data event for editing purposes.

It is a further object of the present invention to provide an improved control for a data system, the control being operable upon detection of the occurrence of preselected data groups to stop the automatic data input device for inspection of the data by the operator and such editing as may be required.

It is still a further object of the present invention to facilitate the editing procedures for a recording and/or printing apparatus.

Another object of the present invention is to facilitate the location of data information by preselected characteristics to permit the manual control of correcting procedures of that data.

It is still a further object of the present invention to provide an improved automatic editing system which is operative only in preselected data zones.

It is a further object of the present invention to provide an improved system for controlling the format of data presented on a data output storage means.

It is another object of the present invention to provide an improved system for automatically compressing and/or expanding the format of data presented on an output data storage device, as for example a printed page.

It is still a further object of the present invention to provide an improved means for automatically changing or establishing right-hand margins of text during data storage device controlled operations of a printer.

It is still a further object of the present invention to provide means for automatically varying printer operations when the printer is in a preestablished right-hand margin control zone.

It is still another object of the present invention to provide an improved system for establishing the proper use of hyphens depending on whether the data is being reproduced in the right-hand margin zone or out of the right-hand margin zone.

It is another object of the present invention to provide an improved sensing means to sense the occurrence of certain conditions in the margin zone and to initiate operation of control means by which the operations necessary to obtain the desired margin changes may be effected.

It is still a further object of the present invention to provide an improved apparatus by which the automatic means for stopping a data storage device controlled operation of a printer upon the occurrence of a preselected data group may be combined with an improved means for automatically changing right-hand margins of the text being printed.

Further objects, features and advantages of this invention will become apparent from a consideration of the following description, the appended claims and the accompanying drawings in which:

FIG. 1 is a schematic diagram of a portion of a preferred edit and margin control system incorporating certain features of the present invention and designated circuit AH 10.10;

FIG. 2 is a schematic diagram of another portion of the preferred embodiment of the present invention and designated circuit AH 20.10;

FIG. 3 is a schematic diagram of another portion of the system of the present invention and designated circuit AH 30.10;

FIG. 4 is a schematic diagram of still another portion of the preferred system and is designated circuit AH 40.10;

FIG. 5 is a schematic diagram of the remaining portion of schematic circuit AH 40.10;

FIG. 6 is a schematic diagram of still a further portion of the preferred embodiment of the present invention and designated circuit AH 50.10;

FIG. 7 is a schematic diagram of another portion of the preferred system and designated circuit AH 60.10;

FIG. 8 is a schematic diagram of the remaining circuit details of the system of the present invention and is designated circuit AH 70.10;

FIG. 9 is a schematic diagram of a preferred interconnection circuit for the system of the present invention;

FIG. 10 is a timing diagram illustrating the timing relationships between various pulses generated within the system when the system is in the margin control mode and a period is sensed, a subsequent carriage return being converted to two spaces;

FIG. 11 is a timing diagram illustrating the relative timing relation of pulses generated within the system wherein the system is set to stop after a period and spaces when in the sentence mode;

FIG. 12 is still another timing diagram illustrating the operation of the system when set to stop after a space is sensed, the system being in the word mode;

FIG. 13 is still another timing diagram wherein the system is set to stop after a carrier return while in the line mode and not in the margin control mode;

FIG. 14 is a timing diagram illustrating the operation of the system when the system is set to stop after two carrier returns while in the paragraph mode and not in the margin control mode;

FIG. 15 is a timing diagram illustrating the operation of the system wherein the system converts a carrier return into a space at the left-hand margin zone while in the margin control mode;

FIG. 16 is still another timing diagram illustrating the operation of the system wherein the system ignores a carrier return at the left-hand margin zone while in the margin control mode;

FIG. 17 is a timing diagram illustrating the operation of the system wherein a carrier return is converted into two spaces at the left-hand margin zone while the system is in the margin control mode because of punctuation code before carrier return;

FIG. 18 is a timing diagram illustrating the operation of the system in the margin control mode wherein a hyphen code is ignored at the left-hand margin zone;

FIG. 19 is another timing diagram illustrating the operation of the system in the margin control mode wherein a space or tab is converted into a carrier return in the right-hand margin zone;

FIG. 20 is still a further timing diagram illustrating the operation of the system in the margin control mode wherein a hyphen code is read in the right-hand margin zone and is acted upon and wherein the system generates a carrier return following the hyphen;

FIG. 21 is a timing diagram illustrating the system in the autoedit mode wherein the system automatically stops after a shift or print code upon entering or while in the right-hand margin zone;

FIG. 22 is a further timing diagram illustrating the system in the autoedit mode wherein a space or tab is converted into a carrier return upon entering or while in the right-hand margin zone;

FIG. 23 is still another timing diagram illustrating the operation of the system in the autoedit mode wherein a carrier return is generated after a hyphen; and

FIG. 24 is a timing diagram illustrating the operation of the system in the tab control mode wherein the number of tabs of the first line is counted and the system subsequently generates the requisite number of tabs. The first line is determined by the sensing of two successive carrier return codes.

Referring now to FIG. 1 of the drawings, there is illustrated a system for decoding these various functions of the edit control system. Particularly, an AND gate 50 is provided to decode the occurrence of a print code on the input data bus system. The AND gate 50 is rendered responsive to a bit in channel 7 as impressed on input conductor 52, the lack of a bit in channel 8 on input conductor 54 and the generation of the clock C pulse on input conductor 56. Upon the occurrence of the clock C pulse, the output of AND gate 50 will drop to a logical zero level to provide an output on conductor 58 and also an input to inverter 60.

The operation codes are sensed by an operation decode AND gate 64 which includes inputs from data bus 7 to indicate the lack of a bit in channel 7 as sensed by input conductor 66, the lack of a bit in channel 8 as sensed by the input conductor 54, the fact that the system is not in the control code mode as sensed by input conductor 68 and the presence of a clock C signal on input conductor 56. The output signal from gate 64 is fed through an inverter circuit 70 to an operations output conductor 72.

The circuit of FIG. 1 includes a plurality of decode gates to sense certain alphanumeric codes and typewriter functions, as for example a hyphen, period, question mark, exclamation point, and the colon, all of the above gates being generally designated a punctuation gate. The system also includes gates for sensing the tab, carriage return, space, upper shift and lower shift codes commonly designated as operation decode gates.

Particularly, a hyphen AND gate 80 is provided with inputs from an edit input conductor 82, input signals from the reset sides of data bus channels 1, 3, 4, 6 and 5, as indicated by the plurality of input conductors 84 to the gate 80, an input signal from the print decode inverter 60, as fed thereto by means of a conductor 86, and an input signal from a shift memory flip-flop 90, as fed thereto by means of a conductor 92. As will be seen from a further description of the shift memory flip-flop 90, the flip-flop 90 is set in response to the sensing of an upper shift code and reset in response to the sensing of a lower shift code.

With the above conditions true, the output of gate 80 will drop to a logical zero level to provide an input to an inverter circuit 96, the output of the inverter circuit 96 being fed to a hyphen output conductor 98. The output of inverter 96 is also fed through a differentiator circuit 100 to set the hyphen flip-flop 102 by means of a conductor 104. The output of the reset side of the hyphen flip-flop 102 provides an output signal to a hyphen output conductor 106.

The output of the hyphen flip-flop 102 is fed to a hyphen line output AND gate 110 by means of a conductor 112, the input of the AND gate also being responsive to a line input conductor 114 as fed thereto through an inverter circuit 116. The flip-flop 102 is reset by either a reset signal fed through a reset input conductor 120 or by means of a differentiator circuit 122. The differentiator circuit 122 provides a resetting signal at the end of the print hyphen and skip signals, which are fed thereto by means of an omit input conductor 126, the hyphen signal on conductor 128 and the print signal as fed by means of conductors 130 and 132.

The first punctuation mark or period is sensed by means of an AND gate 140 which includes inputs from data bus channels 1, 2, 4, 5 and 6 by means of input conductors 142 and an input from the print decode input conductor 130. The output of the period gate 140 is fed by means of conductors 146, 148 to a punctuation flip-flop 150 to provide an indication on a punctuation output conductor 152 that a period or some other punctuation function has been sensed. The flip-flop 150 is reset by means of a signal on the reset conductor 120 and is also reset by means of a differentiator circuit 156.

The differentiator circuit 156 is responsive to input signals from a clock D input conductor 158, the omit conductor 126, the removal of an output signal from one of the punctuation gates including gate 140 as fed to the differentiator circuit 156 by means of a conductor 160 or the sensing of a space, tab or carriage return operation as fed thereto by means of a conductor 162. This latter signal will be more fully explained in conjunction with an explanation of the OR gate connected to the conductor 162.

Accordingly, the flip-flop is reset at either the space, tab or carriage return or the sensing of a print code which does not include a punctuation mark when the system is not in the skip or upper shift modes.

The punctuation flip-flop 150 is similarly set by means of question mark, exclamation point and colon AND gates 170, 172, 174, respectively, the outputs of the gates 170, 172, 174 being interconnected and connected to the setting output conductor 148. The question mark gate 170 is rendered responsive to signals on the data bus channels 3, 4, 5 and 6 by means of conductor 178, and also is rendered responsive to a print decode signal on conductor 130. The gate 172 is rendered responsive to bits in channels 1, 2, 4, 5 and 6 as fed thereto by means of conductors 182 and also is rendered responsive to a print decode signal on conductor 130.

Finally, gate 174 is rendered responsive to bits in data channels 1, 2, 3, 4, 5 and 6 as fed to gate 174 by means of conductor 184, the gate 174 being similarly rendered responsive to a print decode signal on conductor 130. All of the gates 170, 172, 174 set punctuation flip-flop 150 and reset the flip-flop 150 in a manner similar to that described in conjunction with gate 140.

Certain operation functions are sensed and decoded by the system of FIG. 1, particularly the tab, carriage return, space, upper shift and lower shift functions. The tab operation is sensed by means of a tab gate, the gate 188 including an input from data bus channel 1 as impressed on input conductor 190 and an input from the operation inverter circuit 70, the signal from inverter 70 being fed to the gate 188 by means of a conductor 192. The carriage return operation is sensed by means of an AND gate 194 which includes an input from data bus channel 2, as impressed on input conductor 196, and also an input from the operation inverter 70. The space function is sensed by a space gate 198, the gate 198 including an input from data bus channels 3 and 4 and also an input from the inverter 70.

The upper shift and lower shift operations are sensed by an upper shift gate 200 and a lower shift gate 202, the gate 200 being rendered responsive to a signal in data bus channel 3 and 4 and the gate 202 being rendered responsive to a bit in data bus channel 3 and channel 5. Both gates 200 and 202 include inputs from the operation inverter 70.

The output of upper shift gate 200 and lower shift gate 202 is fed to the shift memory flip-flop 90 and particularly the flip-flop 90 is set by means of the upper shift gate 200 and is reset by means of the lower shift gate 202. Thus the shift mode of the system is stored in the flip-flop 90. It is the flip-flop 90 that provides an output signal from the reset side to the hyphen gate 80 and the exclamation mark gate 172 by means of the conductor 92. The output signal from the set side is fed by means of a conductor 208 to the input circuits of colon gate 174 and question mark gate 170.

The output of the upper shift gate 200 is also fed through an inverter circuit 210 and a differentiator 212 to the set side of a second shift memory flip-flop 214, the output of the set side being fed to a shift memory output conductor 216. The output of the lower shift gate 202 is fed through a differentiator circuit 220 to the reset side of the shift memory flip-flop 214 to reset the flip-flop in response to a lower shift code. The differentiator 220 is also rendered responsive to the set condition of flip-flop 214 by means of a signal on a conductor 222 to the fact that upper shift code has not been decoded as sensed by a conductor 224, to the fact that the system is not in the line and carriage return mode as sensed by a signal on conductor 226 and the generation of a clock D signal as sensed on a conductor 228. The flip-flop 214 is also reset in response to a reset signal generated on input conductor 230 to initially reset the flip-flop 214 when the system is turned on.

Certain of the operations are combined, as for example an output signal is generated from a carriage return or hyphen OR gate 236, the input of the OR gate 236 being rendered responsive to a carriage return code or a hyphen code. The space or tab functions are sensed by an OR gate 238 and the space or tab or carriage return operations are sensed by OR gate 240. Similarly, a carriage return operation is sensed by OR gate 240. Similarly, a carriage return operation is sensed by OR gate 242, a space or tab or carriage return or print operation is sensed by an OR gate 244 and the occurrence of an upper shift or a lower shift or print operation is sensed by an OR gate 246. The output signals from OR gates 236, 246 are provided on output conductors 248 to 258, respectively.

Referring now to FIG. 2, there is illustrated another schematic diagram AH 20.10 incorporating certain other features of the present invention, particularly the edit flip-flop. Specifically, a plurality of AND gates 280, 282, 284, 286, 288 provide input signals to set edit flip-flop 290 through a differentiator circuit 292 and an inverter 294. The differentiator circuit 292 is provided with an input signal from the inverter circuit 294 and also an input signal from a keyboard input conductor 298 which indicates that the keyboard is not turned and the system is in the edit mode.

The AND gate 280 is rendered responsive to an input signal from a lower shift or upper shift or print input conductor 300, an automatic edit input conductor 302, and a signal from the reset side of the edit flip-flop 290 is sensed on conductor 306. Thus the output of the gate 280 is at a logical zero level when the conditions are sensed that the system is in the autoedit mode, the edit flip-flop has not been set and an upper shift, lower shift or print code has been sensed. The AND gate 282 is rendered responsive to a word mode input conductor 310 and a space or tab or carriage return input conductor 312. Thus, the gate 282 is responsive to the system being in the word mode and sensing a space, tab or carriage return function.

The gate 284 may be characterized as a sentence mode gate and is responsive to a sentence mode signal on sentence input conductor 316 and also is rendered responsive to the sensing of a space, tab or carriage return function on conductor 212 or a punctuation signal as impressed on input conductor 318. Accordingly, the gate 284 provides a logical zero output signal in response to the system being in the sentence mode and a space or tab or carriage return has been sensed after the punctuation flip-flop has been set. The line mode gate 286 senses the line mode by means of a line input conductor 322 and also senses the occurrence of a carriage return operation by sensing a signal on the carriage return input conductor 324. The output of gate 286 will be at a logical zero level at such time as the system is in the line mode and the carriage return is set. Finally, the paragraph gate 288 includes an input signal from a paragraph input conductor 330 and also input signals from a precedence input conductor 332, a second carriage return input conductor 334 in addition to the sensing of the first carriage return by means of a signal on conductor 324.

As stated above, the output of gates 280 to 288 are connected in parallel to provide a single input signal to inverter circuit 294. Thus, when any of the output of gates 280 to 288 drop to a logical zero level, the output of inverter circuit 294 rises to a logical one level to set the edit flip-flop 290 through differentiator 292.

The edit flip-flop 290 is reset by means of a plurality of signals, the first of which is from an autoedit AND gate 338 which includes input signals from the autoedit input conductor 302 and also a carriage return or hyphen input conductor 340. Thus, the output of gate 338 is at a logical zero level whenever the system is in the autoedit mode and a carriage return or hyphen is sensed. This output signal is fed to the reset side 342 of flip-flop 290 by means of a conductor 344.

The edit flip-flop 290 is also reset by means of a power on reset circuit 348 which feeds an output signal to the reset side 342 by means of a conductor 350. This reset signal is provided whenever the system is initially timed on to reset the flip-flop to an initial state. The edit flip-flop 290 is also reset by means of a hyphen line input conductor 352 and a conductor 354, and finally the reset side 342 of the flip-flop is reset by means of an output signal from the differentiator circuit 356.

The differentiator circuit 356 includes an input from a clock D input conductor 358, a conductor 360 which senses the set condition of the edit flip-flop 290, a logical one signal on conductor 362, and the condition of the upper shift, lower shift or print line 300 rising from a logical zero to a logical one and back to a logical zero signal, as sensed on conductor 366.

A stop AND gate 368 is provided to generate a stop output signal on output conductor 370 and is rendered responsive to an input signal from conductor 362, a signal on the clock D conductor 358, a logical one output signal from an AND gate 370, a logical one signal on the autoedit conductor 302 as fed from conductor 366 and the fact that the edit flip-flop 290 has been set. The output of gate 368 is at a logical zero level whenever the edit flip-flop 290 is set, the upper shift, lower shift or print functions are sensed and the signal level on conductor 362 is at a logical one level. The gate 372 is rendered responsive to the setting of a right-hand margin zone flip-flop 380 as sensed by a signal on conductor 382 and the generation of a space or tab code on space-tab input conductor 382 as fed on conductor 384.

The right-hand margin zone flip-flop 380 is set by means of a differentiator circuit 384 and an AND gate 386. The input to the AND gate includes a hyphen line signal on input conductor 352, an input signal from a right-hand margin zone switch conductor 388, which indicates that the right-hand margin zone switch has been actuated, an input signal from the second carriage return function as fed through an inverter circuit 390 and a conductor 392 and a signal on a margin control conductor 394 as fed thereto by means of a conductor 396. The gate 386 is clocked by means of a clock C signal fed to the input circuit of the gate 386 by means of conductors 396, 398.

Accordingly, the output of the gate 386 is at a logical zero level when the right-hand margin zone switch is actuated, and the system is in the margin control mode. Also, the gate 386 is rendered responsive to the fact that the system is not skipping or in the line mode and also that a second carriage return and hyphen has not been sensed. When all of these conditions are met, the output of gate 386 drops to a logical zero level and the clock C signal causes the output signal to rise to a logical one level. This rise in signal level provides an output signal from the differentiator 384 and thus sets the flip-flop 380.

The right-hand margin zone flip-flop 380 is reset by means of a differentiator circuit 400 which resets the right-hand margin zone flip-flop 380 in response to the sensing of the carriage return operation. The differentiator 400 is rendered responsive to an omit signal on input conductor 402 and also a carriage return signal on input conductor 324. Thus the right-hand margin zone flip-flop is reset in response to the carriage return operation. The flip-flop 380 is also reset in response to an output signal from the power on resetting circuit 348 which resets the flip-flop 380 in response to the initial turn on of the system.

The input bus of the input/output system connected to the edit control system of the present invention is provided with input bus signals, specifically, an input bus 2 and an input bus 3 bit, from this portion AH 20.10 of the system. Particularly, input bus 2 gate 410 is rendered responsive to a space, tab and carriage return 2 signal on an input conductor 412. The AND gate 410 also senses the first carriage return operation by means of a signal on an input conductor 414. The gate 410 is also responsive to a margin control signal on conductor 394 and the fact that an input bus 3 signal is not being generated by an input bus 3 gate 415. The input bus 2 output signal on output conductor 418 is utilized to enable the input/output system to perform the carriage return function. When the system is in the margin control mode, the space, tab and carrier return flip-flops are set and a data bus 3 signal is not being generated from gate 416.

Input bus gate 416 generates the input bus 3 signal on an output conductor 420 to an OR circuit 472 to provide a space function signal for the input/output system. The gate 416 is responsive to the fact that the right-hand margin zone flip-flop is reset, as sensed by means of a signal on conductor 422, the sensing of a carriage return 1 signal on conductor 414, the fact that the carriage return 2 flip-flop is not set as sensed by a signal on conductor 426, and the fact that the system is in the margin control mode as sensed by a signal on conductor 394. Also, the fact that a space-tab signal has been generated to set the space or tab flip-flops, as sensed by means of a conductor 382 and finally the fact that the carriage return 2 flip-flop is not set as sensed by a conductor 428. These signals are clocked during the clock C time due to the connection of the clock C input conductor 396 to the gate 416.

Thus, an input bus 3 data bit is presented to the input/output system to cause the input/output system to perform a space function when the system is in the margin control mode, the space or tab flip-flop has been set and the carrier return 1 flip-flop has been set and finally the fact that the carrier return 2 flip-flop is not set, the system is not in the right-hand margin zone and a clock D signal is not being generated.

The setting of the right-hand margin zone flip-flop 380 by gate 386 is inhibited by a logical zero signal on conductor 362, this logical zero signal being generated by means of an AND gate 430. The gate 430 is rendered responsive to the fact that the carriage 1 flip-flop is set as sensed by a signal on conductor 414, the fact that the system is in the margin control mode as sensed by a logical one signal on input conductor 394 and the generation of a lower shift or an upper shift or a print code as sensed by means of a signal on input conductor 432. Thus, the setting of the right-hand margin zone flip-flop 380 is inhibited by an output signal from gate 430 whenever the system is in the margin control mode, and upper shift, lower shift or print code is sensed or the carrier return 1 flip-flop is set.

The system further includes a punctuation or right-hand margin zone gate 436, a reader inhibit gate 438 and a carriage return 1 and print gate 440. The gate 436 is rendered responsive to the fact that the system is not in the right-hand margin zone and a punctuation code has been read, the output of the gate 436 being a logical zero when the conditions are met. The gate 438 is rendered responsive to the fact that the system is in the margin control mode, as sensed by a signal on conductor 394, and the carriage return 1 flip-flop has been set as sensed by a signal on conductor 414 and the sensing of a space or tab or carriage return 2 signal as indicated by a signal on conductor 412.

The output of the gate 438 is utilized to inhibit the reader whenever the system is in the margin control mode and the carrier 1 flip-flop is set in addition to one of the space, tab or carrier return flip-flops being set. The final gate 440 is rendered responsive to the setting of the carrier return 1 flip-flop as sensed by a signal on conductor 414 and the sensing of a lower shift, upper shift or print code as sensed by the generation of a signal on conductor 432. Thus, the output of gate 440 drops to a logical zero level whenever the carrier return 1 flip-flop is set and an upper shift, lower shift or print code has been detected.

Finally, an additional resetting signal is generated by a reset gate 444 which includes an input signal from an AND gate 446 and an AND gate 448. The gate 446 includes an input signal from the autoedit input conductor 302 and also an input signal from the set side of the right-hand margin zone flip-flop 380. Accordingly, when the system is in the autoedit mode and the right-hand margin zone flip-flop has been set and the output of the gate 446 will be at a logical zero level. This output signal rises to a logical one level whenever either of the conditions are not met, that is the right-hand margin zone flip-flop is not set or the system is not in the autoedit mode.

The gate 448 includes an input from a differentiator circuit 450 which is rendered responsive to the rising of a start switch output conductor 452 from a logical zero to a logical one level and then dropping back to a logical zero level. The gate 448 further includes an input from a second differentiator 454 which is rendered responsive to a clock D signal on input conductor 456 and a stop signal on conductor 458.

Referring now to FIG. 3, there is illustrated a further circuit AH 30.10 forming another portion of the system of the present invention. Particularly, a skip function output conductor 466 generates a skip output signal when the system is in the margin control zone. This signal on conductor 466 is generated by means of an AND gate 468 which includes an input signal from a margin control input conductor 470 and from the output circuit of an OR gate 472. The OR gate is rendered responsive to all of the various functions of the system in which a skip function is desired to be performed. Particularly, the gate 472 is rendered responsive to the sensing of a carriage return 2 signal and a tab or upper shift or lower shift or print code being generated as sensed by a signal on an input conductor 474. The gate 472 is further responsive to the tab skip, carriage return skip and stop codes as sensed on input conductors 476, 478, 480. Also, when the system is in the right-hand margin zone mode and a space or tab operation has been sensed, an output signal will be generated from AND gate 484 due to its interconnection with the right-hand margin zone input conductor 486 and the tab or space input conductor 488.

The gate 472 is further responsive to an output signal from an AND gate 490 which includes an input signal from a hyphen input conductor 492, a right-hand margin zone input conductor 494 and a precedence code signal as generated on an output conductor 496 by an AND gate 498, and is fed to the gate 490 by means of a conductor 500. The gate 472 is further rendered responsive to a logical zero signal generated by AND gate 502, and impressed on a conductor 504, and also to a carriage return 1 and print signal on an input conductor 506, as fed thereto by means of a conductor 508. Both the operation and functions of gates 498 and 502 will be explained hereinafter. Thus the gate 472 is rendered responsive to various functional and operational conditions within the system including tab, skip, carrier return and stop. Also, the gate 472 is responsive to the condition of the system being in the right-hand margin zone mode and the setting of the carriage return 2 and space-tab flip-flops. Further, the gate 472 senses the generation of a setting signal for the hyphen or space-tab flip-flops which is followed by a print code.

The carriage return 1 output signal is generated by a carriage return 1 flip-flop 510 which generates a carriage return 1 output signal on an output conductor 512 and a carriage return 1 signal on output conductor 514. The flip-flop 510 is set in response to a signal generated in a differentiator circuit 514, the differentiator circuit 514 being rendered responsive to a condition of the carriage return 2 flip-flop and the hyphen flip-flop not being set and the sensing of a carriage return. These signals are sensed on conductors 516, 518 and 520, respectively.

The flip-flop 510 is additionally set by a signal generated from the AND gate 502 and fed to the flip-flop 510 by means of a conductor 524. The gate 502 generates a logical zero output signal in response to the system being in the right-hand margin zone, as sensed by a signal on a conductor 486 and fed thereto by means of a conductor 526, the generation of a print upper shift or lower shift code, as sensed by a signal on input conductor 528, and a logical one output signal from an OR gate 530. The OR gate 530 is rendered responsive to the resetting of a space-tab flip-flop 534 or the sensing of a hyphen. The flip-flop 510 is further set in response to a carriage return signal generated on the carriage return gen input conductor 538.

The flip-flop 510 is reset in response to a reset signal on input conductor 540, as fed thereto by means of a conductor 542, or from an output signal from either differentiator 544 or 546. The differentiator 546 is rendered responsive to a carrier return 2 signal on input conductor 548, to a 2 carriage return (2 CR) signal on an input conductor 550 and to the generation of a clock C signal, as sensed on a clock C input conductor 554. The second differentiator 544 includes input signals from the AND gate 502 as described above and a punctuation and right-hand margin zone input conductor 556. The differentiator 554 is also responsive to a logic one signal on input conductor 506, a precedence code as generated by AND gate 498, a 2 CR signal as generated on input conductor 560 and the generation of a space or carriage return 2 signal on a conductor 562. The differentiator 544 is clocked in response to a clock C signal on conductor 554 to reset the flip-flop 510.

The carriage return 2 signal is generated on an output conductor 566 by means of a carriage return 2 flip-flop 568. The carriage return 2 flip-flop is set in response to an output signal from gate 498 on a conductor 570, or an output signal from the differentiator circuit 574. The differentiator circuit is rendered responsive to a carriage return signal on carriage return conductor 520 and also to the setting of the carriage return flip-flop 510. Finally, the flip-flop 568 may be set in response to an output signal from a gate 578 which includes input signals from a paragraph input conductor 580, the set side of flip-flop 510, as fed to the gate 578 by means of a conductor 582, the fact that the keyboard is not turned on as sensed by a signal on keyboard input conductor 584, and the fact that the system is not in the margin control mode as sensed by a signal on a margin control input conductor 586 and fed thereto by means of conductors 588 to 590 and an inverter circuit 592.

The flip-flop 568 is reset in response to a reset signal on input conductor 540, as fed thereto by means of a conductor 596 or by means of an output signal from a differentiator circuit 600. The differentiator circuit 600 includes an input signal from a carriage return input conductor 602, an omit signal on conductor 604 as generated by an omit gate 606. The omit gate 606 includes input signals from the OR gate 472 and the margin control input conductor 586. Finally, the differentiator circuit 600 is clocked in response to the sensing of a space or tab or carriage return or print operation by means of a signal on input conductor 610.

The gate 530 is rendered responsive to the hyphen signal on input conductor 612 and also to the setting of the space or tab flip-flop 534. The precedence AND gate 498 provides a logical zero output signal in response to the sensing of the fact that the carriage return flip-flop 510 is not set, the space or tab flip-flop 534 is not set and that the shift memory mode is true, as sensed by a logical one signal on the shift memory input conductor 620. The reader shutter signal is generated by means of a reader shutter AND gate 622 which includes an input signal from the space or tab or carriage return signal as generated by an OR gate 624, the clock C signal generated on conductor 554, the fact that the carriage return 1 flip-flop 510 is set and the fact that the system is in the margin control mode, as fed thereto by means of a conductor 588. Thus, a reader shutter is simulated in response to the setting of the space or tab or carriage return 2 flip-flop, the fact that the system is in the margin control mode and the carriage return 1 flip-flop is set and the generation of a clock D signal.

A gate 634 is provided to permit the system to skip a carriage return operation when the gate is enabled. This carriage return skip signal is generated on output conductor 636 and the gate 634 is responsive to a logical one signal on the carriage return input conductor 520. The resetting of the carriage return 1 flip-flop is sensed by means of a conductor 638, the resetting of the carriage return 2 flip-flop 568 is sensed by means of a conductor 640, and the fact that the system is in the margin control mode is sensed by the conductor 588. Thus, a carrier return function will be skipped when the carriage return 1 flip-flop and the carriage return 2 flip-flop are not set and the system is in the margin control mode.

Referring now to FIG. 4, there is illustrated a system AH 40.10 including binary flip-flop-type counter circuit 660 which includes a first counter portion 662 which is utilized to count the number of tabs which occurs in the first line of each paragraph and a second binary flip-flop counter portion 664 which is utilized to count the number of tabs which occurs in subsequent lines of a paragraph. The system is also capable of dropping any subsequent tabs occurring after the generation of the requisite tabs as determined by the tab count of the first sentence of the paragraph.

The binary counter 662 includes a plurality of flip-flops 670, 672 and 674 corresponding to the 1, 2 and 4 bit counts. Each of the respective flip-flops are provided with input signals from differentiator circuits 676, 678 and 680 which are rendered responsive to the particular set or reset condition of the respective flip-flop by means of a feedback loop. The binary counter arrangement 662 is the typical binary counter common in the art. Input signals to the binary counter 662 are supplied by means of an AND gate 684, the gate being rendered responsive to a clock D signal on input conductor 686, an operation signal on conductor 688, a skip signal on conductor 690 and the tab code, a bit in channel 1, as sensed on input conductor 694. The gate 684 is enabled in response to the set condition of a tab count flip-flop 700, to be discussed in conjunction with FIG. 5. The tab count flip-flop 700 is responsive to the sensing of a double carriage return as will be seen hereinafter. The output of the flip-flop 700 is fed to the input circuit of the AND gate 684 by means of a conductor 702.

The gate 684, with all of the aforementioned conditions existing, will clock the data bus 1 signals on input conductor 694 to the first differentiator circuit 676. The first differentiator circuit sets the flip-flop 670 to indicate one tab having been sensed. The second signal on data bus 1 resets the flip-flop 670 and sets the flip-flop 672. The flip-flops 670 to 674 are set and reset to indicate the binary count of the tabs being sensed at AND gate 684. Upon the sensing of a carriage return, the gate 684 is disabled by means of the reset condition of flip-flop 700 (FIG. 5), as will be seen hereinafter. The flip-flop 700 is reset in response to the sensing of a single carriage return, and thereafter, the gate 684 will not transmit any further signals to the flip-flop 670 to 674 in the absence of the sensing of a double carriage return.

The counter 664 includes three binary flip-flop circuits 710, 712, 714 which are set or reset in response to three differentiator circuits 716, 718, 720 connected in the respective input circuits of the flip-flops 710 to 714. The counter circuit 664 is utilized to count the number of tabs which are generated in the second and subsequent lines of a paragraph, this tab count being fed to the counter 664 by means of an AND gate 724. The AND gate 724 is rendered responsive to an operation code as sensed on input conductor 688 and fed to the input circuit of the gate 724 by means of a conductor 726 and also the data bus 1 signal on conductor 694 as fed to the gate 724 by means of a conductor 728. The counter 664 is reset each time a tab generator signal is provided on a tab generator input conductor 730, which tab generator signal is generated each time a single carriage return is generated. This tab generate signal is provided by a tab generate flip-flop 734 (FIG. 5), as will be more fully explained hereinafter. The A binary counter 662 is reset in response to a count reset signal on input conductor 732 to reset each of the binary flip-flops 670 to 674 in response to a signal on the conductor 732.

The outputs of the flip-flops 670 to 674 and 710 to 714 are fed to a plurality of AND gates 736 to 750 in various combinations and permutations. Each of the gates 736 to 750 contains a channel from the binary counter 662 and the correlative channel from the binary flip-flop 664. Referring particularly to gate 736, the input to the gate 736 includes an input from channel 1a and channel 1b and also includes inputs from channels 2a, 2b and 3a and 3b. The signals are clocked into the gate 736 by means of a clock C signal impressed on an input conductor 754 and fed thereto by means of a conductor 756. The gates 736 to 750 are utilized to compare the outputs of each flip-flop from counter 662 with the corresponding flip-flop of counter 664.

Accordingly, each gate 736 to 750 compares corresponding channels of flip-flop 662 with flip-flop 664 to provide an output from the gates 736 to 750 when a match of the sensed channels occurs. The outputs from the gates 736 to 750 are fed through an OR gate 758 to reset the flip-flop 734 by means of a signal impressed on output conductor 760. The resetting of flip-flop 734 is sensed by a signal on the tab generator output conductor 762 (FIG. 5) which is interconnected with the tab generator input conductor 730. This latter conductor 730 resets all of the flip-flops 710 to 714 to ready the counter 664 to recondition the counter 664 for a count of the tabs in a subsequent line.

Referring now to FIG. 5, and particularly to the tab count flip-flop 700, it is seen that the tab count flip-flop is fed with a setting signal from an AND gate 770. Gate 770 includes an input from a clock C input conductor 772 as fed thereto by means of a conductor 774 and an input from the carriage return input conductor 776 as fed thereto by means of an inverter circuit 778. The gate 770 further includes an input from a tab control input conductor 780 and a carriage return input conductor 782. Thus the gate 770 provides a setting input to the flip-flop 700 in response to an output signal from the gate 770.

The flip-flop 700 is reset in response to the sensing of a single carriage return, particularly in response to an output signal from the gates 788. The gate 788 includes input signals from the output circuit of gate 770 by means of a conductor 790, an input signal from the carriage return input conductor 782 and an input signal from the right-hand margin zone conductor 792. Accordingly, the flip-flop 700 is set in response to the sensing of a double carriage return and is reset in response to the sensing of a single carriage return.

The resetting signal from gate 788 is clocked in response to the entry of the system into the right-hand margin zone as sensed by means of the right-hand margin zone conductor 792 and fed thereto by means of a differentiator circuit 794 and conductor 796. Also, the reset side of the flip-flop 700 is enabled in response to the absence of a tab control signal on conductor 780. The output of the set side of flip-flop 700, in addition to being fed to FIG. 4 by means of conductor 702, is also fed to a tab count output conductor 800. The reset side is fed as an output to a tab count output conductor 802. The tab count output conductor is also fed to the input circuit of a tab skip gate 806 by means of a conductor 808. The gate 806 provides tab skip signals to skip subsequent tabs after the right-hand margin zone has been reached and the requisite tab count has been achieved, this latter condition being sensed by the binary counter 664.

The gate 806 further includes an input from the reset side of flip-flop 734 to sense when the tab generator flip-flop 734 has been reset by the sensing of a single carriage return. The flip-flop 734 is set in response to a signal condition in differentiator circuit 810, the differentiator circuit being rendered responsive to the carriage return, a skip signal, a space-tab signal on conductor 812 and a 2 CR and carriage 2 signal on output conductor 816. The flip-flop 734 is reset in response to the sensing of a matched condition in counter 662 and 664 due to the output signal from OR gate 758 (FIG. 4), as fed to the reset side of flip-flop 734 by means of the conductor 760. The resetting of flip-flop 734 is enabled or disabled in response to the tab control mode of the system as sensed by the appropriate signal on the tab control input conductor 780.

The gate 806 further includes inputs from the keyboard input conductor 820, which indicates that the keyboard is not turned on, from the tab control input conductor 780, the operation input conductor 688, as fed thereto by means of conductor 822, and the data bus 1 signal, as fed thereto by means of a conductor 824. Thus, when the system senses subsequent data bus 1 or tab signals, these tabs are skipped by means of a tab skip signal generated on tab skip output conductor 828.

The 2 CR or carriage 2 signal on output conductor 816 is generated by means of an AND gate 830 which includes an input from the carriage 2 input conductor 776 and also a 2 CR signal on input conductor 832. An input bus 1 signal is generated on an output conductor 838 by means of an AND gate 840 and fed thereto by means of an OR gate 842. The gate 840 is rendered responsive to a clock C signal on a conductor 844, a tab generator signal from the tab generator output conductor 762 and a keyboard signal impressed on conductor 820, and fed thereto by means of a conductor 846. A reader shutter signal is generated by an output gate 850 and a reader inhibit signal is generated by an inverter circuit 852. The gate 850 includes input signals from a clock C input conductor 854 and a tab generator signal. The reader inhibit signal from inverter circuit 852 is derived from the output of a set side of flip-flop 734 or a tab generator signal.

Referring now to FIG. 6 there is illustrated a system AH 50.10 which includes a plurality of memory devices, in the form of flip-flops, which are utilized to store information derived from a plurality of mode switches utilized in conjunction with the system of the present invention. Also, the system of FIG. 6 provides driving current for visual indicators which provide an indication to the operator of the particular mode in which the system is being operated.

Specifically, FIG. 6 includes a switching circuit 860 which includes a plurality of binary flip-flops 862 to 874 which, when actuated, provide the necessary mode control signals and mode indication signals. Each of the signals is clocked into the flip-flops 862 to 874 by means of a single-shot multivibrator circuit 880 which includes a first single-shot multivibrator 882 and a second single-shot multivibrator 884. The various switches are interconnected with a switch on conductor 886 which generates a first timed signal out of single shot 880 to actuate the second switch single-shot multivibrator 884, the sum of the pulses being fed to a clocking conductor 888. The single shot multivibrator 882 includes a hyphen signal provided by means of an input conductor 892 to disable the single-shot multivibrator under certain hyphen conditions.

The word mode is provided by means of a word switch mounted on the unit which provides a word signal on a word input conductor 894, this latter signal being fed to the flip-flop 862 by means of an AND gate 896 and a differentiator circuit 898. The word signal is clocked through the AND gate 896 by means of the timing signal on conductor 888.

Assuming the flip-flop 862 to be reset initially, the first pulse from the gate 896 will set the flip-flop 862 through the differentiator circuit 898. The feedback loops of the flip-flop 862 permit the second pulse to be generated on the word switch line 894 to reset the flip-flop. The set side of the flip-flop 862 provides a control output signal for the word mode on an output conductor 900 and the reset side of the flip-flop 862 provides driving current for a word indicator output conductor 902, which may be connected to any suitable visual indicator. The flip-flop 862 is initially reset by a power on reset circuit 908 which is connected to the reset side of the flip-flop 862 by means of a conductor 910.

The line mode of operation is selected by a line switch which impresses a line signal on an input conductor 912. This latter signal is utilized in setting the flip-flop 862 by means of a gate 914 and a differentiator circuit 916. The flip-flop 864, when set, provides a line control signal on output conductor 920 and also a driver signal or a visual indicator on output conductor 922. The sentence and paragraph modes are selected by impressing a signal on input conductor 930 and 932, respectively, which signals are utilized in setting the respective flip-flops 866 and 868 through gates 936, 938 and differentiator circuits 940, 942, respectively. The tab control and margin control operations are provided by the actuation of a tab control or margin control switch which impresses an input signal on input conductors 946, 948, respectively. These signals are fed through AND gates 950, 952 and differentiator circuits 954, 956, respectively, to set the flip-flops 870, 872.

The output of the tab control flip-flop 870 is fed as a control signal on output conductor 960 and on an output conductor 962 to provide driving current for a visual indicator. The output of the set side of margin control flip-flop 872 is fed through an AND gate 966 which is also provided with an input signal from a keyboard input conductor 968, as fed thereto by means of a conductor 970, to inhibit the operation of the gate 966 when the keyboard is turned on. The output of gate 966 is inverted by means of an inverter circuit 974.

The autoedit mode is selected by an autoedit switch which impresses a signal on input conductor 980, this signal being fed through an AND gate 982 and differentiator circuit 984 to set the flip-flop 874. The output of the flip-flop is fed through an AND gate 986 and an inverter circuit 988 to autoedit output conductor 990. The gate 986 is also provided with a gating signal from a right-hand margin zone input conductor 994 to inhibit the autoedit signal when the system is not in the right-hand margin zone.

A reader shutter signal is generated on a reader shutter output conductor 998 by means of an AND gate 1000, the gate 1000 being fed with a first signal from the single-shot multivibrator 882 by means of a conductor 1002 and also with a hyphen signal through an inverter circuit 1004.

A stop signal is generated by AND gate 1010 to stop the operation of the system in response to the system being in the paragraph mode and the edit and tab count flip-flops being in the set condition. Particularly, the gate 1010 is provided with an input signal from the keyboard input conductor 968, an edit conductor 1012, a tab count conductor 1014, a paragraph or line conductor 1016 and an upper shift or lower shift or tab or print conductor 1018. The output of gate 1010 is connected to a stop output conductor 1020 and a stop conductor 1022, this latter being fed through an OR gate 1024.

The output of the stop conductor 1022 is also so fed to the input circuit of an AND gate 1030, this latter gate generating an interlock switch signal on an output conductor 1032. The gate 1030, in addition to the stop signal on conductor 1022, is provided with input signals from an upper shift or lower shift or print conductor 1034 and an operation input conductor 1036.

Upon the depression of a control switch, the word switch signal becomes true and the SWS N/O becomes false. The false SWS N/O triggers the 17 millisecond single-shot multivibrator, which in turn, triggers the second single-shot multivibrator at its trailing edge. Accordingly, 17 milliseconds after the depression of the word switch, a second positive pulse will be applied to the input gate of all of the control mode flip-flops, this second positive pulse being of a 1.6 millisecond duration. Since the logic levels of all the control switches except the word switch are false, only the word flip-flop input gate is activated. The storage capacitors of the word flip-flop will be charged during the 1.6 millisecond period and the state of the word flip-flop will be changed at the trailing edge of the single-shot output pulse. When the depressed momentary switch is released, SWS N/O becomes true and the word switch becomes false, this condition being ineffectual to change the state of the system.

As the flip-flops are reset when the power is initially turned on, the flip-flop is set when its switch is first depressed and reset when it is depressed again. The reset side of the flip-flop drives the switch indicator lamp and the switch button, in the preferred embodiment, is eliminated when the flip-flop is set to the set state. The 17 millisecond single shot multivibrator is utilized to eliminate the malfunctions caused by switch bounce of the active switch, as well as the loss of ground continuity of the common terminal of a passive switch due to mechanical vibration caused by depressing another switch.

The autoedit and tab control flip-flops are reset by the false state of the margin control flip-flop. Therefore, these latter flip-flops cannot be set unless the margin control is set.

It is important to note that an illuminated margin control or autoedit switch does not indicate that the system is in the margin control or autoedit mode. The system is only in the margin control mode when both the margin control flip-flop has been set and the keyboard is not on or when the input/output unit is in the read mode. Therefore, unless the carrier stops in the right-hand margin zone due to the autoedit mode, manual entry of carrier return, hyphen, space and tab from the keyboard will not cause margin control operations.

Referring now to FIG. 7, there is illustrated a circuit AH 60.10 for generating the various mode control and function control signals. Specifically, the two carriage return or double carriage return signal is generated by means of a flip-flop 1050 which is set in response to input signals to a differentiator circuit 1052. The differentiator circuit 1052 is provided with enabling input signals from an omit input conductor 1054 which feeds the signal to the differentiator 1052 by means of a gate 1056 and a conductor 1058. The second enabling signal is derived from a carrier return input conductor and fed to the differentiator circuit by a conductor 1062. The clocking signal for the differentiator is provided by a flip-flop circuit 1066, which is binary in nature, and is set and reset in response to signals generated at the output circuit of an AND gate 1070 and fed to the flip-flop 1066.

The gate 1070 provides an initial setting signal in response to the sensing of a carrier return signal on conductor 1060 and the second carrier return signal on conductor 1060 provides an output signal from the flip-flop 1066 through a get 1074. The flip-flop 1066 is reset by means of a signal on a reset input conductor 1080 or by a signal generated in a differentiator circuit 1082. The differentiator circuit 1082 is rendered responsive to a clock C signal on input conductor 1084, a carrier return signal on conductor 1086, and the set condition of the flip-flop 1068, as fed thereto by means of a conductor 1090.

The double carrier return flip-flop 1050 is reset in response to the reset signal on conductor 1080 or from a restore signal on a restore input conductor 1092. The output of the reset side of flip-flop 1050 is connected to a 2 CR output conductor 1094 to provide the opposite polarity signal to that on a 2CR output conductor 1096 connected to the set side of flip-flop 1050.

A 2CR (T +US +LS +PR) signal is generated by an AND gate 1100, the output of which is connected to an output conductor 1102 and the input circuit of which is provided with an input signal from the set side of flip-flop 1050 by means of a conductor 1104 and also from an OR gate 1106. The OR gate 1106 is provided with a lower shift or upper shift or print signal from an input conductor 1110 through a gate 1112. Also, the gate 1106 is provided with a tab signal on conductor 1116. Accordingly, the OR gate will provide a true output signal when the system generates a lower shift or upper shift or a print or a tab code.

The carriage return generator signal is derived from an AND gate 1120 which includes input signals from the set side of the 2CR flip-flop 1050, a clock C input signal impressed on input conductor 1084, a carrier return 1 signal on an input conductor 1122 and a carrier return 2 signal impressed on input conductor 1124.

The paragraph (SM) or line signal is generated by means of an OR gate 1130 and fed to an output conductor 1132 by means of an inverter circuit 1134. The OR gate 1130 includes an input signal from an AND gate 1136, the output of the AND gate 1136 being rendered responsive to a paragraph signal on input conductor 1138 and a (SM) signal on input conductor 1140. The OR gate 1130 further includes an input signal from a gate 1142 which provides a buffer for a line signal impressed on input conductor 1144. Accordingly, the OR gate 1130 will provide an output signal in response to the system being in the paragraph and shift memory (SM) mode or the system being in the line mode.

The line and carrier return signal is generated by means of an AND gate 1150 which includes an input signal from the line input conductor 1144 and an input signal from the carrier return input conductor 1060 as fed thereto by means of conductors 1152 and 1154.

The counter reset signal is generated by either an AND gate 1160 or an AND gate 1162 and fed to an output conductor 1164. The gate 1160 is rendered responsive to a tab control switch input signal on an input conductor 1166 and a switch single-shot signal on input conductor 1168. The second gate 1162 includes input signals from a carrier return 1 input conductor 1170 and a keyboard signal on input conductor 1172 as fed thereto by means of an inverter circuit 1174. The third input to gate 1162 is derived from the carrier return input conductor 1060 and fed thereto by means of conductors 1152 and 1178.

The clock C timing signal is generated by a clock C flip-flop 1184 which impresses a clock C signal on output conductor 1186 and a clock C output signal on conductor 1188. The flip-flop 1184 is set in response to an output signal from an OR gate 1190 which is fed to the set side of the flip-flop 1184 through a differentiator circuit 1192. The OR gate is interconnected with the data bus 1 through data bus 7 signals impressed on input conductors 1194 to 1206, respectively. These latter signals are fed through buffering AND gates 1214 to 1226. The flip-flop 1184 is reset in response to the clock D signal generated in the input/output system and impressed on an input conductor 1230. The conductor 1230 is connected to the reset side of the flip-flop 1184 through a differentiator circuit 1232.

Referring now to FIG. 8, there is illustrated a switch system 70.10 which is utilized in translating the control switch mechanical operations into electrical signals. It is to be noted that the actuation of the switch removes the ground potential from the output conductor. The one exception to this situation is the start switch 1240 which is normally not at ground potential and is placed at ground potential when the zero volt input conductor is connected to the start switch output conductor 1242.

The system includes a tab control, autoedit and margin control with word, line, sentence and paragraph switches 1244 to 1256, which are connected at one end to a ground potential on conductor 1258, and at the other end to the correlative output conductors 1260 to 1272. The output conductors 1260 to 1272 are normally grounded when the switches have not been actuated and the ground is removed at such time as one of the switches is actuated. The normal open condition of the switches is sensed and provides an output signal on switches normally open output conductor 1274. The skip switch is interconnected with a keyboard input conductor 1280 such that when the skip switch is actuated, a skip switch output conductor 1282 is connected to the keyboard input conductor 1280.

It should be noted that the start switch ground is not tied to the control switch ground at the switch bank to provide noise isolation. Upon the depression of a control switch, the particular mode switch output conductor will become true and the normally open switch (SWS) NO will become false.

FIG. 9 illustrates an interconnection system AH 70.20 and provides a common interconnection terminal for the various systems described above. It is to be noted that the particular signal involved is noted above the line and the circuits to which it is connected are noted below the line. For example, data bus 1 signal is interconnected with systems AH 10.10, AH 40.10 and AH 60.10. Certain signals are not interconnected with the various systems and are so indicated, or include the notation n.c.

FIGS. 10 to 24 illustrate the various timing sequence of various elements and circuits of the above described system as data is eliminated, generated or transmitted within the system in response to a margin control operation or the edit control operation. The examples given are merely illustrative and it is to be understood that FIGS. 10 to 24 do not represent the complete operation of the system.

FIG. 10 illustrates the mode of operation wherein the system is in the margin control mode and a period is sensed followed by a carriage return. In the margin control mode of operation where the period and subsequent carriage return are not sensed in the right-hand margin, it is desired to convert the carriage return to two spaces following the period.

As is seen in FIG. 10, the tape is encoded with a period and a carriage return followed by subsequent data signals. In the margin control mode, the sensing of a period and a subsequent carriage return causes the system to convert the carriage return to two spaces to permit the reader to continue with the particular line in the event the system has not achieved the right-hand margin zone.

Accordingly, the input/output unit will sense a period, the carriage return will be dropped and two spaces will be subsequently generated in response to the carriage return. The sensing of the period at the first clock C pulse brings up the punctuation flip-flop with a pulse and the carriage return 1 circuit is energized upon the sensing of the carriage return signal. The combination of the punctuation and carriage return signals brings up the space or tab circuit and the reader shutter is actuated to cycle the input-output timing circuit. Further, it is seen that the input bus 3 is energized with two pulses to indicate a space for each of the pulses, the space being transmitted to the input/output unit. The punctuation flip-flop causes the first space. The second space is caused by the CR 1 flip-flop as would normally be done if the carriage return were not preceded by the punctuation. The reader inhibit presents the reader from driving tape to hold the UC code in the reader.

FIG. 11 illustrates the operation of the system in the sentence mode, for example when a period and double space are sensed. The tape is coded with a period (punctuation) and two spaces which generates a series of clock C signals. The period brings up the upper shift or lower shift or print gate and also the punctuation flip-flop. The sensing of the space brings up the edit flip-flop, and the reader is stopped after the sensing of the second space. The keyboard is turned on to permit the operator to edit the data being fed to the input/output unit after the sensing of the termination of each sentence in the text.

FIG. 12 illustrates the word mode of operation wherein the reader is stopped after the sensing of each space, the indication of the termination of a word. When the letter A is sensed, the upper shift or lower shift or print gate is brought up and the edit flip-flop is set. The reader is stopped and turned off after the sensing of the space and the keyboard is turned on to permit the operator to manually enter data into the system.

FIG. 13 illustrates the system not in the margin control mode when a carrier return is sensed and the system is in the line mode. In this situation the carrier return indicates to the system that the end of a line has been reached and the system is to stop. By way of illustration, the tape is encoded with the letter A, a carriage return and a letter B. The letter A lowers the upper shift or lower shift or print gate at the end thereof and the sensing of the carrier return drops the line and carrier return gate 286. The sensing of the end of the carrier return signal brings up the edit flip-flop 290 and upon the sensing of the character B a stop signal is generated which stops the reader. At such time as the reader is stopped the keyboard is turned on to permit the operator to enter edit material into the printed page.

Referring now to FIG. 14 there is illustrated the operation of the system in the paragraph mode and not in the margin control mode. In this situation, when the system senses a double carrier return, thus indicating the end of the paragraph, the system is directed to stop to permit the edit operation to be performed. Again, the upper shift or lower shift or print gate 246 is brought up upon the sensing of a period and drops after the end of the period code. The sensing of the carrier return brings up the space and tab or carrier return 2 gate 624 on circuit AH 30.10. It also brings up the carrier return 1 flip-flop 510 and the carrier return 1 gate 578. The edit flip-flop 290 is also brought up at the end of the first carrier return and the stop code is generated at gate A368. This stop code stops the reader, skips the code designated upper shift and turns the keyboard on to permit the operator to enter edit material.

FIGS. 15 to 20 illustrate the operation of the system in the margin control mode. In the margin control mode, the right-hand margin is controlled automatically when a prepared tape is modified, or the margin setting is changed from a previous typed copy. Thus, the margin or format of a printed page may be expanded or contracted from that programmed into the record, in this case the tape.

In order to accomplish this operation, the carrier return and hyphen codes not in the margin zone are converted to spaces and ignored. On the other hand, space and tab codes, which are indications of the termination of a word, and hyphens are converted to carrier returns in the margin zone. In the particular system illustrated, a margin control zone is defined by a margin switch which is actuated approximately eight spaces prior to (in the case of RHMZ) or after (in the case of LHMZ) the engagement of the margin stop. This spacing may be varied from system to system, or may be varied in one machine.

Referring particularly to FIG. 15, there is illustrated the operation wherein a carrier return is converted into a space in the left-hand margin zone. The sensing of the first data code brings up the upper shift or lower shift or print gate 246 and the sensing of a carrier return sets the carrier CR1 flip-flop 510. This information is stored until the second data code is sensed. This sensing brings up the space, tab flip-flop 534 and also inhibits the reader through gate 438. At the end of the first reader shutter signal an IB3 signal is generated on gate A416.

When a carrier return code is read, if both CR1 and CR2 are in the false state, a false CR skip signal will appear at the output of gate A634 in the margin control mode. A false signal will also be produced at the outputs of gates 468 and 440. The false signal of the gate 468 will inhibit the print, punch and operation strobe signals in the input/output unit; therefore, the carrier return will not be acted upon. Assume this carrier return code is preceded and followed by print codes. Then, when the carrier return is read, the output of gate 624 is false and holds the differentiator 544 inactive. Thus, CR1 will be set to the true state at the end of the carriage return strobe through differentiator 514.

After the reader has stepped one more step and read a print code, the CR1 dot print input conductor 506 becomes false and sets the flip-flop 534 to the true state and inhibits CR1 to be reset through differentiator 544. The setting of the flip-flop 534 also makes the output of gate 622 and gate 434 become false. This condition inhibits the reader and starts a new clock cycle at the end of clock C. In the new clock cycle channel 3 is set in the register at the end of the clock B. Thus, a space is read and utilized by the input/output system.

FIG. 16 illustrates the margin control mode when a carrier return is sensed in the left-hand margin zone and ignored. Particularly, the tape is coded with the letter A, a space, a carrier return and the letter B. Upon the sensing of the letter A, the upper shift or lower shift or print gate 246 is brought up at the beginning and down at the end of the letter A. The space-tab flip-flop 534 is brought up upon the sensing of the space code and the carrier return skip gate 634 is actuated in response to the sensing of the carrier return.

FIG. 17 is very similar to FIG. 15 in that the carrier return is converted into a space in the left-hand margin zone when the system is in the margin control mode. However, the carrier return follows a punctuation, in this case the period, and the carrier return is converted to two spaces to indicate the end of a sentence. In the case of FIG. 17, the punctuation is sensed and sets the punctuation flip-flop 150. Also, in response to the punctuation and right-hand margin zone signal, the output of gate 436 also drops to a false level. The remaining portion of FIG. 17 is substantially identical to that of FIG. 15 except to accommodate the second space conversion.

Referring to FIG. 18, there is illustrated the situation wherein the hyphen code is ignored in the left-hand margin zone when the system is in the margin control mode. The tape is seen to be coded, by way of example, with the letter A, a hyphen and the letter B. The upper shift or lower shift or print gate 246 rises to a logical one level each time a letter is sensed, in this case the A and the B. The right-hand margin zone and precedence gate 490 goes false and a skip signal on gate 468 becomes false to skip the hyphen in the input/output system.

However, the carrier return and hyphen, when preceded by a precedence mode, are always recognized and utilized by the input/output system. The precedence code, in the preferred system illustrated, is selected to be the upper shift code. When the upper shift code is read or manually entered from the keyboard, gate 210 in circuit AH 10.10 will produce a positive pulse during the clock C time, thus setting the shift memory flip-flop 214 through the differentiator circuit 212 at the trailing edge of the clock C pulse. The flip-flop 214 will be reset at the end of the clock D signal of the first code which is not another shift code or carrier return code in the line mode. If an upper shift code or upper shift--lower shift codes are read with CR1 and SPT in the false state (not during the time of converting or generating codes), gate 498 on FIG. 3 will be false, thus setting the CR2 flip-flop 568 to the true state and inhibiting the CR skip gate 634. This signal also inhibits the gate 490 for hyphen skip at the left-hand margin zone.

Referring now to FIG. 19, if a space or tab code is read in the right-hand margin zone, the gate 484 will be false during the clock C signal and the skip condition is established for the code. Also, the SPT flip-flop 534 will be set to the true state. If the following code is a print or shift code, a false output will result at gate 502 during the clock C pulse which, in turn, provides the skip pulse and sets CR1 flip-flop 510 to the true state. With the setting of the space tab flip-flop 534 and the CR1 flip-flop 510, the reader is inhibited and a new clock cycle is initiated.

The output of gate 410 on FIG. 2 causes the carrier return code to be loaded into the register in the input/output unit. The carrier return code will then be utilized by the input/output unit. The operation of the system is not affected if there is no carrier return code between the space and print code, or there is more than one space code.

FIG. 20 illustrates the situation where the system is in the margin control mode and a hyphen code is read in the right-hand margin zone. This condition indicates that a hyphenated word has occurred in the right-hand margin zone and the line should be terminated by the generation of a carrier return. In this case, the hyphen is read to set the hyphen flip-flop 102 and the CR1 flip-flop 510 is set upon the sensing of the system being in the right-hand margin zone. The reader is then inhibited and a carrier return code or input bus 2 or gate 510 is generated.

FIGS. 21 to 23 illustrate the autoedit mode of operation upon the sensing of certain codes from the reader unit, as for example when a shift or print code is sensed. Also, FIGS. 22 and 23 illustrate the operation of the system converting a space or tab into a carrier return or a carrier return being generated after a hyphen to indicate the end of a word or the end of a hyphenated portion of a word. The purpose of the autoedit mode of operation is to cause the reader to stop in the margin zone and advance one step at a time when a start, skip or nonprint key is depressed to permit the operator to control the margin more precisely.

With the system in the autoedit mode (the autoedit switch illuminated), the autoedit gate 280 is true when the carrier is in the right-hand margin zone. The right-hand margin zone, it will be noted, begins during the clock C pulse. The edit condition is established at the end of the clock C when a shift or print code is read and the reader will stop at the next shift or print code unless a space or tab was manually entered. In this system a carrier return is generated automatically when a space or hyphen code is read or a hyphen is manually entered from the keyboard. It is felt that the operation illustrated in FIGS. 21 to 23 is self-explanatory and requires no further explanation herein.

Referring now to FIG. 24, when the system is operating in the tab control mode, a count of tabs is established on the first of the data block and tabs are generated automatically by the system after a carrier return is acted upon.

This tab counting is accomplished by two three-bit counters in the circuit AH 40.10. The counter A counts and stores the tabs on the first line of a data block, while counter B counts the tabs generated after a carrier return in subsequent lines of the same data block. The contents of these two counters are compared, and the generation of tabs will be stopped when the system has a comparison or an equal count between counter A and counter B.

There are three ways inherent in the system to reset the A counter, the resetting of the A counter indicating a data block is started or terminated. These three ways are (1) two or more consecutive carrier returns, (2) a carrier return in the precedence mode, (3) at the time the tab control flip-flop is first set to the true state.

In the tab control mode, both the margin control and tab control flip-flops are set. Referring particularly to circuit AH 30.10, CR2 is in the true state (1) after a carrier return is acted upon, and (2) in the precedence mode. Therefore, gate 770 on circuit AH 40.10 will have a low output during the clock C pulse of the second carrier return code or a precedence mode carrier return read and utilized by the system. This output is tied to the output of gate 1162 and gate 1160 on circuit AH 60.10, which output would be low during the second manual entry carrier return clock D time and 1.6 millisecond after depression of the start switch. The false logic level will reset the A counter to zero and also set the tab count flip-flop to the true state.

With the tab count set to the true state and an unskipped tab code, the output of gate 684 will drop to a logical zero level at the start of clock D, which triggers the first stage of the A counter. The CR2 flip-flop was previously reset to the false state at the first tab. At the end of the first line, a carrier return code is read, and the output of gate 788 drops to a logical zero level and resets the tab count flip-flop 700. Subsequently, gate 684 is disabled and the counting of tabs is discontinued until a new data block is started.

In the tab control mode, the space-tab (SPT) flip-flop is true when the carrier return is generated in the right-hand margin zone, and a single carrier return is skipped in the left-hand margin zone. Multiple carrier returns can have the SPT signal only when the first two carrier returns are skipped and then automatically generated, and the system provides the 2CR (CR2) signal during the generation of these two carrier returns. Therefore, differentiator 810 on circuit AH 40.10 is true only during the clock C pulse of an unskipped single carrier return in the tab control mode. The differentiator 810 sets the tab generator flip-flop which removes the reset line of the B counter to enable the B counter to count tabs, inhibits the reader from stepping and reading, enables the system to start a clock A pulse at the end of a clock C pulse, and loads channel 1 flip-flop (the tab code) into the register. The tabs will be continuously generated in this way until a logical zero output at gate 758 is generated, which indicates the requisite number of generated tabs has been provided or equals the number of tabs stored in the counter A. When this condition occurs, the tab generator flip-flop is reset to the false state.

It is to be noted that when the operator updates the tape from a manual entry, the tab generator will be set if the SPT flip-flop has been previously set before the carrier return. However, the system will not generate tabs automatically because the gate 840 is inhibited by the keyboard signal. The tab generator flip-flop will be reset to the false state after the manual tab entry equals that stored in the A counter. On the other hand, if the operator depresses the start key before the full count, the remaining number of tabs will be generated automatically.

With the tab control and line or paragraph control modes, the reader will stop at the left-hand margin of a new data block under certain conditions. In addition to the stop demanded by the stop gate 368 on system AH 20.10, the input of gate 1010 on circuit AH 50.10 will cause the system to additionally stop at the tab code. Therefore, with the system in the line or paragraph mode, the reader will stop on the first tab instead of the shift or print code of a new data block in the tab control mode, unless the data block is formed by a single precedence mode carriage return and the line mode is not activated.

While it will be apparent that the embodiments of the invention herein disclosed are well calculated to fulfill the objects of the invention, it will be appreciated that the invention is susceptible to modification, variation and change without departing from the proper scope or fair meaning of the subjoined claims.

Claims

I claim:

1. Textual data editing and revision apparatus for controlling the operation of a keyboard device such as a manually or automatically operable printer during automatic operation in accordance with input data derived from a data input source such as a reader and a coded data storage device, said printer being automatically operable to process textual data arranged in a plurality of different data groups such as characters, words, lines, sentences, and paragraphs with data groups being serially associated and arranged in successive lines of variable length terminating in a margin zone of predetermined length, stop means for automatically terminating automatic operation of the printer after completion of processing of selected ones of the data groups, mode selection means actuable to select one of the data groups for terminating operation of the printer, each of said plurality of data groups having at least one characteristic feature, bistable storage means having a first state and a second state, said bistable storage means being in said first state in response to said the sensing of a characteristic feature of a selected data group and the actuation of said mode selecting means corresponding to said selected data group, and said stop means being energizable in response to said first state of said storage means for stopping the data input source and permitting the manual entry of data into an output storage device.

2. The invention of claim 1 wherein said bistable storage means includes a semiconductor latch circuit.

3. The invention of claim 2 wherein said latch circuit is a flip-flop circuit having a set input for switching said circuit to said first state and a reset input.

4. The apparatus of claim 1 further including an input gate circuit having an input from said mode selecting means.

5. The apparatus of claim 4 wherein said gate circuit further includes an input signal representative of one of said characteristic features, said gate circuit generating a switching signal to switch said latch circuit to said first state in response to the coincidence of said mode selecting means input and said input signal.

6. The apparatus of claim 1 wherein said stop means includes a stop gate, said stop gate generating a disabling signal for said input source in response to a data signal subsequent to said characteristic feature.

7. The apparatus of claim 1 wherein said mode selecting means includes a plurality of edit switches, said edit switches including at least one of a word, line, sentence and paragraph mode of operation.

8. The apparatus of claim 7 wherein said characteristic feature is a coded space, said bistable storage means being switched to said first state in response to the sensing of said coded space and the selection of said word mode.

9. The apparatus of claim 8 further including an input gate circuit having an input from said mode-selecting means.

10. The apparatus of claim 9 wherein said gate circuit further includes an input signal representative of one of said characteristic features, said gate circuit generating a switching signal to switch said latch circuit to said first state in response to the coincidence of said mode-selecting means input and said input signal.

11. The apparatus of claim 10 wherein said stop means includes a stop gate, said stop gate generating a disabling signal for said input source in response to a data signal subsequent to said characteristic feature.

12. The apparatus of claim 7 wherein said characteristic feature is a coded carriage return, said bistable storage means being switched to said first state in response to the sensing of said carriage return and said line mode.

13. The apparatus of claim 12 further including an input gate circuit having an input from said mode-selecting means, said gate circuit further including an input signal representative of one of said characteristic features, said gate circuit generating a switching signal to switch said latch circuit to said first state in response to the coincidence of said mode-selecting means input and said input signal.

14. The apparatus of claim 13 wherein said stop means includes a stop gate, said stop gate generating a disabling signal for said input source in response to a data signal subsequent to said characteristic feature.

15. The apparatus of claim 7 wherein said characteristic feature includes a coded punctuation followed by at least one of a space, tab or carriage return, said bistable storage means being switched to said first state in response to the sensing of one of said space, tab and carriage return and the selection of said sentence mode.

16. The apparatus of claim 15 further including an input gate circuit having an input from said mode selecting means, said gate circuit further including an input signal representative of one of said characteristic features, said gate circuit generating a switching signal to switch said latch circuit to said first state in response to the coincidence of said mode selecting means input and said input signal.

17. The apparatus of claim 16 wherein said stop means includes a stop gate, said stop gate generating a disabling signal for said input source in response to a data signal subsequent to said characteristic feature.

18. The apparatus of claim 16 wherein said apparatus includes punctuation storage means, the sensing of the punctuation being stored in said punctuation storage means for a period at least as long as the period of sensing a next subsequent space, tab or carriage return code.

19. The apparatus of claim 7 wherein said characteristic feature is a shift or print code followed by a first and second carriage return, said bistable storage means being switched to said first state in response to the sensing of said first carriage return and the selection of said paragraph mode.

20. The apparatus of claim 19 wherein said first carriage return is stored for a period which is at least as long as the period to initiate the sensing of said second carriage return.

21. Textual data editing and revision apparatus for controlling the operation of a keyboard device such as a manually or automatically operable printer during automatic operations in accordance with input data derived from a data input source such as a reader and a coded data storage device, said printer being automatically operable to process textual data arranged in a plurality of different data groups such as characters, words, lines, sentences, and paragraphs with data groups being serially associated and arranged in successive lines of variable length terminating in a margin zone of predetermined length, margin control circuit means for establishing a margin control mode of operation of the printer, means for establishing a margin zone of predetermined length having spaced boundaries including switch means associated with the printer and actuable thereby to establish one boundary of said margin zone and semiconductor bistable storage means for indicating the in-margin zone and out-of-margin zone condition of the printer and having a first state and a second state, said storage means being in said first state in response to the actuation of said switch means to indicate an at-the-one-boundary-of-said-margin zone condition of the printer and circuit means for changing the state of said storage means to said second state to indicate an at-the-other-boundary-of-said-margin zone condition of the printer.

22. The apparatus of claim 21 wherein said storage means includes a flip-flop circuit, gate circuit means connected to the set side of the flip-flop to switch the flip-flop to the first state in response to an output signal from said gate, said gate means being responsive to the sensing of said margin zone.

23. The apparatus of claim 22 further including a carriage return flip-flop, said carriage return flip-flop being set to produce a carriage return signal for actuation of the printer.

24. The apparatus of claim 23 wherein said carriage return signal is generated in response to the sensing of at least one of a tab, space, hyphen or carriage return in the margin zone.

25. The apparatus of claim 24 wherein said carriage return signal is generated by a print code following a carriage return signal.

26. The apparatus of claim 24 wherein one of a space or tab code is converted to a carriage return code and including storage flip-flop means for storing said space or tab code, said storage flip-flop being connected to said carriage return flip-flop, and gate means for generating a coded carriage return signal for use by the printer.

27. The apparatus of claim 22 further including carriage return storage means for storing a sensed input carriage return signal, gate means for sensing a print code and generating an output signal, a space-tab flip-flop gate means responsive to both said carriage return signal and said print signal for setting said space-tab flip-flop, and output gate means for generating a coded space signal in response to the setting of said space-tab flip-flop.

28. Apparatus for controlling the operation of a data processing system printer having printing mechanism for printing characters and functional mechanism for selecting the location of printing of characters, first means for sensing a first characteristic operation of the printer, second means enabled in response to the sensing of said first characteristic operation for counting a first succession of second characteristic functional operations including first storage means for storing the count of said second characteristic functional operation, comparison circuit means for counting a second succession of said second characteristic functional operations, and means limiting said second succession of second characteristic functional operations when the count of said second succession bears a preselected relationship to the count of said first succession of second characteristic functional operations.

29. The apparatus of claim 28 wherein said first characteristic is an indication of the start of a block of data having successive lines.

30. The apparatus of claim 29 wherein said first characteristic is a double carriage return.

31. The apparatus of claim 30 wherein said first means includes bistable storage means having a set state and a reset state, said storage means being switched to said set state in response to the sensing of said second carriage return.

32. The apparatus of claim 31 wherein said second means includes gate means having an input circuit connected to said bistable storage means, said gate means being enabled in response to the set state of said bistable storage means.

33. The apparatus of claim 32 wherein said bistable storage means is switched to the reset state in response to the sensing of a carriage return, said gate means being disabled in response to said reset state.

34. The system of claim 28 wherein said first storage means includes a first binary counter circuit and said comparison circuit includes a second binary counter circuit, the outputs of said first and second binary counters being compared during the generation of certain successive lines of data.

35. The apparatus of claim 34 wherein said comparison circuit means includes a plurality of gate circuits, each of said gate circuits having input circuits for receiving selected combinations of output configurations of each of said first and second counters.

36. The apparatus of claim 35 wherein said limiting means includes a skip circuit for skipping subsequent second characteristic operations after achieving coincidence of the outputs of said first and second counters.

37. The apparatus of claim 28 wherein said second characteristic operation includes tab operations.

38. The apparatus of claim 37 wherein said first characteristic is a double carriage return.

39. The apparatus of claim 38 wherein said first means includes bistable storage means having a set state and a reset state, said storage means being switched to said set state in response to the sensing of said second carriage return.

40. The apparatus of claim 39 wherein said first storage means includes a first binary counter circuit and said comparison circuit includes a second binary counter circuit, the outputs of said first and second binary counters being compared during the generation of certain successive lines of data, and wherein said comparison circuit means includes a plurality of gate circuits, each of said gate circuit having input circuits for receiving selected combinations of output configurations of each of said first and second counters.

41. Apparatus for controlling the operation of a data processing system keyboard device such as a printer operable manually or automatically, means for providing continuous automatic operation of said printer from an automatic data input device, means for establishing a controlled zone in the operation of the printer, means for sensing the entry of the printer into said controlled zone, means for interrupting the continuous automatic operation of said printer upon entry into said controlled zone and for resuming continuous automatic operation upon leaving said controlled zone, circuit means for single cycling said system in said controlled zone including pulse means independent of said automatic data input device for generating a pulse to initiate each cycle within said controlled zone and sensing means for resuming continuous automatic operation of said printer upon receipt of a pulse characteristic of a predetermined function of the printer.

42. The apparatus of claim 41 wherein the system includes a data editing and revision system, said controlled zone being a right-hand margin zone, and said circuit means including means for sensing an operation or print code from the input device and stopping the input device after each sensed code.

43. The apparatus of claim 42 wherein said pulse means starts the input device in response to each pulse.

44. The apparatus of claim 43 wherein said pulse means includes manually actuate switch means.

45. The apparatus of claim 44 further including circuit means for generating a carriage return signal in response to sensing at least one of a carriage return, hyphen, space or tab operation code.

46. The apparatus of claim 45 wherein a hyphen code is generated in response to at least one of a carriage return, hyphen, space or tab operation code.