U.S. patent number 3,810,356 [Application Number 05/351,943] was granted by the patent office on 1974-05-14 for time correcting apparatus for an electronic timepiece.
This patent grant is currently assigned to Kabushiki Kaisha Suwa Seikosha. Invention is credited to Kinji Fujita.
United States Patent |
3,810,356 |
Fujita |
May 14, 1974 |
TIME CORRECTING APPARATUS FOR AN ELECTRONIC TIMEPIECE
Abstract
A time correcting apparatus for an electronic timepiece having a
digital time display including a selecting switch for selecting the
digit of the display to be corrected, which digit is visually
identified, and a correcting switch for correcting that digit. Time
correction is achieved by the combined operation of the two
switches.
Inventors: |
Fujita; Kinji (Suwa,
JA) |
Assignee: |
Kabushiki Kaisha Suwa Seikosha
(Tokyo, JA)
|
Family
ID: |
12527791 |
Appl.
No.: |
05/351,943 |
Filed: |
April 17, 1973 |
Foreign Application Priority Data
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|
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Apr 17, 1972 [JA] |
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47-38529 |
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Current U.S.
Class: |
368/69; 368/188;
968/917 |
Current CPC
Class: |
G04G
5/045 (20130101) |
Current International
Class: |
G04G
5/00 (20060101); G04G 5/04 (20060101); G04b
027/00 () |
Field of
Search: |
;58/23R,85.5,5R |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Tomsky; Stephen J.
Assistant Examiner: Weldon; U.
Attorney, Agent or Firm: Blum, Moscovitz, Friedman &
Kaplan
Claims
What is claimed is:
1. In an electronic timepiece having multistage divider time
keeping circuit means and multi-digit display means coupled to said
corresponding multi-stage dividers for the digital display of time,
the improvement which comprises time correcting circuit means, a
manually operable selecting switch means and a manually operable
correcting switch means coupled to said time correcting circuit
means, said time correcting circuit means being operatively coupled
to the dividers of said time keeping circuit means associated with
the digits of time of said display means to be corrected for the
selective sequential selection of each digit of time for correction
by the manual operation of said selecting switch and for the
selective correction of said selected digit of time by the manual
operation of said correcting switch, said time correction circuit
means being further coupled to each digit of time of said display
means and adapted to dispose the selected digits of time of said
digital display means so as to render same distinguishable from the
other digits of said display means.
2. An electronic timepiece as recited in claim 1, including safety
switch means operatively coupled to said time correcting circuit
means and manually operable for the selective actuation of said
time correcting means, whereby said selecting switch means and said
correcting switch means are operable only upon actuation of said
time correcting circuit means by said safety switch means.
3. An electronic timepiece as recited in claim 1, wherein said time
correcting circuit means includes a plurality of gate means
defining outputs of said correcting circuit means, one of said gate
means being operatively coupled to each of the divider stages
producing said time-keeping signals, said correcting switch means
being operatively coupled to each of said gate means for the
application of a correcting signal thereto, said time correcting
circuit means further including counter means having a plurality of
outputs representing the sequential count of said counter means,
one of said counter means outputs being connected to each of said
gate means for the sequential actuation thereof to enable the
actuated gate means to pass said correcting signal, said selecting
switch means being operatively coupled to said counter means for
the sequential indexing of said counter means.
4. An electronic timepiece as recited in claim 3, including a
further gate means associated with each of said first-mentioned
gate means of said time correcting circuit means, each of said
further gate means being operatively coupled to the same output of
said counter means as the associated first-mentioned gate means for
simultaneous actuation thereof, one of the dividers of said time
keeping means supplying a display identification signal through
said counter means to each of said further gate means, each of said
further gate means being operatively coupled to the digits of said
display means associated with the divider stage to which the
associated first-mentioned gate means is connected to render such
digit visually distinguishable from the other digits of said
display means.
5. An electronic timepiece as recited in claim 4, including decoder
means coupled to each of the dividers of said time keeping circuit
means, and NAND gate means intermediate each of said decoder means
and the associated display means, said NAND gate means having a
first input from said decoder means and a second input from said
time correcting signal means for receipt of said identification
signal.
6. An electronic timepiece as recited in claim 5, wherein said
identification signal is derived from an output of one of said
divider stages selected to produce a low-frequency identification
signal for application to each of said further gate means for
transmittal to the selected NAND gate means.
7. An electronic timepiece as recited in claim 4, including safety
switch means manually operable and operatively connected to said
counter means for the selective enabling of the operation of said
counter means to permit time correction.
8. An electronic timepiece as recited in claim 1, wherein the
digits of time to be corrected include seconds, minutes and
hours.
9. An electronic timepiece as recited in claim 1, wherein the
digits of time to be corrected include minute, hour, day and
date.
10. An electronic timepiece as recited in claim 1, wherein said
time correcting circuit means is adapted to render the selected
digit of said display means visually distinguishable by flickering
said selected digits of said display means.
11. An electronic timepiece as recited in claim 1, wherein said
display means are liquid crystal display means.
12. An electronic timepiece as recited in claim 1, wherein said
display means are light emitting diode display means.
Description
BACKGROUND OF THE INVENTION
This invention relates to electronic timepieces, and in particular,
to electronic timepieces provided with a digital time indication
formed from a liquid crystal display, a light emitting diode
display or the like.
In the art, separate correcting switches are generally provided for
each digit to be corrected, an arrangement which occupies a great
deal of the limited space available in a small electronic timepiece
such as a wrist watch, as well as being costly. By providing an
arrangement wherein a plurality of digits of time display may be
corrected by means of two switches, the foregoing deficiencies are
avoided.
SUMMARY OF THE INVENTION
Generally speaking, in accordance with the invention, an electronic
timepiece having a multi-digit digital display of time is provided
with time correcting circuit means including a manually operable
selecting switch and a manually operable correcting switch. Said
circuit means is adapted to select at least one of said digits of
time for correction in response to the operation of said selecting
switch and to correct the selected digit by the operation of said
correcting switch. Said circuit means further includes means for
selectively actuating the selected digits so as to provide a visual
indication of selection. Said visual indication of selection may
constitute the flickering of the digits to be corrected.
Accordingly, it is an object of this invention to provide a time
correcting apparatus for an electronic timepiece which is simple in
structure and of high reliability, and whereby time correction can
be readily achieved.
Still other objects and advantages of the invention will in part be
obvious and will in part be apparent from the specification and
drawings.
The invention accordingly comprises the features of construction,
combinations of elements, and arrangement of parts which will be
exemplified in the constructions hereinafter set forth, and the
scope of the invention will be indicated in the claims.
BRIEF DESCRIPTION OF THE DRAWINGS
For a fuller understanding of the invention, reference is had to
the following description taken in connection with the accompanying
drawings, in which:
FIG. 1 is a top plan view of an electronic timepiece in accordance
with the invention;
FIG. 2 is a circuit diagram of the electronic timepiece of FIG.
1;
FIG. 3 is a circuit diagram of the control circuit of FIG. 2;
and
FIG. 4 is a timing chart of the circuit of FIGS. 2 and 3.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring now to FIG. 1, the electronic wrist watch depicted is
provided for purposes of illustration with a liquid crystal display
adapted to display date, day, hour, minute and second it being
understood that such display could include light emitting diodes or
the like. Two push buttons are mounted on the front of the case of
the watch, the first, push button S.sub.S is a selecting switch for
selecting the digit to be corrected. As used herein, a digit can
refer to one of the two digits representative of each of the
second, minute, hour and day displays, or to both of the respective
digits. Further, it can refer to one of the seven days of the week,
or to all of the seven days of the week. The second push button
S.sub.A is a correcting switch for correcting the selected digit.
Thus, in the watch of FIG. 1, the minutes digit reads "34." If the
minute digit is selected by selecting switch S.sub.S, the digit
starts flickering or blinking. With each depression of correcting
switch S.sub.A, the number appearing in the minute display is
indexed so as to increase by one to effect time correction. By
operating selector switch S.sub.S, each of the other digits of time
can be selected for correction.
The watch is provided with a crown S.sub.L on the side thereof
which constitutes a safety switch. When said crown is pushed in, a
safety circuit is actuated and push buttons S.sub.S and S.sub.A are
deactivated and will not function even if pushed. In order to
render the push buttons operative, the safety circuit must be
released by pulling out crown S.sub.L.
The circuit of the electronic timepiece in accordance with the
invention is shown in the block diagram of FIG. 2, wherein the high
frequency time standard signal of a crystal oscillator X (for
example 16,384 Hz) is divided by a counter chain consisting of six
stages 1-6. Counter 1 divides the high frequency timing signal into
a 1-second signal. Counter 2 divides the 1-second signal into a
1-minute signal, counting 60 seconds. Counter 3 divides the
1-minute signal into a 1-hour signal, counting 60 minutes. Counter
4 divides the 1-hour signal into a 1-day signal, counting 24 hours.
Counter 5 divides the 1-day signal into a 1-month signal by
counting 31 days. The counter 6 likewise divides the 1-day signal,
but to produce a 1-week signal, counting the 7 days of the
week.
A decoder 7-11 is connected to receive the BCD output signal of
each of counters 2-6 to transform the BCD code signal outputs of
said counters into a decimal signal DEC for actuating the
corresponding liquid crystal displays representative of second
(L.sub.S), minute (L.sub.M), hour (L.sub.H), date (L.sub.D) and day
of the week (L.sub.W). Each decoder is connected to its respective
liquid crystal display through a NAND gate circuit, the other input
to each of said NAND gates being from control circuit 12. Thus,
output S.sub.b of control circuit 12 is coupled to the NAND gate
associated with the second liquid crystal display L.sub.S. In like
manner, control circuit 12 outputs M.sub.b, H.sub.b, D.sub.b,
W.sub.b are respectively connected to the NAND gate associated with
minute liquid crystal display L.sub.M, hour liquid crystal display
L.sub.H, day liquid crystal display L.sub.D and day of the week
liquid crystal display L.sub.W. During normal operation of the
watch, the outputs S.sub.b, M.sub.b, H.sub.b, D.sub.b and W.sub.b
are at a high state and the liquid crystal displays are driven
normally by the decimal outputs of the respective decoders
7-11.
When safety switch S.sub.L is pulled out to permit time correction,
a low frequency signal F of a frequency from 20 Hz to several Hz
from counter 1 is applied through control circuit 12 to the digit
selected for correction through one of output S.sub.b, M.sub.b,
H.sub.b, D.sub.b or W.sub.b. For example, if the minute digit is to
be corrected, the low frequency signal F is applied through output
M.sub.b to the NAND gate between decoder 8 and liquid crystal
display L.sub.M so that said liquid crystal display is switched on
and off at the frequency of low frequency signal F. Since the
frequency of signal F is selected so that the rate of switching of
the selected liquid crystal display elements can be detected by the
user's eyes, the selected display is flickered and can clearly be
distinguished from the other displays which are continuously
displayed.
Also during time correction, the signal applied by correcting
switch S.sub.A is applied through control circuit 12 to the
selected one of outputs S.sub.a, M.sub.a, H.sub.a, D.sub.a and
W.sub.a which are respectively connected to the correcting terminal
ADJ of one of counters 2-6 for the selective correction of the
setting of the selected digit.
Referring to FIGS. 3 and 4, we find a circuit diagram for control
circuit 12 and a timing chart for certain of the signals
thereof.
Control circuit 12 includes three D-type flip-flops FF.sub.1,
FF.sub.2 and FF.sub.3 connected to form a hexadic Johnson counter.
Safety switch S.sub.L is connected to the reset terminal R of the
three flip-flops.
Selection switch S.sub.S is connected to input terminal CL of the
three flip-flops. The outputs Q and Q of the three flip-flops are
directly coupled to NOR gates N.sub.1 through N.sub.5. The output
of NOR gates N.sub.1 through N.sub.5 are coupled to a control
terminal of NAND gates G.sub.1 through G.sub.10 in the manner
depicted. The NAND gates circuits are conventional NAND gates
having the following truth tables: ##SPC1##
As is understood, A is a signal for controlling the gate. B is a
signal passing through the gate. As is further depicted in the
second Table above, when A is 0 (zero), the gate is closed and when
A is 1 the gate is open. As is further noted, when the signal B
passes through the gate, a signal having the opposite phase B is
obtained.
Similarly NOR gates N.sub.1 through N.sub.5 are conventional NOR
gates having a truth table as follows: ##SPC2## Finally, a D-type
flip-flop is depicted in FIG. 3 has the following truth table:
##SPC3##
It is noted that when CL is changed from 0 to 1, the signal applied
to the D terminal is written in by Q and the complement thereof D
becomes the output signal of Q. Similarly, when CL is changed from
1 to 0, Q and Q are not changed.
In operation when safety switch S.sub.L is pushed in, a positive
potential illustrated as t1 and t3 in FIG. 4, is applied to reset
terminal R to thereby reset the flip-flops. Accordingly, NAND gates
G.sub.1, G.sub.2, . . . G.sub.10 are all closed, and correcting
switch S.sub.A and selecting switch S.sub.S cannot be actuated. As
is depicted in FIG. 4, even if S.sub.A and S.sub.S are actuated
(signals s.sub.9 and s.sub.10), no changes will occur. When the
crown representing safety switch S.sub.L is pulled out, a negative
electrical potential is applied to reset switch R and the Johnson
counter circuit is actuated, to thereby actuate selecting switch
S.sub.S and to advance, the Johnson counter by one count so that
one of the pairs of NAND gates G.sub.1 and G.sub.2, G.sub.3 and
G.sub.4, and G.sub.5 and G.sub.6, G.sub.7 and, G.sub.8, or G.sub.9
and G.sub.10 are opened while the other four pairs of NAND gates
remain closed. For example, if selecting switch S.sub.S has indexed
the Johnson counter so that gates g.sub.3 and g.sub.4 are open, the
second digits are selected, in the following manner.
Switch S.sub.S is closed thus applying a pulse (s.sub.1) to all
three flip-flops to actuate the same and effect an opening of NAND
gates G.sub.3 and G.sub.4 by the generating of a 1 condition at NOR
gate N.sub.1. The opening of NAND gates G.sub.3 and G.sub.4 allows
signal F supplied from counter 1 to become output S.sub.b (s.sub.2)
of NAND gate G.sub.4 and is therefore applied to display element
L.sub.S causing the same to flicker. Since only display element
L.sub.S is flickering, the operator can easily discern that the
seconds digit is being corrected. Then, upon closing switch S.sub.A
a pulse (s.sub.3) is supplied by opened NAND gate G.sub.3 and
becomes correction signal S.sub.a (s.sub.4) which is applied to the
seconds counter 2 to correct the seconds time display. If it is
then desired to correct the hours digit, selector switch S.sub.S is
closed twice to apply two pulses (s.sub.5) to the flip-flop
circuits, to thereby change the state of the counter. NOR gate
N.sub.3 is opened, thus making the output thereof a 1 hence opening
NAND gates G.sub.1 and G.sub.2. The opening of gate G.sub.2 allows
signal F to be applied through the control circuit to the digital
display element L.sub.H as signal H.sub.b to effect a flickering of
said display elements. Thus, a correction signal (s.sub.8) is
applied by correction switch S.sub.A through gate G.sub.1 to hours
counter 4 to thereby effect correction of the hours display. It is
understood that as the selection switch S.sub.L is closed, and a
pulse is applied to said control circuit 12, the digit to be
corrected and the flickering of such digit is effected in the
following sequence; second, minute, hour, date, day of the week,
and seconds again.
By the foregoing arrangement, two switches permit the selective
correction of any digit of time indication, including second,
minute, hour, day and date of a digital display such as a liquid
crystal display or a light emitting diode display. This structure
eliminates the necessity of separate switches for each digit,
thereby permitting the production of a compact electronic timepiece
such as a wrist watch capable of displaying a wide range of
information.
While in the timepiece depicted, the liquid crystal display is
driven by a DC signal, an AC signal may also be utilized to drive a
liquid crystal display. In such an arrangement, the digit to be
corrected would be indicated by changing the driving frequency of
the digit to be corrected, for example, by providing two AC driving
steps, 32 Hz and 8 Hz.
It will thus be seen that the objects set forth above, and those
made apparent from the preceding description, are efficiently
attained and, since certain changes may be made in the above
constructions without departing from the spirit and scope of the
invention, it is intended that all matter contained in the above
description or shown in the accompanying drawings shall be
interpreted as illustrative and not in a limiting sense.
It is also to be understood that the following claims are intended
to cover all of the generic and specific features of the invention
herein described, and all statements of the scope of the invention
which, as a matter of language, might be said to fall
therebetween.
* * * * *