Electronic Digital Clock Apparatus

Abstract

A plurality of shift registers for storing time information represented by numbers consisting of a plurality of digits are connected to an adder to form a closed loop. The time information stored in the shift registers is circulated through the closed loop in a minimum unit length of time. When the adder is supplied with information on the minimum unit length of time, it receives a single addition pulse per minimum unit length of time. A decoder is supplied with four bit outputs from a shift register corresponding to a particular digit position, and outputs from the decoder are supplied to a plurality of digit indicators in common. The digit indicators are successively impressed with operating voltage to display time information periodically.

Description

This invention relates to an electronic digital clock apparatus and more particularly to an electronic digital clock apparatus whose arrangement is adapted for incorporation of integrated circuitry.

In an electronic digital clock apparatus proposed to date outputs from a crystal oscillator having a very stable oscillation frequency are frequency-divided by a frequency divider to obtain a pulse train having a single unit pulse per minimum unit length of time, for example, per second. The unit pulse is conducted to a plurality of cascade-connected counters. Where time is to be indicated in three categories of hours, minutes and seconds, there are required six counters. In this case, counters for storing digits representing each second, minute and hour may be of a decimal type, and counters for storing digits denoting 10-orders of seconds and minutes have to be of 6-scale type. Further, according as there is used a 12-hour or 24-hour clock, there is required a binary or ternary counter in order to store digits showing 10-orders of hours. Outputs from each counter are connected to the corresponding decoder, an output from which in turn is supplied to the corresponding digit indicator. There are generally required 7 to 10 decoder outputs, though the number varies with the construction of electrodes included in the digit indicators used.

According to the aforementioned arrangement of the prior art electronic digital clock apparatus, there have to be provided decoders in the same number as counters. Further, there have to be used numerous leads for connecting counters with decoders as well as for connecting decoders with the digit indicators. For the above reason and due to the complicated counter arrangement, there are required a large chip and numerous terminals in order to incorporate the clock apparatus into integrated circuitry. Accordingly, the prior art clock apparatus is not suitable for integrated circuit version.

Another conventional electronic digital clock apparatus uses a single common decoder instead of plural decoders as required in the preceding case. Outputs from the common decoder are connected to all plural digit indicators. Between the counters and the common decoder is provided a matrix circuit. There is further provided a scanner for generating sequential pulses in the same number as digit indicators under control by an output from a frequency divider. Outputs from the scanner is conducted to the matrix circuit so as to cause outputs from a given counter to be selectively supplied to the common decoder as well as to the corresponding plural digit indicators, thereby impressing operating voltage on a digit indicator corresponding to the counter connected to said common decoder. The plural digit indicators display digits in turn or dynamically by means of the common decoder and scanner. According to this second prior art clock apparatus, leads connecting the digit indicators with the common decoder naturally decrease in number. On the other hand, there must be additionally used a matrix circuit, requiring a certain number of leads to connect the matrix circuit with the counters. Therefore, the arrangement of the second type of the prior art clock apparatus is neither adapted for employment of integrated circuitry. Accordingly, the arrangement of both conventional clock apparatuses present difficulties in designing a very compact electronic digital clock apparatus resembling an ordinary watch or wrist watch.

It is accordingly an object of this invention to provide an electronic digital clock apparatus of sufficiently simple construction easily to admit of the application of integrated circuitry.

Another object of the invention is to provide an electronic digital clock apparatus which uses an addition circuit simple in construction.

SUMMARY OF THE INVENTION

According to this invention, there is provided an electronic digital clock apparatus comprising: shift register means for storing time information represented by a plurality of digits, said shift register means having stages equal to the digits in number; generating means for generating pulses; an adder means connected to the shift register means to form a closed loop therewith, the adder means including two input terminals, the first one of which being adapted to receive time information stored in the shift register means and the second one of which being adapted to receive one pulse as an addition input from the pulse generating means when the first input terminal receives that portion of the time information stored in the shift register means which corresponds to a predetermined minimum unit length of time; shift pulse generating means for circulating time information stored in the shift register means through the closed loop per the minimum unit length of time; a decoder means connected to the shift register means to decoder outputs from a predetermined stage of the shift register means; and a plurality of digit indicators for displaying time information stored in the shift register means upon receipt of outputs from the decoder means.

One characteristic of the electronic digital clock apparatus of this invention is that shift register means is connected to an adder to form a closed loop. Time information stored in the shift register means and representing a plurality of digits is circulated through the closed loop per minimum unit length of time. When one input terminal of the adder is supplied with information denoting the minimum unit length of time, the other input terminal is impressed with one addition pulse per the unit time to effect clockwise addition.

According to this invention, outputs from a predetermined stage of shift register means have only to be conducted to a common decoder, realizing the prominent decrease of required connection leads.

Another characteristic of the electronic digital clock apparatus of the invention is that the adder is of simple construction which adds a number of "1" per minimum unit length of time to the time information already obtained. Where there arises a carry output in clockwise addition, the sum output always denotes zero. The carry output is added to the time information on a digit of the next higher order. Therefore, it does not happen that the carry output and the unit pulse for addition of a number of 1 are simultaneously supplied to the adder. Therefore, there is not required an adder with three input terminals used in ordinary full addition. The adder included in the digital clock apparatus of this invention consists of an EXCLUSIVE OR circuit with two input terminals, AND gate with two input terminals for carry operation and one bit time delay means.

The present invention can be more fully understood from the following detailed description when taken in connection with the accompanying drawings, in which:

FIG. 1 is a block diagram of an electronic digital clock apparatus according to an embodiment of this invention;

FIG. 2 is a circuit diagram of FIG. 1;

FIG. 3 shows waveforms of various pulses by way of explaining the operation of the circuit of FIG. 2;

FIG. 4 indicates the electrode pattern of a digit indicator which may be used with the clock apparatus of the invention; and

FIG. 5 illustrates the display of time information by means of a plurality of digit indicators having the electrode pattern shown in FIG. 4.

There will now be described an electronic digital clock apparatus according to this invention, wherein time information is given in six digits, for example. In this case, time information consists of three categories of hours, minutes and seconds, each including two digits, so that the minimum unit length of time is one second.

Referring to FIG. 1, reference numeral 11 represents a crystal oscillator including a crystal oscillation element 12. Sinusoidal outputs from the crystal oscillator 11 are subjected to frequency-division by a frequency divider 13. The frequency divided output is supplied to a shift pulse generator 14 to produce two shift pulses .phi..sub.1 and .phi..sub.2 having different phases. The shift pulses .phi..sub.1 and .phi..sub.2 are generated at an interval of a one-bit time, respectively. An output from the shift pulse generator 14 is connected to a bit pulse generator 15 to produce four sequential bit pulses B.sub.1, B.sub.2, B.sub.4 and B.sub.8 shown in FIG. 3. These bit pulses have a binary significance of 1, 2, 4 and 8 respectively, and are generated for a one bit time.

Upon receipt of an output from the bit pulse generator 15, a digit pulse generator 16 produces six sequential digit pulses D.sub.1 to D.sub.6 shown in FIG. 3. Each digit pulse is generated at an interval of the minimum unit length of time, that is, one second. Namely, the duration of each digit pulse is one digit time or 1/6 sec.

Where it is desired to indicate time information at the rate of 1/100 sec., each digit pulse is chosen to be generated at an interval of 1/100 sec. corresponding to the unit length of time in this case.

Now let it be assumed that where one digit time is 1/6 sec., the frequency divider 13 includes six cascade-connected flip-flop circuits and in consequence has a frequency division coefficient of 64. Then the oscillation frequency of the crystal oscillator 11 is chosen to be 1.536 KHz. Where it is desired to obtain time information consisting of eight digits and varying per 1/100 sec., then the frequency of the crystal oscillator 11 may be set at 25.6 KHz (frequency division coefficient of 8) or 204.8 KHz (frequency division coefficient of 64).

The method of generating the aforementioned shift pulses .phi..sub.1 and .phi..sub.2, bit pulses B.sub.1 to B.sub.4 and digit pulses D.sub.1 to D.sub.6 is already well known in the art and description thereof is omitted.

Reference numerals 17, 18 and 19 represent six stage dynamic shift registers. Numeral 17 denotes a four digit or stage shift registers, and numerals 18 and 19 one-digit registers. Each stage of shift registers for storing one digit included in time information stores the value of the digit in the form of a binary coded decimal (BCD) number and in consequence consists of four bit shift register elements.

The fundamental construction of the clock apparatus of this invention is characterized in that an adder 20 is connected to the shift registers 17, 18 and 19 to form a closed loop therewith. The adder 20 has two input terminals 21 and 22 and two output terminals 23 and 24. The time information stored in the shift registers 17, 18 and 19 is circulated through the closed loop by the shift pulses .phi..sub.1 and .phi..sub.2 in the minimum unit length of time via the first input terminal 21 of the adder 20, adder 20 and the first output terminal 23 in turn.

The second output terminal 24 of the adder 20 is intended to produce a carry output which is conducted through an adder gate 25 to the second input terminal 22 of the adder 20. The second input terminal 22 is supplied with one addition pulse per minimum unit length of time when the first input terminal 21 receives, as described later, time information on the minimum unit length of time from the shift register 18, thereby adding a number 1 per minimum unit length of time to the first bit portion of time information on the unit time stored in the shift register 18. Namely, the stored content of the shift registers increases by one per second.

Four bit outputs from the one digit shift register 19 corresponding to a predetermined digit position are supplied to a decoder through a one digit time delay means or parallel-in-parallel-out shift register 26. In this case, the decoder 27 has seven output terminals A to G which are jointly connected to the numeral electrodes of plural digit indicators (there are provided six indicators in this case.) The decoder 27 having seven outputs A to G is intended for use with digit indicators each provided with an electrode assembly formed of seven segmental electrodes as shown in FIG. 4. Output A from the decoder 27 is connected to the A segment of the assembly, output B from the decoder 27 to the B segment and the other outputs to the corresponding segments. Where, among the seven output terminals of the decoder 27, for example, the terminals A, F, G, C and D are supplied with output signals from the decoder 27, then preparation is being made selectively to display a digit "5" as apparent from FIG. 4. Each of the indicators includes a common electrode facing the numerical electrode assembly. This common electrode is supplied with the corresponding one of the sequential digit pulses D.sub.1 to D.sub.6 generated by the digit pulse generator 16 as an operating voltage. As apparent from the waveforms shown in FIG. 3, the indicators successively display digits corresponding to outputs from the decoder 27 periodically for a one digit time interval. FIG. 5 illustrates a pattern of time information including six digits.

To render the electronic clock apparatus compact, the indicator should preferably be constituted by light emitting diodes prepared from gallium phosphide capable of emitting light with small current or diodes prepared from gallium arsenide-phosphide capable of projecting more intense light. Also liquid crystal is effective to render the resultant indicator compact and reduce power consumption. Obviously, it is also possible to use display tubes commercially known as "Nixie" which includes ten electrodes, each shaped like Arabic numerals. In this case the decoder has ten output terminals corresponding to ten numeral-shaped electrodes.

The construction of the aforementioned dynamic display system including a decoder and indicators is already known to those skilled in the art and description thereof is omitted.

In the case of 6-digit time information, the least significant digit and the third digit therefrom are only required to indicate a number up to 10, and the second and fourth digits a number up to 6 respectively. Therefore, bit outputs from the one-digit shift register 19 are supplied to a detector 30 for detecting numbers 10 and 6. This detector 30 generates a detection output when a number stored in the one-digit shift register 19 is 10 or 6. The output from the detector 30 is conducted to a reset gate 31 connected to the output of the register 19 within the closed loop to reset or clear the outputs therefrom. When the shift register 19 is stored with a numeral 10 or 6, this is the time for the digit of the next higher order to be increased by one. To this end, a detection output from the detector 30 is supplied as a carry signal to the second input terminal 22 of the adder 20 through an adder gate 25.

The electronic digital clock apparatus of this invention may be selectively used either as a 12-hour or 24-hour system. To this end, the present clock apparatus is provided with a selector 32 and a detector 33 connected to the output of the selector 32 as well as of the one-digit shift registers 18 and 19 jointly denoting two adjacent digits, the detector 33 being capable of detecting whether the contents of the registers 18 and 19 collectively represent a number 12 or 24. Where there is chosen a 12-hour system by the selector 32, the detector 33 produces an output only when the registers 18 and 19 jointly indicate a number 12. Where there is chosen a 24-hour system, the detector 33 generates an output only when the registers 18 and 19 collectively show a number 24. In either case, an output from the detector 33 is conducted to a reset gate 34 connected to the output of the register 18 within the closed loop and also to the reset gate 31 connected to the output of the register 19 to reset or clear the outputs of both registers 18 and 19.

There will now be described the clock apparatus of FIG. 1 by reference to the circuit arrangement shown in FIG. 2. The same parts of both figures are denoted by the same numerals.

As is well known, the dynamic shift registers 17, 18 and 19 have their contents shifted in turn to the right in response to write-in pulses .phi..sub.1 and read-out pulses .phi..sub.2, causing 6-digit time information to be successively supplied to the adder 20, starting with that portion of the information which denotes the minimum unit length of time. The constituent element of the dynamic shift register should preferably consist of field effect transistors suitable for integration of circuitry. Particularly where the dynamic shift register is formed of complementary field effect transistor assemblies, or the so-called C-MOS FET, then there can be used a relatively low operating voltage, offering advantage in rendering the clock apparatus compact. In this case there are required, as is well known, not only shift pulses .phi..sub.1 and .phi..sub.2 but also their complements .phi..sub.1 and .phi..sub.2.

Time information on the minimum unit length of time is supplied to the first input terminal of the adder 20 from the register 18 through a reset gate 34, when there is generated a digit pulse D.sub.1 shown in FIG. 3. When the input terminal 21 receives the first bit output of the minimum unit time information from the register 18, then the second input 22 is supplied with a bit pulse B.sub.1 having a binary significance of 1 as an addition input through an AND gate 40 and OR gate 41 included in the adder gate 25. The AND gate 40 has an input terminal for receiving the bit pulse B.sub.1 and another input terminal for receiving the digit pulse D.sub.1. Obviously, therefore, the bit pulse B.sub.1 is supplied to the adder 20 once per operating cycle of the shift register or during the minimum unit length of time.

Addition is carried out in an EXCLUSIVE OR circuit 42, an output from which is conducted through the output lead 23 to the register 19. Where the initial bit output from the register 18 denotes 1, there obviously arises a carry operation. To this end, an AND gate 43 for the carry operation is connected to the two input terminals 21 and 22 of the EXCLUSIVE OR circuit 42. An output from the AND gate 43 is conducted to the second input terminal 22 of the adder 20 through a one-bit dynamic shift register or delayed flip-flop 44 and the OR gate 41. The delayed flip-flop 44 is supplied with shift pulses .phi..sub.1 and .phi..sub.2 and conducts the output from the AND gate 43 as a carry input to the adder 20 when the adder 20 is supplied with the second bit output from the register 18.

Four bit outputs of one digit received by the register 19 are further conducted to the decoder 27 through the parallel-in-parallel-out register 26, which is also supplied with a write-in pulse B.sub.8 .phi..sub.1 and read-out pulse B.sub.8 shown in FIG. 3. When outputs from the register 19 are supplied to the register 26 in the manner shown in FIG. 2, then bit outputs having binary significances of 1, 2, 4 and 8 are written into the register 26 by the write-in pulse B.sub.8 .phi..sub.1 and read out therefrom by the rear edge of the read-out pulse B.sub.8. The register 26 holds the outputs read out therefrom for a one-digit time interval.

Bit outputs from the register 19 having binary significances of 2 and 4 are supplied to an AND gate 45 included in the detector 30 for detecting a number 6. The AND gate 45 is supplied with digit pulses D.sub.2 and D.sub.4 through an OR gate 46. Therefore, when the contents of the second and fourth digits from the least significant digit of time information are supplied to the register 19 while the digit pulses D.sub.1 and D.sub.4 are generated, then the aforementioned detector 30 detects whether the contents of both digits denote a number 6. Where the number 6 is detected, the AND gate 45 produces an output. Bit outputs from the register 19 having binary significances of 2 and 8 are connected to an AND gate 47 to detect whether the first and third or fifth digits of time information represent a number 10. Where the content of the digits is 10, the AND gate 47 produces an output. Detection of the number 10 is effected when the contents of the first and third or fifth digits are supplied to the register 19, that is, when there are generated digit pulses D.sub.1 and D.sub.3 or D.sub.5, so that the AND gate 47 may be supplied with the digit pulses D.sub.1 and D.sub.3 or D.sub.5 through an OR gate corresponding to the OR gate 46.

Outputs from the AND gates 45 and 47 are supplied to a delayed flip-flop 49 through an OR gate 48. The flip-flop 49 causes outputs from the AND gates 45 and 47 to be written therein by the write-in pulse B.sub.8 .phi..sub.1 and read out therefrom by the rear edge of the read-out pulse B.sub.8, and holds the output thus read out for a one-digit time interval. While essentially consisting of a one-bit dynamic shift register, the flip-flop 49 may be formed of a semistatic shift register provided on its output side with a circuit for holding its output for a one-digit time interval. Such semistatic shift register is already known to those skilled in the art.

An output from the flip-flop 49 is conducted through a NOR gate 51 to an AND gate 50 included in the reset gate 31. Upon receipt of an output from the flip-flop 49, the AND gate 50 is rendered nonconductive. Accordingly, four-bit information on one digit stored in the register 19 is successively supplied to the AND gate 50 for a one-digit time interval to be reset or cleared. An output from the flip-flop 49 is supplied, together with a bit pulse B.sub.1, to an AND gate 52 included in the adder gate 25. An output from the AND gate 52 is conducted through the OR gate 41 to the second input terminal 22 of the adder 20. Where, therefore, time information on a particular digit stored in the shift register 19 represents a number 10 or 6, the time information stored in the shift register 18 or the next higher order digit receives a carry signal when the first bit output from the register 18 enters the adder 20.

The aforementioned selector 32 for choosing a 12- or 24-hours system includes, for example, a single pole-double throw switch 55, which may be of electronic type. One fixed contact of the switch 55 is grounded and the other fixed contact is connected to a power source 56. The movable contact of the switch 55 is directly connected to a first AND gate 57 included in the aforesaid detector 33, and further to a second AND gate 58 through an inverter 59. The first AND gate 57 is supplied, as shown, with a bit output from the register 18 having a binary significance of 2, as well as with a bit output from the register 19 bearing a binary significance of 4. On the other hand, the second AND gate 58 is supplied with a bit output from the register 18 having a binary significance of 1 and also a bit output from the register 19 having a binary significance of 2.

Where the movable contact of the switch 55 is connected, as shown in FIG. 2, to the grounded fixed contact in order to choose a 12-hour system, then the first AND gate 57 is disabled. Conversely where there is desired a 24-hour system, the movable contact of the switch 55 is switched over to the fixed contact connected to the power source 56 to disable the AND gate 58.

Where, in the case of a 12-hour system, the register 18 is supplied with time information on a digit 1 and the register 19 with time information on a digit 2, then the second AND gate 58 produces an output. Where, in the case of a 24-hour system, the register 18 is supplied with time information on a digit 2 and the register 19 with time information on a digit 4, then the first AND gate 57 generates an output.

Outputs from the first and second AND gates 57 and 58 are conducted to a delayed flip-flop 62 through an OR gate 60 and AND gate 61, which in turn is supplied with a digit pulse D.sub.5. The time information of two digits on hours are stored in the registers 18 and 19 when the digit pulse D.sub.5 exists. Where the digit pulse D.sub.5 is generated, the flip-flop 62 causes an output from the first or second AND gate 57 or 58 to be written therein by the write-in pulse B.sub.8 .phi..sub.1, and read out therefrom by the rear edge of the read-out pulse B.sub.8 and holds an output thus read out for one digit time interval. An output from the flip-flop 62 is supplied through an inverter 64 to an AND gate 63 included in the reset gate 34 and also through the NOR gate 51 to the AND gate 50 included in the reset gate 31. As the result, both AND gates 63 and 50 are disabled to reset or clear the successive four bit outputs from the registers 18 and 19.

The circuitry of an electronic digital clock apparatus according to this invention is adapted to be integrated, particularly on a large scale. For the integration, field effect transistors are preferred.

The clock apparatus of this invention permits incorporation of not only compensation circuits required for time information on numbers 10, 6, 12 and 24 as mentioned above, but also a circuit for resetting contents of all digit positions in time information, a circuit for resetting only contents of specified digit positions, a circuit for holding off the operation of adding a number 1 to any of the digits, that is, a stopwatch circuit, a time correction circuit and a time setting circuit. All various circuits required for such type of clock apparatus can be compactly integrated into a single chip as small as only four square millimeters.

Claims

We claim:

1. An electronic digital clock apparatus comprising:

shift register means for storing time information represented by a plurality of digits, said shift register means having stages equal to said digits in number;

generating means for generating pulses;

an adder means connected to said shift register means to form a closed loop therewith, said adder means including two input terminals, the first one of which being adapted to receive time information stored in said shift register means and the second one of which being adapted to receive one pulse as an addition input from said generating means when said first input terminal receives that portion of the time information stored in said shift register means which corresponds to a predetermined minimum unit length of time, said adder means comprising:

a two-input EXCLUSIVE OR means including a first input terminal for receiving said outputs from said shift register means and a second input terminal for receiving said addition input;

an AND means having two input terminals which are respectively connected to those of said EXCLUSIVE OR means;

a delay means for receiving an output from said AND means to produce an output after a predetermined time interval; and

an OR gate means for coupling said output from said delay means and said addition input to said second input terminal of said EXCLUSIVE OR means;

shift pulse generating means for circulating time information stored in said shift register means through said closed loop per the minimum unit length of time;

a decoder means connected to said shift register means for decoding outputs from a predetermined stage of said shift register means; and

a plurality of digit indicators connected to receive outputs from said decoder means for displaying time information stored in said shift register means.

2. An electronic digital clock apparatus comprising:

shift register means for storing time information represented by a plurality of digits, said shift register means having stages equal to said digits in number;

generating means for generating pulses;

an adder means connected to said shift register means to form a closed loop therewith, said adder means including two input terminals, the first one of which being adapted to receive time information stored in said shift register means and the second one of which being adapted to receive one pulse as an addition input from said generating means when said first input terminal receives that portion of the time information stored in said shift register means which corresponds to a predetermined minimum unit length of time;

shift pulse generating means for circulating time information stored in said shift register means through said closed loop per the minimum unit length of time;

detector means connected to a predetermined stage of said shift register means for detecting whether outputs from said stage correspond to a predetermined number, said detector means producing an output when said outputs correspond to said predetermined number;

reset gate means connected to the output side of said predetermined stage within said closed loop for resetting successive outputs from said predetermined stage in response to said output from said detector means;

an AND gate means for coupling said output from said detector means and said addition input to said second input terminal of said adder means;

a decoder means connected to said shift register means for decoding outputs from a predetermined stage of said shift register means; and

a plurality of digit indicators connected to receive outputs from said decoder means for displaying time information stored in said shift register means.

3. A clock apparatus according to claim 2 wherein said detector means includes means for holding said detection output for a predetermined time interval.

4. An electronic digital clock apparatus comprising:

shift register means for storing time information represented by a plurality of digits, said shift register means having stages equal to said digits in number;

generating means for generating pulses;

an adder means connected to said shift register means to form a closed loop therewith, said adder means including two input terminals, the first one of which being adapted to receive time information stored in said shift register means and the second one of which being adapted to receive one pulse as an addition input from said generating means when said first input terminal receives that portion of the time information stored in said shift register means which corresponds to a predetermined minimum unit length of time;

shift pulse generating means for circulating time information stored in said shift register means through said closed loop per the minimum unit length of time;

selector means for selecting the use of said clock apparatus either as a 12-hour or as a 24 hour system;

detector means connected to outputs of two adjacent stages of said shift register means for detecting whether numerical information stored in said two stages of said shift register means corresponds to a number 12 or 24 in response to selection by means of said selector means, said detector means producing an output where the numerical information stored in said two adjacent stages corresponds to the number 12 or 24;

first and second reset gate means connected to the respective output sides of said two stages of said shift register means within said closed loop resetting successive outputs from each of said two adjacent stages of said shift register means in response to said detection output from said detector means;

a decoder means connected to said shift register means for decoding outputs from a predetermined stage of said shift register means; and

a plurality of digit indicators connected to receive outputs from said decoder means for displaying time information stored in said shift register means.

5. A clock apparatus according to claim 4 wherein said detector means includes means for holding its output for a predetermined time interval.

6. A clock apparatus according to claim 4 wherein said adder means comprises two-input EXCLUSIVE OR means including a first input terminal for receiving said outputs from said shift register means and a second input terminal for receiving said addition input; an AND means having two input terminals which are respectively connected to those of said EXCLUSIVE OR means; a delay means for receiving an output from said AND means to produce an output after a predetermined time interval; and an OR gate means for sending said output from said delay means and said addition input to said second input terminal of said EXCLUSIVE OR means.

7. A clock apparatus according to claim 2 wherein said adder means comprises two-input EXCLUSIVE OR means including a first input terminal for receiving said outputs from said shift register means and a second input terminal for receiving said addition input; an AND means having two input terminals which are respectively connected to those of said EXCLUSIVE OR means a delay means for receiving an output from said AND means to produce an output after a predetermined time interval; and an OR gate means for sending said output from said delay means and said addition input to said second input terminal of said EXCLUSIVE OR means.

8. A clock apparatus according to claim 1 further comprising:

detector means connected to a predetermined stage of said shift register means for detecting whether outputs from said stage correspond to a predetermined number, said detector means producing an output when said outputs correspond to said predetermined number

reset gate means connected to the output side of said predetermined stage within said closed loop for resetting successive outputs from said predetermined stage in response to said output from said detector means; and

an AND gate means for coupling said output from said detector means and said addition input to said second input terminal of said adder means.

9. A clock apparatus according to claim 2 wherein said predetermined number is 6.

10. A clock apparatus according to claim 2 wherein said predetermined number is 10.

11. A clock apparatus according to claim 8 wherein said detector means includes means for holding said detection output for a predetermined time interval.

12. A clock apparatus according to claim 1 further comprising:

selector means for selecting the use of said clock apparatus either as a 12-hour or as a 24-hour system;

detector means connected to outputs of two adjacent stages of said shift register means for detecting whether numerical information stored in said two stages of said shift register means corresponds to a number 12 or 24 in response to selection by means of said selector means, said detector means producing an output where the numerical information stored in said two adjacent stages corresponds to the number 12 or 24; and

first and second reset gate means connected to the respective output sides of said two stages of said shift register means within said closed loop for resetting successive outputs from each of said two adjacent stages of said shift register means in response to said detection output from said detector means.

13. A clock apparatus according to claim 12 wherein said detector means includes means for holding its output for a predetermined time interval.

14. A clock apparatus according to claim 1 wherein said shift register means is of dynamic type.

15. A clock apparatus according to claim 1 wherein each stage of said shift register means includes four register elements.