U.S. patent number 3,778,810 [Application Number 05/178,926] was granted by the patent office on 1973-12-11 for display device.
This patent grant is currently assigned to Hitachi, Ltd.. Invention is credited to Yokitaka Hayashi.
United States Patent |
3,778,810 |
Hayashi |
December 11, 1973 |
DISPLAY DEVICE
Abstract
A display device comprising a computer processing unit, a
controlling unit including a pattern generator, and a display tube.
The pattern generator not only memorizes the predetermined patterns
for displaying the normal figures, letters, etc. but also has a
read-write function for displaying special figures, etc.
Inventors: |
Hayashi; Yokitaka (Hitachi,
JA) |
Assignee: |
Hitachi, Ltd. (Tokyo,
JA)
|
Family
ID: |
22654467 |
Appl.
No.: |
05/178,926 |
Filed: |
September 9, 1971 |
Current U.S.
Class: |
345/440 |
Current CPC
Class: |
G09G
1/14 (20130101) |
Current International
Class: |
G09G
1/14 (20060101); G08b 005/36 () |
Field of
Search: |
;340/324AD |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Trafton; David L.
Claims
I claim:
1. A display device for displaying a pattern as an assembly of a
plurality of sectional patterns, each sectional pattern being
displayed in one of the sections defined by horizontally and
vertically dividing a display plane, each section containing a
plurality of horizontal and vertical dot positions; said device
comprising a processing unit, memory means controlled by said
processing unit for storing selection signals for selecting a
sectional pattern for each section of said display plane, and a
pattern generator for storing a plurality of groups of digital
signals corresponding to various sectional patterns represented by
dot positions in the section and generating, according to the
selection signal from said memory means and horizontal and vertical
timing signals, a video signal composed of the digital signals so
derived from the signal groups of the selected sectional patterns
as to develop the whole pattern, said pattern generator including
means responsive to said processing unit for altering sectional
patterns stored in said pattern generator.
2. A display device according to claim 1, which further includes a
second pattern generator similar to the first pattern generator,
only said first pattern generator having means for altering
sectional patterns stored therein.
3. A display device according to claim 1, wherein said means for
altering sectional patterns stored in the pattern generator
comprises an address register for designating the address of a
pattern to be altered and a memory register through which a digital
signal to be written at the address designated by said address
register is supplied.
4. A display device according to claim 1, which includes a key
board for designating the address of data to be written in or the
data per se.
Description
BACKGROUND OF THE INVENTION
1. FIELD OF THE INVENTION
This invention relates to a display device, and more particularly
to a graphic device which can easily display any complicated
figures. More precisely, this invention is a display device based
on the standard television system and displaying any figures.
2. DESCRIPTION OF THE PRIOR ART
For example, consider the case where the figure of an automobile is
to be displayed in a display device, as is shown in FIG. 1. In FIG.
1, a display surface is divided into n and m sections in X and Y
directions respectively. One block of this display surface shown in
FIG. 1 is further divided into eight dots in X and Y directions,
respectively, as is shown in FIG. 2. FIG. 2 shows the blocks of (j
+ 5)th row (k + 3)the column, (j + 5)th row (k + 4)th column, (j +
6)th row (k + 3)th column, and (j + 6)th row (k + 4)th column.
For displaying such figures, there has been known a method in which
many kinds of display patterns, each for one block of the display
surface, are stored in a fixed memory and appropriately combined to
represent a desired figure.
According to this method, however, complicated figures cannot be
accurately represented unless a great many kinds of patterns such
as those shown in FIG. 2 are prepared. When the number of patterns
is limited, complicated curves may become unnatural and blocks of
complicated figures cannot be displayed unless appropriate patterns
are preliminarily stored.
When one wants to represent complicated figures accurately without
increasing the number of patterns very much, the size of one block
may be selected smaller. Namely, the number of dots per one block
may be decreased to simplify the patterns of the respective blocks
and thereby to decrease the number of possible patterns for one
block. The extreme case is one dot per one block. In such a case,
however, the main memory for storing the contents of respective
blocks would become very large. This invention intends to eliminate
these drawbacks.
SUMMARY OF THE INVENTION
An object of this invention is to provide a display device capable
of displaying complicated figures appropriately while having a
small number of patterns. According to one embodiment of the
invention, there is provided a display device comprising a memory
for storing signals for selecting a pattern, and a pattern
generator for storing the patterns and capable of changing the
patterns arbitrarily, i.e. having pattern amending function.
BRIEF DESCRIPTION OF THE DRAWING
FIG. 1 is an example of a figure displayed on a display
surface.
FIG. 2 is an elevation of some blocks on the display surface of
FIG. 1.
FIG. 3 is a block diagram of an embodiment of a display device
according to the invention.
FIG. 4 is a block diagram of another embodiment of a display device
according to the invention.
DESCRIPTION OF THE PREFERRED EMBODIMENTS
An embodiment of the invention is shown in FIG. 3, in which a
processing unit 1 such as an electronic computer supplies data of
the figure to be displayed to a controlling unit 2 for graphic
display, which unit stores the data therein, and the controlling
unit reads out the video signal continuously and cyclically
corresponding to said data and supplies it to a display unit 3 to
display the figure therein. The display unit 3 may be a cathode ray
tube.
In the controlling unit 2, a pattern generator 25 stores the
patterns of figures, characters, symbols, etc. to be represented in
respective blocks of the display surface. The pattern generator
contains memories for accommodating the address of one block of the
display surface and stores the video signal representing the states
of dots for respective scanning lines as in shown in the figure.
For example, when one scanning line is made up of five dots,
memories such as core memories of five bits are provided in the
pattern generator as shown in FIG. 3, corresponding to the address
and scanning lines on the display surface. An address register 24
receives the address of the pattern and a timing signal concerning
the order of the scanning lines from main memory 22 and a timing
control circuit 28, respectively. Then, the address register 24
supplies a signal to the pattern generator 25 to generate the
predetermined pattern. The pattern generator 25 supplies parallel
video signals as shown in the figure, which are stored in a memory
register 26. These parallel signals are converted into a series
signal in a parallel-series converter 27 and displayed on the
predetermined scanning line of the predetermined block on the
display tube 3.
A main memory 22 stores the information of pattern and address,
i.e. the information that patterns of which addresses are to be
displayed on which locations on the display surface, and reads out
the information in synchronism with the scanning line of the
display tube, the timing being provided by a timing controller 28.
A buffer register 21 stores the write signal when a memory in the
main memory 22 is to be altered. Now, the operation of the device
will be described taking the case of displaying letter "A" in
predetermined blocks. First, the image plane to be displayed is
divided into respective blocks as is shown in FIG. 1. Then, the
addresses of patterns, which patterns are displayed in the
respective blocks, are stored in the main memory 22 according to
the formation of the image plane. When letter "A" stored in address
(X,Y) of the main memory is to be displayed in said predetermined
blocks, the memory in address (X,Y) is read out from the main
memory in synchronism with the scanning on the scanning surface.
Thus, the information (X,Y) of address (X, Y) is read out to the
address register 24 at the timing. This is done through the fact
that the program of the processing unit 1 is made corresponding to
the formation of the image plane and that the output of the
processing unit 1 is memorized in the main memory 22. By this
procedure, the main memory 22 is synchronous with the scanning on
the display tube 3 and the address of the pattern to be represented
on the scanned block is successively read out. The content read out
from the memory 22 is sent to the pattern generator 25 through the
address register 24. When address (x, y) is read out at the
predetermined timing, the pattern generator 25 sends signals
corresponding to the dots as shown in the figure parallelly to the
memory register 26 in accordance with the signal designating
address (x, y) and the scanning line in the block.
Namely, for the first scanning line of address (x, y), five bit
digital signal of (00100) is parallelly supplied, where "1"
represents that the dot is a bright spot and "0" represents that
the dot is a dark spot.
Similarly, for the second scanning line of address (x, y), five bit
signal of (01010) is supplied. Similar operations are repeated for
the third, fourth and fifth scanning lines of the address. Parallel
signal (00100) of the first scanning line of address (x, y) is
converted into a series signal with respect to time t in the
parallel-series converter 27 and then displayed in the first
scanning line of the predetermined block of the display tube 3.
In such a display device, the feature of this invention lies in
that the pattern generator 25 is also provided with a read-write
function for forming and storing a new and appropriate pattern
corresponding to the figure to be displayed, as well as the
predetermined patterns.
The pattern generator 25 is so constructed that it receives the
address and the order of scanning line of a pattern to be written
in from the processing unit 1 through the address register 24 and
stores the data (pattern) to be written in supplied from the
processing unit 1 through the memory register 26.
Therefore, it is only necessary for the pattern generator 25 to
first store basic patterns of figures, characters and symbols which
are relatively frequently used and not special ones which are
rarely used.
A predetermined address or addresses may conveniently be reserved
for patterns to be changed in necessity. Hence, the contents
necessarily stored in the pattern generator may be very little and
yet any complicated figures can be appropriately displayed
easily.
FIG. 4 shows another embodiment of the invention in which separate
pattern generators are provided for letters, symbols and for
figures. Similar numerals indicate similar parts as those of FIG.
3.
A pattern generator 251 stores patterns of letters and symbols such
as alphabet and numerals and another pattern generator 252 stores
factors of figures in read-write fashion. References AND 1 to AND 3
are AND gates and INH is an inhibit gate. Further, DVA 1 is a
selection signal of the main memory 22 in the case of altering the
memorized content of the main memory, which memorizes the data from
the processing unit 1 or the key board in the main memory 22. DVA 2
is a selection signal of the address register 242, which supplies
the address designated by the processing unit 1 or the key board to
the pattern generator through the AND gate AND 2 and the address
register 242, and stores the pattern of the desired figure in the
memory of the selected address in the pattern generator sent from
the processing unit through the AND gate AND 3 and the memory
register 26. The inhibit gate INH prevents the address register 242
from accepting the address from the main memory 22 when selection
signal DVA 2 exists. DVA 3 is a selection signal of the memory
register 26.
Such a system as shown in FIG. 4 is very useful in constructing a
display device having a basic structure of a character display as
indicated by the dotted line I for displaying letters, symbols,
etc. and an optional structure of an image forming function for
supplying variable image patterns as indicated by the dotted line
II and further capable of adding various functions.
* * * * *