U.S. patent number 3,758,791 [Application Number 05/043,497] was granted by the patent office on 1973-09-11 for current switch circuit.
This patent grant is currently assigned to Hitachi, Ltd.. Invention is credited to Ichiro Imaizumi, Kenji Taniguchi.
United States Patent |
3,758,791 |
Taniguchi , et al. |
September 11, 1973 |
CURRENT SWITCH CIRCUIT
Abstract
A current switch circuit consisting of a couple of transistors,
one transistor acting as a reference element and the other as an
input element, a pair of series connections of a resistance element
and a diode being connected between the respective collectors of
the said transistors with the polarity of the diodes opposite to
each other, so that the emitter current of the transistors are
automatically regulated to maintain a predetermined value, whereby
the DC levels of the output voltages of the current switch circuit
are kept constant against temperature variation of the
transistors.
Inventors: |
Taniguchi; Kenji (Kodaira,
JA), Imaizumi; Ichiro (Kodaira, JA) |
Assignee: |
Hitachi, Ltd. (Tokyo,
JA)
|
Family
ID: |
12679681 |
Appl.
No.: |
05/043,497 |
Filed: |
June 4, 1970 |
Foreign Application Priority Data
|
|
|
|
|
Jun 6, 1969 [JA] |
|
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44/44009 |
|
Current U.S.
Class: |
326/33; 326/126;
326/32; 327/540 |
Current CPC
Class: |
H03K
17/14 (20130101); H03K 19/086 (20130101) |
Current International
Class: |
H03K
17/14 (20060101); H03K 19/086 (20060101); H03k
019/30 (); H03k 019/34 () |
Field of
Search: |
;307/202,213,214,215,218,237,297,310 ;330/23,3D |
References Cited
[Referenced By]
U.S. Patent Documents
Primary Examiner: Huckert; John W.
Assistant Examiner: Anagnos; L. N.
Claims
I claim:
1. A current switch circuit comprising:
at least one input transistor to whose base an input signal is
applied;
a reference transistor to whose base a reference voltage is applied
and whose emitter is connected with the emitter of said input
transistor;
load resistors connected respectively with the collectors of said
input and reference transistors;
emitter followers connected respectively with the collectors of
said input and reference transistors;
two diode circuits connected in parallel between the collectors of
said input and reference transistors, each of said diode circuits
comprising a diode and a resistor connected in series with said
diode for controlling current flowing through said diode, and
wherein said diodes disposed in said two diode circuits are
oriented in mutually opposite directions with respect to each
other;
emitter current regulating means connected in common with the
emitters of said input and reference transistors for regulating the
emitter current flowing through the commonly connected emitters, so
that said emitter current has a certain temperature coefficient;
and
a power supply source having a first power terminal connected with
said load resistors respectively and a second power terminal
connected with said emitter current regulating means for providing
a power potential between said first and second power
terminals,
whereby the D.C. voltage levels of the output signals derived out
from said emitter followers changeable due to temperature change
are stabilized.
2. A current switch circuit as defined in claim 1, wherein said
diodes in said diode circuits respectively provide a forward
voltage drop whose temperature coefficient is substantially the
same as that of the base-emitter forward voltage drop in said input
and the reference transistors, and said resistors in said diode
circuits respectively have the same resistance as that of said load
resistors.
3. A current switch circuit as defined in claim 2, which further
comprises a temperature-compensated biasing circuit which produces
a reference voltage having a substantially zero temperature
coefficient coupled to the base of said reference transistor.
4. A current switch circuit as defined in claim 1, wherein said
emitter current regulating means comprises a first transistor whose
collector is connected in common with the emitters of said input
and reference transistors and to whose base a regulation voltage is
applied, and means for connecting the emitter of said first
transistor with said second power terminal.
5. A current switch circuit as defined in claim 4, which further
comprises a temperature-compensated biasing circuit including:
a second transistor having its emitter-collector circuit coupled
between said first power supply terminal and the base of said
reference transistor;
a first biasing resistor coupled between the base of said second
transistor and said first power supply terminal;
at least one diode and a second biasing resistor connected in
series between said second power supply terminal and the base of
said second transistor; and
a voltage dividing circuit which comprises first and second
impedance means connected in series between the emitter of said
second transistor and the second power supply terminal, the common
connection of said first and second impedance means being connected
with the base of said first transistor.
6. A current switch circuit as defined in claim 5, wherein said
first and second impedance means are composed of third and fourth
biasing resistors respectively, and said means for connecting the
emitter of said first transistor with said second power supply
terminal is composed of a feedback resistor whose resistance value
is equal to one-half of that of said load resistors.
7. A current switch circuit as defined in claim 5, wherein said
first impedance means is composed of a diode, said second impedance
element is composed of a biasing resistor, and said means for
connecting the emitter of said first transistor with said second
power supply terminal is composed of a feedback resistor whose
resistance value is equal to that of said load resistors.
8. A current switch circuit as defined in claim 5, wherein said
first and second impedance means are composed of a biasing resistor
and a diode respectively, and said means for connecting the emitter
of said first transistor with said first power supply terminal is
composed of a conductor for directly connecting therebetween, the
resistance value R.sub.D of said first impedance means being so
selected as to satisfy the equation 1/2 R.sub.CN = R.sub.D
/.gamma., wherein R.sub.CN is the resistance value of said load
resistors and .gamma. is the ratio of the area of the emitter
junction in the first transistor to that of the junction in said
diode which comprises said second impedance means.
9. A current switch comprising:
at least one input transistor having an emitter, a base and a
collector;
means for connecting a biasing power supply across the collector
and emitter of said input transistor;
first and second output circuits, each of which is connected to
receive a signal from the collector of said at least one input
transistor and to provide output signals therefrom, the output of
one of said output circuits being at a first level while the output
of the other of said output circuits is at a level, different from
said first output level; and
means, coupled between said pair of output circuits for maintaining
the two different output levels from each of said first and second
output circuits substantially constant over a prescribed
temperature range, including a pair of pn junction-resistor
circuits, each of which comprises a pn junction and a resistor
connected in series, said pn junction-resistor circuits being
connected in parallel, and wherein the pn junctions are oppositely
poled with respect to each other within said parallel-connected
circuits.
10. A current-switch according to claim 9, further including a
reference transistor having an emitter, a base, and a collector,
the emitter of said reference transistor coupled to the emitter of
said at least one input transistor, and the collector of said
reference transistor being connected to one end of said pn
junction-resistor circuit, the other end of said pn junction
-resistor circuit being connected to the collector of said input
transistor.
11. A current switch according to claim 10, further including an
emitter current regulating means coupled in series between the
emitters of said input and reference transistor and a power supply
terminal.
Description
BACKGROUND OF THE INVENTION
1. Field Of The Invention
This invention relates to a current switch circuit, particularly to
such a circuit of which the DC level of the output voltage is kept
constant against the variation of the temperature of
transistors.
2. Description Of The Prior Art
The conventional current switch circuit consists of a so-called
reference transistor of which a reference voltage is impressed on
the base and a so-called input transistor of which an input signal
to the circuit is impressed on the base, both transistors being
connected with the emitters common.
A typical circuit including the current switch circuit as the basic
component is a circuit known as a CML (current mode logic) which
includes a plurality of input transistors, the respective emitters
as well as collectors of the input transistors being mutually
connected respectively, so that an OR output can be taken out from
the collector of the reference transistor and a NOR output from the
common collector lead of the input transistors.
The CML in which the transistors are operated in the respective
non-saturation regions so as not to be affected by the stored
charge, is an effective logic circuit compatible to the so-called
CTL (complementary transistor logic) especially in the operation
speed. In the practical use of a CML, a further stage of an emitter
follower is connected to each output circuit of the reference and
the input transistors so as to reduce the output impedance and to
equalize the levels of the input and output signals.
Conventional current switch circuits including the above-mentioned
CML, however, have a common drawback that the DC voltage levels of
the output signals change with variation in the temperature at the
junctions of the transistors because of the temperature dependence
of the forward base-emitter voltage. For example, with a typical
practical CML which is designed so as to have a logic swing voltage
of approximately 0.8 V with the "1" level of the output signal set
at -0.8 V or so, the "0" level at -1.6 V or so and the reference
level at -1.2 V or so, the 1 level signal is subject to the
variations with a temperature coefficient of about 1.3 to 2.0
mV/.degree.C, especially under the influence of transistors of the
emitter followers. As for the 0 level signal, the temperature
coefficient of the drift is found to be about 0.5 to 0.8
mV/.degree.C which is much lower than that for the 1 level signal.
This is due to the fact that the 0 level signal is affected also by
the temperature characteristics of the input transistors and
reference transistors which more or less compensate for the
influence of the drift of the emitter follower transistors.
Anyway, such temperature dependence of the output levels results in
a poor immunity of the signal against noise in the conventional
CML. Especially, if the conventional CML is fabricated in an
integrated circuit formation, such a circuit would sometimes fail
to operate at the intended logic swing voltage, as the component
circuit elements are not allowed sufficient heat dissipation.
Further, the limit level of the input signal below which the logic
circuit can operate in a non-saturation state, also varies with the
temperature coefficient of about -1.5 to -1.8 mV/.degree.C in a
range of -0.4 to -0.8 V. Therefore, if the 1 level signal rises
with a temperature rise, it is possible for the signal level to
trespass on the saturation region, exceeding the above-mentioned
limit level. This necessitates a more limited tolerance of the
temperature characteristics of the component circuit elements.
SUMMARY OF THE INVENTION
The object of this invention is to provide a current switch circuit
of which the DC levels of the output voltages are not affected by
temperature variations of transistors.
In order to achieve the above object, the current switch circuit of
this invention comprises a reference transistor and an input
transistor with the respective emitters connected together, the
common emitter lead being connected to an emitter source terminal
through a means for regulating the emitter current, output signals
being derived from the respective collectors of the said
transistors through emitter follower circuits respectively, and
further the said current switch circuit is provided with a pair of
additional routes connecting both collectors, each consisting of a
series connection of a diode and a resistance element, the
conducting direction of said pair of routes being mutually
opposite.
Other objects, features and merits of this invention will be
clarified by the following description with reference to the
accompanying drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
FIG. 1 is a circuit diagram of an embodiment of this invention.
FIG. 2 is a characteristic diagram of a transistor showing the
relation between the temperature coefficient of the base-emitter
forward voltage and the emitter current.
FIG. 3 is a diagram showing manners of connection of semiconductor
elements used in this invention.
FIGS. 4a and 4b are circuit diagrams of two other embodiments of
this invention.
FIG. 5 is a complete circuit diagram of a logic circuit
incorporating the circuit shown in FIG. 1.
FIGS. 6 and 7 are circuit diagrams showing modifications of a
portion of the circuit shown in FIG. 5.
FIG. 8 is a circuit diagram of an alternative setup of the circuit
shown in FIG. 5
DESCRIPTION OF THE PREFERRED EMBODIMENTS
Referring to FIG. 1 which shows a current switch circuit of this
invention applied to a CML, reference numeral 10 designates a
reference transistor to whose base terminal 11 is applied a
reference voltage V.sub.BB, and 20 an input transistor to whose
base terminal 21 is applied an input voltage. It is assumed that
the input transistor 20 represents a plurality of similar
transistors connected in parallel to receive a corresponding number
of input signals of the CML. The emitters 12 and 22 of the
reference and input transistors 10 and 20 are connected together
and led to the emitter source terminal 31 through an emitter
current regulating means 30. The respective collectors 13 and 23 of
the reference and input transistors 10 and 20 are connected to the
collector source terminal 32 respectively through load resistors 14
and 24 whose resistance values are R.sub.CP and R.sub.CN
respectively. Another transistor 15 constitutes an emitter follower
with the base thereof connected with the collector 13 of the
reference transistor 10. The emitter of the transistor 15 is the OR
output terminal 16 of the CML. On the other hand, still another
transistor 25 constitutes another emitter follower with the base
thereof connected with the collector 23 of the input transistor 20.
The emitter of the transistor 25 is the NOR output terminal 26 of
the CML. Reference numerals 17 and 27 respectively designate load
resistors connected between the emitter source terminal 31 and the
emitters of the transistors 15 and 25. Further, a pair of series
connections respectively consisting of a resistance element 36 and
a diode 33, and a resistance element 35 and a diode 34, are
connected between the collector 13 and 23 of the transistors 10 and
20 in a manners that the conducting direction of the series
connections are opposite to each other. The temperature
compensation for the output signal of the CML is acheved by
providing these series connections, as will be described
hereinafter.
The circuit shown in FIG. 1 is operated, for example, with the
collector source terminal 32 grounded, therefore the potential
V.sub.CC at the collector source terminal 32 being zero Volt and
the potential V.sub.EE at the emitter source terminal 31 being
negative. It is assumed in the following description that the input
signal V.sub.IN is at the 1 level and the input transistor 20 is
conducting while the reference transistor 10 is in the shutoff
state. For convenience of the explanation, it is further assumed
that the emitter-grounded current amplification factor .beta. and
the base-emitter forward voltage drop V.sub.BE are identical for
all of the above transistors, and that the forward voltage drop
V.sub.D of the diodes 33 and 34 are identical. Moreover, the base
current of the transistors 15 and 25 are neglected in the following
explanation.
With the input signal V.sub.IN at the 1 level, the diode 33 is not
conducting while the other diode 34 conducts, and an output signal
V.sub.1 of the 1 level appears at the output terminal 16 while an
output signal V.sub.0 of the 0 level appears at the output terminal
26. These output voltages V.sub.1 and V.sub.0 can be expressed in
the following formulas.
V.sub.1 = (R.sub.CN /R.sub.S + R.sub.CP + R.sub.CN) (V.sub.D -
R.sub.CN.sup.. .alpha. I.sub.E) - V.sub.BE (1) V.sub.0 = (R.sub.CN
/R.sub.S + R.sub.CP + R.sub.CN) [ - V.sub.D - (R.sub.S +
R.sub.CP).sup. . .alpha. I.sub.E ] - V.sub.BE (2)
where,
I.sub.E is the emitter current;
R.sub.S is the resistance of the resistance elements 35 and 36;
and
.alpha. = .beta. / (.beta. + 1)
In order to determine the temperature dependence of the output
voltage V.sub.1 and V.sub.0, the above equations 1 and 2 are
differentiated by the temperature T. As the terms of the resistance
ratio have nothing to do with the temperature dependence, the
following equations are derived
dV.sub.1 /dT = (R.sub.CP /R.sub.S +R.sub.CP +R.sub.CN) [ (dV.sub.D
/dT) - d(R.sub.CN.sup.. .alpha..sup.. I.sub.E)/dT ] - dV.sub.BE /dT
(3) dV.sub.0 /dT = (R.sub.CN /R.sub.S +R.sub.CP +R.sub.CN) [ -
(dV.sub.D /dT) - (R.sub.S +R.sub.CP /R.sub.CN) .sup.. d(R.sub.CN.su
p.. .alpha. .sup.. I.sub.E)/dT ] - dV.sub.EB /dT (4)
therefore, the conditions for eliminating the temperature
dependence of the output voltage V.sub.1 and V.sub.0 can be
determined by regarding that the left side of each of the above
equations 3 and 4 is zero. That is:
R.sub.S /R.sub.CP = (dV.sub.D /dT)/(dV.sub.BE /dT) (5)
d(R.sub.CN.su p.. .alpha. .sup.. I.sub.E)/dT = (dV.sub.D /dT) -
(R.sub.S + R.sub.CP + R.sub.CN /R.sub.CP) .sup.. (dV.sub.BE /dT)
(6)
in the above equations 5 and 6, the term dV.sub.BE /dT representing
the temperature dependence of the base-emitter voltage of the
transistors is related to the emitter current as shown in FIG. 2,
the range of the value being roughly -1.5 to -2.0 mV/.degree.C. It
is known that the term dV.sub.D /dT has a value near to that of
dV.sub.BE /dT. Especially, if the diode is constituted by
connecting together the base and the collector of a transistor as
shown in FIG. 3, as is often found in semiconductor integrated
circuits, the value of dV.sub.D /dT can be made equal to that of
dV.sub.BE /dT. Therefore, assuming dV.sub.BE /dT = dV.sub.D /dT
.apprxeq. - 2 (mV/.degree.C) (7)
from the equation 5, R.sub.S = R.sub.CP.
As the load resistances R.sub.CP and R.sub.CN are nearly identical
in ordinary current switch circuits, one of the required conditions
for stabilizing the circuit against temperature variations is
presented as follows:
R.sub.S = R.sub.CP = R.sub.CN (8)
similarly, from the above-mentioned assumption 7 and the equation
6,
d(R.sub.CN.sup.. .alpha. .sup.. I.sub.E)/dT = - 2 (dV.sub.BE
/dT)
therefore, it will be seen that the required stabilizing conditions
can be achieved by setting the temperature characteristics of the
emitter current I.sub.E so that the condition of the above equation
9 is satisfied. Various methods for setting the emitter current in
such a manner as mentioned above will be shown in the following
description of the embodiments of this invention.
Meanwhile, in the conventional CML, the output signal levels
V.sub.1 and V.sub.0 would drift at different temperature
coefficients. Therefore, the reference voltage source in the
conventional CML should be so designed that the reference voltage
V.sub.BB renders an intermediate temperature coefficient between
those for the levels V.sub.1 and V.sub.0, 1.1 mV/.degree.C for
example. According to the present invention, however, the reference
voltage source should be designed so as to produce a constant
voltage, as both output signals V.sub.1 and V.sub.0 have zero
temperature coefficient.
FIGS. 4a and 4b show further embodiments of this invention. In FIG.
4a are shown the diodes 33 and 34 connected in parallel in opposite
directions, the parallel connection of these diodes being connected
between the respective collectors of the transistors 10 and 20
through resistors 35 and 36. Further, in FIG. 4b, a resistor 37 is
seen to be substituted for the two resistors 35 and 36 in FIG. 4a,
the resistance value of the resistor 37 being equal to the sum of
the resistance values R.sub.1 and R.sub.2 of the resistors 35 and
36. Other components shown in FIGS. 4a and 4b correspond to those
indicated by similar reference numerals in FIG. 1. Also, the
principle and operation of the temperature compensation with the
circuits shown in FIGS. 4a and 4b are the same as those described
above in connection with FIG. 1. Therefore, repeated explanation is
omitted.
Referring to FIG. 5 which more tangibly shows a CML incorporating
the circuit of this invention, elements or components corresponding
to those shown in FIG. 1 are designated with similar reference
numerals. The reference base voltage V.sub.BB of the reference
transistor 10 is supplied from a biasing circuit 40 indicated by a
dot-and-dash line box in FIG. 5. This biasing circuit consists of a
transistor 41, biasing resistance elements 42, 43, 44 and 45, and
an appropriate number of diodes 46 for temperature compensation,
and is composed in a manner that the variation in the base-emitter
voltage drop of the transistor 41 due to the change of the
temperature is compensated by a voltage drop in the above diodes 46
to thereby make the temperature coefficient for the reference
voltage V.sub.BB zero. Further, the emitter current regulating
means 30 which is connected between the emitter source terminal and
the common emitter lead of the reference and input transistors,
consists of a transistor 50 and a resistance element 54 connected
to the emitter 51 of this transistor for providing a feedback
voltage. The base 53 of the transistor 50 is connected to the
biasing circuit 40 to be driven with a voltage divided by the
resistors 44 and 45 in the biasing circuit 40.
Defining that R.sub.EE is the resistance value of the resistor 54,
V.sub.J the potential of the base 53 of the transistor 50, and
V.sub.BE the base-emitter forward voltage drop, and further,
assuming that the current amplification factor .beta. of the
transistor 50 is sufficiently high, the condition for producing an
emitter current I.sub.E which will satisfy the condition of the
afore-mentioned equation 9 can be determined as follows.
Firstly, as is seen from FIG. 5, I.sub.E = (V.sub.J - V.sub.BE -
V.sub.EE /R.sub.EE) .times. .alpha. (10)
where, .alpha. = (.beta./.beta. + 1)
As the biasing circuit 40 is designed so as to have no temperature
dependence as mentioned previously, the voltage V.sub.J does not
change with variations of temperature. Therefore, substituting the
above formula 1 into the left side of the equation 9,
d(R.sub.CN.sup.. .alpha. .sup.. I.sub.E)/dT = (R.sub.CN.sup..
.alpha..sup.2 /R.sub.EE) .sup.. [ - (dV.sub.BE /dT) ] = -2 .sup..
(dV.sub.BE /dT) (11)
therefore, R.sub.CN /R.sub.EE = 2/.alpha. .sup.2 .apprxeq. 2
(12)
this is the condition for setting the value of the emitter current
I.sub.E at the desired level. Thus, in the circuit shown in FIG. 5,
the condition of the equation 9 is satisfied by setting the
resistance of the element 54 at approximately one half of the
resistance of the load resistor 24, as will be clear from the
relation between the resistances R.sub.CN and R.sub.EE shown in the
above formula 12. In this manner, the temperature dependence of the
output signal levels V.sub.1 and V.sub.0 are completely
eliminated.
In the above embodiment, the biasing circuit 40 may be constructed
integrally with the other part of the CML, that is, may be
incorporated in a semiconductor integrated circuit. Or, it may be a
separate unit from the main part of a CML. Further, various other
circuit configurations are possible for the biasing circuit 40 so
as to be adapted for various emitter source voltages V.sub.EE,
reference voltages V.sub.BB and other requirements.
FIG. 6 shows one example of such other configurations of the
biasing circuit 40. As is seen in the Figure, a resistance element
47 is connected across one (46a) of the plurality of temperature
compensating diodes 46 in order to facilitate accurate matching of
the temperature coefficients of the reference voltage V.sub.BB and
the driving voltage V.sub.J.
FIG. 7 is another example of the biasing circuit 40. In this
example, it will be noted that the driving voltage V.sub.J for the
transistor 50 is not kept constant, as a diode 48 is inserted
between the reference voltage terminal 11 for the reference
transistor 10 and the driving voltage terminal 53 for the
transistor 50. Thus, the circuit is designed so that the reference
voltage V.sub.BB is immune to temperature variation, while the
driving voltage V.sub.J increases with the temperature rise because
of the temperature dependence of the forward voltage drop V.sub.D
of the diode 48. As is clear from FIG. 7,
V.sub.J = V.sub.BB - V.sub.D .apprxeq. V.sub.BB - V.sub.BE.
Substituting the above formula into the afore-mentioned equation
10, and further the resultant formula to the equation 9, the
following is obtained as the condition for setting the emitter
current I.sub.E.
R.sub.CN /R.sub.EE .apprxeq. 1
Thus, even when the driving voltage V.sub.J is variable against
temperature, the temperature dependence of the output signal level
can be eliminated by setting the resistance value of the emitter
resistor 54 to be nearly equal to the resistance value of the load
resistor 24.
FIG. 8 shows another example of the CML in which the circuit of
this invention is incorporated. In this circuit, the base-emitter
voltage of the transistor 50 which regulates the emitter currents
of the reference and input transistors 10 and 20, is set by a diode
55 connected between the base 53 and the emitter 51 of the
transistor 50, and the base 53 is also connected to the reference
voltage terminal 11 through a resistance element 44. Assuming that
the circuit is constructed in the form of a semiconductor
integrated circuit and that the ratio of the area of the emitter
junction in the transistor 50 to that of the junction in the diode
55 is .gamma., the emitter current I.sub.E is about .gamma. times
as large as the current flowing through the diode 55. The greater
part of the current I.sub.1 which flows through the resistance
element 44 (whose resistance value is assumed to be R.sub.D) flows
through the diode 55. Therefore, assuming that the forward voltage
drop in the diode 55 is V.sub.D, the emitter current I.sub.E of the
transistor 50 is determined by the following formula.
I.sub.E .apprxeq. .gamma. .sup.. [V.sub.BB - (V.sub.BE +
V.sub.D)/R.sub.D
The value of V.sub.D is nearly equal to the base-emitter voltage
drop V.sub.BE of the transistor. Substituting the formula 14 into
the left side of the previously shown equation 9 (note that .alpha.
is nearly equal to 1),
[R.sub.CN /(R.sub.D /.gamma.)] .apprxeq. 2 (15)
the above relation is the condition for setting the emitter current
I.sub.E in this circuit.
It will be clear from the above description that in the current
switch circuit of this invention, the DC voltage levels of the
output signals can be stabilized against temperature variations by
setting the emitter currents of the reference and input transistors
at a proper amount.
Though, in this specification the manner of setting the emitter
current of the current switch circuit has been described under the
assumption expressed by the previously shown equation 7, it will be
clear that the principle of this invention can be put into practice
regardless of the above assumption. Further, it will be understood
that the emitter current regulating means used in the circuit of
this invention is not limited to such types as shown in the above
embodiments, and that other types of circuits which can render the
emitter current to have an appropriate temperature characteristics
can also be used as the regulating means.
* * * * *