Electronic Amusement Device

Abstract

Electronic apparatus for simulating the throwing of a pair of dice including two counters each of which is operable to count continuously in sequence through six operating states. The counters are each caused to count by high frequency triggering pulses from respective pulse generators. The particular operating state of each counter is indicated on a suitable display. A single push-button switch is depressed momentarily to actuate the two pulse generators thus causing the counters to switch continuously through the six operating states. When the push-button switch is released, the counters stop and the operating states at which they remain can be determined from their respective displays.

Description

BACKGROUND OF THE INVENTION

This invention relates to amusement devices for generating numbers by chance. More particularly, it is concerned with electronic apparatus for selecting numbers by chance from a set of numbers; for example, in order to simulate the throwing of dice.

Many games and pastimes which employ chance as a factor require the generation of numbers by chance from a set of numbers. One common method of generating these numbers is by shaking and rolling out two ivory cubes with a different number of spots, from one through six, marked on each of the six faces of each cube. These cubes, called dice, have been widely used for centuries.

There are various problems in employing dice to generate numbers by chance. Mechanical imperfections in a die may alter the probability that each of the six faces has an equal chance of being turned up. In addition, it is difficult to throw dice in a confined space which permits only limited physical movement, and it is extremely difficult to employ dice when undergoing motion as when in automotive vehicles or aircraft.

SUMMARY OF THE INVENTION

Many of the problems associated with the chance selection of numbers by throwing dice are eliminated by employing apparatus in accordance with the present invention. An amusement device in accordance with the invention includes a counter circuit means which is operable to be switched through a predetermined recurring sequence of operating states by triggering pulses applied at its input. A pulse generating means is connected to the input of the counter circuit means and operates to produce triggering pulses during the occurrence of an energizing signal at its control connection. A manually-operated switch means is connected to the control connection of the pulse generating means and is operable to produce this energizing signal when it is actuated. An output means is connected to the counter circuit means to provide an indication of the operating state of the counter circuit means.

Thus, actuation of the manually-operated switch means causes the counter circuit means to be switched continuously through the predetermined recurring sequence of operating states by triggering pulses from the pulse generating means. Upon termination of the actuation of the manually-operated switch means, the counter circuit means stops switching, and the output means provides an indication of the particular opening state in which the counter circuit means remains upon termination of actuation of the manually-operated switch means.

BRIEF DESCRIPTION OF THE DRAWINGS

Additional objects, features, and advantages of amusement devices in accordance with the present invention will be apparent from the following detailed discussion together with the accompanying drawings wherein:

FIG. 1 is a logic diagram of an amusement device in accordance with the invention for simulating the throwing of a pair of dice;

FIG. 2 is a perspective view of an amusement device for incorporating circuitry corresponding to the logic diagram of FIG. 1 showing the operating controls and an arrangement for displaying the readout from the circuitry;

FIG. 3 is a logic diagram of a modification of the logic diagram of FIG. 1 employing an alternative form of the display of the readout;

FIG. 4 is a detailed circuit diagram of a pulse generating circuit which may be employed in the devices of FIGS. 1 and 3; and

FIG. 5 is a detailed circuit diagram of a circuit which may be employed in driving incandescent lamps employed as indicators in the displays of FIGS. 1 and 3.

DETAILED DESCRIPTION OF THE INVENTION

FIG. 1 is a logic diagram illustrating electronic apparatus in accordance with the invention for simulating the throwing of a pair of dice. The apparatus includes two counters 10 and 11 each of which is caused to switch through a recurring sequence of six different possible operating states by triggering pulses applied at its input from a respective pulse generator 12 and 13. The two pulse generators 12 and 13 are actuated by depressing a single push-button switch 14.

As shown in FIG. 1, each of the counters 10 and 11 provides a binary readout of its operating state. As is well understood, a binary readout of six possible states requires three binary indicators. As shown, the readout for each counter 10 and 11 is a display of three incandescent lamps 15, 16, and 17, and 18, 19, and 20 having assigned values of "1," "2," and "4," respectively. The lamps are operated by driving circuits 21, 22, and 23, and 24, 25, and 26 connected to output connections from the counters 10 and 11, respectively. The decimal value of each counter state is determined by adding together the values of each of the lighted indicator lamps associated with that counter.

The device is operated by momentarily depressing the push-button switch 14 causing pulse generators 12 and 13 each to produce a train of triggering pulses to the respective counters 10 and 11. The counters switch continuously through the sequences of the six operating states and upon termination of the pulse trains remain operating in the last operating states to which they were switched. Since the frequency of the trigger pulses is extremely high, it is impossible to control or predict the particular operating states at which the counters stop. Thus, these states are determined solely by chance. The values of the lighted lamps of each set of indicator lamps 15, 16, and 17 and 18, 19, and 20 are individually added to provide numbers simulating numbers obtainable from each of the two dice of a pair.

The logic arrangement of each counter 10 and 11 is the same. Counter 10, for example, includes three bistable circuits 31, 32, and 33. The bistable circuits includes J-K flip-flops having two AND gates connected through an OR gate to each of the J and K inputs, respectively. As is well understood, a J-K flip-flop is switched from one stable condition during which an output signal is produced at its Q output to another stable condition during which an output signal is produced at its Q output by a triggering pulse if input signals at its input logic provide a signal at its J input. Similarly, it is switched from the other stable condition to the one stable condition by a triggering pulse if input signals at its input logic provide a signal at its K input.

The connections as shown between the Q and Q outputs of the bistable circuits and the AND gate inputs are such that the J-K flip-flops are conditioned to switch continuously through six combinations of operating conditions. As shown, the bistable circuits 31, 32, and 33 are designated as having values of 1, 2, and 4, respectively. The bistable circuits may be considered as producing these respective values when their respective Q outputs are at the more positive or higher of two voltage levels. The driving circuits 21, 22, and 23 are inverters in a logic sense and thus a relatively high voltage level at a Q output causes the respective incandescent lamp to light. The counter 10 as shown counts in repetitive sequence from 1 through 6, as indicated by summing the values of the lighted lamps 15, 16, and 17. The count advances a value of 1 for each triggering pulse.

The pulse generator 12 for producing the triggering pulses to the counter 10 includes a Schmitt trigger circuit 35 having a delay in its switching characteristic caused by an RC network R1 and C1. A NAND gate 36 has its output connected to the input of the Schmitt trigger circuit 35. A feedback connection 37 from the output of the Schmitt trigger circuit is connected to one of the input connections of the NAND gate 36. Another input to the NAND gate 36 is connected through the normally-closed push-button switch 14 to ground.

While the normally-closed push-button switch 14 remains closed, the low voltage at the control input connection of the NAND gate 36 holds the output of the NAND gate 36 and thus the output of the Schmitt trigger circuit relatively high. When the push-button switch 14 is actuated, the pulse generator becomes a free-running multivibrator. That is, when a relatively high voltage level occurs at the output of the Schmitt trigger circuit 35, it is inverted by the NAND gate 36 producing a relatively low voltage level at the input to the Schmitt trigger circuit. After a delay caused by the RC network R1 and C1 the Schmitt trigger circuit switches states to produce a relatively low level voltage at its output. This voltage level is applied to the NAND gate 36 and inverted to produce the relatively high voltage level at the input to the Schmitt trigger circuit. After a delay, the Schmitt trigger circuit switches and the voltage at its output again becomes relatively high. Thus, the pulse-generator 12 produces a continuous train of triggering pulses to the counter 10 while the push-button switch 14 is depressed. Whenever the push-button switch 14 is released, the control input connection to the NAND gate 36 is grounded, and the input to the Schmitt trigger circuit 35 and also the output of the Schmitt trigger circuit remains at the relatively high voltage level thus terminating the train of triggering pulses.

Apparatus in accordance with the logic diagram of FIG. 1 has been fabricated by assembling standard integrated circuits. Each of the bistable circuits 31, 32, and 33, and 41, 42, and 43 of the two counters 10 and 11 was a Sylvania SF-60 series J-K flip-flop with OR inputs. The two Schmitt trigger circuits 35 and 45 were the two separate circuits of a Sylvania SG-80 series dual pulse-shaper/delay AND gate. Each of these circuits has an internal resistance R1 and R2 of 4000 ohms and external capacitors C1 and C2 of 1 microfarad were employed. The NAND gates 36 and 46 of the pulse generators 12 and 13 were each one of the gate circuits of a Sylvania SG-140 series quad 2-input NAND/NOR gate. The inverter driving circuits 21, 22, and 23, and 24, 25, and 26 were individual circuits of Sylvania SG-350 series quad 2-input/lamp drivers.

The logic circuitry of the apparatus of FIG. 1 together with four D-size batteries connected in series to provide the Vcc operating voltage for the apparatus may be mounted within an enclosure 51 such as that illustrated in FIG. 2. The logic circuitry is connected to the batteries by means of an on-off switch 52. The push-button switch 14 is depressed causing the pulse generators 12 and 13 to produce triggering pulses. The counters 10 and 11 switch continuously through their sequences of six possible operating states until the push-button switch 14 is released terminating the trains of triggering pulses. The indicator lamps 15, 16, and 17, and 18, 19, and 20 may be located within a suitable light transmitting display arrangement 53 which represents the spots on dice. Thus, a simulated throw of the dice is accomplished by momentarily depressing the push-button switch 14 and adding together the number of spots on the lighted simulated dice of each set of three dice.

A modifications of the apparatus of FIG. 1 is illustrated in the logic diagram of FIG. 3. The apparatus of FIG. 3 employs the same counters 10 and 11, pulse generators 12 and 13, and push-button switch 14 as the apparatus of FIG. 1. However, a different form of display 61 and 62 is employed requiring a different decoding arrangement 63 and 64 between the Q and Q outputs of the bistable circuits 31, 32, and 33 and 41, 42, and 43 of the counters and the incandescent lamps of the displays 61 and 62. Each display, 61 for example, includes seven incandescent lamps 71, 72, 73, 74, 75, 76, and 77 arranged in a pattern which corresponds to all six of the possible arrangements of spots on the six faces of a die.

The decoder 63 includes an arrangement of NAND gates and inverting driver circuits for causing appropriate lamps of the display to be lighted in response to each particular combination of operating conditions of the bistable circuits 31, 32, and 33. The six possible combinations of operating conditions and the corresponding lamps which are lighted are summarized in the following table.

Bistable Circuits Display Output Terminals Having Relatively High Output Voltage Lighted Lamps 1 F/F 2 F/F 4 F/F 1 Q Q Q 74 2 Q Q Q 71, 77 3 Q Q Q 71, 74, 77 4 Q Q Q 71, 73, 75, 77 5 Q Q Q 71, 73, 74. 75, 77 6 Q Q Q 71, 72, 73, 75, 76, 77

thus, the display simulates the familiar pattern of spots on the faces of a die.

FIG. 4 is a circuit diagram of a Schmitt trigger circuit 35 employed in the pulse generators 12 and 13 of FIGS. 1 and 3. The circuit illustrated within the dashed lines 80 is one of the circuits in a Sylvania SG-80 series dual pulse-shaper/delay AND gate. An external capacitance C1 is connected as shown to provide with the internal resistance R1 and RC delay network. In the pulse generators 12 and 13 employed, the AND arrangement of inputs to the Schmitt trigger circuit is not required and only a single input to the input transistor T1 is used.

In brief, the Schmitt trigger circuit 35 operates as follows. When the voltage applied at the input of transistor T1 increases from a relatively low level toward a relatively high level, current flow through resistance R1 and across the base-emitter junction of transistor T1 is reduced and the voltage at its collector increases. This action is delayed because of the RC network R1 and C1 connected between the base of transistor T1 and ground. Current flow increases in transistor T2 causing the previously conducting transistors T3 and T4 to become non-conducting. Transistors T5 and T6 then conduct to establish the relatively high voltage level at the output terminal.

When the voltage at the input of transistor T1 decreases, current flow through the resistance R1 and across the base-emitter junction of transistor T1 increases and the voltage at its collector decreases. This action is also delayed because of the RC network R1 and C1 connected to the base of the transistor T1. Current flow decreases in the collector circuit of transistor T2 causing transistor T3 to be biased heavily into conduction. Transistor T4 is thereby caused to conduct heavily reducing the voltage at the output terminal to the low level.

The Sylvania SG-80 series gate has an internal resistance R1 of 4000 ohms. When an external capacitor C1 of 1 microfarad is employed, the pulse generator 12 produces triggering pulses at a rate of approximately 1,000 pulses per seconds. It should be noted that because of minute circuit differences, particularly in the capacitors, the two pulse generators 12 and 13 will not operate at precisely the same rate.

FIG. 5 is a circuit diagram of one of the driver inverter gates employed in the decoding arrangements of FIG. 1 and FIG. 3. The gate illustrated is one of the circuits in a Sylvania SG-350 series quad 2-input line/lamp driver. The circuit has two inputs to transistor T7 thus providing a NAND arrangement. When only a single input is used, the circuit is an inverter. As shown in FIGS. 1 and 3 an indicator lamp is connected between the output terminal of the driver circuit and the supply voltage Vcc. Thus, when a low voltage level is present at any one of the inputs to transistor T7, the output transistor T8 is non-conducting presenting a high impedance to current flow through the lamp and thus the lamp is not lighted. When a high voltage level is present at all of the inputs being used, the output transistor T8 is biased into conduction and the lamp is lighted.

Although in the disclosed embodiments the counters count upward and numerical values are displayed in order from 1 through 6, different sequences of counting and of displaying are possible. Two different forms of displays are illustrated. However, by the use of suitable decoding arrangements other forms of output indicia may be employed. For example, separate indicators of various types may be employed to designate each of the six states of each counter, or a single standard seven-segment numeric display may be employed for each counter. Furthermore, although apparatus for simulating the throwing of a pair of dice has been described in detail herein, the set of numbers, as determined by the possible combination of operating states of a counter, from which a number is to be selected by chance may be increased or decreased.

Thus, while there has been shown and described what are considered preferred embodiments of the present invention, it will be obvious to those skilled in the art that various changes and modifications may be made therein without departing from the invention as defined in the appended claims.

Claims

What is claimed is:

1. An amusement device for producing one of a plurality of possible output indications selected by chance including in combination

counter circuit means operable to be switched through a predetermined recurring sequence of operating states by triggering pulses applied at the input thereto, and operable to remain in an operating state in the absence of triggering pulses;

pulse generating means connected to the input of the counter circuit means and operable to produce triggering pulses during the occurrence of an energizing signal at a control connection;

manually-operated switch means connected to the control connection of the pulse generating means and operable to produce said energizing signal when actuated; and

output means connected to the counter circuit means and operable to provide an indication of the operating state of the counter circuit means;

said pulse generating means including

Schmitt trigger circuit means operable to produce a continuous train of pulses at its output in response to a first voltage condition being present at its input and operable to cease producing said continuous train of pulses at its output in response to a second voltage condition being present at its input,

resistance-capacitance delay means coupled to the Schmitt trigger circuit means and operable to cause a delay in the operation of the Schmitt trigger circuit means in producing said pulses at its output in response to the occurrence of said first voltage condition at its input, and

inverting gate means having a first input connection connected to the output of the Schmitt trigger circuit means and a second input connection constituted by said control connection, and an output connection connected to the input of said Schmitt trigger circuit means, said inverting gate means being operable while said energizing signal is present at its control connection as a result of said switch means actuation to produce the first voltage condition at its output connection, said inverting gate means being operable while said energizing signal is absent at its control connection as a result of said switch means deactuation to produce the second voltage condition at its output; whereby actuation of the manually-operated switch means causes the counter circuit means to be switched continuously through the predetermined recurring sequence of operating states by triggering pulses from the pulse generating means, and termination of actuation of the manually-operated switch means causes the counter circuit means to stop switching and the output means to provide an indication of the particular operating state of the counter circuit means upon termination of actuation of the manually-operated switch means.