Analog Display Using Light Emitting Diodes

Abstract

A scanned solid state planar display wherein two successive rows are simultaneously energized. Only the latest row energized is written as the columns are driven because the light emitting elements are polarized the same in alternate rows and are oppositely polarized for each suceeding row, and the column generators reverse their driving current polarity for each suceeding row. Interlaced scanning is provided in one embodiment of the invention. Light emitting diodes are used as the display elements. Other light sources with series rectifiers are optionally used.

Description

BACKGROUND OF THE INVENTION

The planar display device of the present invention performs the basic functions of a cathode ray tube, e.g., analog display with half tones, storage and raster type scan without the requirement of high voltages and weighs only a fraction of the weight of a comparable cathode ray tube display unit. The planar display device of the present invention employs light emitting diodes which are fast, easily addressable, do not require high voltages and have long lifetimes. Electroluminescent displays, on the other hand, are slow, very difficult to address, require high voltages (A.C. electroluminescence) and have a comparatively short life.

Other contemporary light emitting diode displays are exclusively alpha-numeric. Those that do provide storage in the display do not employ raster type scan and are thereby inherently incompatible with many sensor devices, such as vidicons, that must employ a raster scan. Other displays that do provide raster scan, but which do not have storage, are quite dim due to the low duty cycle on which the light emitting diodes operate. In providing half tones, line storage and raster scan, the planar display device of the present invention overcomes the aforementioned deficiencies of contemporary display devices.

SUMMARY OF THE INVENTION

A planar television type display device comprising a rectangular array of light emitting diodes or light-diode combinations arranged in rows and columns each having a common conductor. In a first embodiment of the invention, alternate rows of the light emitting diodes or light-diode combinations are poled in an opposite sense between the respective intersections of the orthogonal column and row conductors. Each column conductor is driven by a "sample and hold" apparatus responsive to unipolar video that is reversed for alternate rows. A first shift register controls the taking of video samples along successive rows and a second shift register controls switches which progressively ground adjacent row conductors from top to bottom.

In operation, the first shift register is stepped with a clock pulse that is sufficiently fast to sample each horizontal line of video. The second shift register is stepped with horizontal synchronizing pulses and recycled with vertical synchronizing pulses. The changes in polarity of the video samples which occur for successive horizontal scans for alternate rows automatically switch the luminous element to the next succeeding row, leaving an entire row of luminous elements illuminated at all times during operation.

In an alternate embodiment of the invention, the array of light emitting diodes or light-diode combinations are programmed to accommodate the interlaced scan generally used in television video signals.

BRIEF DESCRIPTION OF THE DRAWINGS

FIG. 1 illustrates a schematic block diagram of the planar display device of the present invention;

FIG. 2 shows a schematic circuit diagram of a sample and old current generator in the apparatus of FIG. 1;

FIG. 2 a is a schematic circuit diagram illustrating the switching from a light emitting diode in row n to a light emitting diode in row (n+1) in the apparatus of FIG. 1;

FIG. 2b is a schematic circuit diagram illustrating the switching from row n to row (n+1) when light-diode combinations are used in the apparatus of FIG. 1; and

FIG. 3 illustrates a schematic block diagram of a planar display device in accordance with the invention programmed to be compatible with television scanning.

Referring now to FIG. 1 of the drawings, there is shown a schematic block diagram of a preferred embodiment of the present invention. In particular, the planar display is composed of light emitting diodes or light-diode combinations D.sub.ij where i is the row and j the column arranged as follows:

D.sub.11 d.sub.12 d.sub.13 . . . d.sub.in

D.sub.21 d.sub.22 d.sub.23 . . . d.sub.2n

D.sub.31 d.sub.32 d.sub.33 . . . d.sub.3n

. . .

. . .

. . .

D.sub.m1 D.sub.m2 D.sub.m3 . . . D.sub.mn

wherein m is the number of rows and n the number of columns. Normally m will correspond to the number of horizontal lines in the display and n will correspond to the number of elements of each line to be presented. In the typical case, n is made equal to the number of horizontal lines, m, times the aspect ratio of the display in order to have horizontal and vertical resolution the same.

In addition to the above, the planar display includes horizontal conductors 10-1, 10-2, . . . 10-m and vertical conductors 12-1, 12-2, . . . 12-n corresponding to each row and column of the light emitting diodes, D.sub.ij. Each light emitting diode D.sub.ij is connected between the horizontal conductor 10-i and the vertical conductor 12-j with the diodes D.sub.ij being poled in opposite directions from the diodes D.sub.(i.sub.+l)j. That is, light emitting diodes D.sub.ij in alternate rows are poled in opposite directions between the horizontal and vertical conductors 10, 12.

Electronically actuated switches S.sub.1, S.sub.2, S.sub.3 . . . S.sub.m are connected, respectively, from the row conductors 10-1, 10-2, 10-3, . . . 10-m to a common bus 14 which is connected to ground. A shift register 16 possesses m outputs, a clock input and a set input which when energized causes the shift register 16 to revert to its initial load setting. The clock input receives horizontal synchronizing pulses available at a terminal 17 and the set input of register 16 receives vertical synchronizing pulses available at a terminal 18. The shift register 16 is initially loaded with two adjacent 1's which revert, when the register 16 is set, to the first and last outputs. The outputs of register 16 are connected to actuate the electronically actuatable switches S.sub.1, S.sub.2, S.sub.3 . . . S.sub.m from top to bottom in sequence, as viewed in the drawing. Thus, switches S.sub.1 and S.sub.m are closed in response to a vertical synchronizing pulse, then S.sub.1 and S.sub.2 in response to the first horizontal synchronizing pulse, and S.sub.i and S.sub.i.sub.+1 in response to the i .sup.th horizontal synchronizing pulse following the set pulse. That is, two successive switches S.sub.i and S.sub.i.sub.+1 are always closed as shown in FIGS. 2a and 2b except in the initial case when switches S.sub.1 and S.sub.m are closed. It is thus desirable that there be an even number of horizontal lines so as to have a continuity of scan, as will hereinafter be explained.

The column conductors 12-1, 12-2, . . . 12-n are driven by sample and hold current generators 20 each of which receive polarized video through a polarity reversal network 22. The polarity reversal network 22 receives unipolar video to be displayed available at a terminal 24 and horizontal synchronizing pulses available at the terminal 17. Video sampling by the sample and hold current generators 20 is controlled by a shift register 26 which is initially loaded with a single "1". The shift register 26 has outputs connected to the sample inputs of the sample and hold current generators 20 corresponding to the column conductors 12-1 to 12-n, respectively. In addition, shift register 26 receives inputs from a clock generator 28 which controls the rate at which the "1" is stepped along the outputs thereof from left to right, as viewed in the drawing, and horizontal synchronizing pulses at a set input thereto which causes the "1" to revert to the far left output thereof, as viewed in the drawing. The clock generator 28 also receives horizontal synchronizing pulses at a set input thereto which causes the first clock pulse to be generated thereafter to have a fixed relationship to the horizontal synchronizing pulse received so that the samples in each horizontal line occur at the same time.

The light emitting diode, D.sub.ij is a solid state device having characteristics that are readily predictable on theoretical grounds and that differ little from the characteristics of other well-known semiconductor devices. In general, the light emitting diode operates on the principle of injection electroluminescence. Electrons injected into the p region radiatively recombine with holes, emitting light. The wavelength of the emitted light is determined by the energy gap in the material. Efficiency considerations dictate the selection of materials which exhibit direct rather than indirect transitions. Gallium arsenide (GaAs) is an efficient direct emitter, but of infrared energy (9,000A), while gallium phosphide is an inefficient indirect emitter of green visible light (5,600A). An appropriate alloy, Ga(As.sub.0.4 P.sub.0.6) remains sufficiently direct to exhibit reasonable efficiency, while emitting red light. Amber, green and blue are other possible colors. Contemporary light emitting diodes generally require of the order of 1.6 volts d.c. excitation, have a cell size of from 0.010 to 0.100 inch, switch in less than 10 nanoseconds and have a maximum light output of the order of 1,000 Foot-lamberts. It is contemplated that a mozaic approach would be desirable but not essential in fabricating the display apparatus of the present invention.

A segment of the light emitting diode matrix in the apparatus of FIG. 1 is shown in FIG. 2a wherein the light emitting diode is illustrated with an open diode mark. An alternative to light emitting diodes is illustrated in FIG. 2b wherein a light and diode are connected in series. The solid diode mark is employed to indicate a conventional diode element. A light connected in series with a diode may be useful in very large displays.

Referring to FIG. 2, there is shown a schematic circuit diagram of an illustrative embodiment of the sample and hold current generator 20. Bipolar video available from the polarity reversal network 22 is applied to a video input terminal 30 which is connected to a source terminal 31 of a low leakage insulated gate field-effect transistor 32. The drain 33 of transistor 31 is connected to a gate 38 of an N-type channel junction field-effect transistor 37; the substrate 34 of transistor 31 is biased to a point slightly above the peak positive excursions of the input video at terminal 30 by a connection to the junction between serially connected resistors 40, 41 from sources of potential +V to -V, respectively; and the gate terminal 35 is connected to an appropriate output of the shift register 26. Next, a resistor 43, diodes 44, 45 and resistor 46 are serially connected in the order named between sources of potential +V and -V with the diodes 44, 45 poled in a direction to allow current flow therethrough. The source terminal 48 of field-effect transistor 37 is connected to the source of potential +V, and the drain terminal 49 to the junction between the diodes 44, 45. An n-p-n transistor 50 and p-n-p transistor 52 are connected between the sources of potential +V and -V with the base of transistor 50 connected to the junction between resistor 46 and diode 45 and the base of transistor 52 connected to the junction between resistor 43 and diode 44. Lastly, the junction between the emitters of transistors 50, 52 is connected to an output 54 and, in addition, is connected through a feedback capacitor 53 to the drain terminal 33 of field-effect transistor 32. Field-effect transistors 32, 37 may be of types designated commercially as FN1034 and 2N3823, respectively.

In operation of the sample and hold current generator 20, bipolar video at input terminal 30 is applied to source terminal 31 of field-effect transistor 32. Since transistor 32 is normally "biased off," no current flows until a negative pulse available from shift register 26 represented by waveform 55 is applied to the gate terminal 35. At this time, transistor 32 provides a high conductance path between the source and drain terminals 31, 33 thereof thereby allowing capacitor 53 to charge to the instantaneous video level during the duration of the pulse 55. This potential will remain on the capacitor 53 until the next pulse 55 from the shift register 26 which will normally be at the same point during the next horizontal scan. The voltage at the drain terminal 33, determined by the charge on capacitor 53, is applied to the gate of N-type channel junction field-effect transistor 37, which is configured as a source follower. Thus, the potential on the drain terminal 49 will be the same as that applied to the gate 38 and is applied through the diodes 44, 45 to the respective bases of transistors 50, 52 thereby to provide a bipolar output. It will be appreciated that sample and hold current generators are considered within the state of the electronics art.

In the operation of the apparatus of the present invention, unipolar video is applied through terminal 24 to polarity reversal network 22 which alternates the polarity of the output thereof in synchronism with the horizontal synchronizing pulses available at terminal 17. The bipolar video thus generated is applied to the video input 30 of each of the sample and hold current generators 20. Shift register 26 and clock generator 28 are both "set" by the horizontal synchronizing pulses. In the case of shift register 26, the "1" is shifted to the left output, as viewed in the drawing, while the clock generator 28 is set to a predetermined reference. The "1" in shift register 26 which corresponds to the pulse 55, FIG. 2 is stepped along the outputs of shift register 26 at a rate determined by the clock pulses generated by clock generator 28. This will normally be fast enough to take the appropriate number of samples compatible with the resolution desired such as the aspect ratio of the display times the number of horizontal lines. These samples are taken during each of the intervals between the horizontal synchronizing pulses.

Concurrently with the above, vertical synchronizing pulses available at terminal 18 "set" the shift register 16 to place the two successive "1's" to the first and last outputs (top and bottom outputs as viewed in the drawing). Subsequent occurrence of the horizontal synchronizing pulses applied to the clock input step the "1's" along the outputs of the shift register 16 from top to bottom, as viewed in the drawing. Occurrence of a one at an output of the shift register 16 closes the corresponding switch S.sub.i. The two successive 1's thus close switches S.sub.i and S.sub.i.sub.+1 as illustrated in FIGS. 2a and 2b. Inasmuch as light emitting diodes D.sub.i1, D.sub.i2 . . . D.sub.in are poled in a direction opposite from light emitting diodes D.sub.(i.sub.+1)1, D.sub.(i.sub.+1)2, . . . D.sub.(i.sub.+1)n, current from the sample and hold current generators 20 will flow through only one diode in any one column at any one time. When an entire row has been completed, the sample and hold current generators 20 will be developing current of the same polarity whereby all the light emitting diodes D.sub.i1, D.sub.i2, . . . D.sub.in in an entire row i will be lit. A horizontal synchronizing pulse will then cause the polarity of the output of polarity reversal network 22 to change and will step the shift register 16 to close switches S.sub.i and S.sub.i.sub.+1. The clock generator 28 will continue to "step" the shift register 26 to now cause samples of opposite polarity to be taken by the sample and hold current generators 20 whereby current flow will switch and flow through diodes D.sub.(i.sub.+1)j. From the foregoing, it is apparent that each row of diodes D.sub.ij remains lit for an entire horizontal scan irrespective of the position of the diode. In order to have proper switching from bottom to top, as viewed in the drawing, it is evident that the number of rows should but not essentially be even. Also, the light diode combinations of FIG. 2b will operate in the same manner, with respect to switching, as the light emitting diodes D.sub.ij.

Referring to FIG. 3 there is shown a planar display device in accordance with the invention programmed to present an interlaced scan so as to be compatible with television video. In the apparatus of FIG. 3, like reference numerals designate like elements. One significant difference is the light emitting diodes D.sub.ij are poled the same for two rows and then poled oppositely for two rows. Consequently, the rows are numbered 10-1(a), 10-1(b), 10-2(a), 10-2(b), . . . 10-m(a), and 10-m(b). Switches .sub.1(a), S.sub.1(b), S.sub.2(a), S.sub.2(b), . . . S.sub.m(a), S.sub.m(b), are connected in a manner to ground the row conductors 10-1(a), 10-1(b), 10-2(a), 10-2(b), . . . 10-m(a), 10-m(b), respectively, as before. Switches S.sub.1(a), S.sub.1(b), S.sub.2(a), S.sub.2(b), . . . S.sub.m(a), S.sub.m(b), in the apparatus of FIG. 3, however, respond to an information level signal on the respective outputs of two-input "and" gates G.sub.1, G.sub.2, . . . G.sub.m. A flip-flop 60 which responds to vertical synchronizing pulses has a first output 61 connected to respective inputs of "and" gates G.sub.1, G.sub.3, G.sub.5, . . . G.sub.m.sub.-1 and a second output 62 connected to respective inputs of "and" gates G.sub.2, G.sub.4, G.sub.6, . . . G.sub.m. Lastly, a shift register 64 of one-half the capacity of shift register 16 in the apparatus of FIG. 1 has outputs, commencing from top to bottom, as viewed in the drawing, connected to the remaining inputs of each successive pair of "and" gates G.sub.1, G.sub.2, G.sub.3, G.sub.4, . . . G.sub.m.sub.-1, G.sub.m, respectively. It is necessary that each pair of "and" gates so connected correspond to rows of the planar display wherein the diodes D.sub.ij are poled in the same direction. A manual change at an input 65 is provided to change the output state of flip-flop 60 in the event that it is desired to reverse the interlacing of the planar display so as to correspond to the video presented.

The operation of the apparatus of FIG. 3 is generally the same as that of FIG. 1 with the exception that shift register 64 together with flip-flop 60 and "and" gates G.sub.1, G.sub.2, . . . G.sub.m program the display to lite the light emitting diodes D.sub.ij in one set of alternate rows before lighting the light emitting diodes in the intervening rows. In the event the display does not correspond to the video to be presented, the sets of interlaced rows of light emitting diodes, D.sub.ij, can be reversed by means of the manual change input to flip-flop 60. In particular, a vertical synchronizing pulse applied to flip-flop 60 causes the shift register 64 to close only switches S.sub.i(a) and S.sub.(i+1) (a) whereby only diodes D.sub.ij in the rows 10-i(a) and 10-(i+1) (a) are lit, i.e., only diodes in the a rows are lit. Subsequently, upon the occurrence of an immediately succeeding vertical synchronizing pulse, flip-flop 60 changes state whereby shift register 64 closes only switches S.sub.i(b) and S.sub.(i.sub.+1(b) whereby only diodes D.sub.ij in the rows 10-i(b) and 10-(i+1) b) are lit. As before, each diode D.sub.ij stays lit for an entire horizontal scan. The switching, however, occurs between alternate rows thereby to achieve interlacings.

Claims

What is claimed is:

1. An analog planar device for displaying a unipolar electrical signal, said device comprising elemental unidirectional conducting light cell units mounted in rows and columns;

an orthogonal set of conductors connected across each of said unidirectionally conducting light cell units at the respective junctions thereof, the light cell units in any row being poled in a common direction and the next succeeding row to be scanned being poled in an opposite direction;

means responsive to said unipolar electrical signal for reversing the polarity thereof commencing with each horizontal scan thereby to provide a bipolar electrical signal;

means for taking successive samples of said bipolar electrical signal during each horizontal scan; and

means for generating currents in proportion to said successive samples and for directing said currents to corresponding light cell units in the row being scanned and the prior row scanned whereby a composite row of light cell units remain energized during presentation of the display.

2. The analog planar device for displaying a unipolar electrical signal as defined in claim 1 wherein said elemental unidirectionally conducting light cell units are light-emitting diodes.

3. The analog planar device for displaying a unipolar electrical signal as defined in claim 1 wherein said elemental unidirectionally conducting light cell units are serially connected light and diode combinations.

4. An analog planar device for displaying a unipolar electrical signal having associated horizontal and vertical synchronizing pulses, said device comprising elemental unidirectionally conducting light cell units mounted in rows and columns;

an orthogonal set of conductors connected across each of said unidirectionally conducting light cell units at the respective junctions thereof, the light cell units in any row being poled in a common direction and the light cells in alternate rows being poled in opposite directions;

means responsive to said horizontal and vertical synchronizing pulses for successively connecting two adjacent row conductors to a terminal maintained at a reference potential level concurrent with each horizontal scan period commencing from the extremities of the display upon the occurrence of each successive vertical synchronizing pulse and moving one row conductor in a non-changing direction upon the occurrence of each successive horizontal synchronizing pulse;

means responsive to said unipolar electrical signal and said horizontal synchronizing pulses for making the polarity thereof commencing with each horizontal synchronizing pulse conform to current flow through said light cells connected to said last row conductor connected to said terminal maintained at said reference potential level thereby to provide a bipolar electrical signal;

means for taking periodic successive samples of said bipolar electrical signal; and

means for generating direct currents in proportion to the amplitude of said successive samples and for directing said currents from the time of said respective samples to corresponding light cell units connected to said last row conductor connected to said terminal maintained at said reference potential level.

5. An analog planar device for displaying a unipolar electrical signal having associated horizontal and vertical synchronizing pulses, said device comprising elemental unidirectionally conducting light cell units mounted in rows and columns;

an orthogonal set of conductors connected across each of said unidirectionally conducting light cell units at the respective junctions thereof, the light cell units in any row being poled in a common direction and the light cells in alternate rows being poled in opposite directions;

means responsive to said horizontal and vertical synchronizing pulses for successively connecting two row conductors spaced one row apart to a terminal maintained at a reference potential level concurrent with each horizontal scan period commencing from alternate adjacent row conductors at the extremities of the display upon the occurrence of each successive vertical synchronizing pulse and moving two row conductors in a non-changing direction upon the occurrence of each successive horizontal synchronizing pulse;

means responsive to said unipolar electrical signal and said horizontal synchronizing pulses for making the polarity thereof commencing with each horizontal synchronizing pulse conform to current flow through said light cells connected to said last row conductor connected to said terminal maintained at said reference potential level thereby to provide a bipolar electrical signal;

means for taking periodic successive samples of said bipolar electrical signal; and

means for generating direct currents in proportion to the amplitude of said successive samples and for directing said currents from the time of said respective samples to corresponding light cell units connected to said last row conductor connected to said terminal maintained at said reference potential level.