Solid-state Display Circuit With Inherent Memory

Abstract

The need for external memory and image regeneration circuitry in light-emitting semiconductor diode display circuits is eliminated by providing each light-emitting diode with a respective capacitive storage element and bilateral breakdown switch. The bilateral switch and storage element function as inherent memory for the light-emitting diode, operating in conjunction with an AC bias voltage to maintain the diode lighted upon application of a write pulse.

Description

BACKGROUND OF THE INVENTION

This invention relates to display systems and, more particularly, to display systems upon which images are generated by the selective energization of independent display cells or elements.

Display systems are typically used for generating patterns of information, or images, in a two-dimensional raster for information display media, computer input/output terminals, telemetered data, instrumentation, high-speed printing, and the like. The principal types of display systems currently available include matrix arrangements of light bulbs and various forms of cathode-ray tube presentations, both of which suffer from well-known disadvantages related to size, cost, ruggedness and power requirements. The need for a display system which would overcome these disadvantages has been apparent for some time and considerable effort has been expended toward achieving such a display system. The solution was thought initially to lie in phosphor-type electroluminescent panels which, however, present problems related to rather high voltage requirements and to the need for an audiofrequency poser supply for operation.

Currently one of the areas of greatest promise appears to be solid-state semiconductor displays. Known solid-state semiconductor displays eliminate the need for high operating voltages and are compatible with semiconductor switching circuitry, but they suffer from certain limitations in that they require external memory storage and associated circuitry to regenerate the display image. This substantially increases the cost and complexity of such solid-state display systems.

SUMMARY OF THE INVENTION

It is accordingly a general object of this invention to provide a new and improved arrangement for displaying patterns of information without the disadvantages of known display arrangements.

More particularly, it is an object of this invention to provide a solid-state semiconductor display circuit with inherent memory, thereby eliminating the requirement in known solid-state display circuits for external memory and image regeneration circuitry.

According to a feature of my invention the above and other objects are attained in a simple and economical manner in an illustrative embodiment of a display circuit comprising a coordinate array of display cells, each cell including the serially connected combination of a light-emitting electroluminescent diode, a charge storage element, and a bilateral switch. The bilateral switch and charge storage element provide the inherent memory for the display cell, operating in conjunction with an alternating current bias voltage, to maintain the cell diode "lighted " upon application of a write pulse.

In operation the alternating current bias voltage is continually applied across each display cell of the array. A particular cell is turned ON, i.e., is lighted, by a write pulse applied to the particular cell row and column conductors, the write pulse being sufficient to switch the cell bilateral switch to a conducting state. The resulting current flow charges the cell storage element and energizes the electroluminescent diode for light emission. During succeeding half-cycles of the bias voltage, the stored charge, in combination with the bias voltage, causes periodic operation of the bilateral switch to permit sufficient current flow to maintain the electroluminescent diode lighted. The display cell is turned OFF by an erase pulse applied to the cell row and column conductors to operate the bilateral switch to a conducting state at a time when the bias voltage is near zero, thereby removing the charge from the storage element and preventing the recharging thereof.

It is desirable in many display circuit applications that an operator or user be able to draw images directly on the display by manual manipulation of a pen-shaped instrument. According to a further aspect of my invention this feature is provided advantageously by the use of a low voltage pen, manual placement of the pen adjacent a display cell causing operation of the cell bilateral switch. Thus, as an operator manipulates the pen, each cell of the array that the pen passes adjacent is lighted to create the desired image.

A display circuit, in accordance with my invention, is compact, rugged, and reliable and is inexpensive to manufacture, being susceptible to integrated circuit manufacturing techniques. Further, it has low operating power requirements, simple addressing circuit requirements, and may be operated directly by high-speed digital signals of the amplitude generated by integrated circuits, thereby eliminating the need for interface or buffer circuitry.

BRIEF DESCRIPTION OF THE DRAWING

The above and other objects and features of the invention may be fully apprehended from the following detailed description and the accompanying drawing, in which:

FIG. 1 is a diagram of an illustrative embodiment of a solid-state display circuit with inherent memory in accordance with the principles of my invention;

FIG. 2 A -2C are time charts useful in describing the operation of the illustrative embodiment of FIG. 1;

FIG. 3 depicts an alternative illustrative embodiment of a display circuit with inherent memory in accordance with the principles of my invention; and

FIG. 4 depicts a typical voltage-current characteristic for an illustrative bilateral switch employed in the embodiments of FIGS. 1 and 3.

DETAILED DESCRIPTION

In FIG. 1 of the drawing an illustrative embodiment of the invention comprising an n times m display matrix 50 is shown for generating images by the selective energization of individual ones of display cells 100. For example, matrix 50 may comprise a conventional 5 .times.7 array for generating characters of the ASCII alphanumeric code. However, it will be apparent from the description herein that display cells 100 may be employed individually or in combination in any form of array desired for particular display system applications.

Each display cell 100 includes the serially connected combination of a light-emitting electroluminescent diode 116, a charge storage element 113, and a bilateral breakdown switch 112 extending between a particular row and column conductor of matrix 50. A diode 114 is connected in parallel with electroluminescent diode 116 and is poled opposite thereto. Electroluminescent diodes 116 may, for example, be red light-emitting gallium-aresnide-phosphide diodes, green light-emitting gallium-phosphide diodes, or any other of the known types of light-emitting diodes. Charge storage element 113 may comprise a capacitor as shown illustratively in FIG. 1, and bilateral switch 112 may comprise, for example, a silicon PNPN breakdown diode, an Ovonic threshold switch, or the like, having the typical voltage-current characteristic shown in FIG. 4.

Specifically referring to FIG. 4, when the magnitude of the voltage across switch 112 equals or exceeds the forward breakdown voltage V.sub.BF or the reverse breakdown voltage V.sub.BR, which are typically of substantially like magnitude, switch 112 breaks down to a low impedance conducting state. Switch 112 remains in the low impedance conducting state until the voltage across the switch falls below the sustaining voltage level V.sub.SF or V.sub.SR, at which point switch 112 returns to its quiescent high impedance non conducting state. For an illustrative silicon PNPN switch, by way of example, the breakdown voltage may be on the order of .+-.8 volts and the sustaining voltage level on the order of .+-.0.5 volts.

Alternating current bias voltage provided by source 20, which may be either sinusoidal or pulsed, is extended by control circuit 80 across each display cell 100 via row conductors R1 through Rm and column conductors C1 through Cn. The bias voltage extended by source 20 across each cell 100 is of a magnitude less than the breakdown voltage level for switch 112 but advantageously is greater than the sustaining voltage level therefor. Assuming use of the illustrative PNPN switches mentioned above, for example, the bias voltage provided by source 20 may be on the order of 5 or 6 volts 0 to peak with a frequency on the order of 10 kHz., for example.

Addressing of a selected display cell 100 is effected by application of coincident signals to the particular row and column conductors connected to the display cell under control of control circuit 80. The voltage thus extended across the selected display cell by the coincident row and column signals, in conjunction with the bias voltage applied to the row and column conductors, is sufficient to effect breakdown of switch 112 at the selected cell. At the same time, however, the voltage extended across the other display cells connected to the addressed row conductor and to the addressed column conductor is insufficient to effect breakdown of the bilateral switches at these other cells.

The addressing signals, as well as the bias voltage in the embodiment of FIG. 1, are applied to the row and column conductors of matrix 50 through respective row drivers 40 and column drivers 30, illustratively shown in FIG. 1 as pulse transformers. Thus source 20 is connected to each column conductor C1 through Cn via the secondary winding 302 of a respective column driver 30 and to each row conductor R1 through Rm via the secondary winding 402 of a respective row driver 40. Column conductors C1 through Cn are addressed selectively by signals from write-erase circuitry 81 on leads X1 through Xn, respectively connected to the primary windings 301 of respective column drivers 30. Similarly, row conductors R1 through Rm are addressed selectively by signals from write-erase circuitry 82 on leads Y1 through Ym, respectively connected to primary windings 401 of respective row drivers 40.

With the above description in mind and with reference to FIGS. 2A, 2B and 2C, consider now the operation of the illustrative embodiment of FIG. 1. Assume initially that display cell 100 located at the intersection of row conductor R1 and column conductor C1 is OFF, i.e., that no charge appears on charge storage element 113, that switch 112 is in a high impedance nonconducting state, and that electroluminescent diode 116 is thus not lighted. The bias voltage from source 20, extended through the respective row and column drivers to row conductor R1 and column conductor C1, appears across the display cell, as shown in FIG. 2A. Since the bias voltage is less than the breakdown voltage of switch 112, no significant current flow through the display cell occurs.

Assume now that it is desired to turn ON the display cell 100 located at the intersection of row conductor R1 and column conductor C1. This is accomplished by addressing row conductor R1 and column conductor C1 with coincident signals in the form of a write pulse which, in conjunction with the bias voltage applied across the display cell, is sufficient to effect breakdown of switch 112 at the addressed cell. In the manner mentioned above, in the illustrative embodiment of FIG. 1 the write pulse is extended over row conductor R1 and column conductor C1 to the selected display cell via coincident signals applied on leads Y1 and X1 from write-erase circuitry 82 and 81, which signals are reflected through the corresponding row and column drivers. Advantageously, to minimize the magnitude of the write pulse required, the write pulse is applied to the selected display cell under control of control circuit 80 near a peak of the bias voltage, as shown at time t.sub.w, by way of example, in FIG. 2A.

The write pulse is shown in FIG. 2A as applied to the right side of the peak of the bias voltage to minimize loading of the write pulse circuitry, which is particularly important in the case of integrated write pulse circuitry. Although the write pulse can be applied at the peak or to the left of the peak of the bias voltage, as will be apparent from the description below other cells of matrix 50 which are ON will be operating during this interval to break down the respective switches thereat. Any such ON cells connected to row conductor R1 or column conductor C1, therefore, will tend to provide low impedance shunt paths for the write pulse during the interval to the left of the bias voltage peak. However, during the interval to the right of the bias voltage peak the other cells of matrix 50 will present a high impedance state to the write pulse, and thus will minimize loading of the write pulse circuitry.

The write pulse applied to row conductor R1 and column conductor C1 causes momentary breakdown of switch 112 at the selected display cell, permitting current flow therethrough to charge storage element 113 and to energize electroluminescent diode 116. The resulting current flow through the display cell during breakdown of switch 112 is in the form of a current pulse, shown as pulse 201 in FIG. 2C, which may illustratively be on the order of 80 ma. magnitude with a duration on the order of several hundred nanoseconds.

The current flow through the display cell charges storage element 113, as depicted in FIG. 2B, to a level V.sub.c determined principally by the net voltage across switch 112 during breakdown. During the following negative half-cycle of bias voltage applied across the display cell the charge on storage element 113 adds to the bias voltage, as shown in FIG. 2A. At time t.sub.1 the combined voltage exceeds the breakdown voltage V.sub.BR of switch 112, momentarily switching switch 112 to a low impedance conducting state. The resulting negative current pulse 202 through diode 114 discharges storage element 113 and charges element 113 in a reverse direction, as indicated in FIG. 2B.

During the following positive half-cycle of bias voltage, therefore, the reverse charge on storage element 113 adds to the bias voltage, as shown in FIG. 2A, reaching a level sufficient to break down switch 112 again at time t.sub.2. The positive current pulse 203 resulting therefrom through electroluminescent diode 116 reverses the charge on element 113 and lights diode 116. During succeeding half-cycles of the bias voltage the charge stored on element 113, in combination with the bias voltage, causes periodic breakdown of switch 112 to permit sufficient current flow to maintain electroluminescent diode 116 lighted.

It will be noted, of course, that current flow through electroluminescent diode 116 occurs only during the positive current pulses, such as current pulses 201 and 203 in FIG. 2C. Thus, diode 116 is advantageously energized for light emission only briefly during each cycle of bias voltage from source 20; however, diode 116 appears to an observer to emit light continuously at a steady level during the period the display cell is ON. Moreover, it will be apparent that diode 114 may also be a light-emitting electroluminescent diode if desired for a particular application, diode 114 then being energized by the negative current pulses such as current pulses 202 and 204 in FIG. 2C.

An important advantage arises through the above-described current pulsed energization of electroluminescent diodes 116 in accordance with my invention. In particular, the operating power requirements are substantially lower, up to several orders of magnitude lower, than for known solid state display arrangements. Further, driving diodes 116 with high current pulses permits the diodes to be operated at or near maximum efficiency, unlike known semiconductor display arrangements, thereby increasing the apparent brightness of the display image while reducing the power required.

Additional ones of display cells 100 in matrix 50 are turned ON in a similar manner by application of a write pulse to the particular row and column conductors to which the additional cells are connected. Conversely, a selected display cell is turned OFF by applying an erase pulse to the row and column conductors to which the selected cell is connected such that the erase pulse removes or erases the charge stored at the selected cell. This is effected advantageously by applying an erase pulse to the particular row and column conductors of sufficient magnitude to break down switch 112 at a point when the instantaneous magnitude of the bias voltage applied to the row and column conductors is at or near zero. During the resulting momentary breakdown of switch 112, therefore, no significant charge is stored on element 113. Accordingly, when switch 112 returns to its high impedance state the net voltage across the display cell is approximately equal to the bias voltage and is thus insufficient to cause subsequent breakdown of switch 112.

For example, assume that display cell 100 connected to row conductor R1 and column conductor C1 is ON and that it is desired to turn if OFF. Row conductor R1 and column conductor C1 are addressed via coincident signals applied on leads Y1 and X1 in the form of an erase pulse at a time when the instantaneous value of the bias voltage is near zero, as shown at time t.sub.e, by way of example, in FIG. 2A.

The erase pulse is assumed to be sufficient in magnitude to cause momentary breakdown of switch 112 at the selected display cell. The resulting current flow, depicted in FIG. 2C by current pulse 210, discharges charge storage element 113, as shown in FIG. 2B, and energizes electroluminescent diode 116. As mentioned above, since the instantaneous value of bias voltage across the cell at time t.sub.e is approximately zero, no significant charge builds up on storage element 113 during the momentary breakdown of switch 112. As switch 112 returns to its high impedance nonconducting state, therefore, diode 116 is deenergized and remains so until another write pulse is applied to the particular display cell.

Although in the description above it is tacitly assumed that only a single display cell is addressed by a write or erase pulse during each cycle of the bias voltage, it will be apparent that more than one cell can be addressed during each bias voltage cycle by consecutively or concurrently addressing a number of cells in each cycle. Further, although a capacitor is illustratively depicted as charge storage element 113 in the embodiment of FIG. 1, as the frequency of the bias voltage is increased, the capacity required for storage decreases such that other types of charge storage elements may be employed advantageously.

An alternative display cell embodiment is shown in FIG. 3 comprising the serially connected combination of bilateral switch 312, electroluminescent diode 316, and charge storage diode 315 poled opposite to electroluminescent diode 316. The operation of the display cell embodiment of FIG. 3 is substantially the same as that described above for the embodiment of FIG. 1, except that charge storage is provided by back-to-back diodes 315 and 316 rather than by a capacitor. The display cell is turned ON by the application of a write pulse across the cell, advantageously near a peak of the bias voltage, and the cell is turned OFF by application of an erase pulse when the bias voltage is at or near zero.

During the flow of current in the forward direction through electroluminescent diode 316, diode 316 is energized and diode 315 is charged. During the flow of current in the opposite direction through diode 315, diode 315 is discharged and diode 316 is charged in the reverse direction. Thus, when the display cell is ON the charge stored on diode 315 adds to the bias voltage to breakdown switch 312 during one polarity half-cycle of the bias voltage, and the charge stored on diode 316 adds to the bias voltage to breakdown switch 312 during the opposite polarity half-cycle.

Of course it will be appreciated that if desired in the embodiment of FIG. 3 charge storage diode 315 also may be an electroluminescent diode poled opposite to diode 316, diode 315 thereby providing a charge storage function for one polarity current and a light emission function for the other polarity current, while diode 316 emits light for the one polarity current and provides a charge storage function for the other polarity current. The use of a pair of back-to-back electroluminescent diodes for diodes 315 and 316 in FIG. 3 further advantageously facilitates fabrication of the display cell since the two diodes in each cell can then be manufactured as a single unit, without the need for subsequent electrical interconnection or for affixing electrical leads to the diode light emission surfaces.

As mentioned above, it is desirable in many display circuit applications that an operator or user be able to draw images directly on the display, such as by manual manipulation of a low voltage pen. According to an aspect of my invention manual placement of a low voltage pen adjacent a display cell, the pen providing a voltage sufficient in conjunction with the bias voltage to effect breakdown of the cell bilateral switch, energizes the electroluminescent diode at the cell. Thus, as an operator manipulates the pen adjacent the display matrix to draw a desired image, each cell of the matrix that the pen passes adjacent is lighted. The image can be erased subsequently by applying erase pulses to each display cell, such as in the manner described above.

The write pulses and the erase pulses may be applied consecutively to the display cells one cell at a time, as described above; or they may be applied to a plurality of cells concurrently, such as to a row or a column of cells, as may be desired for high-speed display applications. When a narrow write or erase pulse, illustratively on the order of 100 nanoseconds in duration, is applied across a display cell in accordance with my invention, very little current is drawn from the pulsing circuitry due to the slight delay inherent in the bilateral switch switching from a high impedance state to a low impedance state. Thus, the narrow write or erase pulse sees a high impedance and the cell storage element is charged by the bias voltage, after termination of the pulse, while the bilateral switch is momentarily in a low impedance state. Accordingly, a plurality of display cells advantageously can be addressed concurrently with substantially little loading of the write or erase pulse circuitry.

What has been disclosed herein, therefore, is a simple, rugged and reliable, high-speed solid-state display circuit having inherent memory, which display circuit is operable at low power levels and is addressable with digital signals derived from integrated circuits.

It is to be understood that the above-described arrangements are but illustrative of the application of the principles of my invention. Numerous other arrangements may be devised by those skilled in the art without departing from the spirit and scope of the invention.

Claims

What is claimed is:

1. A two-terminal display cell comprising the serially connected combination of a bilateral breakdown switch, a light-emitting semiconductor device and charge storage means.

2. A display cell in accordance with claim 1 wherein said semiconductor device comprises a light-emitting diode and said charge storage means comprises a capacitor, said display cell further comprising a second diode connected in parallel with said light-emitting diode and poled opposite thereto.

3. A display cell in accordance with claim 1 wherein said semiconductor device comprises a light-emitting diode and said charge storage means comprises a second diode poled opposite to said light-emitting diode.

4. A display cell in accordance with claim 3 wherein said second diode is a light-emitting diode.

5. A display circuit comprising an array of display cells individually including the serially connected combination of light-emitting semiconductor device means and bilateral switch means, said light-emitting means including a pair of serially connected light-emitting diodes poled opposite to one another.

6. A display circuit comprising an array of display cells individually including the serially connected combination of light-emitting semiconductor device means, bilateral switch means and charge storage means connected in circuit with said switch means.

7. A display circuit in accordance with claim 6 wherein said charge storage means comprises a capacitor.

8. A display circuit in accordance with claim 7 wherein said switch means are normally nonconducting and are operable to a conducting state, said display circuit further comprising means for selectively addressing said display cells to initially operate said switch means at said addressed cells, said initial operation of said switch means placing a charge on said respective charge storage means connected to said switch means at said addressed cells, and alternating bias signal means connected to each of said cells, said bias signal means operative in conjunction with said charge on said respective charge storage means for periodically operating said switch means connected to said charge storage means.

9. A display circuit comprising an array of display cells individually including the serially connected combination of light-emitting semiconductor device means and bilateral switch means, said switch means being normally nonconducting and being operable to a conducting state; means for selectively addressing individual ones of said display cells to initially operate said switch means thereat; and bias means connected to each of said display cells and operative upon the initial operation of individual ones of said switch means for thereafter periodically operating said individual switch means.

10. A display circuit in accordance with claim 9 wherein said bias means comprises an alternating signal source connected to each of said display cells and of a magnitude insufficient to initially operate said switch means at said cells.

11. A display circuit in accordance with claim 9 wherein said display cells are arranged in a coordinate array and said addressing means comprises respective pulse transformers having secondary windings connected to the individual rows and columns of said coordinate array, each said transformer having a primary winding connected to a respective address signal input lead and wherein said bias means comprises an alternating signal source connected to the secondary windings of each of said pulse transformers.