U.S. patent number 10,141,278 [Application Number 15/804,478] was granted by the patent office on 2018-11-27 for chip mounting structure.
This patent grant is currently assigned to International Business Machines Corporation. The grantee listed for this patent is International Business Machines Corporation. Invention is credited to Akihiro Horibe, Keiji Matsumoto, Keishi Okamoto, Kazushige Toriyama.
United States Patent |
10,141,278 |
Horibe , et al. |
November 27, 2018 |
Chip mounting structure
Abstract
Highly reliable chip mounting is accomplished by using a
substrate having such a shape that a stress exerted on a
flip-chip-connected chip can be reduced, so that the stress exerted
on the chip is reduced and separation of an interlayer insulating
layer having a low dielectric constant (low-k) is minimized.
Specifically, in a chip mounting structure, a chip including an
interlayer insulating layer having a low dielectric constant
(low-k) is flip-chip connected to a substrate via bumps is shown.
In the chip mounting structure, the substrate has such a shape that
a mechanical stress exerted on the interlayer insulating layer at
corner portions of the chip due to a thermal stress is reduced, the
thermal stress occurring due to a difference in coefficient of
thermal expansion between the chip and the substrate.
Inventors: |
Horibe; Akihiro (Yokohama,
JP), Matsumoto; Keiji (Kawasaki, JP),
Okamoto; Keishi (Kawasaki, JP), Toriyama;
Kazushige (Kawasaki, JP) |
Applicant: |
Name |
City |
State |
Country |
Type |
International Business Machines Corporation |
Armonk |
NY |
US |
|
|
Assignee: |
International Business Machines
Corporation (Armonk, NY)
|
Family
ID: |
53265961 |
Appl.
No.: |
15/804,478 |
Filed: |
November 6, 2017 |
Prior Publication Data
|
|
|
|
Document
Identifier |
Publication Date |
|
US 20180076162 A1 |
Mar 15, 2018 |
|
Related U.S. Patent Documents
|
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
Issue Date |
|
|
15255588 |
Sep 2, 2016 |
9893031 |
|
|
|
14930984 |
Nov 3, 2015 |
9508594 |
|
|
|
14548583 |
Nov 20, 2014 |
9299606 |
|
|
|
Foreign Application Priority Data
|
|
|
|
|
Nov 29, 2013 [JP] |
|
|
2013247505 |
Dec 13, 2013 [JP] |
|
|
2013257637 |
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
24/17 (20130101); B23K 3/0623 (20130101); H01L
23/34 (20130101); H01L 24/83 (20130101); H01L
23/5226 (20130101); H01L 24/27 (20130101); H01L
24/14 (20130101); H01L 24/08 (20130101); H01L
24/92 (20130101); H01L 25/50 (20130101); H01L
24/11 (20130101); H01L 24/73 (20130101); H01L
24/13 (20130101); H01L 24/742 (20130101); H01L
25/0657 (20130101); H01L 23/345 (20130101); H01L
23/49894 (20130101); H01L 21/4867 (20130101); H01L
23/49816 (20130101); H01L 24/32 (20130101); H01L
24/81 (20130101); H01L 21/76877 (20130101); H01L
21/76802 (20130101); H01L 24/29 (20130101); H01L
2224/27416 (20130101); H01L 2224/29012 (20130101); H01L
2224/29076 (20130101); H01L 2224/73104 (20130101); H01L
2224/81 (20130101); H01L 2224/94 (20130101); H01L
2224/29011 (20130101); H01L 2224/29111 (20130101); H01L
2224/81191 (20130101); H01L 2224/29109 (20130101); H01L
2224/11618 (20130101); H01L 2924/3512 (20130101); H01L
2224/13014 (20130101); H01L 2224/81815 (20130101); H01L
2924/3841 (20130101); H01L 2924/014 (20130101); H01L
2224/11312 (20130101); H01L 2224/27515 (20130101); H01L
2924/12042 (20130101); H01L 2224/16145 (20130101); H01L
2224/83 (20130101); H01L 2225/06513 (20130101); H01L
2225/06568 (20130101); H01L 2224/13015 (20130101); H01L
2224/2919 (20130101); H01L 23/488 (20130101); H01L
2224/1148 (20130101); H01L 2224/16238 (20130101); H01L
2224/73204 (20130101); H01L 2224/0401 (20130101); H01L
2924/06 (20130101); H01L 2224/16111 (20130101); H01L
2224/17519 (20130101); H01L 2224/27 (20130101); H01L
2224/83204 (20130101); H01L 24/16 (20130101); H01L
2224/11013 (20130101); H01L 2224/27618 (20130101); H01L
2924/37001 (20130101); H01L 2224/11416 (20130101); H01L
2224/13013 (20130101); H01L 2224/13111 (20130101); H01L
2224/83203 (20130101); H01L 2924/00 (20130101); H01L
2224/05027 (20130101); H01L 23/481 (20130101); H01L
2224/81203 (20130101); H01L 2224/13109 (20130101); H01L
2224/9211 (20130101); H01L 2224/81801 (20130101); H01L
2224/1131 (20130101); H01L 2224/16227 (20130101); H01L
2224/81193 (20130101); H01L 2224/14051 (20130101); H01L
2224/81204 (20130101); H01L 2224/94 (20130101); H01L
2224/11 (20130101); H01L 2924/12042 (20130101); H01L
2924/00 (20130101); H01L 2224/27416 (20130101); H01L
2924/00014 (20130101); H01L 2224/2919 (20130101); H01L
2924/00014 (20130101); H01L 2224/13111 (20130101); H01L
2924/0103 (20130101); H01L 2224/13111 (20130101); H01L
2924/01083 (20130101); H01L 2224/13111 (20130101); H01L
2924/01049 (20130101); H01L 2224/13111 (20130101); H01L
2924/01051 (20130101); H01L 2224/13111 (20130101); H01L
2924/01028 (20130101); H01L 2224/13111 (20130101); H01L
2924/01027 (20130101); H01L 2224/13111 (20130101); H01L
2924/01032 (20130101); H01L 2224/13111 (20130101); H01L
2924/01026 (20130101); H01L 2224/13111 (20130101); H01L
2924/01047 (20130101); H01L 2224/13111 (20130101); H01L
2924/01029 (20130101); H01L 2224/13111 (20130101); H01L
2924/014 (20130101); H01L 2924/00013 (20130101); H01L
2224/13109 (20130101); H01L 2924/01047 (20130101); H01L
2224/13109 (20130101); H01L 2924/01029 (20130101); H01L
2224/13109 (20130101); H01L 2924/0103 (20130101); H01L
2224/13109 (20130101); H01L 2924/01083 (20130101); H01L
2224/13109 (20130101); H01L 2924/01049 (20130101); H01L
2224/13109 (20130101); H01L 2924/01051 (20130101); H01L
2224/13109 (20130101); H01L 2924/01028 (20130101); H01L
2224/13109 (20130101); H01L 2924/01027 (20130101); H01L
2224/13109 (20130101); H01L 2924/01032 (20130101); H01L
2224/13109 (20130101); H01L 2924/01026 (20130101); H01L
2224/13109 (20130101); H01L 2924/014 (20130101); H01L
2924/00013 (20130101); H01L 2224/94 (20130101); H01L
2224/27 (20130101); H01L 2224/9211 (20130101); H01L
2224/81 (20130101); H01L 2224/83 (20130101); H01L
2224/13014 (20130101); H01L 2924/00014 (20130101); H01L
2224/29109 (20130101); H01L 2924/014 (20130101); H01L
2224/29111 (20130101); H01L 2924/014 (20130101); H01L
2224/29012 (20130101); H01L 2924/00012 (20130101); H01L
2224/13111 (20130101); H01L 2924/01047 (20130101); H01L
2924/01029 (20130101) |
Current International
Class: |
H01L
21/00 (20060101); H05K 7/00 (20060101); H01L
23/00 (20060101); H01L 23/34 (20060101); H01L
21/768 (20060101); H01L 25/065 (20060101); H01L
25/00 (20060101); H01L 23/498 (20060101); H01L
21/48 (20060101); H01L 23/495 (20060101); B23K
3/06 (20060101); H01L 23/522 (20060101); H01L
23/488 (20060101); H01L 23/48 (20060101) |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
|
|
|
|
|
|
|
05047842 |
|
Feb 1993 |
|
JP |
|
05047955 |
|
Feb 1993 |
|
JP |
|
06045401 |
|
Feb 1994 |
|
JP |
|
08008354 |
|
Jan 1996 |
|
JP |
|
08064717 |
|
Mar 1996 |
|
JP |
|
2002100699 |
|
Apr 2002 |
|
JP |
|
20130257637 |
|
Dec 2013 |
|
JP |
|
Other References
US. Appl. No. 15/255,588, filed Sep. 2, 2016. cited by applicant
.
U.S. Appl. No. 14/930,987, filed Nov. 9, 2016, U.S. Pat. No.
9,508,594. cited by applicant .
U.S. Appl. No. 14/548,583, filed Mar. 9, 2016, U.S. Pat. No.
9,299,606. cited by applicant.
|
Primary Examiner: Chambliss; Alonzo
Attorney, Agent or Firm: Fleit Gibbons Gutman Bongini Bianco
PL Gibbons; Jon A.
Claims
What is claimed is:
1. A method for changing a shape of a substrate to reduce stress
exerted on an interlayer insulating layer of a chip, the method
comprising: providing the substrate; mounting the chip on the
substrate such that a center of the chip corresponds to a center of
the substrate and such that sides of the chip are parallel to sides
of the substrate; measuring a distance B between a side of the chip
and a nearest side of the substrate; and cutting off square
portions of the substrate from each corner of the substrate such
that a distance between a corner of the chip and a nearest corner
of the substrate is less than the distance B, wherein each square
portion has sides of a length c, and wherein >.times.
##EQU00006##
2. A method for mounting a chip on a substrate, the method
comprising: providing a chip having an interlayer insulating layer,
the interlayer insulating layer having a low dielectric constant;
mounting the chip to a substrate such that there is a distance B
between a side of the chip and a nearest side of the substrate;
connecting the chip to the substrate using flip-chip bumps; and
cutting off right-angle isosceles triangle portions of the
substrate from each corner of the substrate such that a distance
between each corner of the chip and a nearest corner of the
substrate is less than the distance B, wherein each right-angle
isosceles triangle portion has two sides of a length d, and wherein
d>(2- {square root over (2)})B.
3. The method of claim 2, wherein the substrate is square.
4. The method of claim 3, wherein the chip is square.
5. The method of claim 2, wherein the chip is square.
6. The method of claim 5, wherein the substrate is square.
7. A method for forming a chip mounting structure, the method
comprising: providing a square substrate; connecting a square chip
to the square substrate by flip-chip bumps such that a center of
the square chip corresponds to a center of the square substrate and
such that sides of the square chip are parallel to sides of the
square substrate; measuring a distance B between a side of the
square chip and a nearest side of the square substrate; and
removing elongated portions of the square substrate from each
corner of the square substrate, the elongated portions extending a
length e from corners of the square substrate toward corresponding
corners of the square chip, wherein e>( {square root over
(2)}-1)B.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
This application is based upon and claims priority from prior U.S.
patent application Ser. No. 15/255,588 filed on Sep. 2, 2016, which
claims priority from prior U.S. patent application Ser. No.
14/930,984 filed on Nov. 3, 2015, which claims priority from
Japanese Patent Application Number 2013247505 filed on Nov. 29,
2013 and Japanese Patent Application Number 2013257637 filed on
Dec. 13, 2013, the entire disclosure of each is hereby incorporated
by reference in its entirety.
BACKGROUND
The present invention relates to a technology of mounting an
integrated circuit (IC) chip (or simply "a chip", below) on a
substrate and particularly to a chip mounting structure in which a
chip is mounted on a substrate having such a shape that a stress
exerted on a flip-chip-connected chip is reduced.
In these years, with size reduction of semiconductor devices, the
dielectric constant (k) of a material of interlayer insulators in
the back end of line (BEOL) has been decreasing. However, a
material of insulators having a low dielectric constant, such as
SiCOH (hydroxyl silicon carbide), is porous and is thus very
brittle. The interlayer insulating layer itself thus has a low
mechanical strength and becomes separated due to a stress being
exerted at the time of cooling after being subjected to flip chip
mounting and reflow soldering.
Since a chip and a substrate on which the chip is mounted are
connected together with a lead-free solder, which is harder and
less ductile than a lead solder that has been used thus far, the
stress exerted on the interlayer insulating layer due to a
difference in coefficient of thermal expansion between the chip and
the substrate has been increasing.
In addition, thinning of printed circuit boards employing, for
example, organic substrates for the purpose of an improvement of
electrical characteristics or a cost reduction as a result of
reduction of the number of layers increases the warpage of the
substrate, leading to an increase of the stress exerted on the
interlayer insulating layer.
FIG. 1 roughly illustrates the state where the interlayer
insulating layer is separated from an adjacent layer. A low-k layer
105 is disposed on the surface of a semiconductor substrate 100
made of a material such as silicon, an insulating layer 110 made of
a material such as an oxide is disposed on the low-k layer 105, and
a protective layer 115 made of a material such as photosensitive
polyimide (PSPI) is disposed on the insulating layer 110. The
protective layer 115 has an opening at a position corresponding to
an electrode of the low-k layer 105 and an under-bump metallurgy
(UBM) layer 120 is disposed in the opening. A bump 125 such as a
solder is disposed on the UBM layer 120. When a stress is exerted
on the bump 125 in the direction indicated with the arrow of FIG.
1, a crack 130 develops between the low-k layer 105 and the
insulating layer 110 so as to separate these layers.
Japanese Patent Application Publication No. 5-47955 describes a
support board disposed between a semiconductor device and a circuit
board. Electrode terminals are disposed on the surface of the
support board so as to face electrode terminals disposed on the
peripheral portion of the semiconductor device. Electrode terminals
electrically connected with the electrode terminals on the surface
of the support board are arranged in a grid form on the back
surface of the support board. The electrode terminals on the
surface of the support board and the electrode terminals on the
back surface of the support board are respectively connected, via
bumps, with the semiconductor device and the circuit board. Thus,
the stress that occurs due to a difference in coefficient of
thermal expansion between the semiconductor device and the circuit
board is dispersed into bumps arranged in the grid form, whereby
malfunctions of a circuit device due to stress concentration are
minimized.
In the technology of Patent Application Publication No. 5-47955,
the stress exerted on the semiconductor device is reduced by
dispersing the stress that occurs due to the difference in
coefficient of thermal expansion between the semiconductor device
and the circuit board into bumps arranged in the grid form on the
back surface of the support board disposed between the
semiconductor device and the circuit board. Since this technology
involves disposition of the support board between the semiconductor
device and the circuit board, an arrangement of electrode terminals
on the back surface of the support board is limited to the grid
form and is not allowed to be changed in accordance with the design
of the circuit device.
Japanese Patent Application Publication No. 2002-100699 describes a
semiconductor device in which a semiconductor chip has
through-holes at corner portions and a reinforcement land having a
ball bump on the connection side is formed through each
through-hole. When the chip is mounted on a mounting substrate, the
reinforcement lands are connected to the substrate so that the
thermal stress exerted on circuit connection pads adjacent to the
corners of the semiconductor chip attenuates, whereby separation or
electrical disconnection of the circuit connection pads is
minimized.
The technology of Japanese Patent Application Publication No.
2002-100699 involves formation of a reinforcement land at each
corner portion of a semiconductor chip and occupation of an area
for the reinforcement land at each corner portion of the
semiconductor chip, whereby the use of the corner portions of the
semiconductor chip is limited and thus the corner portions are not
allowed to be used freely.
SUMMARY
An object of the present invention is to accomplish highly reliable
chip mounting by using a substrate having such a shape that a
stress exerted on a flip-chip-connected chip can be reduced, so
that the stress exerted on the chip is reduced and separation of an
interlayer insulating layer having a low dielectric constant
(low-k) is minimized. The object of the present invention includes
providing a chip mounting structure in which a chip is mounted on a
substrate having the above-described shape. A chip mounting
structure according to an embodiment of the present invention
includes a chip including an interlayer insulating layer having a
low dielectric constant and a substrate to which the chip is
flip-chip connected via a bump, wherein the substrate has such a
shape that a mechanical stress exerted on the interlayer insulating
layer at a corner portion of the chip due to a thermal stress is
reduced, the thermal stress occurring due to a difference in
coefficient of thermal expansion between the chip and the
substrate.
Preferably, the substrate has such a shape that satisfies A<B
where A denotes a distance from each of corners of the chip to a
corresponding position on an edge of the substrate that is on a
line extending from a center of the chip, positioned at the same
position as a center of the substrate, through the corner of the
chip and B denotes a distance from each of sides of the chip to a
corresponding portion of the edge of the substrate, the
corresponding portion being parallel to the side of the chip.
Preferably, the substrate has a shape of a square from which
squares each having sides of a length c are cut off at corner
portions of the square, where the length c is expressed as the
following expression:
>.times..times..times. ##EQU00001##
Preferably, the substrate has a shape of a square from which
right-angled isosceles triangles each having two sides of a length
d are cut off at corner portions of the square, where the length d
is expressed as the following expression: d>(2- {square root
over (2)})B Expression 2
Preferably, the substrate has a shape of a square from which
elongated cuts that extend a length e from the corresponding
corners of the square toward the corresponding corners of the chip
are cut off, where the length e is expressed as the following
expression: e>( {square root over (2)}-1)B Expression 3
Preferably, the substrate has a shape of a circle having a center
positioned at the same position as a center of the chip and having
a radius longer than a distance from the center of the chip to each
of corners of the chip.
In the present invention, highly reliable chip mounting is
accomplished by using a substrate having such a shape that a stress
exerted on a flip-chip-connected chip can be reduced, so that the
stress exerted on the chip is reduced and separation of an
interlayer insulating layer having a low dielectric constant
(low-k) is minimized. Particularly, the highly reliable chip
mounting is accomplished by a chip mounting structure, in which a
chip is mounted on a substrate having the above-described shape,
provided through the present invention.
In a chip mounting structure according to the present invention,
the stress exerted on a chip is reduced by using a substrate having
a predetermined shape. Thus, unlike in the case of the technology
of Japanese Patent Application Publication No. 5-47955, the chip
mounting structure according to the present invention does not
involve the use of an additional support board between a
semiconductor device and a circuit board, whereby the production
cost of the chip mounting structure can be minimized. Moreover,
unlike in the case of the technology of Japanese Patent Application
Publication No. 2002-100699, the chip mounting structure does not
involve occupation of an area adjacent to each corner of a
semiconductor chip for reinforcement, whereby the area adjacent to
each corner of the chip can be effectively used.
BRIEF DESCRIPTION OF THE DRAWINGS
The accompanying figures wherein reference numerals refer to
identical or functionally similar elements throughout the separate
views, and which together with the detailed description below are
incorporated in and form part of the specification, serve to
further illustrate various embodiments and to explain various
principles and advantages all in accordance with the present
invention, in which:
FIG. 1 is a cross-sectional view that roughly illustrates the state
where an interlayer insulating layer is separated from an adjacent
layer.
FIG. 2 is a perspective view schematically illustrating a first
chip mounting structure subjected to structure analysis.
FIG. 3 is a perspective view schematically illustrating a second
chip mounting structure subjected to structure analysis.
FIG. 4 is a perspective view schematically illustrating a third
chip mounting structure subjected to structure analysis.
FIG. 5 is a bar graph illustrating a normalized form of the stress
that occurs at the corners of a chip in each of the first to third
chip mounting structures subjected to structure analysis.
FIG. 6(A) is a top plan view schematically illustrating a chip
mounting structure according to a first embodiment of the present
invention.
FIG. 6(B) is a side view of the chip mounting structure according
to the first embodiment.
FIG. 7(A) is a top plan view schematically illustrating a chip
mounting structure according to a second embodiment of the present
invention.
FIG. 7(B) is a side view of the chip mounting structure according
to the second embodiment.
FIG. 8(A) is a top plan view schematically illustrating a chip
mounting structure according to a third embodiment of the present
invention.
FIG. 8(B) is a side view of the chip mounting structure according
to the third embodiment.
FIG. 9(A) is a top plan view schematically illustrating a chip
mounting structure according to a fourth embodiment of the present
invention.
FIG. 9(B) is a side view of the chip mounting structure according
to the fourth embodiment.
DETAILED DESCRIPTION
As required, detailed embodiments are disclosed herein; however, it
is to be understood that the disclosed embodiments are merely
examples and that the systems and methods described below can be
embodied in various forms. Therefore, specific structural and
functional details disclosed herein are not to be interpreted as
limiting, but merely as a basis for the claims and as a
representative basis for teaching one skilled in the art to
variously employ the present subject matter in virtually any
appropriately detailed structure and function. Further, the terms
and phrases used herein are not intended to be limiting, but
rather, to provide an understandable description of the
concepts.
The description of the present invention has been presented for
purposes of illustration and description, but is not intended to be
exhaustive or limited to the invention in the form disclosed. Many
modifications and variations will be apparent to those of ordinary
skill in the art without departing from the scope and spirit of the
invention. The embodiment was chosen and described in order to best
explain the principles of the invention and the practical
application, and to enable others of ordinary skill in the art to
understand the invention for various embodiments with various
modifications as are suited to the particular use contemplated.
Best modes for embodying the present invention will be illustrated
below in detail with reference to the drawings. However, the
present invention within the scope of claims is not limited to the
following embodiments. In addition, all the combinations of the
characteristics described in the embodiments are not necessarily
essential to solution to problems. The present invention may be
embodied in various different modes and should not be understood as
being limited to the contents described in the embodiments.
Throughout the entire description of the embodiments, the same
components are denoted by the same reference numerals.
The inventors have studied the relationship between the shape of a
substrate and a stress exerted on the chip by performing structure
analysis of a chip mounting structure using, for example, a finite
element method (FEM). The inventors have thus found that changing
the shape of the substrate on the basis of the studied relationship
reduces the stress exerted on the interlayer insulating layer
through bumps at the corners of the chip.
FIG. 2 is a perspective view schematically illustrating a first
chip mounting structure 200 subjected to structure analysis. The
chip mounting structure 200 has such a structure in which a chip
205 is mounted on an existing rectangular substrate 210. In a
portion 215 in FIG. 2, an arrangement of bumps 220 at a corner
portion of the chip 205 is schematically illustrated in an enlarged
manner. In the chip mounting structure 200, a distance A from a
corner of the chip 205 to the corresponding position on the edge of
the substrate 210 is longer than a distance B from a side of the
chip 205 to the corresponding side of the substrate 210 that is
parallel to the side of the chip 205, that is, A>B.
FIG. 3 is a perspective view schematically illustrating a second
chip mounting structure 300 subjected to structure analysis. The
chip mounting structure 300 has such a structure in which a chip
205 is mounted on a substrate 305 having such a shape that small
rectangular corner portions are cut off. In the chip mounting
structure 300, a distance A from a corner of the chip 205 to the
corresponding position on the edge of the substrate 305 is equal to
a distance B from a side of the chip 205 to the corresponding side
of the substrate 305 that is parallel to the side of the chip 205,
that is, A=B.
FIG. 4 is a perspective view schematically illustrating a third
chip mounting structure 400 subjected to structure analysis. The
chip mounting structure 400 has such a structure in which a chip
205 is mounted on a substrate 405 having such a shape that large
rectangular corner portions are cut off. In the chip mounting
structure 400, a distance A from a corner of the chip 205 to the
corresponding position on the edge of the substrate 405 is shorter
than a distance B from a side of the chip 205 to the corresponding
side of the substrate 405 that is parallel to the side of the chip
205, that is, A<B.
FIG. 5 is a bar graph illustrating a normalized form of the stress
that occurs at the corners of a chip in each of the first to third
chip mounting structures 200, 300, and 400 subjected to structure
analysis. The stress is normalized with reference to the stress
that occurs in the first chip mounting structure 200 (where
A>B). In the case of the second chip mounting structure 300
(where A=B), the stress is reduced, although to a small degree,
compared to the existing rectangular structure where A>B as a
result of cutting off small rectangular corner portions so that
A=B. In the case of the third chip mounting structure 400 (where
A<B), the stress is substantially reduced compared to the
existing rectangular structure where A>B as a result of cutting
off large rectangular corner portions so that A<B.
On the basis of this finding, the inventor has developed the use of
a substrate having a shape in which A<B and in which the
mechanical stress exerted on the interlayer insulating layer at
corner portions of the chip is reduced. Highly reliable chip
mounting is accomplished by using a chip mounting structure in
which a chip is mounted on a substrate having such a shape.
FIG. 6 schematically illustrates a chip mounting structure 500
according to a first embodiment of the present invention. FIG. 6(A)
is a top plan view of the chip mounting structure 500 and FIG. 6(B)
is a side view of the chip mounting structure 500. In the chip
mounting structure 500, a substrate 505 has a shape of a square
from which squares 510 each having sides of a length c are cut off
at corner portions of the square. In order that the substrate 505
has a shape that satisfies the condition A<B, the length c has
to satisfy the following condition. Firstly, a distance A is
calculated. The distance from a corner of the chip 205 to the
corresponding corner of an original square of the substrate 505
from which the squares 510 are not cut off is expressed by the
following expression: {square root over (2)}B Expression 4
The length of the diagonal of the squares 510 is expressed by the
following expression: {square root over (2)}c Expression 5
Thus, the distance A is expressed by the following expression: A=
{square root over (2)}B- {square root over (2)}c= {square root over
(2)}(B-c) Expression 6
Since A<B, the following expression is satisfied: {square root
over (2)}(B-c)<B Expression 7
When this expression is changed by changing the subject to the
length c, the length c is expressed by the following
expression:
>.times..times..times. ##EQU00002##
In order that the substrate 505 has a shape that satisfies A<B,
the length c has to satisfy the above expression. For example, when
the chip 205 is a 20 mm square and the original square of the
substrate 505 is a 50 mm square, the distance B is 50/2-20/2, that
is, 15 mm. When the distance B is 15 mm, the length c has to be
longer than 4.4 mm.
FIG. 7 schematically illustrates a chip mounting structure 600
according to a second embodiment of the present invention. FIG.
7(A) is a top plan view of the chip mounting structure 600 and FIG.
7(B) is a side view of the chip mounting structure 600. In the chip
mounting structure 600, a substrate 605 has a shape of a square
from which right-angled isosceles triangles 610 each having two
sides of a length d are cut off at corner portions of the square.
In order that the substrate 605 has a shape that satisfies the
condition A<B, the length d has to satisfy the following
condition. Firstly, a distance A is calculated. A distance from a
corner of the chip 205 to the corresponding corner of an original
square of the substrate 605 from which the right-angled isosceles
triangles 610 are not cut off is expressed by the following
expression: {square root over (2)}B Expression 9
The length or the height from the base to the vertex of each
right-angled isosceles triangle 610 is expressed by the following
expression:
.times..times. ##EQU00003##
Thus, the distance A is expressed by the following expression:
.times..times..times. ##EQU00004##
Since A<B, the following expression is satisfied:
.times.<.times..times. ##EQU00005##
When this expression is changed by changing the subject to the
length d, the length d is expressed by the following expression:
d>(2- {square root over (2)})B Expression 13
In order that the substrate 605 has a shape that satisfies A<B,
the length d has to satisfy the above expression. For example, when
the chip 205 is a 20 mm square and the original square of the
substrate 605 is a 50 mm square, the distance B is 50/2-20/2, that
is, 15 mm. When the distance B is 15 mm, the length d has to be
longer than 8.8 mm.
FIG. 8 schematically illustrates a chip mounting structure 700
according to a third embodiment of the present invention. FIG. 8(A)
is a top plan view of the chip mounting structure 700 and FIG. 8(B)
is a side view of the chip mounting structure 700. In the chip
mounting structure 700, a substrate 705 has a shape of a square
from which cuts 610 that extend a length e from the corresponding
corners of the square toward the corners of the chip 205 are cut
off. In order that the substrate 705 has a shape that satisfies the
condition A<B, the length e has to satisfy the following
condition. Firstly, a distance A is calculated. A distance from a
corner of the chip 205 to the corresponding corner of an original
square of the substrate 705 from which the cuts are not cut off is
expressed by the following expression: {square root over (2)}B
Expression 14
Since the cuts having a length e are cut off at corner portions of
the original square, the distance A is expressed by the following
expression: A= {square root over (2)}B-e Expression 15
Since A<B, the following expression is satisfied: {square root
over (2)}B-e<B Expression 16
When this expression is changed by changing the subject to the
length e, the length e is expressed by the following expression:
e>( {square root over (2)}-1)B Expression 17
In order that the substrate 705 has a shape that satisfies A<B,
the length e has to satisfy the above expression. For example, when
the chip 205 is a 20 mm square and the original square of the
substrate 705 is a 50 mm square, the distance B is 50/2-20/2, that
is, 15 mm. When the distance B is 15 mm, the length e has to be
longer than 6.2 mm.
FIG. 9 schematically illustrates a chip mounting structure 800
according to a fourth embodiment of the present invention. FIG.
9(A) is a top plan view of the chip mounting structure 800 and FIG.
9(B) is a side view of the chip mounting structure 800. In the chip
mounting structure 800, a substrate 805 has a circular shape that
has a center at the same position as the center of the chip 205 and
that has a radius longer than a distance from the center of the
chip 205 to each corner of the chip 205. When the substrate 805 has
such a circular shape, the distance A is calculated by subtracting
half the diagonal of the chip 205 from the radius and the distance
B is calculated by subtracting half the length of one side of the
chip 205 from the radius. Since the diagonal of the chip 205 is
longer than the length of one side of the chip 205, the substrate
805 has a shape that satisfies A<B. For example, when the chip
205 is a 20 mm square and the substrate 805 is a circle having a
diameter of 50 mm, the distance A is calculated as 10.9 mm by
subtracting half the diagonal of the chip 205, which is 14.1 mm,
from the radius of 25 mm and the distance B is calculated as 15 mm
by subtracting half the length of one side of the chip 205, which
is 10 mm, from the radius of 25 mm. Thus, the substrate 805 has a
shape that satisfies A<B.
Non-Limiting Examples
Although the present invention has been described thus far using
some embodiments, the technical scope of the invention is not
limited to the scope described in relation to these embodiments.
The embodiments may be modified or improved in various manners and
modes to which such modification or improvement has been made are
also naturally included in the technical scope of the
invention.
The description of the present application has been presented for
purposes of illustration and description, but is not intended to be
exhaustive or limited to the invention in the form disclosed. Many
modifications and variations will be apparent to those of ordinary
skill in the art without departing from the scope and spirit of the
invention. The embodiment was chosen and described in order to best
explain the principles of the invention and the practical
application, and to enable others of ordinary skill in the art to
understand the invention for various embodiments with various
modifications as are suited to the particular use contemplated.
* * * * *