U.S. patent number 10,158,015 [Application Number 15/687,753] was granted by the patent office on 2018-12-18 for finfets with strained well regions.
This patent grant is currently assigned to Taiwan Semiconductor Manufacturing Company, Ltd.. The grantee listed for this patent is Taiwan Semiconductor Manufacturing Company, Ltd.. Invention is credited to Chih-Hsin Ko, Yi-Jing Lee, Clement Hsingjen Wann, Cheng-Hsien Wu.
United States Patent |
10,158,015 |
Lee , et al. |
December 18, 2018 |
FinFETs with strained well regions
Abstract
A device includes a substrate and insulation regions over a
portion of the substrate. A first semiconductor region is between
the insulation regions and having a first conduction band. A second
semiconductor region is over and adjoining the first semiconductor
region, wherein the second semiconductor region includes an upper
portion higher than top surfaces of the insulation regions to form
a semiconductor fin. The semiconductor fin has a tensile strain and
has a second conduction band lower than the first conduction band.
A third semiconductor region is over and adjoining a top surface
and sidewalls of the semiconductor fin, wherein the third
semiconductor region has a third conduction band higher than the
second conduction band.
Inventors: |
Lee; Yi-Jing (Hsinchu,
TW), Wu; Cheng-Hsien (Hsinchu, TW), Ko;
Chih-Hsin (Fongshan, TW), Wann; Clement Hsingjen
(Carmel, NY) |
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Company, Ltd. |
Hsinchu |
N/A |
TW |
|
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Assignee: |
Taiwan Semiconductor Manufacturing
Company, Ltd. (Hsin-Chu, TW)
|
Family
ID: |
51369665 |
Appl.
No.: |
15/687,753 |
Filed: |
August 28, 2017 |
Prior Publication Data
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Document
Identifier |
Publication Date |
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US 20170352596 A1 |
Dec 7, 2017 |
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Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
Issue Date |
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15253958 |
Sep 1, 2016 |
9748143 |
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14725299 |
Sep 27, 2016 |
9455320 |
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13779015 |
Jul 21, 2015 |
9087902 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L
21/31051 (20130101); H01L 29/66795 (20130101); H01L
29/7842 (20130101); H01L 29/7848 (20130101); H01L
29/7849 (20130101); H01L 29/66787 (20130101); H01L
21/3212 (20130101); H01L 29/66431 (20130101); H01L
29/7786 (20130101); H01L 29/7787 (20130101); H01L
29/7789 (20130101); H01L 29/161 (20130101); H01L
29/165 (20130101); H01L 29/0649 (20130101); H01L
29/0653 (20130101); H01L 29/157 (20130101); H01L
29/785 (20130101); H01L 21/823431 (20130101); H01L
21/02532 (20130101); H01L 21/823412 (20130101); H01L
29/1054 (20130101); H01L 29/0847 (20130101); H01L
29/41791 (20130101); H01L 21/31053 (20130101); H01L
29/432 (20130101); H01L 29/0657 (20130101) |
Current International
Class: |
H01L
29/78 (20060101); H01L 29/417 (20060101); H01L
21/8234 (20060101); H01L 29/15 (20060101); H01L
29/06 (20060101); H01L 21/3105 (20060101); H01L
29/10 (20060101); H01L 29/66 (20060101); H01L
29/778 (20060101); H01L 29/08 (20060101); H01L
21/02 (20060101); H01L 29/161 (20060101); H01L
29/165 (20060101); H01L 21/321 (20060101); H01L
29/43 (20060101) |
References Cited
[Referenced By]
U.S. Patent Documents
Foreign Patent Documents
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101189730 |
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May 2008 |
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CN |
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102832236 |
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Dec 2012 |
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CN |
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102010038742 |
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Feb 2012 |
|
DE |
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1020050078145 |
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Aug 2005 |
|
KR |
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101145959 |
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Oct 2010 |
|
KR |
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1020110052432 |
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May 2011 |
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KR |
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2007046150 |
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Apr 2007 |
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WO |
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Other References
Daembkes, Heinrich, et al., "The n-Channel SiGe/Si Modulation-Doped
Field-Effect Transistor," IEEE Transactions on Electron Devices,
vol. ED-33, No. 5, May 1986, pp. 633-638. cited by applicant .
Pillarisetty, R., et al., "High Mobility Strained Germanium Quantum
Well Field Effect Transistor as the P-Channel Device Option for Low
Power (Vcc=0.5V) III-V CMOS Architecture," IEEE, IEDM10-159, pp.
6.7.1-6.7.4., Dec. 6-8, 2010. cited by applicant.
|
Primary Examiner: Lopez; Fei Fei Yeung
Attorney, Agent or Firm: Slater Matsil, LLP
Parent Case Text
PRIORITY CLAIM AND CROSS-REFERENCE
This application is a continuation of U.S. patent application Ser.
No. 15/253,958, entitled "FinFETs with Strained Well Regions,"
filed on Sep. 1, 2016, which is a continuation of U.S. patent
application Ser. No. 14/725,299, entitled "FinFETs with Strained
Well Regions," filed on May 29, 2015, now U.S. Pat. No. 9,455,320
issued Sep. 27, 2016, which application is a divisional of U.S.
patent application Ser. No. 13/779,015, entitled "FinFETs with
Strained Well Regions," filed on Feb. 27, 2013, now U.S. Pat. No.
9,087,902 issued Jul. 21, 2015, which applications are incorporated
herein by reference.
Claims
What is claimed is:
1. A device comprising: a substrate; insulation regions over a
portion of the substrate; a first semiconductor region between the
insulation regions; a second semiconductor region over and
adjoining the first semiconductor region, wherein the second
semiconductor region comprises an upper portion higher than top
surfaces of the insulation regions to form a semiconductor fin; a
third semiconductor region over the semiconductor fin, wherein the
third semiconductor region comprises at least a first sub layer
doped with an n-type impurity, wherein the first, the second and
the third semiconductor regions are formed of different materials;
a silicon cap over the third semiconductor region, wherein the
silicon cap is free from n-type and p-type impurities; and a source
region and a drain region on opposite sides of the semiconductor
fin.
2. The device of claim 1, wherein the second semiconductor region
is intrinsic.
3. The device of claim 1, wherein the third semiconductor region
extends from the source region to the drain region.
4. The device of claim 1, wherein the first semiconductor region
and the third semiconductor region comprise silicon germanium, and
have germanium atomic percentages higher than an atomic percentage
of the second semiconductor region.
5. The device of claim 1, wherein the third semiconductor region
comprises: a second sub layer on sidewalls and a top surface of the
semiconductor fin, wherein the first sub layer is over the second
sub layer, and the second sub layer is an un-doped layer
substantially free from n-type impurities.
6. The device of claim 5, wherein the third semiconductor region
further comprises a third sub layer overlying the first sub layer,
and the third sub layer is substantially free from n-type
impurities.
7. The device of claim 6, wherein each of the first sub layer, the
second sub layer, and the third sub layer comprises silicon
germanium, and atomic percentages of silicon in the first sub
layer, the second sub layer, and the third sub layer are equal to
each other, and atomic percentages of germanium in the first sub
layer, the second sub layer, and the third sub layer are equal to
each.
8. The device of claim 1, wherein the second semiconductor region
has a conduction band lower than conduction bands of the first
semiconductor region and the third semiconductor region.
9. A device comprising: a silicon substrate; Shallow Trench
Isolation (STI) regions extending into the silicon substrate; a
semiconductor fin protruding higher than top surfaces of the STI
regions, wherein the semiconductor fin is between opposite portions
of the STI regions; a silicon germanium region contacting a top
surface and sidewalls of the semiconductor fin, wherein the silicon
germanium region comprises: a first sub layer having a first n-type
impurity concentration; and a second sub layer over the first sub
layer, wherein the second sub layer has a second n-type impurity
concentration higher than the first n-type impurity concentration;
a gate dielectric over the silicon germanium region; a gate
electrode over the gate dielectric; and a source region and a drain
region on opposite sides of the gate dielectric and the gate
electrode, wherein the source region and the drain region are
n-type regions, and wherein the silicon germanium region extends
from the source region and the drain region.
10. The device of claim 9, wherein the first sub layer is free from
p-type impurities.
11. The device of claim 10 further comprising a third sub layer
over the second sub layer, and the third sub layer is free from
both n-type impurities and n-type impurities.
12. The device of claim 9, wherein the semiconductor fin is
intrinsic.
13. The device of claim 9 further comprising an additional silicon
germanium region located between and in contact with the STI
regions, wherein the additional silicon germanium region is
relaxed.
14. The device of claim 9 further comprising a silicon cap over the
silicon germanium region, wherein the silicon cap is substantially
free from germanium, and the silicon cap is intrinsic.
15. A device comprising: a silicon germanium region comprising: a
first layer having a first n-type impurity concentration; a second
layer over the first layer, wherein the second layer has a second
n-type impurity concentration; and a third layer over the second
layer, wherein the third layer has a third n-type impurity
concentration, and the second n-type impurity concentration is
higher than both the first n-type impurity concentration and the
third n-type impurity concentration; a gate dielectric over the
silicon germanium region; a gate electrode over the gate
dielectric; and a source region and a drain region on opposite
sides of the gate dielectric and the gate electrode.
16. The device of claim 15, wherein the first layer and the third
layer are substantially free from n-type impurities.
17. The device of claim 16, wherein the first layer and the third
layer are further free from p-type impurities.
18. The device of claim 15 further comprising a silicon layer free
from germanium between the third layer and the gate dielectric,
wherein the silicon layer and the silicon germanium region extend
from the source region to the drain region, and the silicon layer
is undoped with p-type and n-type impurities.
19. The device of claim 15 further comprising: isolation regions;
and a semiconductor fin protruding higher than top surfaces of the
isolation regions, wherein the silicon germanium region is on a top
surface and sidewalls of the semiconductor fin, and the
semiconductor fin is undoped with p-type and n-type impurities.
20. The device of claim 15, wherein the first layer, the second
layer, and the third layer have a same germanium atomic percentage.
Description
BACKGROUND
The speed of metal-oxide-semiconductor (MOS) transistors are
closely related to the drive currents of the MOS transistors, which
are further closely related to the mobility of charges in the
channels of the MOS transistors. For example, NMOS transistors have
high drive currents when the electron mobility in their channel
regions is high, while PMOS transistors have high drive currents
when the hole mobility in their channel regions is high. Germanium,
silicon germanium, and compound semiconductor materials (referred
to as III-V compound semiconductors hereinafter) comprising group
III and group V elements are thus good candidates for forming their
high electron mobility and/or hole mobility.
Germanium, silicon germanium, and III-V compound semiconductor
regions are also promising materials for forming the channel
regions of Fin Field-Effect transistors (FinFETs). Methods and
structures for further improving the drive currents on the FinFETs
are currently being studied.
BRIEF DESCRIPTION OF THE DRAWINGS
For a more complete understanding of the embodiments, and the
advantages thereof, reference is now made to the following
descriptions taken in conjunction with the accompanying drawings,
in which:
FIGS. 1 through 9C are cross-sectional views of intermediate stages
in the manufacturing of a semiconductor fin and a Fin Field-Effect
Transistor (FinFET) in accordance with some exemplary embodiments;
and
FIG. 10 illustrates a band diagram of a plurality of semiconductor
regions in the FinFET.
DETAILED DESCRIPTION
The making and using of the embodiments of the disclosure are
discussed in detail below. It should be appreciated, however, that
the embodiments provide many applicable concepts that can be
embodied in a wide variety of specific contexts. The specific
embodiments discussed are illustrative, and do not limit the scope
of the disclosure.
Fin Field-Effect Transistors (FinFETs) and methods of forming the
same are provided in accordance with various exemplary embodiments.
The intermediate stages of forming the FinFETs in accordance with
some embodiments are illustrated. The variations of the embodiments
are discussed. Throughout the various views and illustrative
embodiments, like reference numbers are used to designate like
elements.
Referring to FIG. 1, substrate 20 is provided. Substrate 20 may be
a semiconductor substrate such as a crystalline silicon substrate.
Substrate 20 may also include silicon, germanium, carbon, or the
like. Insulation regions such as Shallow Trench Isolation (STI)
regions 22 are formed in substrate 20. STI regions 22 may be formed
by recessing semiconductor substrate 20 to form trenches, and then
filling the trenches with dielectric materials such as silicon
oxide. A Chemical Mechanical Polish (CMP) is then performed to
remove excess portions of the dielectric materials, and the
remaining portions are STI regions 22. The top surfaces of STI
regions 22 are thus level with the top surface of substrate 20.
STI regions 22 include neighboring regions having their sidewalls
facing each other. Portions 20' of substrate 20 extend between the
neighboring STI regions. Width W1 of substrate portions 20' may be
between about 10 nm and about 200 nm. It is appreciated that the
dimensions recited throughout the description are merely examples,
and may be changed to different values. The neighboring STI regions
may be separate regions, or may be portions of a continuous region,
which may form a STI ring in some embodiments.
Referring to FIG. 2, substrate portions 20' are recessed, forming
recesses 24 between neighboring STI regions 22. In some
embodiments, the bottoms of recesses 24 are higher than the bottom
surfaces of STI regions 22. In alternative embodiments, the bottoms
of recesses 24 are substantially level with or lower than the
bottoms of STI regions 22.
Referring to FIG. 3, semiconductor regions 26 are grown in recesses
24 through epitaxy. The top surfaces of semiconductor regions are
lower than the top surfaces of STI regions 22. Semiconductor
regions 26 may have a first lattice constant greater than the
lattice constant of substrate 20. In some embodiments,
semiconductor regions 26 comprises silicon germanium, which is
expressed as Sil-xGex, wherein value X is the atomic percentage of
germanium in semiconductor regions 26, which atomic percentage may
be between about 0.2 (20 percent) and 1 (100 percent) in exemplary
embodiments. Semiconductor regions 26 are a relaxed semiconductor
region, which means that at least the top portions of semiconductor
regions are relaxed with substantially no stress. This may be
achieved by, for example, making thickness T1 great enough, since
the stresses in upper portions of semiconductor regions 26 are
increasingly smaller than the lower portions. In some exemplary
embodiments, thickness T1 is greater than about 30 nm, and may be
between about 30 nm and about 150 nm. In some exemplary
embodiments, the conduction band of semiconductor regions 26 is
lower than the conduction band of bulk silicon by between about
0.036 eV and about 0.144 eV, wherein the conduction band of silicon
is about 1.1 eV. FIG. 10 schematically illustrates bandgap BG1,
conduction band Ec1, and valence band Ev1 of semiconductor regions
26.
Next, referring to FIG. 4, semiconductor regions 28 are grown in
recesses 24 through epitaxy, wherein semiconductor regions 28 are
grown over and contacting semiconductor regions 26. Semiconductor
regions 28 have a tensile strain, and may be un-doped with n-type
and p-type impurities. In some embodiments, the tensile strain is
generated by making the lattice constant of semiconductor regions
28 smaller than the lattice constant of semiconductor regions 26.
In some embodiments, the tensile strain is higher than about 1.36
MPa, and may be higher than about 6.8 GPa. Semiconductor regions 28
include portions in recesses 24 (FIG. 3), which portions have
thickness T2. Thickness T2 is small enough, so that after the
subsequent Chemical Mechanical Polish (CMP) in FIG. 5,
semiconductor regions 28 are not relaxed and have the tensile
strain. In some exemplary embodiments, thickness T2 is smaller than
about 150 nm, and may be between about 30 nm and about 150 nm.
FIG. 10 schematically illustrates bandgap BG2, conduction band Ec2,
and valence band Ev2 of semiconductor regions 28. Conduction band
Ec2 is lower than the conduction band Ec1 of semiconductor regions
26, with the difference (Ec1-Ec2) being greater than about 0.036
eV, for example. In some embodiments, semiconductor regions 28
comprise Sil-yGey, wherein value Y is the atomic percentage of
germanium in semiconductor regions 28. Value Y may be smaller than
about 0.3 (30 percent), and may be between 0 and about 0.3. Value Y
may also be equal to 0, which means that semiconductor regions 28
are silicon regions free from germanium. Furthermore, value Y is
smaller than value X of semiconductor regions 26, with the
difference (X-Y) being greater than about 0.1, greater than about
0.3, or greater than about 0.5, for example. A greater difference
(X-Y) may advantageously result in a greater tensile strain in
semiconductor regions 28, and a greater conduction band difference
(Ec1-Ec2).
Semiconductor regions 28 may be grown to a level higher than the
top surfaces of STI regions 22. A CMP is then performed to level
the top surface of STI regions 22 and semiconductor regions 28. The
resulting structure is shown in FIG. 5. In alternative embodiments,
the growth of semiconductor regions 28 stops at a time when the top
surface of semiconductor regions 28 is level with or lower than the
top surfaces of STI regions 22. In these embodiments, the CMP may
be performed, or may be skipped.
Referring to FIG. 6, STI regions 22 are recessed, for example,
through an etching step. The top surfaces 22A of the remaining STI
regions 22 are higher than the interfaces 27 between semiconductor
regions 26 and semiconductor regions 28. The portions of
semiconductor regions 28 that are higher than top surfaces 22A are
referred to as semiconductor fins 30 hereinafter.
FIG. 7 illustrates the formation of semiconductor regions 34, which
are epitaxially grown on the exposed top surfaces and sidewalls of
semiconductor fins 30. Semiconductor regions 34 are substantially
conformal layers, with the portions on the top surfaces of
semiconductor fins 30 having substantially the same thickness T3 as
the portions on the sidewalls of semiconductor fins 30. In some
embodiments, thickness T3 is between about 5 nm and about 150
nm.
Bandgap BG3, conduction band Ec3, and valence band Ev3 of
semiconductor regions 34 are schematically illustrated in FIG. 10.
Conduction band Ec3 is higher than conduction band Ec2 of
semiconductor regions 28, with the difference (Ec3-Ec2) being
greater than about 0.036 eV, for example. In some embodiments,
semiconductor regions 34 comprise Sil-zGez, wherein value Z is the
atomic percentage of silicon in semiconductor regions 34. Value Z
may be greater than about 0.3, and maybe between about 0.3 and 1.
Value Z may also be equal to 1, which means that semiconductor
regions 34 are pure germanium regions free from silicon.
Furthermore, value Z is greater than value Y of semiconductor
regions 28, with the difference (Z-Y) being greater than about 0.1,
or greater than about 0.3, for example. A greater difference (Z-Y)
may advantageously result in a greater conduction band difference
(Ec3-Ec2).
In some embodiments, semiconductor regions 34 include layers 34A
and layers 34B, which are formed over layers 34A. Layers 34A and
layers 34B may have substantially the same atomic percentage of
silicon and substantially the same atomic percentage of germanium,
although their compositions may also be different from each other.
In some exemplary embodiments, layers 34A are not doped with n-type
impurities, and may also be free from p-type impurities. In
alternative embodiments, layers 34A are n-type doped layers with
the n-type impurity concentration lower than about 1016/cm 3, for
example. Thickness T4 of layers 34A may be greater than 0 nm and
smaller than about 50 nm. Layers 34B are n-type layers, wherein the
n-type impurity concentration in layers 34B may be higher than
about 1018/cm 3. In these embodiments, the n-type impurity
concentration in layers 34A is lower than the n-type impurity
concentration in layers 34B. Layers 34B act as the electron-supply
layers for supplying electrons to the underlying carrier channels
46 (FIGS. 9A through 9C).
The doped n-type impurity may include phosphorous, arsenic,
antimony, or combinations thereof. Layers 34A and layers 34B may be
formed in-situ in a same vacuum chamber, and may be formed using
essentially the same process conditions, except that in the
formation of layers 34A, no n-type dopant is added, while the
n-type dopant is added in the formation of layers 34B.
Alternatively, in the formation of both layers 34A and 34B, n-type
dopants are added, and the n-type dopant amount for forming layers
34A is smaller than that for forming layers 34B. In some
embodiments, thickness T5 of doped layers 34B is between about 1 nm
and about 20 nm.
In some embodiments, semiconductor regions 34 further include
layers 34C over layers 34B. Layers 34C may have atomic percentages
of silicon and germanium same as either one, or both, of layers 34A
and 34B. In alternative embodiments, the silicon and germanium
atomic percentages in layers 34A, 34B, and 34C are all different
from each other. Layers 34C may also be un-doped with n-type
impurities, or doped with n-type impurities that have a lower
impurity concentration than the respective underlying layers 34B.
In alternative embodiments, layers 34C are not formed, and the
respective structure may be found in FIG. 9B.
FIG. 8 illustrates the formation of silicon caps 36, which may be
substantially pure silicon regions with no germanium added. Silicon
caps 36 may also be formed through epitaxy, and hence are over the
top portions and sidewall portions of semiconductor regions 34. In
some embodiments, no n-type and p-type impurities are added into
silicon caps 36, although n-type and p-type impurities with low
concentrations, for example, lower than about 1016/cm 3, may also
be added. Thickness T6 of silicon caps 36 may be between about 1 nm
and about 20 nm in some embodiments. In alternative embodiments,
silicon caps 36 are not formed.
The structure shown in FIG. 8 may be used to form FinFET 38, as
shown in FIGS. 9A, 9B, and 9C. Referring to FIG. 9A, gate
dielectric 40 and gate electrode 42 are formed. Gate dielectric 40
may be formed of a dielectric material such as silicon oxide,
silicon nitride, an oxynitride, multi-layers thereof, and/or
combinations thereof. Gate dielectric 40 may also be formed of
high-k dielectric materials. The exemplary high-k materials may
have k values greater than about 4.0, or greater than about 7.0.
Gate electrode 42 may be formed of doped polysilicon, metals, metal
nitrides, metal silicides, and the like. The bottom ends of gate
dielectric 42 may contact the top surfaces of STI regions 22. After
the formation of gate dielectric 40 and gate electrode 42, source
and drain regions 50 (FIG. 9C) are formed.
As shown in FIG. 9A, semiconductor regions 28 form interfaces 44
with the adjoin semiconductor regions 34. Carrier channels 46,
which are alternatively referred to as Two-Dimensional Electron Gas
(2DEG) channels, are formed and located in semiconductor regions
28. 2DEG channels 46 may also be close to interfaces 44. Although
semiconductor regions 28 may not be doped with n-type impurities,
carrier channels 46 still have a high density of electrons, which
are supplied by the respective overlying electron-supply layers
34B.
FIG. 9B illustrates a cross-sectional view of FinFET 38 in
accordance with alternative embodiments. These embodiments are
essentially the same as the embodiments in FIG. 9A, except that no
layer 34C is formed. Accordingly, silicon caps 36 are in physical
contact with the respective underlying layers 34B.
FIG. 9C illustrates a cross-sectional view of FinFET 38, wherein
the cross-sectional view is obtained from the plane crossing line
9C-9C in FIG. 9A. Source and drain regions 50 are formed on the
opposite sides of gate dielectric 40 and gate electrode 42. Source
and drain regions 50 are doped with an n-type impurity such as
phosphorous, arsenic, antimony, or the like, and hence the
respective FinFET 38 is an n-type FinFET. 2DEG channel 46
interconnects the source and drain regions 50.
FIG. 10 schematically illustrates a band diagram of semiconductor
regions 26, 28, and 34. As shown in FIG. 10, the conduction band
Ec2 of semiconductor region 28 is lower than conduction band Ec1 of
semiconductor region 26 and conduction band Ec3 of semiconductor
region 34. Accordingly, conduction bands Ec1, Ec2, and Ec3 form a
well, with conduction band Ec2 forming the bottom of the well.
Electrons 48, which are supplied by electron-supply layers 34B
(FIGS. 9A and 9B), are confined in the well to form the 2DEG
channels. The formation of the well is attributed to that
semiconductor region 28 is tensile strained, and hence conduction
band Ec2 is suppressed to a level lower than conduction bands Ec1
and Ec3. As a comparison, if semiconductor region 28 is not tensile
strained, the conduction band of semiconductor region 28 will be
higher than the conduction bands of semiconductor regions 26 and
34, and hence the well region and the 2DEG channel will not be
formed. In addition, since semiconductor region 28 may not be doped
with impurities, electrons can move freely without collision or
with substantially reduced collisions with the impurities.
In the embodiments of the present disclosure, by forming relaxed
semiconductor region 26 that has a greater lattice constant than
the lattice constant of semiconductor region 28, the overlying
semiconductor region 28 may have a tensile strain. The tensile
strain results in a conduction band well to be formed in
semiconductor region 28. Furthermore, electron-supply layer 34B is
formed overlying semiconductor region 28 to supply electrons, which
are confined in the well formed in semiconductor region 28 to form
the 2DEG channel. Accordingly, the resulting FinFET has a high
saturation current.
In accordance with some embodiments, a device includes a substrate
and insulation regions over a portion of the substrate. A first
semiconductor region is between the insulation regions and having a
first conduction band. A second semiconductor region is over and
adjoining the first semiconductor region, wherein the second
semiconductor region includes an upper portion higher than top
surfaces of the insulation regions to form a semiconductor fin. The
semiconductor fin has a tensile strain and has a second conduction
band lower than the first conduction band. A third semiconductor
region is over and adjoining a top surface and sidewalls of the
semiconductor fin, wherein the third semiconductor region has a
third conduction band higher than the second conduction band.
In accordance with other embodiments, a device includes a silicon
substrate and STI regions over a portion of the silicon substrate.
A first SiGe region is located between and in contact with the STI
regions, wherein the first SiGe region has a first germanium atomic
percentage. A silicon-containing region is over the first SiGe
region, with edges of the silicon-containing region vertically
aligned to respective edges of the first SiGe region. The
silicon-containing region has a tensile stress. A second SiGe
region contacts a top surface and sidewalls of the
silicon-containing region. The second SiGe region has second
germanium atomic percentage. The first and the second germanium
atomic percentages are higher than a third germanium atomic
percentage of the silicon-containing region. The device further
includes a gate dielectric over the second SiGe region, a gate
electrode over the gate dielectric, and a source region and a drain
region on opposite sides of the gate dielectric and the gate
electrode.
In accordance with yet other embodiments, a method includes
recessing a portion of a substrate between two insulation regions
to form a recess, performing a first epitaxy to grow a first
semiconductor region in the recess, and performing a second epitaxy
to grow a second semiconductor region in the recess. The first
semiconductor region is relaxed. The second semiconductor region is
over and contacting the first semiconductor region. The second
semiconductor region has a tensile strain. A planarization is
performed to level top surfaces of the second semiconductor region
and the insulation regions. The insulation regions are recessed,
wherein a top portion of the second semiconductor region over the
insulation regions forms a semiconductor fin. A third epitaxy is
performed to grow a third semiconductor region on a top surface and
sidewalls of the semiconductor fin. The second semiconductor region
has a conduction band lower than conduction bands of the first and
the third semiconductor regions.
Although the embodiments and their advantages have been described
in detail, it should be understood that various changes,
substitutions and alterations can be made herein without departing
from the spirit and scope of the embodiments as defined by the
appended claims. Moreover, the scope of the present application is
not intended to be limited to the particular embodiments of the
process, machine, manufacture, and composition of matter, means,
methods and steps described in the specification. As one of
ordinary skill in the art will readily appreciate from the
disclosure, processes, machines, manufacture, compositions of
matter, means, methods, or steps, presently existing or later to be
developed, that perform substantially the same function or achieve
substantially the same result as the corresponding embodiments
described herein may be utilized according to the disclosure.
Accordingly, the appended claims are intended to include within
their scope such processes, machines, manufacture, compositions of
matter, means, methods, or steps. In addition, each claim
constitutes a separate embodiment, and the combination of various
claims and embodiments are within the scope of the disclosure.
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