U.S. patent application number 17/518215 was filed with the patent office on 2022-06-16 for passivation layer for an integrated circuit device that provides a moisture and proton barrier.
This patent application is currently assigned to STMicroelectronics Pte Ltd. The applicant listed for this patent is STMicroelectronics Pte Ltd. Invention is credited to Ditto ADNAN, Maurizio Gabriele CASTORINA, Eng Hui GOH, Voon Cheng NGWAN, Fadhillawati TAHIR, Boon Kiat TUNG.
Application Number | 20220189840 17/518215 |
Document ID | / |
Family ID | 1000006003706 |
Filed Date | 2022-06-16 |
United States Patent
Application |
20220189840 |
Kind Code |
A1 |
GOH; Eng Hui ; et
al. |
June 16, 2022 |
PASSIVATION LAYER FOR AN INTEGRATED CIRCUIT DEVICE THAT PROVIDES A
MOISTURE AND PROTON BARRIER
Abstract
An integrated circuit device includes a metal contact and a
passivation layer extending on a sidewall of the metal contact and
on first and second surface portions of a top surface of the metal
contact. The passivation layer is format by a stack of layers
including: a tetraethyl orthosilicate (TEOS) layer; a Phosphorus
doped TEOS (PTEOS) layer on top of the TEOS layer; and a
Silicon-rich Nitride layer on top of the PTEOS layer. The TEOS and
PTEOS layers extend over the first surface portion, but not the
second surface portion, of the top surface of the metal contact.
The Silicon-rich Nitride layer extends over both the first and
second surface portions, and is in contact with the second surface
portion.
Inventors: |
GOH; Eng Hui; (Singapore,
SG) ; NGWAN; Voon Cheng; (Singapore, SG) ;
TAHIR; Fadhillawati; (Singapore, SG) ; ADNAN;
Ditto; (Singapore, SG) ; TUNG; Boon Kiat;
(Singapore, SG) ; CASTORINA; Maurizio Gabriele;
(Singapore, SG) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics Pte Ltd |
Singapore |
|
SG |
|
|
Assignee: |
STMicroelectronics Pte Ltd
Singapore
SG
|
Family ID: |
1000006003706 |
Appl. No.: |
17/518215 |
Filed: |
November 3, 2021 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
63126096 |
Dec 16, 2020 |
|
|
|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/45 20130101;
H01L 23/3171 20130101; H01L 29/511 20130101 |
International
Class: |
H01L 23/31 20060101
H01L023/31; H01L 29/51 20060101 H01L029/51; H01L 29/45 20060101
H01L029/45 |
Claims
1. An integrated circuit device, comprising: a metal contact having
a top surface, the top surface of the metal contact including a
first surface portion, a second surface portion and a third surface
portion; and a passivation layer extending on the first and second
surface portions of the top surface of the metal contact; wherein
the passivation layer comprises a stack of layers including: a
tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS
(PTEOS) layer on top of the TEOS layer; and a high-density
Silicon-rich Nitride layer on top of the PTEOS layer; wherein the
TEOS and PTEOS layers extend over the first surface portion of the
top surface of the metal contact, but not over the second and third
surface portions of the top surface of the metal contact; and
wherein the high-density Silicon-rich Nitride layer extends over
the first and second surface portions of the top surface of the
metal contact, but not over the third surface portion of the top
surface of the metal contact.
2. The integrated circuit device of claim 1, wherein the
high-density Silicon-rich Nitride layer is in contact with the
second surface portion of the top surface of the metal contact.
3. The integrated circuit device of claim 1, wherein the
high-density Silicon-rich Nitride layer is in contact with side
edge surfaces of the TEOS and PTEOS layers at a transition from the
first surface portion to the second surface portion.
4. The integrated circuit device of claim 1, wherein the TEOS layer
is in contact with the first surface portion of the top surface of
the metal contact.
5. The integrated circuit device of claim 1, further comprising a
Silicon flash layer in the stack of layers for the passivation
layer, wherein said Silicon flash layer is positioned between the
PTEOS layer and the high-density Silicon-rich Nitride layer.
6. The integrated circuit device of claim 5, wherein the Silicon
flash layer has a thickness of less than 100 .ANG..
7. The integrated circuit device of claim 5, wherein the Silicon
flash layer is in contact with the second surface portion of the
top surface of the metal contact.
8. The integrated circuit device of claim 5, wherein the Silicon
flash layer is in contact with side edge surfaces of the TEOS and
PTEOS layers at a transition from the first surface portion to the
second surface portion.
9. The integrated circuit device of claim 5, wherein the
high-density Silicon-rich Nitride layer is in contact with the
Silicon flash layer.
10. The integrated circuit device of claim 1, wherein the TEOS
layer has a thickness in a range of about 12,000-16,000 .ANG..
11. The integrated circuit device of claim 1, wherein the PTEOS
layer has a thickness in a range of about 4,000-6,000 .ANG..
12. The integrated circuit device of claim 1, wherein the
high-density Silicon-rich Nitride layer has a thickness in a range
of about 8,000-12,000 .ANG..
13. The integrated circuit device of claim 1, wherein the
high-density Silicon-rich Nitride layer has a ratio of N/Si that is
less than about 1.3 and the high-density Silicon-rich Nitride layer
has a refractive index greater than 2.
14. The integrated circuit device of claim 1, wherein a
stoichiometry of the high-density Silicon-rich Nitride layer
comprises Si.sub.xN.sub.y where x:y is greater than or equal to 3:4
and the high-density Silicon-rich Nitride layer has a refractive
index greater than 2.
15. The integrated circuit device of claim 1, wherein the metal
contact extends over a premetallization dielectric layer.
16. The integrated circuit device of claim 12, wherein the
premetallization dielectric layer is formed solely of TEOS.
17. The integrated circuit device of claim 1, wherein the metal
contact is a gate contact of a discrete transistor.
18. The integrated circuit device of claim 1, wherein the metal
contact is a source contact of a discrete transistor.
19. The integrated circuit device of claim 1, wherein the metal
contact includes a sidewall, and wherein the passivation layer
further extends on the sidewall of the metal contact.
20. The integrated circuit device of claim 1, wherein the metal
contact is a contact for a transistor source or gate terminal.
21. The integrated circuit device of claim 1, wherein the metal
contact is a contact for a transistor emitter or base terminal.
22. The integrated circuit device of claim 1, wherein the metal
contact is a contact for an anode or cathode terminal of a diode.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority from United States
Provisional Application for Patent No. 63/126,096, filed Dec. 16,
2020, the disclosure of which is incorporated herein by
reference.
TECHNICAL FIELD
[0002] The present invention generally relates to integrated
circuit devices and, in particular, to a passivation layer for such
an integrated circuit device that provides a barrier against a
contaminant, such as moisture and proton, intrusion.
BACKGROUND
[0003] Reference is made to FIG. 1 which shows a cross-section of a
portion of an integrated circuit device 10. The illustrated device
in this embodiment is a discrete power transistor of, for example,
a vertical gate n-channel MOSFET type.
[0004] A semiconductor substrate 12 is lightly doped with a
first-type dopant (for example, N-type). The semiconductor
substrate 12 includes a top surface 14 and a bottom surface 16. A
peripheral edge surface 18 of the semiconductor substrate 12 joins
the top surface 14 and bottom surface 16. The semiconductor
substrate 12 forms the drain region of the discrete power
transistor. A metal layer 58 at the bottom surface 16 provides the
drain (D) electrical contact. The metal layer 58 may, for example,
be made of a stack of layers including: a Titanium (Ti) layer; a
Nickel (Ni) or alloy of Nickel and Vanadium (NiV) layer; and a
Silver (Ag) or Gold (Au) layer.
[0005] A plurality of trenches 20 extend into the semiconductor
substrate 12 from the top surface 14. The trenches 20 have a depth
which is less than a thickness of the semiconductor substrate 12.
In an embodiment, each trench 20 has a width (extending in the
plane of the cross-section) and a length (extending perpendicular
to the width and in a plane into and out of the cross-section). In
an embodiment, the length is substantially greater than the width,
and thus each trench 20 is a strip trench extending into and out of
the cross-section and having a rectangular shape in top view. Each
trench 20 is lined by an insulating liner 22, with the remainder of
each trench filled by an electrical conductor 24 forming the gate
electrode of the discrete power transistor. In an embodiment, the
insulating liner 22 is made of a dielectric material, for example
an oxide, and the electrical conductor 24 is made of a conducting
material, for example polysilicon (that may, if desired, be doped
with a suitable dopant species/type).
[0006] The semiconductor substrate 12 further includes a first
semiconductor well 26 that is doped with a second-type dopant (for
example, P-type). The first semiconductor well 26 has a depth
extending from the top surface 14 which is less than the depth of
the trenches 20. The first semiconductor well 26 forms the body
(channel) region of the discrete power transistor.
[0007] The peripheral termination region PR at the perimeter of the
semiconductor substrate 12 includes a second semiconductor well 27
that is doped with the second-type dopant (for example, P-type).
The second semiconductor well 27 has a depth extending from the top
surface 14 which is greater than the depth of the trenches 20. The
second semiconductor well 27 forms the ring region of the discrete
power transistor.
[0008] The semiconductor substrate 12 further includes a
semiconductor region 28 that is doped with the first-type dopant.
The semiconductor region 28 has a depth extending from the top
surface 14 which is less than the depth of the semiconductor well
26. The semiconductor region 28 forms the source region of the
discrete power transistor. The semiconductor region 28 does not
extend across the entire top surface 14 of the semiconductor
substrate 12, but rather is present only in an active region AR
corresponding generally to the area where the trenches 20 are
present.
[0009] A field oxide region 30 is provided at the top surface 14 of
the semiconductor substrate 12 in the peripheral region PR outside
of the active region AR and adjacent the peripheral edge surface
18. This field oxide region 30 may, for example, surround the
active region AR.
[0010] A premetallization dielectric layer 32 is deposited to cover
the top surface 14 of the semiconductor substrate 12 and the oxide
region 30. The premetallization dielectric layer 32 may be made of
a dielectric material such as, for example, tetraethyl
orthosilicate (tetraethoxysilane--TEOS). In an embodiment, the
premetallization dielectric layer 32 may comprise a stack of layers
including a TEOS layer covering the top surface 14 of the
semiconductor substrate 12 and the oxide region 30 and a Boron and
Phosphorus doped TEOS (BPTEOS) layer covering the TEOS layer. In
another embodiment, the premetallization dielectric layer 32 may
comprise a stack of layers including a TEOS layer covering the top
surface 14 of the semiconductor substrate 12 and the oxide region
30 and a Phosphorus doped TEOS (PTEOS) layer covering the TEOS
layer.
[0011] A plurality of trenches 34 extend through the
premetallization dielectric layer 32 and into the semiconductor
substrate 12. The trenches 34 have a depth which is less than the
depth of the semiconductor well 26 and greater than the depth of
the semiconductor region 28. Thus, the trenches 34 extend fully
through the premetallization dielectric layer 32 and the
semiconductor region 28 and partially into the semiconductor well
26. In an embodiment, each trench 34 has a width (extending in the
plane of the cross-section) and a length (extending perpendicular
to the width and extending in a plane into and out of the
cross-section). In an embodiment, the length is substantially
greater than the width, and thus each trench 34 is a strip trench
extending into and out of the cross-section and having a
rectangular shape in top view. Each trench 34 is located between
(and extends parallel to) two trenches 20. The upper surface of the
premetallization dielectric layer 32 and the sidewalls and bottom
of each trench 34 are lined with a stack of layers 36 comprising,
for example, a thin metal layer and a thin metal nitride layer. The
thin metal layer may, for example, be made of Titanium, and the
thin metal nitride layer may, for example, be made of a Titanium
Nitride (TiN) material. The remainder of each trench 34 filled by
an electrical conductor 38 forming the source and body contact of
the discrete power transistor. The electrical conductor 38 may, for
example, be made of a Tungsten (W) material.
[0012] A first metal layer 42 is deposited over the thin metal
nitride layer 36. This first metal layer 42 may, for example, be
made of Titanium (Ti).
[0013] A second metal layer 44 is deposited over the first metal
layer 42. The second metal layer 44 may, for example, be made of
Aluminum (Al) or an alloy of Copper and Aluminum (AlCu).
[0014] The second metal layer 44, first metal layer 42 and the
metal/metal nitride layer stack 36 are lithographically patterned
to define a source (S) electrical contact 46 and a gate (G)
electrical contact 48.
[0015] The lithographic patterning exposes an upper surface of the
premetallization dielectric layer 32 in areas where the source (S)
electrical contact 46 and gate (G) electrical contact 48 are not
present. A passivation layer 50 is deposited over the source (S)
electrical contact 46, the gate (G) electrical contact 48 and the
exposed upper surface of the premetallization dielectric layer 32.
Detail of the passivation layer 50 configuration at the source (S)
electrical contact 46 and gate (G) electrical contact 48 is shown
in FIG. 2. In an embodiment, the passivation layer 50 may comprise
a TEOS layer 50a, or a Silicon Nitride (SiN) layer 50b, or a stack
of layers including the TEOS layer 50a and the Silicon Nitride
(SiN) layer 50b. The TEOS layer 50a may, for example, have a
thickness of about 10,000 .ANG. and the SiN layer 50b may, for
example, have a thickness of about 10,000 .ANG.. The passivation
layer 50 is lithographically patterned to form openings exposing an
upper surface of the source (S) electrical contact 46 and gate (G)
electrical contact 48.
[0016] The passivation layer 50 is provided to inhibit a
contaminant (such as moisture and proton) intrusion. However,
stress can cause cracks to form in the passivation layer 50.
Contaminants can enter through the cracks and contribute to device
failure. For example, moisture penetration can lead to temperature
humidity bias (THB) reliability failure and proton intrusion can
cause high temperature reverse bias (HTRB) reliability failure.
[0017] There is a need in the art for a passivation layer that can
provide for an improved barrier against a contaminant, such as
moisture and proton, intrusion.
SUMMARY
[0018] In an embodiment, an integrated circuit device comprises: a
metal contact having a top surface and a sidewall, the top surface
of the metal contact including a first surface portion, a second
surface portion and a third surface portion; and a passivation
layer extending on the sidewall of the metal contact and on the
first and second surface portions of the top surface of the metal
contact.
[0019] The passivation layer comprises a stack of layers including:
a tetraethyl orthosilicate (TEOS) layer; a Phosphorus doped TEOS
(PTEOS) layer on top of the TEOS layer; and a high-density
Silicon-rich Nitride layer on top of the PTEOS layer.
[0020] The TEOS and PTEOS layers extend over the first surface
portion of the top surface of the metal contact, but not over the
second and third surface portions of the top surface of the metal
contact.
[0021] The high-density Silicon-rich Nitride layer extends over the
first and second surface portions of the top surface of the metal
contact, but not over the third surface portion of the top surface
of the metal contact.
BRIEF DESCRIPTION OF THE DRAWINGS
[0022] For a better understanding of the embodiments, reference
will now be made by way of example only to the accompanying figures
in which:
[0023] FIG. 1 shows a cross-section of a portion of an integrated
circuit device;
[0024] FIG. 2 shows detail of a passivation layer configuration at
a source electrical contact and a gate electrical contact of the
integrated circuit device of FIG. 1;
[0025] FIG. 3 shows detail of a passivation layer configuration at
the source electrical contact and the gate electrical contact of
the integrated circuit device of FIG. 1;
[0026] FIG. 4 shows a scanning electron micrograph of an example of
the passivation layer configuration;
[0027] FIGS. 5A-5E show steps of a fabrication process for making
the passivation layer configuration of FIGS. 3 and 4;
[0028] FIG. 6 shows detail of a passivation layer configuration at
the source electrical contact and the gate electrical contact of
the integrated circuit device of FIG. 1;
[0029] FIG. 7 illustrates a relationship between N/Si ratio and
refractive index for Si-rich silicon nitride material; and
[0030] FIGS. 8A-8C show cross-sections of other integrated circuit
devices utilizing the passivation layer configuration.
DETAILED DESCRIPTION
[0031] Reference is now made to FIGS. 3 and 6 which show detail of
a passivation layer 50' configuration at the source electrical
contact 46 and the gate electrical contact 48 of the integrated
circuit device of FIG. 1. In this embodiment, the passivation layer
50' comprises a stack of layers including: a TEOS layer 50a', a
Phosphorus doped TEOS (PTEOS) layer 50b' covering the TEOS layer
50a', and a Silicon Nitride (SiN) layer 50c'. The TEOS layer 50a'
may, for example, have a thickness in a range of about
12,000-16,000 .ANG., the PTEOS layer 50b' may, for example, have a
thickness in a range of about 4,000-6,000 .ANG., and the SiN layer
50c' may, for example, have a thickness in a range of about
8,000-12,000 .ANG.. In the implementation as shown in FIG. 6,
adhesion of the SiN layer 50c' on the metal layer 44 may be
enhanced by the use of a thin Silicon flash layer 70 between the
PTEOS layer 50b' and the SiN layer 50c'. The Silicon flash layer 70
may, for example, have a thickness of less than 100 .ANG.. The
passivation layer 50' is lithographically patterned to form
openings exposing an upper surface of the source (S) electrical
contact 46 and gate (G) electrical contact 48.
[0032] The TEOS layer 50a' provides a layer made of a material that
is softer than Silicon Nitride to provide a stress relieving
structure and also presents a good adhesion property with respect
to the Aluminum material of the second metal layer 44. The TEOS
layer 50a' also provides a diffusion barrier that inhibits the
diffusion of Phosphorus from the PTEOS layer 50b'. The PTEOS layer
50b' functions as a gettering layer presenting a proton H+
gettering center. The SiN layer 50c' is preferably implemented as a
high-density Silicon-rich Nitride (referred to in the art as a
"Yellow Nitride") and functions as a moisture resistant barrier
which inhibits penetration of contaminants such as proton H+ and
moisture.
[0033] FIG. 4 shows a scanning electron micrograph of an example of
the passivation layer 50' configuration relative to a contact (C)
made of Aluminum.
[0034] All three layers 50a', 50b' and 50c' of the stack for the
passivation layer 50' extend over the exposed upper surface of the
premetallization dielectric layer 32 in areas where the source (S)
electrical contact 46 and gate (G) electrical contact 48 are not
present (see, right side). All three layers 50a', 50b' and 50c' of
the stack for the passivation layer 50' further extend over
sidewalls (S) of the contact C (i.e., on the side edge surfaces of
the lithographically patterned layers 42 and 44). The three layers
50a', 50b' and 50c' of the stack for the passivation layer 50'
further extend over a first surface portion 52 of the top surface
of the contact C (i.e., on the top surface of the lithographically
patterned layer 44). However, only the SiN layer 50c' extends over
a second surface portion 54 of the top surface of the contact C.
The SiN layer 50c' (along with flash layer 70, when present)
extends on side edge surfaces of the layers 50a', 50b' at a
transition from the first surface portion 52 to the second surface
portion 54. A third surface portion 56 of the top surface of the
contact C is not covered by any of the passivation layer 50'.
Additionally, the SiN layer 50c' extends over sidewalls S1 of the
layers 50a', 50b'.
[0035] Fabrication of the passivation layer 50' requires the use of
two masks in lithographically patterning the three layers 50a',
50b' and 50c' (plus layer 70, if present) of the stack. The steps
of the fabrication process are shown by FIGS. 5A-5E. In FIG. 5A,
the layers 50a', 50b' are deposited over the metal contact C (44).
The layers 50a' and 50b' may, for example, be deposited using
plasma-enhanced chemical vapor deposition (PECVD). In FIG. 5B, a
first mask 60 is formed from a developed photoresist. The first
mask 60 covers the first surface portion 52 of the top surface of
the metal contact. An etch is then performed to remove portions of
the layers 50a', 50b' which are not covered by the first mask 60.
The first mask 60 is then removed. In FIG. 5C, the layer 50c' (with
interposed Silicon flash layer 70, see FIG. 6, if desired) is
conformally deposited to cover the patterned layers 50a', 50b' as
well as the second and third surface portions 54 and 56 of the top
surface of the metal contact. The layer 50c' and may, for example,
be deposited using SiH.sub.4-based plasma-enhanced chemical vapor
deposition (PECVD). The stoichiometry of the SiN layer 50c' may,
for example, comprise Si.sub.xN.sub.y where the bond ratio x:y, for
example, determinable by analysis techniques such as R-ray
photoelectron spectroscopy (XPS), Fourier transform infrared
spectroscopy (FTIS) or Rutherford backscattering (RBS) showing a
N/Si ratio that is less than about 1.3 (or x:y greater than 3:4)
and a refractive index, for example measured by the optical
ellipsometry method, that is greater than 2 (see, FIG. 7). In FIG.
5D, a second mask 62 is formed from a developed photoresist. The
second mask 62 covers the first and second surface portions 52 and
54 of the top surface of the metal contact. An etch is then
performed to remove portions of the layer 50c' which is not covered
by the second mask 62 so as to provide a contact opening 64 over
the third surface portion 56 of the top surface of the metal
contact. The second mask 62 is then removed. The result is shown in
FIG. 5E.
[0036] Although FIGS. 3 and 6 show use of the passivation layer 50'
in connection with a power MOSFET transistor, it will be understood
that the passivation layer 50' may be used in connection with the
metal contact/bonding pad of any suitable integrated circuit
device. Examples of such devices include, but are not limited to, a
shielded gate trench power MOSFET (FIG. 8A) where the passivation
is provided at a source and/or a gate contact, a trench gate field
stop IGBT (FIG. 8B) where the passivation is provided at an emitter
and/or gate contact, a superjunction MOSFET (FIG. 8C) where the
passivation is provided at a source and/or gate contact, and a
power diode where the passivation is provided at an anode and/or
cathode contact.
[0037] While the invention has been illustrated and described in
detail in the drawings and foregoing description, such illustration
and description are considered illustrative or exemplary and not
restrictive; the invention is not limited to the disclosed
embodiments. Other variations to the disclosed embodiments can be
understood and effected by those skilled in the art in practicing
the claimed invention, from a study of the drawings, the
disclosure, and the appended claims.
* * * * *