U.S. patent application number 16/952968 was filed with the patent office on 2022-02-10 for semiconductor device with sealed semiconductor chip.
This patent application is currently assigned to TOSHIBA MEMORY CORPORATION. The applicant listed for this patent is TOSHIBA MEMORY CORPORATION. Invention is credited to Isao OZAWA.
Application Number | 20220044987 16/952968 |
Document ID | / |
Family ID | 1000006104951 |
Filed Date | 2022-02-10 |
United States Patent
Application |
20220044987 |
Kind Code |
A9 |
OZAWA; Isao |
February 10, 2022 |
SEMICONDUCTOR DEVICE WITH SEALED SEMICONDUCTOR CHIP
Abstract
A semiconductor device includes a semiconductor chip with
bonding pads, the bonding pads being arranged along one side of an
element forming surface of the semiconductor chip, a lead frame
including first and second internal leads arranged such that tips
thereof correspond to some of the bonding pads of the semiconductor
chip, and first and second bonding wires by which the first
internal leads and the some of the bonding pads are bonded to each
other. The semiconductor device further includes a hanging pin
section provided on the element non-forming surface of the
semiconductor chip, and a sealing member with which the
semiconductor chip is sealed including the hanging pin section and
a bonding section between the first and second internal leads and
the first and second bonding wires.
Inventors: |
OZAWA; Isao; (Chigasaki-shi,
JP) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TOSHIBA MEMORY CORPORATION |
Tokyo |
|
JP |
|
|
Assignee: |
TOSHIBA MEMORY CORPORATION
Tokyo
JP
|
Prior
Publication: |
|
Document Identifier |
Publication Date |
|
US 20210074609 A1 |
March 11, 2021 |
|
|
Family ID: |
1000006104951 |
Appl. No.: |
16/952968 |
Filed: |
November 19, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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16438826 |
Jun 12, 2019 |
10872844 |
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16952968 |
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14617637 |
Feb 9, 2015 |
10366942 |
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16438826 |
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13029466 |
Feb 17, 2011 |
8970019 |
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14617637 |
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11430965 |
May 10, 2006 |
7919837 |
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13029466 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/4951 20130101;
H01L 24/49 20130101; H01L 2924/12042 20130101; H01L 2924/01037
20130101; H01L 2924/181 20130101; H01L 2924/1532 20130101; H01L
2924/01023 20130101; H01L 2924/01075 20130101; H01L 23/28 20130101;
H01L 2924/01005 20130101; H01L 2924/01019 20130101; H01L 2924/07802
20130101; H01L 2225/06562 20130101; H01L 2924/01033 20130101; H01L
2924/01004 20130101; H01L 23/49575 20130101; H01L 2924/01002
20130101; H01L 2924/01082 20130101; H01L 2924/01006 20130101; H01L
2924/3025 20130101; H01L 2924/14 20130101; H01L 2224/48247
20130101; H01L 2924/00014 20130101; H01L 23/495 20130101; H01L
2924/01058 20130101; H01L 24/48 20130101; H01L 2224/48257 20130101;
H01L 2224/49171 20130101; H01L 2224/48091 20130101 |
International
Class: |
H01L 23/495 20060101
H01L023/495; H01L 23/00 20060101 H01L023/00; H01L 23/28 20060101
H01L023/28 |
Foreign Application Data
Date |
Code |
Application Number |
May 11, 2005 |
JP |
2005-138718 |
Oct 4, 2005 |
JP |
2005-291391 |
Apr 19, 2006 |
JP |
2006-115959 |
Claims
1. (canceled)
2: A semiconductor device comprising: a resin; a first terminal
group, which is located outside the resin and is provided on a
first side; a second terminal group, which is located outside the
resin and is provided on a second side, which is an opposite side
of the first side; wherein a terminal at one end of the first
terminal group is a first terminal, a terminal at another end is a
second terminal, and a distance between the first terminal and the
second terminal is a first distance, a terminal at one end of the
second terminal group and closer to the first terminal than the
second terminal is a third terminal, a terminal at another end is a
fourth terminal, and a distance between the third terminal and the
fourth terminal is a second distance, a distance between the first
terminal and the third terminal is a third distance, the third
distance being larger than the first distance and the second
distance, a distance between the second terminal and the fourth
terminal is the fourth distance, the fourth distance being larger
than the first distance and the second distance, a fifth terminal,
which is one terminal in the first terminal group, and a sixth
terminal, which is one terminal in the second terminal group, are
physically connected inside the resin via a center wiring; and a
semiconductor chip, having a plurality of first pads and a
plurality of second pads on a first surface, placed inside the
resin and provided on the center wiring.
3: The semiconductor device of claim 2, further comprising: a first
internal wiring, which is placed inside the resin and physically
connects to the first terminal; a second internal wiring, which is
placed inside the resin and physically connects to the second
terminal; a third internal wiring, which is placed inside the resin
and physically connects to the third terminal; and a fourth
internal wiring, which is placed inside the resin and physically
connects to the fourth terminal, wherein, the first internal
wiring, the second internal wiring, the third internal wiring, and
the fourth internal wiring are electrically insulated from the
semiconductor chip.
4: The semiconductor device of claim 3, wherein each of the first
internal wiring, the second internal wiring, the third internal
wiring, and the fourth internal wiring has a hanging pin
portion.
5: The semiconductor device of claim 2, wherein a fifth internal
wiring group connected to some terminals of the second terminal
group, passes through a second surface side opposite to the first
surface and has a plurality of first tip portions on the first
side.
6: The semiconductor device of claim 5, wherein a sixth internal
wiring group connected to some terminals of the first terminal
group has a plurality of second tip portions on the first side.
7: The semiconductor device of claim 6, further comprising a
plurality of first bonding wires that connects the plurality of
first tip portions and the plurality of first pads, and a plurality
of second bonding wires that connects the plurality of second tip
portions and the plurality of second pad.
8: The semiconductor device of claim 7, wherein the fifth internal
wiring group is divided into a first group and a second group with
the central wiring in between, and the first group is closer to the
first terminal.
9: The semiconductor device of claim 8, wherein the sixth internal
wiring group is divided into a third group and a fourth group with
the central wiring in between, and the third group is closer to the
first terminal.
10: The semiconductor device of claim 9, wherein a tip of an
internal wiring of the third group closest to the first terminal is
closer to the first terminal along the first side than a tip of an
internal wiring of the first group closest to the first
terminal.
11: The semiconductor device of claim 9, wherein a tip of an
internal wiring of the fourth group closest to the second terminal
is closer to the second terminal along the first side than a tip of
an internal wiring of the second group closest to the second
terminal.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation application of U.S.
application Ser. No. 16/438,826, filed on Jun. 12, 2019, which is a
continuation of U.S. application Ser. No. 14/617,637 (now U.S. Pat.
No. 10,366,942), filed on Feb. 9, 2015, which is a continuation of
U.S. application Ser. No. 13/029,466 (now U.S. Pat. No. 8,970,019),
filed on Feb. 17, 2011, which is a continuation of U.S. application
Ser. No. 11/430,965 (now U.S. Pat. No. 7,919,837), filed on May 10,
2006, and is based upon and claims the benefit of priority from
prior Japanese Patent Applications No. 2005-138718, filed May 11,
2005; No. 2005-291391, filed Oct. 4, 2005; and No. 2006-115959,
filed Apr. 19, 2006, the entire contents of all of which are
incorporated herein by reference.
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0002] The present invention relates to a semiconductor device.
More specifically, the invention relates to a semiconductor device
having a package structure in which a semiconductor chip with a
plurality of pads along one side thereof is mounted on a lead frame
and sealed with resin or the like (referred to as a packaged
semiconductor device hereinafter).
2. Description of the Related Art
[0003] A packaged semiconductor device having a ball grid array
(BGA) structure in which a plurality of pads are all arranged along
one side of a semiconductor chip, has recently been developed (Jpn.
Pat. Appln. KOKAI Publication No. 2001-102515, pages 4 and 5 and
FIG. 1, for example). In the packaged semiconductor device, the
semiconductor chip is stacked on and displaced from a low-level
chip, thereby reducing the size of the semiconductor chip and
facilitating wire bonding.
[0004] If, however, a semiconductor chip with a plurality of pads
along one side thereof is applied to a packaged semiconductor
device having a thin small outline package (TSOP) structure, the
following problem occurs. In this packaged semiconductor device,
the semiconductor chip is fixed on a die pad section of a lead
frame by an insulative adhesive, and the pads on the chip are
connected to the internal leads of the lead frame by bonding wires,
respectively. Some of the internal leads are arranged close to the
pads, whereas the others are arranged away from the pads. In order
to connect the latter internal leads to the pads, very long bonding
wires are required. In the subsequent resin-sealing process, the
long bonding wires are easily dropped due to resin, and adjacent
bonding wires are easily brought into contact with each other
(electrically short-circuited).
[0005] Jpn. Pat. Appln. KOKAI Publication No. 2001-217383 discloses
a semiconductor device in which a semiconductor chip with a
plurality of bonding pads along one side of the main surface
thereof and another semiconductor chip of the same type are stacked
on the substrate and thus the bonding pads of these chips are close
to each other.
BRIEF SUMMARY OF THE INVENTION
[0006] According to a first aspect of the present invention, there
is provided a semiconductor device comprising a semiconductor chip
with bonding pads, the bonding pads being arranged along one side
of an element forming surface of the semiconductor chip; a lead
frame including first internal leads and second internal leads, the
first internal leads being arranged such that tips thereof
correspond to some of the bonding pads of the semiconductor chip,
and the second internal leads being arranged such that tips thereof
pass a element non-forming surface of the semiconductor chip and
correspond to some of other bonding pads of the semiconductor chip;
first bonding wires by which the first internal leads and the some
of the bonding pads are connected to each other; second bonding
wires by which the second internal leads and the some of other
bonding pads are connected to each other; a hanging pin section
provided on the element non-forming surface of the semiconductor
chip; and a sealing member with which the semiconductor chip is
sealed including the hanging pin section and a bonding section
between the first and second internal leads and the first and
second bonding wires.
[0007] According to a second aspect of the present invention, there
is provided a semiconductor device comprising a semiconductor chip
with bonding pads, the bonding pads being arranged along one side
of an element forming surface of the semiconductor chip; a lead
frame including internal leads, the internal leads being arranged
on the element forming surface of the semiconductor chip and close
to the bonding pads thereof such that tips of the internal leads
correspond to the bonding pads of the semiconductor chip; bonding
wires by which the tips of the internal leads and the bonding pads
of the semiconductor chip are bonded; a hanging pin section
provided on the element forming surface of the semiconductor chip;
and a sealing member with which the semiconductor chip is sealed
including the hanging pin section and a bonding section between the
internal leads and the bonding wires, the sealing member being
rectangular.
BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING
[0008] FIG. 1 is a sectional view showing a configuration of a
packaged semiconductor device having a TSOP structure according to
a first embodiment of the present invention;
[0009] FIG. 2 is a bottom view of the packaged semiconductor device
shown in FIG. 1 to view the inside thereof from the bottom
thereof;
[0010] FIG. 3 is a top view of the packaged semiconductor device
shown in FIG. 1 to view the inside thereof from the top
thereof;
[0011] FIG. 4A is a plan (top) view showing a configuration of a
semiconductor chip that is applied to the packaged semiconductor
device shown in FIG. 1;
[0012] FIG. 4B is a side view of the semiconductor chip shown in
FIG. 4A;
[0013] FIG. 5 is a plan view of external terminals assigned to
bonding pads of the semiconductor chip shown in FIGS. 4A and
4B;
[0014] FIG. 6 is a plan view showing a configuration of a lead
frame that is applied to the packaged semiconductor device shown in
FIG. 1;
[0015] FIG. 7 is a plan view showing another configuration of the
lead frame that is applied to the packaged semiconductor device
shown in FIG. 1;
[0016] FIG. 8 is a plan view of the layout of a semiconductor chip,
taking a NAND flash memory with bonding pads on one side as an
example;
[0017] FIG. 9 is a top view of a packaged semiconductor device
having a TSOP structure according to a second embodiment of the
present invention to view the inside thereof from the top
thereof;
[0018] FIG. 10 is a sectional view showing a configuration of a
packaged semiconductor device having a TSOP structure according to
a third embodiment of the present invention;
[0019] FIG. 11 is a bottom view of a packaged semiconductor device
having a TSOP structure according to a fourth embodiment of the
present invention to view the inside thereof from the bottom
thereof;
[0020] FIGS. 12A and 12B are sectional views each showing a
configuration of the packaged semiconductor device shown in FIG.
11;
[0021] FIG. 13 is a plan (top) view showing a configuration of a
semiconductor chip that is applied to the packaged semiconductor
device shown in FIG. 11;
[0022] FIG. 14 is a top view of a packaged semiconductor device
having a TSOP structure according to a fifth embodiment of the
present invention to view the inside thereof from the top
thereof;
[0023] FIGS. 15A and 15B are sectional views each showing a
configuration of a packaged semiconductor device having a TSOP
structure according to a sixth embodiment of the present
invention;
[0024] FIG. 16 is a bottom view showing a configuration of a
packaged semiconductor device having a TSOP structure according to
a seventh embodiment of the present invention;
[0025] FIG. 17 is a sectional view of the configuration of the
packaged semiconductor device shown in FIG. 16;
[0026] FIGS. 18A and 18B are comparative diagrams showing a
comparison between a section of the packaged semiconductor device
shown in FIG. 16 and that of another packaged semiconductor device;
and
[0027] FIG. 19 is a sectional view showing a configuration of a
packaged semiconductor device having a TSOP structure according to
an eighth embodiment of the present invention.
DETAILED DESCRIPTION OF THE INVENTION
[0028] Embodiments of the present invention will be described with
reference to the accompanying drawings. It should be noted that the
drawings are schematic ones and the dimension ratios shown therein
are different from the actual ones. The dimensions vary from
drawing to drawing and so do the ratios of dimensions.
First Embodiment
[0029] FIGS. 1 to 3 show a basic configuration of a semiconductor
device (packaged semiconductor device) having a TSOP structure
according to a first embodiment of the present invention. Of these
figures, FIG. 1 is a sectional view of the packaged semiconductor
device, FIG. 2 is a bottom view of the packaged semiconductor
device to view the inside thereof from the back surface, and FIG. 3
is a top view of the packaged semiconductor device to view the
inside thereof from the top surface.
[0030] Referring to FIGS. 1 to 3, a lead frame 11 includes external
leads 11c and 11d, internal leads 11a and 11b, and a hanging pin
section 11f. The internal leads 11a and 11b correspond to
internally extended portions of the external leads 11c and 11d. The
internal leads 11a and 11b differ from each other in length. For
example, some (middle ones) of the internal leads 114, which are
longer than the internal leads 11a, are used as a die lead section
(chip mounting section) on which a semiconductor chip 10 is
mounted. The internal leads 11a and 11b are not depressed from each
other, but almost flush with each other.
[0031] The hanging pin section 11f is connected to each of the
outermost ones of the longer internal leads 11b.
[0032] As shown in FIGS. 4A and 4B, bonding pads 13 are arranged on
the element forming surface of the semiconductor chip 10 and along
one side of the chip 10. A thin sheet-shaped organic insulation
film 12 having a thickness of about 20 .mu.m to 40 .mu.m is adhered
to the back surface (element non-forming surface) of the chip 10.
The organic insulation film 12 is made of, e.g., polyimide epoxy
resin.
[0033] The semiconductor chip 10 is mounted on the die lead section
of the longer internal leads 11b and the hanging pin section 11f by
the organic insulation film 12 and a normal mounting agent. The
bonding pads 13 are close to the shorter internal leads 11a on
which the semiconductor chip 10 is not mounted. In other words, the
tips of the shorter internal leads 11a are opposed to the bonding
pads 13, and the longer internal leads 11b pass the back surface of
the chip 10 and extend such that their tips are located between the
chip 10 and the shorter internal leads 11a.
[0034] The organic insulation film 12 is used to enhance the
insulativeness between the back surface of the chip 10 and the die
lead section. A film-shaped insulative adhesive, which is attached
to the back of a wafer, can be used as the organic insulation film
12 in a scribe (dicing) step of separating the chip 10 from the
wafer. There is a case where the organic insulation film 12 is not
used when a plurality of semiconductor chips are stacked one on
another.
[0035] As shown in FIGS. 1 and 2, the shorter internal leads 11a on
which the chip 10 is not mounted, or the internal leads 11a located
away from the bonding pads 13 are connected to some of the bonding
pads 13 by first bonding wires 141. On the other hand, the tips of
the longer internal leads 11b on which the chip 10 is mounted are
connected to some of the other bonding pads 13 by second bonding
wires 142.
[0036] The internal leads 11a and 11b, hanging pin section 11f,
chip 10 and bonding wires 141 and 142 of the lead frame 11 are
sealed with resin (sealing member) 15 to form a resin package. The
resin package is so configured that the sealed portion of the lead
frame 11 on the chip-mounting surface (the back of the packaged
semiconductor device) is thicker than that on the chip non-mounting
surface (the surface of the packaged semiconductor device). Thus,
the chip 10 is sealed in almost the middle part of the resin
package in its thickness direction.
[0037] The portions communicating with the internal leads 11a and
11b protrude from at least opposing sides of the resin package to
form the external leads 11c and 11d (parts of the lead frame 11).
In other words, the external leads 11c and 11d protrude from a
position that is higher than the middle of the resin package in its
thickness direction. The external leads 11c and 11d extend along
the sides of the semiconductor chip 10 and bend toward the chip
mounting surface of the lead frame 11. The tips of the external
leads 11c and 11d bend away from the resin package and serve as
external terminals. In other words, the chip 10 is sealed facedown
in the resin package.
[0038] The packaged semiconductor device shown in FIGS. to 3 has a
chip-on-lead (CCL) structure in which the chip 10 is adhesively
fixed to the longer internal leads 11b and the internal leads 11a
and 11b are connected to the bonding pads 13 by the bonding wires
141 and 142. The internal leads 11a and 11b are arranged on almost
the same plane and not depressed. Since none of them are depressed,
a mounting step and a bonding step can easily be executed. If the
lead frame is depressed, variations in depression affect the
mounting and bonding steps. If a lead frame has to be depressed, a
depressing step is required in manufacturing the lead frame. The
depressing step makes the manufacturing complicated and exerts an
adverse influence on frame manufacturing yields.
[0039] The hanging pin section 11f of the lead frame 11 is fixed to
the element non-forming surface of the chip 10. When the lead frame
11 is sealed with resin 15, the moldability of the sealed frame 11
can be stabilized. The appearance of the semiconductor device can
thus be enhanced more than a device in which the chip 10 is fixed
by the internal leads 11b only.
[0040] The chip 10 is fixed on the die lead section corresponding
to almost the middle portions of the longer internal leads 11b. The
bonding pads 13 of the chip 10 are connected to the tips of the
internal leads 11a and 11b which are close to the bonding pads 13
and, in other words, wire bonding is performed on one side of the
chip 10 along which the bonding pads 13 are arranged. The bonding
wires 141 and 142 need not be long; consequently, it is not likely
that the bonding wires will be dropped or adjacent bonding wires
will be electrically short-circuited when the lead frame is sealed
with resin after the wire-bonding step. Accordingly, the
semiconductor device is improved in reliability.
[0041] The resin package is so configured that the sealed portion
of the chip mounting section of the lead frame 11 is thicker than
that of the chip non-mounting section thereof. The chip 10 can thus
be sealed close to almost the middle of the resin package in its
thickness direction.
[0042] The external leads 11c and 11d protrude from the sides of
the resin package, extend along the sides of the semiconductor chip
10 and bend toward the chip mounting section of the lead frame 11.
The chip 10 is sealed facedown in the resin package. In a device
assembly step, when the top surface of the formed resin package, or
the resin package surface on the chip non-mounting surface of the
lead frame 11 is irradiated with laser beams for marking, the
internal leads 11b are interposed between the irradiated surface
and the chip 10. The adverse effects of causing damage to the chip
10 by laser beams transmitted through the resin 15 or causing a
disconnection by laser beams transmitted through the bonding wires
141 and 142 can thus be lessened.
[0043] Since the bonding pads 13 are arranged locally along one
side of the element forming surface of the semiconductor chip 10,
the chip 10 can be decreased in size. A large-capacity memory chip
such as a NAND flash memory varies in area because the wire
connection of peripheral circuits is made efficient depending on
how the peripheral circuits are laid out. When bonding pads are
arranged locally along one side of the memory chip as in the chip
10 of the first embodiment, the wires are efficiently connected
between the pads and the peripheral circuits and accordingly the
memory chip is decreased in size. Thus, the first embodiment is
favorably applied to, for example, a NAND flash memory as a
large-capacity memory chip, which requires a low-cost multilayer
packaging technique. An example of layout of a NAND flash memory
with pads along one side thereof will be described later.
[0044] Since the internal leads 11a and 11b of the lead frame 11
are supplied with external signals or power supply or ground
potentials, they have to be insulated from the semiconductor chip
10. An insulation-type pasty mounting agent or film-like mounting
agent and the organic insulation film 12 of the back surface of the
chip 10 can increase the electrical insulativeness between the chip
10 and the internal leads 11b with high reliability.
[0045] Since the chip 10 is adhered onto the die lead section by
the thin organic insulation film 12, it is suitable for the TSOP
structure. The difference in level between the top surface (element
forming surface) of the chip 10 and the tips of the internal leads
11a and 11b can thus be lessened to facilitate wire bonding. Since,
moreover, the bonding wires 141 and 142 are arranged locally in the
direction of one side of the chip 10 mounted on the internal leads
11b, a larger chip can be mounted.
[0046] FIG. 5 shows an example of external terminals assigned to
the bonding pads 13 arranged on the element forming surface of the
semiconductor chip 10. In this example, a memory integrated circuit
device such as a NAND flash memory is employed as the packaged
semiconductor device. In the example of FIG. 5, the bonding pads 13
of the semiconductor chip 10 are laterally opposed to those of the
chip shown in FIG. 4.
[0047] In the first embodiment, the number of bonding pads 13 is
eighteen. For example, external terminals VCC, VSS, I/O (I/O-0 to
I/O-7), RB, RE, CE, CLE, ALE, WE and WP are assigned to the bonding
pads. In particular, VSS is assigned to two bonding pads.
[0048] The bonding pad to which VCC is assigned is a VCC input pad
for applying a power supply potential (VCC). The bonding pads to
which VSS are assigned are VSS input pads for applying a ground
potential (VSS). The bonding pads to which I/O-0 to I/O-7 are
assigned are input pads for inputting/outputting an address, a
command and input/output data. The bonding pad to which RB is
assigned is an output pad for notifying an external device of the
internal operating status of the device. The bonding pad to which
RE is assigned is an output pad for outputting data serially. The
bonding pad to which CE is assigned is an input pad for receiving a
device selecting signal. The bonding pad to which CLE is assigned
is a pad for receiving a signal to control the transmission of an
operating command to a command register (not shown) in the device.
The bonding pad to which ALE is applied is a pad for receiving a
signal to control the transmission of address data and input data
to an address register and a data register (neither of which is
shown) in the device. The bonding pad to which WE is applied is a
pad for receiving a signal to control the transmission of data into
the device from an I/O terminal. The bonding pad to which WP is
applied is a pad for receiving a signal to forcibly inhibit data
from being written and erased.
Example 1 of Lead Frame
[0049] FIG. 6 specifically shows an example of a lead frame that is
applied to the packaged semiconductor device according to the first
embodiment of the present invention. In this example, a memory
integrated circuit device such as a NAND flash memory is employed
as the packaged semiconductor device. FIG. 6 shows a lead frame 11A
whose internal leads are laterally opposed to the internal leads
11a and 11b of the lead frame 11 in the first embodiment. In FIG.
6, VCC, VSS, I/O-0 to I/O-7, RB, RE, CE, CLE, ALE, WE and WP are
external terminals, and N.C is an unused (noncontact) internal
lead.
[0050] Referring to FIG. 6, the tips of longer internal leads 11b
are located locally close to the middle of the lead frame 11A in
its width direction, and the tips of shorter internal leads 11a are
located on both sides of a group of the longer internal leads 11b.
Since the shorter internal leads 11a are difficult to bend sharply
in terms of the manufacture of the lead frame 11A, it is favorable
that they should be formed outside the longer internal leads 11b as
described above. Since the longer internal leads 11b can be
extended with a high degree of freedom, they are located close to
the middle of the lead frame 11A.
[0051] The shorter internal leads 11a correspond to the external
terminals I/O-0 to I/O-7 for 8-bit data input/output and are
connected to their nearby pads by wire bonding.
[0052] In the lead frame 11A, the outermost leads, which are
broader than the internal leads 11a and 11b, are connected to the
hanging pin sections 11f and supported by the outside main body of
the frame.
Example 2 of Lead Frame
[0053] FIG. 7 specifically shows an example of a lead frame that is
applied to the packaged semiconductor device according to the first
embodiment of the present invention. In this example, a memory
integrated circuit device such as a NAND flash memory is employed
as the packaged semiconductor device. FIG. 7 shows a lead frame 11B
whose internal leads are laterally opposed to the internal leads
11a and 11b of the lead frame 11 in the first embodiment. In FIG.
7, VCC, VSS, I/O-0 to I/O-7, RB, RE, CE, CLE, ALE, WE and WP are
external terminals, and N.C is an unused (noncontact) internal
lead.
[0054] Referring to FIG. 7, in each of two sections into which the
lead frame 11B is divided in its width direction, the tips of
longer internal leads 11b are located locally close to the middle
of the section, and the tips of shorter internal leads 11a are
located on both sides of a group of the longer internal leads
11b.
[0055] The shorter internal leads 11a corresponding to the external
terminals I/O-0 to I/O-7 for 8-bit data input/output are remote
from the bonding pads 13 and connected to their nearby pads by wire
bonding.
[0056] In the lead frame 11B, the outermost leads, which are
broader than the internal leads 11a and 11b, are connected to the
hanging pin sections 11f and supported by the outside main body of
the frame.
[0057] In the lead frame 11 of the first embodiment, preferably,
the outermost leads are thickened and connected to the hanging pin
sections 11f on the sides of the frame, or the hanging pin sections
11f are connected to each other in the package, and the support
area of the chip 10 is increased when the chip 10 is to be mounted,
as shown in FIGS. 6 and 7. Thus, the tips of the internal leads 11b
are inhibited from being warped and the internal leads 11b can be
prevented from being deformed due to the weight of the chip 10, as
compared with the structure in which the chip 10 is supported by
only the internal leads 11b arranged along one side thereof.
Consequently, when the lead frame 11 is sealed with resin 15, the
moldability of the sealed frame 11 can be improved, and the
appearance of the device can be enhanced more than a device in
which the chip 10 is fixed by the internal leads 11b only.
[0058] FIG. 8 shows a specific layout of a semiconductor chip that
is applied to the packaged semiconductor device according to the
first embodiment of the present invention. In this semiconductor
chip, a NAND flash memory with pads along one side thereof is
integrated monolithically.
[0059] The semiconductor chip 10 shown in FIG. 8 has a layout for a
cell array 10a, a bit line selection circuit 10b, a sense amplifier
and latch circuit 10c, a column decoder 10d, a driver 10e, a row
decoder 10f, and a peripheral circuit 10g.
[0060] The cell array 10a includes a plurality of memory cells
arranged in matrix. The cell array 10a also includes a plurality of
word lines and selection gate lines that run in the row direction
of the matrix, a plurality of bit lines that run in the column
direction thereof, and a shield power supply (not shown) that
supplies potential to shield odd-numbered bit lines and
even-numbered bit lines.
[0061] The bit line selection circuit 10b is arranged adjacent to
the cell array 10a in the column direction. The sense amplifier and
latch circuit 10c and the column decoder 10d are arranged adjacent
to one side of the bit line selection circuit 10b, which does not
face the cell array 10a. The row decoder 10f is arranged adjacent
to the cell array 10a in the row direction. The driver 10e is
arranged close to the row decoder 10f in the column direction and
close to the bit line selection circuit 10b, sense amplifier and
latch circuit 10c and column decoder 10d in the row direction. The
peripheral circuit 10g is arranged close to the driver 10e and the
column decoder 10d in the column direction.
[0062] As described above, the driver 10e, which drives the bit
line selection circuit 10b, is integrated. The degree of
integration is thus improved and the device can be decreased in
size.
[0063] The sense amplifier and latch circuit 10c amplifies and
latches the data read out of a memory cell via a bit line.
[0064] When an odd-numbered bit line conducts to the sense
amplifier and latch circuit 10c, the bit line selection circuit 10b
conducts an even-numbered bit line to the shield power supply. When
an even-numbered bit line conducts to the sense amplifier and latch
circuit 10c, the bit line selection circuit 10b conducts an
odd-numbered bit line to the shield power supply. The bit line
selection circuit 10b has both a function of selecting a bit line
and connecting it to the sense amplifier and latch circuit 10c and
a function of connecting a non-selected bit line to the shield
power supply. As compared with the case of two different circuits
having these functions, the degree of integration can be improved
and the device can be decreased in size.
[0065] A read operation of the NAND flash memory will be described
in brief. The row decoder 10f selects one of blocks (not shown) of
the cell array 10a and one of word lines (not shown). The driver
10e applies a potential Vsg (e.g., 3.5V) to a select gate in the
selected block via the row decoder 10f and applies a ground
potential GND to a select gate in the non-selected block. In read
mode, the driver 10e applies a ground potential GND to the selected
word line via the row decoder 10f and applies a voltage Vs (e.g.,
3.5V) to the non-selected word line.
[0066] The column decoder 10d selects one of bit lines (not shown)
in response to a column address signal from an address buffer of
the peripheral circuit 10g. The sense amplifier and latch circuit
10c amplifies and latches the data that is received from the
selected bit line via the bit line selection circuit 10b. The data
is supplied from the sense amplifier and latch circuit 10c to an
I/O buffer of the peripheral circuit 10g via the column decoder
10d.
Second Embodiment
[0067] FIG. 9 shows a basic configuration of a semiconductor device
(packaged semiconductor device) having a TSOP structure according
to a second embodiment of the present invention. FIG. 9 is a plan
(top) view of the packaged semiconductor device to view the inside
thereof from the top surface thereof. The same components as those
of the packaged semiconductor device of the first embodiment are
denoted by the same reference numerals and their detailed
descriptions are omitted.
[0068] The second embodiment differs from the first embodiment in
that a hanging pin section 11f is not connected to the outermost
one of longer internal leads 11b, but adhered to the back surface
of a semiconductor chip 10.
[0069] In the second embodiment, too, when a lead frame is sealed
with resin 15, the moldability of the sealed frame can be
stabilized and thus the appearance of the semiconductor device can
be enhanced more than a device in which the chip 10 is fixed by the
internal leads 11b only.
[0070] When the packaged semiconductor device according to the
second embodiment is applied to, for example, a NAND flash memory,
the lead frames 11A and 11B shown in FIGS. 6 and 7 can be adopted,
except that the hanging pin sections are connected to the internal
leads.
Third Embodiment
[0071] FIG. 10 is a sectional view showing a configuration of a
semiconductor device (packaged semiconductor device) having a TSOP
structure according to a third embodiment of the present invention.
The packaged semiconductor device of the third embodiment differs
from that of the first embodiment in the following respect. As
shown in FIG. 10, the device includes two semiconductor chips 10
and 102 each having pads along one side thereof. The pads of the
chips 10 and 102 are of the same type and/or the same size and
close to each other. The chips 10 and 102 are horizontally
displaced from each other and stacked one on another with an
insulative adhesive 122 between them. Since the other components
are the same as those of the first embodiment, they are denoted by
the same reference numerals as those in FIG. 1.
[0072] In the semiconductor device shown in FIG. 10, the first chip
10 having first bonding pads (not shown but corresponding to the
bonding pads 13 shown in FIG. 4A) is mounted on a hanging pin
section (not shown) and a die lead section of longer internal leads
11b of a lead frame 11 with a thin organic insulation film 12 and a
normal mounting agent therebetween. The second chip 102 has the
same configuration as that of the first chip 10 and includes second
bonding pads (not shown) along one side thereof. The second bonding
pads of the second chip 102 are close to the first bonding pads of
the first chip 10. The second chip 102 is stacked on but displaced
from the first chip 10 with the insulative adhesive 122
therebetween.
[0073] The bonding wires of the third embodiment are divided into
four bonding wire groups 141 to 144. The first bonding wire group
141 is used to connect the tips of some of the internal leads 11a
on which the first chip 10 is not mounted to some of the first
bonding pads on the first chip 10.
[0074] The second bonding wire group 142 is used to connect the
tips of some of the internal leads 11a on which the first chip 10
is mounted to some of the first bonding pads on the first chip
10.
[0075] The third bonding wire group 143 is used to connect the tips
of some of the internal leads 11a on which the first chip 10 is not
mounted to some of the second bonding pads on the second chip
102.
[0076] The fourth bonding wire group 144 is used to connect the
tips of some of the internal leads 11a on which the first chip 10
is mounted to some of the second bonding pads on the second chip
102.
[0077] The resin 15 is used to seal the internal leads 11a and 11b,
hanging pin section, first and second chips 10 and 102 and bonding
wire groups 141 to 144 to thereby form a resin package.
[0078] External leads 11c and 11d (each of which is part of the
lead frame 11) communicate with their respective internal leads 11a
and 11b and protrude as external terminals from at least opposed
sides of the resin package.
[0079] The packaged semiconductor device shown in FIG. 10 has a CCL
structure and brings the same advantages as those of the first
embodiment. More specifically, the first chip 10 is adhesively
fixed to almost the middle portions of the longer internal leads
11b in their length direction, and the second chip 102 is
adhesively fixed onto the first chip 10 and horizontally displaced
therefrom. The bonding pads on the first and second chips 10 and
102 are connected to the tips of their nearby internal leads 11a
and 11b by bonding pads. No long bonding wires are therefore
required. Consequently, it is not likely that the bonding wires
will be dropped or adjacent bonding wires will be electrically
short-circuited when the lead frame is sealed with resin after the
wire-bonding step. Accordingly, the semiconductor device is
improved in reliability.
[0080] In particular, the hanging pin section of the lead frame 11
is fixed to the non-element-forming surface of the chip 10. When
the lead frame 11 is sealed with resin 15, the moldability of the
sealed frame 11 can be improved, and the appearance of the device
can be enhanced more than a device in which the chip 10 is fixed by
the internal leads 11b only.
[0081] Since the first chip 10 is fixed onto the internal leads 11b
by the organic insulation film 12, it is suitable for the TSOP
structure, and the difference in level between the top surface of
the chip and the internal leads 11a and 11b can be lessened to
facilitate wire bonding. Since, moreover, the chips are stacked one
on another, they can be mounted at high densities.
[0082] The present invention is not limited to the above first to
third embodiments. For example, a lead frame having a lead fixing
tape with an insulative adhesive can be adopted in order to prevent
the longer internal leads 11b from being relatively shifted from
each other or prevent the tips of the internal leads from
contacting each other.
Fourth Embodiment
[0083] FIGS. 11 and 12A and 12B show a basic configuration of a
semiconductor device (packaged semiconductor device) having a TSOP
structure according to a fourth embodiment of the present
invention. A memory integrated circuit device such as a NAND flash
memory is employed as the packaged semiconductor device. Of these
figures, FIG. 11 is a plan (top) view of the packaged semiconductor
device to view the inside thereof from the top thereof, FIG. 12A is
a sectional view of the tips of internal leads extending from
external leads of the packaged semiconductor device, and FIG. 12B
is a sectional view of a hanging pin section that is perpendicular
to the longitudinal direction of the external leads.
[0084] Referring to FIGS. 11 and 12A and 12B, a lead frame 211
includes a plurality of hanging pin sections 211f, a plurality of
external leads 211c which are drawn from the shorter sides of resin
215 of a package, and a plurality of internal leads 211 which are
extended into the package from the external leads 211c and some of
which are bent toward one of the longer sides of resin 215. The
internal leads 211a are longer in the middle of the resin 215 in
its longitudinal direction and become shorter with distance from
the middle. The internal leads connected to the external leads that
are far from one of the longer sides of resin 215 are longer, while
the internal leads connected to the external leads that are close
to the one of the longer sides of resin 215 are shorter.
[0085] The internal leads 211a excluding their tips are used as a
die lead section (chip mounting section) on which a semiconductor
chip 210 is mounted as a memory chip. The internal leads 211a are
not depressed but almost flush with each other. Since the lead
frame 211 is not depressed, there is no fear that a variation in
amount of depression will affect a device manufacturing process,
complicate a frame manufacturing step, or adversely affect frame
manufacturing yields.
[0086] In the fourth embodiment, the hanging pin sections 211f are
not connected any of the internal leads 211a or the semiconductor
chip (memory chip) 210.
[0087] The semiconductor chip 210 has bonding pads along one longer
side of the element forming surface thereof, as shown in FIG. 13. A
thin sheet-shaped organic insulation film 212 having a thickness of
about 20 .mu.m to 40 .mu.m is adhered to the back surface (element
non-forming surface) of the chip 210. The organic insulation film
212 is made of, e.g., polyimide epoxy resin. In the fourth
embodiment, too, the bonding pads are arranged locally along one of
the longer sides of the chip 210; therefore, the chip 210 can be
decreased in size.
[0088] As shown in FIGS. 12A and 12B, the chip 210 is mounted on
the die lead section of the internal leads 211a with the organic
insulation film 212 and a normal mounting agent therebetween. The
chip 210 is so provided that their bonding pads are arranged close
to the tips of the internal leads 211a. In other words, the longer
sides of the chip 210 correspond to the longer sides of the resin
215, and the bonding pads are arranged to face the tips of the
internal leads 211a.
[0089] The organic insulation film 212 is used to enhance the
insulativeness between the back surface of the chip 210 and the die
lead section. A film-shaped insulative adhesive, which is attached
to the back of a wafer, can be used as the organic insulation film
212 in a scribe (dicing) step of separating the chip 210 from the
wafer. There is a case where the organic insulation film 212 is not
used when a plurality of semiconductor chips are stacked one on
another.
[0090] The bonding pads of the semiconductor chip 210 are connected
to the internal leads 211a of the lead frame 211 by bonding wires
240, respectively.
[0091] The internal leads 211a, hanging pin sections 211f, chip 210
and bonding wires 240 of the lead frame 211 are sealed with the
resin 215 to form a rectangular resin package having a COL
structure. The resin package is so configured that the sealed
portion of the lead frame 211 on the chip-mounting surface (the
back of the packaged semiconductor device) is thicker than that on
the chip non-mounting surface (the surface of the packaged
semiconductor device). Thus, the chip 210 is sealed facedown in
almost the middle part of the resin package in its thickness
direction.
[0092] The portions communicating with the internal leads 211a
protrude from one of shorter sides of the resin package to form the
external leads 211c (parts of the lead frame 211). Furthermore, the
external leads 211c protrude from a position that is higher than
the middle of the resin package in its thickness direction. The
external leads 211c extend along the sides of the semiconductor
chip 210 and bend toward the chip mounting surface of the lead
frame 211. The tips of the external leads 211c bend away from the
resin package and serve as external terminals.
[0093] According to the packaged semiconductor device shown in
FIGS. 11, 12A and 12B, even though the longer side of the chip 210
along which the bonding pads are locally arranged cannot correspond
to the shorter side of the resin 215 from which the external leads
are protruded, the longer side of the chip 210 can correspond to
the longer side of the resin 215 to thereby package the
semiconductor device. A larger-sized semiconductor chip such as the
chip 210 can thus be incorporated into the resin package by simply
changing the design of the lead frame 211.
[0094] The bonding pads of the chip 210 are brought nearer to the
tips of the internal leads 211a, or wire bonding is performed on
one side of the chip 210 along which the bonding pads are arranged.
The bonding wires 240 need not be long. Consequently, it is not
likely that the bonding wires will be dropped or adjacent bonding
wires will be electrically short-circuited when the lead frame is
sealed with resin after the wire-bonding step. Accordingly, the
semiconductor device is improved in reliability.
[0095] The chip 210 is sealed facedown in the resin package. Even
though the resin package surface on the chip non-mounting surface
of the lead frame 211 is irradiated with laser beams for marking in
a device assembly step, the adverse effects of causing damage to
the chip 210 by laser beams transmitted through the resin 215 or
causing a disconnection by laser beams transmitted through the
bonding wires 240 can be lessened.
[0096] The packaged semiconductor device according to the fourth
embodiment is not limited to a NAND flash memory. If, however, it
is applied to a NAND flash memory, a lead frame 211' as shown in
FIG. 14 can be adopted.
Fifth Embodiment
[0097] FIG. 14 shows a basic configuration of a semiconductor
device (packaged semiconductor device) having a TSOP structure
according to a fifth embodiment of the present invention. FIG. 14
is a plan (top) view of the packaged semiconductor device to view
the inside thereof from the top surface thereof. The same
components as those of the packaged semiconductor device of the
fourth embodiment are denoted by the same reference numerals and
their detailed descriptions are omitted.
[0098] The fifth embodiment differs from the fourth embodiment in
the following respect. Some of hanging pin sections 211f are not
connected to internal leads 211a but adhered to the back surface of
a semiconductor chip 210, and/or some of hanging pin sections 211f
are used as some of internal leads 211a and adhered to the back
surface of the semiconductor chip 210.
[0099] According to the fifth embodiment, when a lead frame 211' is
sealed with resin 215, the moldability of the sealed frame can be
stabilized further. Since the hanging pin sections 211f of the lead
frame 211' are fixed to the element non-forming surface of the chip
210, the appearance of the semiconductor device can be enhanced
more than a device in which the chip 210 is fixed by the internal
leads 211a only.
Sixth Embodiment
[0100] FIGS. 15A and 15B show a basic configuration of a
semiconductor device (packaged semiconductor device) having a TSOP
structure according to a sixth embodiment of the present invention.
FIG. 15A is a sectional view of the tips of internal leads
extending from external leads of the packaged semiconductor device,
and FIG. 15B is a sectional view of a hanging pin section that is
perpendicular to the longitudinal direction of the external
leads.
[0101] The packaged semiconductor device of the sixth embodiment
differs from that of the fourth embodiment in the following
respect. As shown in FIGS. 15A and 15B, the device includes two
semiconductor chips 210a and 210b each having pads along one side
thereof. The pads of the chips 210a and 210b are of the same type
and/or the same size and close to each other. The chips 210a and
210b are horizontally displaced from each other and stacked one on
another with an insulative adhesive between them. Since the other
components are the same as those of the fourth embodiment, they are
denoted by the same reference numerals as those in FIG. 11.
[0102] In the semiconductor device shown in FIGS. 15A and 15B, the
first chip 210a having first bonding pads (not shown) is mounted on
a die lead section of internal leads 211a of a lead frame 211 with
a thin organic insulation film 12 and a normal mounting agent
therebetween. The second chip 210b has the same configuration as
that of the first chip 210a and includes second bonding pads along
one side thereof. The second bonding pads of the second chip 210b
are close to the first bonding pads of the first chip 210a. The
second chip 210b is stacked on but displaced from the first chip
210a with the insulative adhesive therebetween.
[0103] The bonding wires of the sixth embodiment are divided into
two bonding wire groups 241 and 242. The first bonding wire group
241 is used to connect the tips of some of the internal leads 211a
to some of the first bonding pads on the first chip 210a. The
second bonding wire group 242 is used to connect the tips of some
of the internal leads 211a to some of the second bonding pads on
the first chip 210b.
[0104] The internal leads 211a, hanging pin sections 211f, chips
210a and 210b and bonding wire groups 241 and 242 of the lead frame
211 are sealed with resin 215 to form a rectangular resin
package.
[0105] The external leads 211c (parts of the lead frame 211)
communicating with the internal leads 211a protrude from the
shorter sides of the resin package to form external terminals.
[0106] The packaged semiconductor device shown in FIGS. 15A and 15B
has a COL structure and brings almost the same advantage as that of
the device according to the fourth embodiment. In other words, a
large-sized semiconductor chip, such as chips 210a and 210b whose
longer sides are longer than the shorter sides of the resin package
(or shorter than the longer sides thereof), can be incorporate into
the resin package.
[0107] In particular, since the first chip 210a is fixed onto the
internal leads 211a by the thin organic insulation film, it is
suitable for the TSOP structure and the difference in level between
the top surface of the chip and the internal leads 211a can be
lessened to facilitate wire bonding.
[0108] Since the chips 210a and 210b are stacked one on another,
they can be mounted at high densities. Therefore, the sixth
embodiment is favorably applied to, for example, a NAND flash
memory as a large-capacity memory chip, which requires a low-cost
multilayer packaging technique.
[0109] The first chip 210a is adhesively fixed on the internal
leads 211a, and the second chip 210b is adhesively fixed onto but
horizontally displaced from the first chip 210a. The bonding pads
of these chips 210a and 210b are connected to their nearby tips of
the internal leads 211a. Thus, the bonding wires 241 and 242 need
not be long. Consequently, it is not likely that the bonding wires
will be dropped or adjacent bonding wires will be electrically
short-circuited when the lead frame is sealed with resin after the
wire-bonding step; accordingly, the semiconductor device is
improved in reliability.
[0110] When the hanging pin sections 211f of the lead frame 211'
are fixed on the element non-forming surface of the chip 210a (see
FIG. 14), the lead frame 211' is sealed with resin 215 and its
moldability can be stabilized further. The appearance of the
semiconductor device can be enhanced more than a device in which
the chip 210a is fixed by the internal leads 211a only.
[0111] The present invention is not limited to the above fourth to
sixth embodiments. For example, a lead frame having a lead fixing
tape with an insulative adhesive can be adopted in order to prevent
the internal leads 211a from being relatively shifted from each
other or prevent the tips of the internal leads from contacting
each other.
Seventh Embodiment
[0112] FIGS. 16 and 17 show a configuration of a semiconductor
device (packaged semiconductor device) having a TSOP structure
according to a seventh embodiment of the present invention. A
memory integrated circuit device such as a NAND flash memory is
employed as the packaged semiconductor device. Of these figures,
FIG. 16 is a plan (bottom) view of the packaged semiconductor
device to view the inside thereof from the bottom thereof, and FIG.
17 is a sectional view of the tips of internal leads extending from
external leads of the packaged semiconductor device.
[0113] Referring to FIGS. 16 and 17, a lead frame 311 includes a
plurality of hanging pin sections 311f, a plurality of external
leads 311c which are drawn from the shorter sides of resin 315 of a
package, and a plurality of internal leads 311a which are extended
into the package from the external leads 311c and some of which are
bent toward one of the longer sides of the resin 315. The internal
leads 311a are longer in the middle of the resin 315 in its
longitudinal direction and become shorter with distance from the
middle. The internal leads connected to the external leads that are
far from one of the longer sides of the resin 315 are longer, while
the internal leads connected to the external leads that are close
to the one of the longer sides of the resin 315 are shorter.
[0114] The internal leads 311a including their tips are used as a
die lead section (chip mounting section) on which a semiconductor
chip 310 is mounted as a memory chip. The internal leads 311a are
not depressed but almost flush with each other. Since the lead
frame 311 is not depressed, there is no fear that a variation in
amount of depression will affect a device manufacturing process,
complicate a frame manufacturing step, or adversely affect frame
manufacturing yields.
[0115] In the seventh embodiment, the hanging pin sections 311f are
not connected to any of the internal leads 311a, but some of the
hanging pin sections 311f are fixed onto the element forming
surface of the semiconductor chip 310.
[0116] The semiconductor chip 310 has bonding pads along one longer
side of the element forming surface thereof. A thin sheet-shaped
organic insulation film 312 having a thickness of about 20 .mu.m to
40 .mu.m is adhered to the same element forming surface of the chip
310. The organic insulation film 312 is made of, e.g., polyimide
epoxy resin. In the seventh embodiment, too, the bonding pads are
arranged locally along one of the longer sides of the chip 310;
therefore, the chip 310 can be decreased in size.
[0117] As shown in FIG. 16, the chip 310 is mounted on the die lead
section including the tips of the internal leads 311a of the lead
frame 311, with the organic insulation film 312 and a normal
mounting agent therebetween. The chip 310 is so provided that their
bonding pads are arranged close to the tips of the internal leads
311a. In other words, the longer sides of the chip 310 correspond
to the longer sides of the resin 315, and the bonding pads are
arranged close to the tips of the internal leads 311a. In
particular, the bonding pads of the semiconductor chip 310
correspond to extended portions of the tips of the internal leads
311a.
[0118] The bonding pads of the semiconductor chip 310 are connected
to the internal leads 311a of the lead frame 311 by bonding wires
340, respectively. In the seventh embodiment, the wire bonding, or
the bonding between the bonding pads and the tips of the internal
leads by the bonding wires 340 is performed on the element forming
surface of the semiconductor chip 310.
[0119] The internal leads 311a, hanging pin sections 311f, chip 310
and bonding wires 340 of the lead frame 311 are sealed with the
resin 315 to form a rectangular resin package having a lead on chip
(LOG) structure. The resin package is so configured that the sealed
portion of the lead frame 311 on the chip non-mounting surface (the
back of the packaged semiconductor device) is thicker than that on
the chip mounting surface (the surface of the packaged
semiconductor device). Thus, the chip 310 is sealed facedown
slightly above almost the middle part of the resin package in its
thickness direction.
[0120] The portions communicating with the internal leads 311a
protrude from one of shorter sides of the resin package to form the
external leads 311c (parts of the lead frame 311). Furthermore, the
external leads 311c protrude from a position that is slightly
displaced downward from the middle of the resin package in its
thickness direction. The external leads 311c extend along the sides
of the semiconductor chip 310 and bend toward the chip non-mounting
surface of the lead frame 311. The tips of the external leads 311c
bend away from the resin package and serve as external
terminals.
[0121] According to the packaged semiconductor device shown in
FIGS. 16 and 17, even though the longer side of the chip 310 along
which the bonding pads are locally arranged cannot correspond to
the shorter side of the resin 315 from which the external leads are
protruded, the longer side of the chip 310 can correspond to the
longer side of the resin 315 to thereby package the semiconductor
device. A larger-sized semiconductor chip such as the chip 310 can
thus be incorporated into the resin package by simply changing the
design of the lead frame 311.
[0122] In particular, when the wire bonding for bonding the bonding
pads and the internal leads 311a is performed on the surface
(element forming surface) of the semiconductor chip 310, a
larger-sized semiconductor chip can be mounted on the packaged
semiconductor device of the same size. Conversely, a smaller-sized
packaged semiconductor device can be achieved if the size of the
chip 310 is unchanged.
[0123] Moreover, when the hanging pin sections 311f of the lead
frame 311 are fixed on the element forming surface of the chip 310,
the moldability of the frame sealed with the resin 315 can be
stabilized, and the appearance of the device can be improved more
than a device in which the chip 310 is fixed by the internal leads
311a only.
[0124] The bonding pads of the chip 310 are brought nearer to the
tips of the internal leads 311a, or wire bonding is performed on
one side of the chip 310 along which the bonding pads are arranged.
The bonding wires 340 need not be long. Consequently, it is not
likely that the bonding wires will be dropped or adjacent bonding
wires will be electrically short-circuited when the lead frame is
sealed with resin after the wire-bonding step. Accordingly, the
semiconductor device is improved in reliability.
[0125] The chip 310 is sealed facedown in the resin package. Even
though the resin package surface on the chip mounting surface of
the lead frame 311 is irradiated with laser beams for marking in a
device assembly step, the adverse effects of causing damage to the
chip 310 by laser beams transmitted through the resin 315 or
causing a disconnection by laser beams transmitted through the
bonding wires 340 can be lessened.
[0126] FIGS. 18A and 18B are sectional views of an end portion of
the packaged semiconductor device, which is taken along the line
perpendicular to the projection direction of the external lead.
FIG. 18A shows the packaged semiconductor device shown in FIG. 16
as an example, and FIG. 18B shows the packaged semiconductor device
shown in FIG. 11 as an example.
[0127] If the length of a short side of the packaged semiconductor
device shown in FIG. 18A is Xa, Xa is defined by xa+2.times.ha
where xa is the length of a short side of the chip 310 and ha is
the width of resin. In contrast, if the length of a short side of
the packaged semiconductor device shown in FIG. 18B is Xa, Xa is
defined by xa+2.times.ha+k where xa is the length of a short side
of the chip 210, ha is the width of resin, and k is the length of a
lead projection. The width ha of resin corresponds to the thickness
of resin 315 from one end of the resin package to the chip 310 and
the thickness of resin 215 from one end of the resin package to the
tip of the lead 211a.
[0128] In short, when Xa and ha are the same, the semiconductor
chip 310 which is larger than the semiconductor chip 210 by the
length k of the lead projection can be mounted. In contrast, xa in
the chip 210 and xa in the chip 310 are the same, a packaged
semiconductor device of smaller size (Xa) can be achieved.
[0129] None of the above embodiments are limited to a configuration
in which a semiconductor chip is sealed facedown in a resin
package. The embodiments can be applied to a configuration in which
a semiconductor chip is sealed face up in a resin package.
Eighth Embodiment
[0130] FIG. 19 shows a configuration of a semiconductor device
(packaged semiconductor device) having a TSOP structure according
to an eighth embodiment of the present invention. FIG. 19 is a
sectional view of the tips of internal leads extending from
external leads of the packaged semiconductor device. The top view
of the packaged semiconductor device is almost equivalent to the
bottom view of FIG. 16.
[0131] The eighth embodiment differs from the seventh embodiment in
that a semiconductor chip mounted on a lead frame is sealed face up
in a resin package. More specifically, the packaged semiconductor
device shown in FIG. 19 differs from that of the seventh embodiment
in the following respect. The external leads 311c of a lead frame
311 extend along the sides of the semiconductor chip 310 and bend
toward the chip mounting surface of the lead frame 311. The tips of
the external leads 311c bend away from the resin package and serve
as external terminals. Since the other components are the same as
those of the seventh embodiment, they are denoted by the same
reference numerals as those in FIG. 17.
[0132] The semiconductor chip 310 has bonding pads on its one side.
Referring to FIG. 19, the chip 310 is mounted on a die lead section
of internal leads 311a of the lead frame 311, with a thin organic
insulation film 312 and a normal mount agent interposed
therebetween.
[0133] Bonding wires 340 are formed on the surface (element forming
surface) of the chip 310 to bond the tips of the internal leads
311a and the bonding pads on the chip 310.
[0134] The internal leads 311a, hanging pin sections (not shown),
chip 310 and bonding wires 340 are sealed with resin 315 to form a
rectangular resin package.
[0135] The external leads 311c (parts of the lead frame 311) are
connected to the internal leads 311a and protruded from a pair of
short sides of the resin package. The external leads 311c thus
serve as external terminals.
[0136] According to the semiconductor package device shown in FIG.
19, a large-sized semiconductor chip whose long sides are longer
than the short sides of the resin package (shorter than the long
sides of the resin package) can be mounted in the resin package, as
in the foregoing seventh embodiment.
[0137] In particular, when the wire bonding for bonding the bonding
pads and the internal leads 311a is performed on the surface
(element forming surface) of the semiconductor chip 310, a
larger-sized semiconductor chip can be mounted on the packaged
semiconductor device of the same size. Conversely, a smaller-sized
packaged semiconductor device can be achieved if the size of the
chip 310 is unchanged.
[0138] Moreover, when the hanging pin sections of the lead frame
311 are fixed on the element forming surface of the chip 310, the
moldability of the frame sealed with the resin 315 can be
stabilized, and the appearance of the device can be improved more
than a device in which the chip 310 is fixed by the internal leads
311a only.
[0139] The bonding wires 340 need not be long; consequently, it is
not likely that the bonding wires will be dropped and adjacent
bonding wires will be electrically short-circuited when the lead
frame is sealed with resin after the wire-bonding step.
Accordingly, the semiconductor device is improved in
reliability.
[0140] Since the chip 310 is fixed on the internal leads 311a by
the thin organic insulation film 312, it is suitable for the TSOP
structure. A difference between the level of the top of the chip
and that of the internal leads 311a can be lessened to facilitate a
wire bonding process.
[0141] None of the above embodiments are limited to a product using
a resin package, but they can be applied to, for example, a
packaged plastic product.
[0142] Additional advantages and modifications will readily occur
to those skilled in the art. Therefore, the invention in its
broader aspects is not limited to the specific details and
representative embodiments shown and described herein. Accordingly,
various modifications may be made without departing from the spirit
or scope of the general inventive concept as defined by the
appended claims and their equivalents.
* * * * *