U.S. patent application number 16/941509 was filed with the patent office on 2022-02-03 for an adhesive and thermal interface material on a plurality of dies covered by a lid.
This patent application is currently assigned to Taiwan Semiconductor Manufacturing Co., Ltd.. The applicant listed for this patent is Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Chih-Hao Chen, Li-Hui Cheng, Chin-Fu Kao, Szu-Wei Lu, Chih-Chien Pan.
Application Number | 20220037229 16/941509 |
Document ID | / |
Family ID | 1000006090823 |
Filed Date | 2022-02-03 |
United States Patent
Application |
20220037229 |
Kind Code |
A1 |
Chen; Chih-Hao ; et
al. |
February 3, 2022 |
AN ADHESIVE AND THERMAL INTERFACE MATERIAL ON A PLURALITY OF DIES
COVERED BY A LID
Abstract
Provided are a package structure and a method of forming the
same. The package structure includes a first die, a second die, an
interposer, an underfill layer, a thermal interface material (TIM),
and an adhesive pattern. The first die and the second die are
disposed side by side on the interposer. The underfill layer is
disposed between the first die and the second die. The TIM is
disposed on the first die, the second die, and the underfill layer.
The adhesive pattern is disposed between the underfill layer and
the TIM to separate the underfill layer from the TIM.
Inventors: |
Chen; Chih-Hao; (Taipei
City, TW) ; Kao; Chin-Fu; (Taipei City, TW) ;
Cheng; Li-Hui; (New Taipei City, TW) ; Lu;
Szu-Wei; (Hsinchu City, TW) ; Pan; Chih-Chien;
(Taipei City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Hsinchu |
|
TW |
|
|
Assignee: |
Taiwan Semiconductor Manufacturing
Co., Ltd.
Hsinchu
TW
|
Family ID: |
1000006090823 |
Appl. No.: |
16/941509 |
Filed: |
July 28, 2020 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 24/29 20130101;
H01L 27/0688 20130101; H01L 2224/2958 20130101; H01L 24/27
20130101; H01L 23/3185 20130101; H01L 23/42 20130101; H01L 21/565
20130101 |
International
Class: |
H01L 23/42 20060101
H01L023/42; H01L 27/06 20060101 H01L027/06; H01L 23/31 20060101
H01L023/31; H01L 23/00 20060101 H01L023/00; H01L 21/56 20060101
H01L021/56 |
Claims
1. A package structure, comprising: a first die and a second die
group, disposed side by side on an interposer; an underfill layer,
disposed between the first die and the second die group; a thermal
interface material (TIM), disposed on the first die, the second die
group, and the underfill layer; an adhesive pattern, disposed
between the underfill layer and the TIM to separate the underfill
layer from the TIM; and an encapsulant laterally encapsulating the
first die, the second die group, and the underfill layer, wherein a
sidewall of the encapsulant is substantially aligned with a
sidewall of the interposer.
2. The package structure of claim 1, wherein the second die group
comprises at least one second die or a plurality of second dies,
the plurality of second dies are respectively disposed at both
sides of the first die, and the adhesive pattern comprises a
plurality of adhesive layers discretely distributed on the
underfill layer between the first die and the plurality of second
dies.
3. The package structure of claim 2, wherein a portion of the
plurality of adhesive layers is disposed between the encapsulant
and the TIM to separate the encapsulant from the TIM.
4. (canceled)
5. The package structure of claim 2, wherein one of the plurality
of adhesive layers has a curved top surface and has a thickness
decreasing along a direction from center to edge.
6. The package structure of claim 1, wherein the adhesive pattern
extends from a top surface of the underfill layer to cover a
portion of a top surface of the first die and a portion of a top
surface of the second die group.
7. The package structure of claim 1, wherein a first interface is
formed between the adhesive pattern and the TIM, and a second
interface is formed between the adhesive pattern and the underfill
layer.
8. The package structure of claim 1, wherein the TIM has a
plurality of fillers, and the adhesive pattern is free of
fillers.
9. The package structure of claim 1, wherein the adhesive pattern
comprises a first metal layer extending to cover the first die and
the second die group.
10. The package structure of claim 9, further comprising: a circuit
substrate, bonded to the interposer; a lid, adhered to the circuit
substrate, the first die, and the second die group, the lid
covering and surrounding the first die and the second die group;
and a second metal layer, disposed between the TIM and the lid,
wherein a composite structure including the TIM, the first metal
layer, and the second metal layer thermally couples the lid and the
first die and the second die group.
11. The package structure of claim 10, wherein the first metal
layer and the second metal layer are both electrically
floating.
12. The package structure of claim 1, wherein the TIM has an edge
thickness greater than a center thickness of the TIM.
13. The package structure of claim 1, wherein the TIM has a thermal
conductivity greater than a thermal conductivity of the adhesive
pattern.
14. A package structure, comprising: a first die and a second die,
disposed side by side on an interposer; an underfill layer,
disposed between the first die and the second die; a thermal
interface material (TIM), disposed on the first die, the second
die, and the underfill layer, wherein the TIM has an edge thickness
greater than a center thickness of the TIM; and a lid, adhered to
the TIM, wherein the TIM has a first concave top surface, the lid
conformally covers the first concave top surface of the TIM, and
the lid has a second concave top surface corresponding to the first
concave top surface.
15. The package structure of claim 14, further comprising: a
circuit substrate, bonded to the interposer; a passive device,
bonded to the circuit substrate; and the lid, further adhered to
the circuit substrate, the lid covering and surrounding the passive
device, the first die, and the second die.
16. (canceled)
17. A method of forming a package structure, comprising: bonding a
first die and a second die onto an interposer; dispensing an
underfill layer between the first die and the second die; forming a
first encapsulant to laterally encapsulate the first die, the
second die, and the underfill layer; forming an adhesive pattern on
the underfill layer between the first die and the second die and on
the first encapsulant; and dispensing a thermal interface material
(TIM) on the adhesive pattern, wherein a sidewall of the first
encapsulant is substantially aligned with a sidewall of the
interposer.
18. The method of claim 17, wherein the forming the adhesive
pattern comprises: forming a first metal layer extending to cover
the first die and the second die.
19. The method of claim 18, further comprising: forming a second
metal layer on the TIM, so that the first metal layer, the TIM, and
the second metal layer form as a composite structure; bonding the
interposer onto a circuit substrate; and adhering a lid onto the
circuit substrate and the composite structure, wherein the
composite structure thermally couples the lid with the first die
and the second die.
20. The method of claim 17, wherein the adhesive pattern is formed
to have a plurality of adhesive layers laterally spaced from each
other in a cross-sectional view.
21. The method of claim 17, further comprising: bonding the
interposer onto a circuit substrate; and adhering a lid onto the
circuit substrate, the first die, and the second die, wherein the
lid covers and surrounds the first die and the second die.
22. The method of claim 21, further comprising: forming a second
encapsulant on the circuit substrate to laterally encapsulate the
first encapsulant and the interposer.
Description
BACKGROUND
[0001] In the packaging of integrated circuits, semiconductor dies
may be stacked through bonding, and may be bonded to other package
components such as interposers and package substrates. The
resulting packages are known as Three-Dimensional Integrated
Circuits (3DICs). Heat dissipation is a challenge in the 3DICs.
[0002] In a typical 3DIC, a heat spreader is adhered to the
semiconductor dies to dissipate the heat generated from the
semiconductor dies. However, there exist encapsulating materials
such as underfill, molding compound, and the like, which have a
poor adhesion with the heat spreader, thereby resulting in a
delamination issue between the heat spreader and the encapsulating
materials. As a result, there are quite a few challenges to be
handled for the 3DIC technology.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIG. 1A to FIG. 1C are cross-sectional views of a method of
forming a package structure in accordance with a first
embodiment.
[0005] FIG. 2 is a top view of the package structure illustrated in
FIG. 1C.
[0006] FIG. 3A and FIG. 3B are enlarged views of a portion of the
package structure illustrated in FIG. 1C.
[0007] FIG. 4A to FIG. 4C are cross-sectional views of a method of
forming a package structure in accordance with a second
embodiment.
[0008] FIG. 5A to FIG. 5D are cross-sectional views of a method of
forming a package structure in accordance with a third
embodiment.
[0009] FIG. 6 is a cross-sectional view of a package structure in
accordance with a fourth embodiment.
DETAILED DESCRIPTION
[0010] The following disclosure provides many different
embodiments, or examples, for implementing different features of
the provided subject matter. Specific examples of components and
arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the purpose of simplicity and clarity and does
not in itself dictate a relationship between the various
embodiments and/or configurations discussed.
[0011] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0012] Other features and processes may also be included. For
example, testing structures may be included to aid in the
verification testing of the 3D packaging or 3DIC devices. The
testing structures may include, for example, test pads formed in a
redistribution layer or on a substrate that allows the testing of
the 3D packaging or 3DIC, the use of probes and/or probe cards, and
the like. The verification testing may be performed on intermediate
structures as well as the final structure. Additionally, the
structures and methods disclosed herein may be used in conjunction
with testing methodologies that incorporate intermediate
verification of known good dies to increase the yield and decrease
costs.
[0013] In accordance with some embodiments, a plurality of adhesive
layers are dispensed selectively on an underfill layer between a
first die and a plurality of second dies and on an encapsulant
aside the first die and the second dies. A thermal interface
material (TIM) is then formed on the first die, the second dies,
and the adhesive layers, so that the adhesive layers are wrapped by
the TIM. In the case, the adhesive layers separate the TIM from the
underfill layer and the encapsulant, so as to improve an adhesion
between the TIM and the underfill layer and the encapsulant,
thereby decreasing the delamination issue and increasing the
reliability.
[0014] FIG. 1A to FIG. 1C are cross-sectional views of a method of
forming a package structure in accordance with a first embodiment.
FIG. 2 is a top view of the package structure illustrated in FIG.
1C.
[0015] Referring to FIG. 1A to FIG. 1C, a method of forming a
package structure 10 (as shown in FIG. 1C) includes following
steps. First, an initial structure 10a illustrated in FIG. 1A is
provided. The initial structure 10a includes a package 100 bonded
on a circuit substrate 200 to form a chip-on-wafer-on-substrate
(CoWoS) package, although it should be appreciated that embodiments
may be applied to other 3DIC packages.
[0016] In detail, the package 100 may include a first die 110, a
second die group having a plurality of second dies 120, an
underfill layer 115, a first encapsulant 125, and an interposer
130. Specifically, the first die 110 has a front-side 110a (i.e.,
an active surface) and a back-side 110b (i.e., a non-active
surface) opposite to each other. Each second die 120 also has a
front-side 120a (i.e., an active surface) and a back-side 120b
(i.e., a non-active surface) opposite to each other. The first die
110 and the second dies 120 are flipped, so that the front-side
110a of the first die 110 and the front-sides 120a of the second
dies 120 all face toward an upper surface 130a of the interposer
130. The first die 110 and the second dies 120 are bonded onto the
upper surface 130a of the interposer 130 by a plurality of die
connectors 112, 122, so as to form a chip-on-wafer (CoW) package,
although it should be appreciated that embodiments may be applied
to other 3DIC packages.
[0017] In some embodiments, the first die 110 and the second dies
120 each has a single function (e.g., a logic device, memory die,
etc.), or may have multiple functions (e.g., a SoC). In a
particular embodiment, the first die 110 is a processor and the
second dies 120 are memory modules. In some alternative
embodiments, the first die 110 is referred to as a die stack, which
includes two bonded integrated circuit dies. The two integrated
circuit dies are bonded such that the active surfaces are facing
each other ("face-to-face") by hybrid bonding, fusion bonding,
direct bonding, dielectric bonding, metal bonding, or the like. In
other embodiments, the first die 110 is a processor, such as a
central processing unit (CPU), graphics processing unit (GPU),
application-specific integrated circuit (ASIC), or the like. In a
specific embodiment, the first die 110 is a system-on-chip
(SoC).
[0018] In some embodiments, the second dies 120 are memory devices,
such as dynamic random access memory (DRAM) dies, static random
access memory (SRAM) dies, hybrid memory cube (HMC) modules, high
bandwidth memory (HBM) modules, or the like. In a specific
embodiment, the second dies 120 is HBM modules.
[0019] As shown in FIG. 1A, in some embodiments, the die connectors
112, 122 is formed from a conductive material, such as solder,
copper, aluminum, gold, nickel, silver, palladium, tin, the like,
or a combination thereof. In a specific embodiment, the die
connectors 112, 122 are micro bumps including a solder sandwiched
between two metal layers. In addition, a redistribution layer (RDL)
structure 134 is optionally disposed between the die connectors
112, 122 and the upper surface 130a of the interposer 130 to
electrically connect the die connectors 112, 122 and trough
substrate vias (TSVs) 132 in the interposers 130. In some
embodiments, the RDL structure 134 includes a plurality of polymer
layers and a plurality of redistribution layers stacked
alternately. The redistribution layers may be formed in the polymer
layers to electrically connect the die connectors 112, 122 and the
TSVs 132. The redistribution layers respectively include a
plurality of vias and a plurality of traces connected to each
other. In the case, a shown in FIG. 1A, the first die 110 and the
second dies 120 may be electrically connected to the TSVs 132 in
the interposer 130 by the die connectors 112, 122 and RDL structure
134.
[0020] As shown in FIG. 1A, the underfill layer 115 is disposed
between the first die 110 and the second dies 120 and laterally
encapsulates the die connectors 112, 122. In some embodiments, the
underfill layer 115 is formed from any acceptable material, such as
a polymer, epoxy, molding underfill, or the like. The underfill
layer 115 may be formed by a capillary flow process after the first
die 110 and the second dies 120 are attached or may be formed by a
suitable deposition method before the first die 110 and the second
dies 120 are attached.
[0021] The first encapsulant 125 is disposed to laterally
encapsulate the underfill layer 115 and the second dies 120. In
some embodiments, the first encapsulant 125 is formed from any
acceptable material, such as a molding compound, epoxy, or the
like. The first encapsulant 125 may be formed by compression
molding, transfer molding, or the like. In some other embodiments,
the first encapsulant 125 have fillers with average particle size
greater than or equal to fillers of the underfill layer 115. The
first encapsulant 125 may be formed over the interposer 130, such
that the first die 110 and the second dies 120 are buried or
covered. The first encapsulant 125 is then cured and planarized to
expose the back-side 110b (top surface 110t) of the first die 110
and the back-sides 120b (top surfaces 120t) of the second dies 120
by a chemical mechanical polishing (CMP) process, a grinding
process, or the like. After the planarization, as shown in FIG. 1A,
a top surface 125t of the first encapsulant 125, the top surface
110t of the first and second die 110, the top surfaces 120t of the
second dies 120, and a top surface 115t of the underfill layer 115
are substantial level or coplanar.
[0022] In some embodiments, the package 100 is formed by performing
a singulation process on a wafer including a plurality of first and
second dies 110 and 120, the underfill layer 115, and the first
encapsulant 125 thereon. As a result of the singulation process,
the wafer is singulated into a plurality of interposers 130, with
each of the packages 100 having one interposer 130. In some
embodiments, the singulation process includes a sawing process, a
laser process, or a combination thereof. In the case, as shown in
FIG. 1A, edges of the first encapsulant 125 and interposer 130 are
coterminous, namely, a sidewall 125s of the first encapsulant 125
is substantially aligned with a sidewall 130s of the interposer
130.
[0023] After the singulation process, the CoW package 100 is bonded
onto the circuit substrate 200 by a plurality of conductive
connectors 136. In some embodiments, the conductive connectors 136
are electrically and/or physically connected to the circuit
substrate 200. The conductive connectors 136 may be BGA connectors,
solder balls, metal pillars, controlled collapse chip connection
(C4) bumps, micro bumps, electroless nickel-electroless
palladium-immersion gold technique (ENEPIG) formed bumps, or the
like. In some embodiments, the conductive connectors 136 are formed
by initially forming a layer of solder through such commonly used
methods such as evaporation, electroplating, printing, solder
transfer, ball placement, or the like. Once a layer of solder has
been formed on the structure, a reflow may be performed in order to
shape the material into the desired bump shapes.
[0024] In some embodiments, the circuit substrate 200 is made of a
semiconductor material, such as silicon, germanium, diamond, or the
like. Alternatively, compound materials such as silicon germanium,
silicon carbide, gallium arsenic, indium arsenide, indium
phosphide, silicon germanium carbide, gallium arsenic phosphide,
gallium indium phosphide, combinations of these, and the like, may
also be used. Additionally, the circuit substrate 200 may be a SOI
substrate. Generally, an SOI substrate includes a layer of a
semiconductor material such as epitaxial silicon, germanium,
silicon germanium, SOI, SGOI, or combinations thereof. The circuit
substrate 200 is, in one alternative embodiment, based on an
insulating core such as a fiberglass reinforced resin core. One
example core material is fiberglass resin such as FR4. Alternatives
for the core material include bismaleimide-triazine BT resin, or
alternatively, other PCB materials or films. Build up films such as
ABF or other laminates may be used for circuit substrate 200.
[0025] The circuit substrate 200 may include active and passive
devices (not shown), such as transistors, capacitors, resistors,
combinations of these, and the like may be used to generate the
structural and functional requirements of the design. The circuit
substrate 200 may also include metallization layers and vias (not
shown) and bond pads 202 over the metallization layers and vias.
The metallization layers may be formed over the active and passive
devices and are designed to connect the various devices to form
functional circuitry. The metallization layers may be formed of
alternating layers of dielectric (e.g., low-k dielectric material)
and conductive material (e.g., copper) with vias interconnecting
the layers of conductive material and may be formed through any
suitable process (such as deposition, damascene, dual damascene, or
the like). In some other embodiments, the circuit substrate 200 is
substantially free of active and passive devices.
[0026] In some embodiments, the conductive connectors 136 are
attached onto the bond pads 202, thereby bonding the interposer 130
to the circuit substrate 200. The conductive connectors 136 are
electrically and/or physically connected the circuit substrate 200
to the package 100. In some embodiments, a plurality of passive
devices 140 (e.g., surface mount devices (SMDs)) is attached to the
circuit substrate 200 (e.g., bonded to the bond pads 202). In such
embodiment, the passive devices 140 are bonded to a same surface of
the circuit substrate 200 as the conductive connectors 136. The
conductive connectors 136 may have an epoxy flux (not shown) formed
thereon before they are reflowed with at least some of the epoxy
portion of the epoxy flux remaining after the package 100 is
attached to the circuit substrate 200. This remaining epoxy portion
may act as an underfill to reduce stress and protect the joints
resulting from the reflowing the conductive connectors 136.
[0027] As shown in FIG. 1A, a second encapsulant 135 is formed to
laterally encapsulate the conductive connectors 136, the interposer
130, a lower sidewall of the first encapsulant 125. In one
embodiment, the second encapsulant 135 is formed from any suitable
underfill material, such as a polymer, epoxy, molding underfill, or
the like. The second encapsulant 135 may be formed by a capillary
flow process after the package 100 is attached or may be formed by
a suitable deposition method before the package 100 is
attached.
[0028] Referring to FIG. 1B, an adhesive pattern 150 is selectively
dispensed on the underfill layer 115 between the first die 110 and
the second dies 120 and on the first encapsulant 125 by a dispenser
152. In some embodiments, the adhesive pattern 150 includes a
polymer material, such as a liquid die attaching film (DAF), a
polyimide (PI) based polymer, an epoxy based polymer, or the like.
In some alternative embodiments, the adhesive pattern 150 is free
of fillers.
[0029] Referring to FIG. 1B and FIG. 1C, a thermal interface
material (TIM) 160 is dispensed on the first die 110, the second
dies 120, and the adhesive pattern 150. A lid 170 is then attached
to the package 100 and circuit substrate 200 to form the package
structure 10. As shown in FIG. 1C, the lid 170 covers and surrounds
the package 100 and the passive devices 140. In some embodiments,
the lid 170 is formed from a material with high thermal
conductivity (k), such as steel, stainless steel, copper, the like,
or combinations thereof. In some alternative embodiments (discussed
below), the lid 170 is coated with another metal, such as gold,
nickel, or the like. In some other embodiments, the lid 170 is a
single contiguous material. In another embodiment, the lid 170
includes multiple pieces that may be the same or different
materials.
[0030] Specifically, the lid 170 is adhered to the package 100 by
the TIM 160. The TIM 160 is sandwiched between the lid 170 and the
first and second dies 110, 120, so as to thermally couple the lid
170 and the first and second dies 110, 120. In addition, the TIM
160 is formed to a thickness sufficiently large to bury the
adhesive pattern 150. That is, as shown in FIG. 1C, the adhesive
pattern 150 may be surrounded or wrapped by the TIM 160. In some
embodiments, the adhesive pattern 150 is formed to a height of
about 0.5 .mu.m to 100 .mu.m, such as about 10 .mu.m. The TIM 160
may be formed to a thickness of from about 5 .mu.m to about 300
.mu.m, such as about 60 .mu.m. The thickness of the TIM is greater
than the height or thickness of the adhesive pattern 150. On the
other hands, the lid 170 is adhered to the circuit substrate 200 by
an adhesive 172. In some embodiments, the adhesive 172 is epoxy,
glue, or the like. Alternatively, the adhesive 172 may be a
thermally conductive material.
[0031] In some embodiments, the first die 110 and the second dies
120 may trap heat to become hot spots in the package structure 10.
Therefore, the TIM 160 thermally couples the package 100 and lid
170 to dissipate the heat from the first and second dies 110, 120
to the lid 170. It should be noted that the adhesive pattern 150
may be disposed between the TIM 160 and the underfill layer 115
and/or the first encapsulant 125 to improve the adhesion between
the TIM 160 and the underfill layer 115 and/or the first
encapsulant 125, thereby decreasing the delamination issue and
increasing the reliability. From the cross-sectional view of FIG.
1C, the adhesive pattern 150 may include a plurality of adhesive
layers laterally spaced from each other. That is, the adhesive
layers are discretely distributed on the underfill layer 115
between the first and second dies 110 and 120 and on the first
encapsulant 125. The adhesive pattern 150 separates the TIM 160 and
the underfill layer 115 and/or the first encapsulant 125, so that
the TIM 160 is not in (physical) contact with the underfill layer
115 and/or the first encapsulant 125.
[0032] In some embodiments, the TIM 160 and the adhesive pattern
150 have different materials. The TIM 160 may have a thermal
conductivity (k) greater than a thermal conductivity of the
adhesive pattern 150. In the case, an area of the TIM 160
contacting the top surfaces 110t, 120t of the first and second dies
110, 120 may be referred to as a thermal path for dissipating the
heat from the first and second dies 110, 120. In some embodiments,
the TIM 160 is formed from a material with higher thermal
conductivity (k), such as Ag, Cu, Sn, In, carbon nanotube (CNT),
graphite, or the like. The adhesive pattern 150 may be formed from
a material with lower thermal conductivity (k), such as a liquid
die attaching film (DAF), a polyimide (PI) based polymer, an epoxy
based polymer, or the like. In some embodiments, the thermal
conductivity (k) of the TIM 160 is from about 0.5 Wm.sup.-1K.sup.-1
to about 200 Wm.sup.-1K.sup.-1, or from about 10 Wm.sup.-1K.sup.-1
to about 50 Wm.sup.-1K.sup.-1, such as about 10 Wm.sup.-1K.sup.-1.
The thermal conductivity (k) of the adhesive pattern 150 may be
from about 0.5 Wm.sup.-1K.sup.-1 to about 100 Wm.sup.-1K.sup.-1, or
from about 0.5 Wm.sup.-1K.sup.-1 to about 10 Wm.sup.-1K.sup.-1,
such as about 2 Wm.sup.-1K.sup.-1.
[0033] In some alternative embodiments, the TIM 160 is formed from
another material, such as a polymer material, solder paste, indium
solder paste, or the like. In some alternative embodiments, the
thermal conductivity (k) of the TIM 160 is from about 0.5
Wm.sup.-1K.sup.-1 to about 200 Wm.sup.-1K.sup.-1, or from about 10
Wm.sup.-1K.sup.-1 to about 50 Wm.sup.-1K.sup.-1, such as about 10
Wm.sup.-1K.sup.-1.
[0034] In some embodiments, since the adhesive pattern 150 and the
TIM 160 have different materials, a first interface S1 is included
between the adhesive pattern 150 and the TIM 160. In some other
embodiments, the TIM 160 has a plurality of fillers, while the
adhesive pattern 150 is free of fillers. Accordingly, the fillers
in the TIM 160 may surround an upper surface of the adhesive
pattern 150 to form the first interface S1.
[0035] Similarly, the adhesive pattern 150 and the underfill layer
115 may have different materials, thus a second interface S2 is
included between the adhesive pattern 150 and the underfill layer
115. In some other embodiments, the underfill layer 115 has a
plurality of fillers, while the adhesive pattern 150 is free of
fillers. Accordingly, the fillers in the underfill layer 115 may
surround a lower surface of the adhesive pattern 150 to form the
second interface S2. In addition, the adhesive pattern 150 and the
first encapsulant 125 have different materials, thus a third
interface S3 is included between the adhesive pattern 150 and the
first encapsulant 125. In some other embodiments, the first
encapsulant 125 has a plurality of fillers, while the adhesive
pattern 150 is free of fillers. Accordingly, the fillers in the
first encapsulant 125 may surround a lower surface of the adhesive
pattern 150 to form the third interface S3.
[0036] From a top view of FIG. 2, the package structure 10 includes
the first die 110 and the second dies 120 disposed side by side. In
the present embodiment, the first die 110 is the SoC and the second
dies 120 are HBM modules. In detail, an area of the first die 110
may be greater than an area of one of the second dies 120. The
number of the second dies 120 may be greater than the number of the
first die 110. The second dies 120 are disposed at both sides of
the first die 110. The first die 110 and the second dies 120 may be
electrically connected to each other by the RDL structure 134, the
interposer 130, and the circuit substrate 200, as shown in FIG. 1C.
As show in the top view of FIG. 2, the adhesive pattern 150 has a
plurality of openings 154 to expose the first and second dies 110
and 120. In other word, the adhesive pattern 150 is disposed on the
underfill layer 115 and the first encapsulant 125, so as to
surround a perimeter 110p of the first die 110 and perimeters 120p
of the second dies 120 in the top view. In alternative embodiments,
the adhesive pattern 150 includes two adhesive layers respectively
disposed on the underfill layer 115 between the first and second
dies 110 and 120. In other word, the two adhesive layers may be
disposed along both sides (e.g., right and left sides) of the first
die 110. In other embodiments, the adhesive pattern 150 includes a
plurality of dot structures discretely distributed and surrounding
the perimeter 110p of the first die 110 and perimeters 120p of the
second dies 120 in the top view.
[0037] In some embodiments, a layout area of the adhesive pattern
150 is less than that of the whole package 100. For example, a
ratio of the layout area of the adhesive pattern 150 to the layout
area of the package 100 is about 5% to about 99%.
[0038] FIG. 3A and FIG. 3B are enlarged views of a portion 150p of
the package structure 10 illustrated in FIG. 1C.
[0039] Referring to FIG. 3A, an adhesive pattern 150a is formed and
restricted on the underfill layer 115 without extending onto the
top surfaces 110t, 120t of the first and second dies 110, 120. In
detail, the adhesive pattern 150a may have a width W1 substantially
equal to or less than a distance D1 between the first die 100 and
the adjacent second die 120. In some embodiments, the width W1 is
about 10 .mu.m to about 300 .mu.m, such as 100 .mu.m. The distance
D1 may be about 10 .mu.m to about 300 .mu.m, such as 100 .mu.m. In
addition, the adhesive pattern 150a may have a flat bottom surface
150bt and a curved top surface 150t. In some embodiments, the
bottom surface 150bt of the adhesive pattern 150a is substantially
aligned with the top surfaces 110t, 120t of the first and second
dies 110, 120. The curved top surface 150t of the adhesive pattern
150a may be a convex surface that protrudes along a direction from
the bottom surface 150bt to the top surface 150t. An included angle
.theta.1 is between the top surface 150t and the bottom surface
150bt of the adhesive pattern 150a, wherein the included angle
.theta. may be an acute angle. In some embodiments, the included
angle .theta.1 is about 5 degree to about 85 degree, such as 45
degree. In addition, a thickness T1 of the adhesive pattern 150a
gradually decreases along a direction from center to edge. For
example, the highest thickness T1 of the adhesive pattern 150a is
about 0.5 .mu.m to 100 .mu.m, such as about 10 .mu.m.
[0040] Referring to FIG. 3B, an adhesive pattern 150b not only
covers on the underfill layer 115, but also extends to cover a
portion of the top surfaces 110t, 120t of the first and second dies
110, 120. In the case, the adhesive pattern 150b further covers and
protects interfaces between the underfill layer 115 and the first
and second dies 110, 120, thereby avoiding the defects.
Specifically, the adhesive pattern 150b may have a width W2 greater
than the distance D1 between the first die 100 and the adjacent
second die 120. In some embodiments, the width W2 is about 10 .mu.m
to about 300 .mu.m, such as 140 .mu.m. In the case, the adhesive
pattern 150b may in contact with the portions of the top surfaces
110t, 120t of the first and second dies 110, 120. The adhesive
pattern 150b may have an extending length L1 which is measured from
an interface between the first die 110 and the underfill layer 115
to a right edge of the adhesive pattern 150b. In addition, the
adhesive pattern 150b may have another extending length L2 which is
measured from an interface between the second die 120 and the
underfill layer 115 to a left edge of the adhesive pattern 150b. In
one embodiment, the extending length L1 is the same with the
extending length L2. In another embodiment, the extending length L1
is different from the extending length L2. For example, the
extending length L1 is about 3 .mu.m to 60 .mu.m, such as about 20
.mu.m. The extending length L2 may be about 3 .mu.m to 60 .mu.m,
such as about 20 .mu.m. An included angle .theta.2 is between the
top surface 150t' and the bottom surface 150bt' of the adhesive
pattern 150b, wherein the included angle .theta.2 may be an acute
angle. In some embodiments, the included angle .theta.2 is about 5
degree to about 85 degree, such as 45 degree. In one embodiment,
the included angle .theta.2 is less than the included angle
.theta.1. In other embodiments, the included angle .theta.2 is
greater than or substantial equal to the included angle .theta.1.
In addition, a thickness T2 of the adhesive pattern 150b also
gradually decreases along the direction from center to edge. For
example, the highest thickness T2 of the adhesive pattern 150b is
about 0.5 .mu.m to 100 .mu.m, such as about 10 .mu.m.
[0041] FIG. 4A to FIG. 4C are cross-sectional views of a method of
forming a package structure in accordance with a second
embodiment.
[0042] Referring to FIG. 4A, the CoWoS package 10a is provided. The
structures, materials, and functions may be similar to what are
shown in, and discussed referring to, FIG. 1A. The details are thus
no repeated herein.
[0043] Referring to FIG. 4B, a TIM 260 is dispensed on the first
die 110, the second dies 120, the underfill layer 115, and the
first encapsulant 125 by a dispenser 262. In some embodiments, the
TIM 260 includes a material with higher thermal conductivity (k),
such as Ag, Cu, Sn, In, carbon nanotube (CNT), graphite, or the
like. It should be noted that the TIM 260 has an edge thickness T3
greater than or substantially equal to a center thickness T4 of the
TIM 260. The thicker edge thickness T3 may provide a better
adhesion between the TIM 260 and the edge encapsulant 125, thereby
decreasing the delamination issue and increasing the reliability
for high-warpage area. The thinner center thickness T4 may achieve
better thermal dissipation, especially from the first die 110
(e.g., SoC or GPU). In some embodiments, the edge thickness T3 is
about 5 .mu.m to about 400 .mu.m, such as about 200 .mu.m; the
center thickness T4 is about 3 .mu.m to about 300 .mu.m, such as
about 100 .mu.m; a ratio (T3/T4) of the edge thickness T3 to the
center thickness T4 is about 1.1 to about 5, such as about 2. In
the case, the specific range of the edge thickness T3 and/or the
center thickness T4 of the TIM 260 may provide a better coverage
than the thinner TIM and a better thermal dissipation than the
thicker TIM. That is, when the edge thickness T3 is less than 5
.mu.m and the center thickness T4 is less than 3 .mu.m, the TIM 260
may have a bad coverage without completely covering the underlying
structure. On the other hand, when the edge thickness T3 is greater
than 400 .mu.m and the center thickness T4 is greater than 300
.mu.m, the TIM 260 may have a bad thermal dissipation.
[0044] Referring to FIG. 4C, a lid 270 is then attached to the
package 100 and circuit substrate 200 to form a package structure
20. As shown in FIG. 4C, the lid 270 covers and surrounds the
package 100 and the passive devices 140. Specifically, the lid 270
is adhered to the package 100 by the TIM 260 and adhered to the
circuit substrate 200 by an adhesive 172. Since the TIM 260 has the
thicker edge thickness T3 and the thinner center thickness T4, the
TIM 260 has a concave top surface 260t. The concave top surface
260t may be recessed along a direction from the first die 110 to
the interposer 130. Further, the lid 270 may conformally covers the
concave top surface 260t of the TIM 260 and has a concave top
surface 270ct corresponding to the concave top surface 260t of the
TIM 260. As shown in FIG. 4C, the lid 270 has a top surface 270t
including a flat top surface 270ft and the concave top surface
270ct. The concave top surface 270ct is surrounded by the flat top
surface 270ft. The flat top surface 270ft is higher than the
concave top surface 270ct. The arrangement and material of the TIM
260 and the lid 270 are similar to the arrangement and material of
the TIM 160 and the lid 170 and has been described in detail in the
above embodiments. Thus, details thereof are omitted here.
[0045] FIG. 5A to FIG. 5D are cross-sectional views of a method of
forming a package structure in accordance with a third
embodiment.
[0046] Referring to FIG. 5A, the CoWoS package 10a is provided. The
structures, materials, and functions may be similar to what are
shown in, and discussed referring to, FIG. 1A. The details are thus
no repeated herein.
[0047] Referring to FIG. 5B, a first metal layer 362 is formed on
the package 100. The first metal layer 362 may be formed on the
package 100 before or after the package 100 is singulated. The
first metal layer 362 may be formed from a conductive material or
metal, such as Ag, Au, Ti, NiV, Al, TiN, Cu, Sn, the like, or a
combination thereof. The first metal layer 362 may be formed by
depositing a seed layer over the interposer 130 (e.g., on the first
encapsulant 125, the first and second dies 110, 120, and the
underfill layer 115), and then electroplating the conductive
material onto the seed layer. The first metal layer 362 may also be
formed by sputtering the conductive material onto the package 100.
In some embodiments, the first metal layer 362 is a continuous
structure that blanketly covers the first encapsulant 125, the
first and second dies 110, 120, and the underfill layer 115. In
some embodiments, the first metal layer 362 is electrically
floating. That is, the first metal layer 362 may be electrically
insulated from the active and/or passive devices of the first and
second dies 110, 120 and other surrounding devices.
[0048] Referring to FIG. 5C and FIG. 5D, a TIM 360 is then
dispensed on the first metal layer 362. The material of the TIM 360
is similar to the material of the TIM 160 and has been described in
detail in the above embodiments. Thus, details thereof are omitted
here. The lid 170 coated with a second metal layer 364 is then
attached to the package 100 and the circuit substrate 200 to form a
package structure 30. In the case, as shown in FIG. 5D, the first
metal layer 362, the second metal layer 364, and the TIM 360
sandwiched between the first and second metal layers 362, 364
constitutes a composite structure 365 to thermally couple the lid
170 and the first and second dies 110, 120. The second metal layer
364 may be formed from a conductive material or metal, such as Ag,
Au, Ti, NiV, Al, TiN, Cu, Sn, the like, or a combination thereof.
The second metal layer 364 may be formed by depositing a seed layer
and then electroplating the conductive material onto the seed
layer. The second metal layer 364 may also be formed by sputtering
the conductive material onto an inner surface of the lid 170. In
some embodiments, the second metal layer 364 is a continuous
structure that covers the TIM 360. In some embodiments, the second
metal layer 364 is electrically floating. That is, the second metal
layer 364 may be electrically isolated from the active and/or
passive devices of the first and second dies 110, 120 and other
surrounding devices. Alternatively, the second metal layer 364 may
be omitted and the TIM 360 is in contact with the lid 170.
[0049] In some embodiments, the first metal layer 362 and the
second metal layer 364 have the same material or different
materials. In some embodiments, the first metal layer 362 has a
thickness 362t substantially equal to a thickness 364t of the
second metal layer 364. The thickness 362t of the first metal layer
362 may be about 0.1 .mu.m to about 10 .mu.m, such as about 1
.mu.m. The thickness 364t of the second metal layer 364 may be
about 0.1 .mu.m to about 10 .mu.m, such as about 1 .mu.m. In the
case, the specific range of the thickness 362t and/or the thickness
364t may provide a better coverage than the thinner metal layer and
a better thermal dissipation than the thicker metal layer. That is,
when the thickness 362t and/or the thickness 364t is less than 0.1
.mu.m, the first metal layer 362 and/or the second metal layer 364
may have a bad coverage without completely covering the underlying
structure. On the other hand, when the thickness 362t and/or the
thickness 364t is greater than 10 .mu.m, the first metal layer 362
and/or the second metal layer 364 may have a bad thermal
dissipation. In some alternative embodiments, the thickness 362t of
the first metal layer 362 is less than or greater than the
thickness 364t of the second metal layer 364. In some embodiments,
the TIM 360 has a thickness 360t greater than or substantially
equal to the thickness 362t of the first metal layer 362 and/or the
thickness 364t of the second metal layer 364. The thickness 360t of
the TIM 360 may be about 3 .mu.m to about 300 .mu.m, such as about
60 .mu.m.
[0050] It should be noted that the first metal layer 362 may
improve an adhesion between the TIM 360 and the package 100
(especially the underfill layer 115 and the first encapsulant 125),
thereby decreasing the delamination issue and increasing the
reliability. In other words, the first metal layer 362 may be
referred to as an adhesive film, layer, or pattern. Similarly, the
second metal layer 364 may improve an adhesion between the TIM 360
and the lid 170, thereby decreasing the delamination issue and
increasing the reliability. The second metal layer 364 may also be
referred to as an adhesive film, layer, or pattern. Further, the
composite structure 365 including the TIM 360 sandwiched between
the first metal layer 362 and the second metal layer 364 may have a
high thermal conductivity and may conform to the shape of the
package 100, including conforming to any warpage that may have been
introduced in the package 100. As such, the overall thermal
resistance of the package structure 30 may be reduced.
[0051] FIG. 6 illustrates a package structure 40 having an adhesive
pattern 450 and the TIM 260. Specifically, the adhesive pattern 450
is dispensed on the underfill layer 115. The TIM 260 with different
thickness is then dispensed on the adhesive pattern 450, the first
encapsulant 125, and the first and second dies 110 and 120, so that
the adhesive pattern 450 is surrounded by the TIM 260. The material
of the adhesive pattern 450 is similar to the material of the
adhesive pattern 150 and has been described in detail in the above
embodiments. Thus, details thereof are omitted here. In the case,
the package structure 40 may have advantages combined from the
package structures 10 and 20. That is, the adhesive pattern 450 may
improve the adhesion between the TIM 260 and the underfill layer
115. The thicker edge thickness T3 may improve the adhesion between
the TIM 260 and the edge encapsulant 125, thereby decreasing the
delamination issue and increasing the reliability for high-warpage
area. The thinner center thickness T4 may achieve better thermal
dissipation, especially from the first die 110 (e.g., SoC or GPU).
In some embodiments, the adhesive pattern 450 is formed and
restricted on the underfill layer 115. In some other embodiments,
the adhesive pattern 450 extends to cover portions of the first and
second dies 110, 120. In some embodiments, a layout area of the
adhesive pattern 450 is less than that of the adhesive pattern 150
illustrated in FIG. 2. For example, a ratio of the layout area of
the adhesive pattern 450 to the layout area of the package 100 is
about 5% to about 99%. Alternatively, the adhesive pattern 450 may
be optionally formed on the first encapsulant 125 to separate the
first encapsulant 125 from the TIM 260.
[0052] According to some embodiments, a package structure includes
a first die, a second die group, an interposer, an underfill layer,
a thermal interface material (TIM), and an adhesive pattern. The
first die and the second die group are disposed side by side on the
interposer. The underfill layer is disposed between the first die
and the second die group. The TIM is disposed on the first die, the
second die group, and the underfill layer. The adhesive pattern is
disposed between the underfill layer and the TIM to separate the
underfill layer from the TIM.
[0053] According to some embodiments, a package structure includes
a first die, a second die, an interposer, an underfill layer, a
thermal interface material (TIM), and a first metal layer. The
first die and the second die are disposed side by side on the
interposer. The TIM is disposed on the first die, the second die,
and the underfill layer. The TIM has an edge thickness greater than
a center thickness of the TIM.
[0054] According to some embodiments, a method of forming a package
structure includes: bonding a first die and a second die onto an
interposer; dispensing an underfill layer between the first die and
the second die; forming a first encapsulant to laterally
encapsulate the first die, the second die, and the underfill layer;
forming an adhesive pattern on the underfill layer between the
first die and the second die and on the first encapsulant; and
dispensing a thermal interface material (TIM) on the adhesive
pattern.
[0055] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *