U.S. patent application number 17/502980 was filed with the patent office on 2022-02-03 for method of manufacturing a flip chip package and an apparatus for testing flip chips.
This patent application is currently assigned to SK hynix Inc.. The applicant listed for this patent is SK hynix Inc.. Invention is credited to Jee Won CHUNG, Byeung Ho KIM, Chang Hyun KIM, Dong Jin KIM.
Application Number | 20220037214 17/502980 |
Document ID | / |
Family ID | |
Filed Date | 2022-02-03 |
United States Patent
Application |
20220037214 |
Kind Code |
A1 |
CHUNG; Jee Won ; et
al. |
February 3, 2022 |
METHOD OF MANUFACTURING A FLIP CHIP PACKAGE AND AN APPARATUS FOR
TESTING FLIP CHIPS
Abstract
A method of manufacturing a flip chip package includes forming a
plurality of semiconductor chips and bonding the semiconductor
chips to a package substrate. The method further includes
electrically testing the plurality of semiconductor chips on the
package substrate, molding the tested semiconductor chips, and
singulating the molded chips. Electrically testing the
semiconductor chips includes covering the semiconductor chips with
a protection member.
Inventors: |
CHUNG; Jee Won; (Seoul,
KR) ; KIM; Dong Jin; (Icheon-si Gyeonggi-do, KR)
; KIM; Byeung Ho; (Cheongju-si Chungcheongbuk-do, KR)
; KIM; Chang Hyun; (Hwaseong-si Gyeonggi-do, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SK hynix Inc. |
Icheon-si Gyeonggi-do |
|
KR |
|
|
Assignee: |
SK hynix Inc.
Icheon-si Gyeonggi-do
KR
|
Appl. No.: |
17/502980 |
Filed: |
October 15, 2021 |
Related U.S. Patent Documents
|
|
|
|
|
|
Application
Number |
Filing Date |
Patent Number |
|
|
16669050 |
Oct 30, 2019 |
11177184 |
|
|
17502980 |
|
|
|
|
International
Class: |
H01L 21/66 20060101
H01L021/66; H01L 21/56 20060101 H01L021/56; H01L 21/78 20060101
H01L021/78; H01L 21/67 20060101 H01L021/67; H01L 23/00 20060101
H01L023/00 |
Foreign Application Data
Date |
Code |
Application Number |
May 10, 2019 |
KR |
10-2019-0054896 |
Claims
1. A method of manufacturing a flip chip package, the method
comprising: forming a plurality of semiconductor chips; bonding the
plurality of semiconductor chips to a package substrate;
electrically testing the plurality of semiconductor chips on the
package substrate; molding the tested semiconductor chips; and
singulating the molded semiconductor chips, wherein electrically
testing the plurality of semiconductor chips comprises covering the
semiconductor chips with a protection member.
2. The method of claim 1, wherein forming the plurality of
semiconductor chips comprises, for each semiconductor chip: forming
at least one electrode pad on a semiconductor substrate with a
device layer; and forming at least one conductive bump on the at
least one electrode pad.
3. The method of claim 2, wherein the package substrate comprises:
an upper layer including a plurality of first connection terminals;
a lower layer including a plurality of second connection terminals;
and a body layer interposed between the upper layer and the lower
layer to electrically connect the plurality of first connection
terminals with the plurality of second connection terminals.
4. The method of claim 3, wherein bonding the semiconductor chips
to the package substrate comprises flipping the semiconductor chips
so the at least one conductive bump for each semiconductor chip
contacts the plurality of first connection terminals.
5. The method of claim 3, wherein electrically testing the
plurality of semiconductor chips comprises applying at least one of
a voltage and a current to the plurality of semiconductor chips
through the plurality of second connection terminals of the package
substrate to test electrical characteristics between the package
substrate and the plurality of semiconductor chips.
6. The method of claim 1, further comprising forming, after
electrically testing the plurality of semiconductor chips and
before molding the tested semiconductor chips, an underfilling
layer between the at least one conductive bump for each
semiconductor chip and the package substrate.
7. The method of claim 1, further comprising repairing, after
electrically testing the plurality of semiconductor chips and
before molding the tested semiconductor chips, a semiconductor chip
of the plurality of semiconductor chips that failed being
electrically tested.
8. The method of claim 3, further comprising mounting, after
molding the tested semiconductor chips and before singulating the
molded semiconductor chips, external terminals to the plurality of
second connection terminals.
Description
CROSS-REFERENCES TO RELATED APPLICATION
[0001] The present application is a divisional application of U.S.
patent application Ser. No. 16/669,050, filed on Oct. 30, 2019, and
claims priority under 35 U.S.C. .sctn. 119(a) to Korean application
number 10-2019-0054896, filed on May 10, 2019, in the Korean
Intellectual Property Office, which is incorporated herein by
reference in its entirety.
BACKGROUND
1. Technical Field
[0002] Various embodiments may generally relate to a method of
manufacturing a semiconductor device, and more particularly, to a
method of manufacturing a flip chip package and an apparatus for
testing flip chips.
2. Related Art
[0003] In manufacturing semiconductor chips, various levels of
testing may be performed on the semiconductor chips. A
semiconductor chip failing such a test may be determined to be
abnormal. For example, testing may be related to process
variations, voltage, and temperature (PVT) of a semiconductor chip,
an inter-symbol interference (ISI) of a semiconductor chip, etc.
When an abnormal semiconductor chips are detected early,
unnecessary costs are avoided so that the price of manufacturing
semiconductor devices is reduced.
[0004] In order to provide semiconductor devices with a small size,
a flip chip package structure using a bump as a conductive member
has been proposed as a semiconductor package. The flip chip package
may be manufactured by bonding the bump on the flip chip, molding
an upper portion of the flip chip, marking a molded portion of the
flip chip using a laser, attaching a solder ball on the flip chip
to connect the solder ball with the bump, singulating a
semiconductor substrate to form a plurality of the flip chip
packages, and testing electrical characteristics of each of the
flip chip packages.
[0005] In manufacturing the flip chip packages, errors may be
frequently generated in bonding the semiconductor chip to a package
substrate. However, because the electrical characteristics of the
flip chip package may be tested after the molding process, it may
be difficult to repair the errors of the flip chip package.
SUMMARY
[0006] In accordance with the present disclosure, a method of
manufacturing a flip chip package includes forming a plurality of
semiconductor chips and bonding the semiconductor chips to a
package substrate. The method further includes electrically testing
the plurality of semiconductor chips on the package substrate,
molding the tested semiconductor chips, and singulating the molded
chips. Electrically testing the semiconductor chips includes
covering the semiconductor chips with a protection member.
[0007] Also in accordance with the present disclosure, an apparatus
for testing flip chips includes a test wall configured to define a
test space and a test board arranged in the test space to provide a
package substrate to which a plurality of semiconductor chips is
electrically connected during testing. The apparatus further
includes a protecting member coupled to the test wall and
configured to cover the semiconductor chips during testing.
[0008] Further in accordance with the present disclosure, an
apparatus for testing non-molded bare semiconductor chips on a
package substrate includes a protecting member configured to
contact an edge portion of the package substrate during a test
process, the protection member including a groove divided into a
plurality of partitions configured to individually receive the
semiconductor chips. Each of the plurality of partitions has a size
for forming a gap between the partition and a corresponding
semiconductor chip in the partition to provide clearance between
the partition and each surface of the semiconductor chip.
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] The above and other aspects, features, and advantages of the
subject matter of the present disclosure will be more clearly
understood from the following detailed description taken in
conjunction with the accompanying drawings, in which:
[0010] FIG. 1 is a flow chart illustrating a method of
manufacturing a flip chip package in accordance with example
embodiments;
[0011] FIG. 2 is a perspective view illustrating a semiconductor
chip in accordance with example embodiments;
[0012] FIG. 3 is a cross-sectional view illustrating a pad region
of the semiconductor chip in FIG. 2;
[0013] FIG. 4 is a cross-sectional view illustrating a bonding
process of a flip chip in accordance with example embodiments;
[0014] FIG. 5 is a cross-sectional view illustrating an apparatus
for testing a flip chip in accordance with example embodiments;
[0015] FIG. 6 is a plan view illustrating a substrate-fixing member
in accordance with example embodiments;
[0016] FIG. 7 is a perspective view illustrating a protection
member in accordance with example embodiments;
[0017] FIG. 8 is a perspective view illustrating a protection
member in accordance with example embodiments;
[0018] FIG. 9 is a cross-sectional view taken along a line
VIII-VIII' in FIG. 8; and
[0019] FIG. 10 is a cross-sectional view illustrating a molding
process and a mounting process of a semiconductor chip in
accordance with example embodiments.
DETAILED DESCRIPTION
[0020] Various embodiments of the present teachings are described
in detail with reference to the accompanying drawings. The drawings
are schematic illustrations of various embodiments (and
intermediate structures). As such, variations from the
configurations and shapes of the illustrations as a result, for
example, of manufacturing techniques and/or tolerances, are to be
expected. Thus, the described embodiments should not be construed
as being limited to the particular configurations and shapes
illustrated herein but may include deviations in configurations and
shapes which do not depart from the spirit and scope of the present
teachings as defined in the appended claims.
[0021] The present teachings are described herein with reference to
cross-section and/or plan illustrations of idealized embodiments.
However, embodiments of the present teachings should not be
construed as limiting the present teachings. Although a few
embodiments of the present teachings are shown and described, it
will be appreciated by those of ordinary skill in the art that
changes may be made in these embodiments without departing from the
principles and spirit of the present teachings.
[0022] FIG. 1 is a flow chart illustrating a method of
manufacturing a flip chip package in accordance with example
embodiments.
[0023] Referring to FIG. 1, a method of manufacturing a flip chip
package in accordance with example embodiments may include forming
a semiconductor chip (S1), bonding the semiconductor chip as a flip
chip to a package substrate (S2), electrically testing the flip
chip (S3), molding/soldering the flip chip, (S4) and singulating
the flip chip (S5).
[0024] Forming the Semiconductor Chip (S1)
[0025] FIG. 2 is a perspective view illustrating a semiconductor
chip in accordance with example embodiments.
[0026] Referring to FIG. 2, the semiconductor chip 100 may include
device layers such as semiconductor circuits (not shown), a
plurality of conductive layers (not shown), and insulating layers
(not shown).
[0027] The semiconductor chip 100 may have a pad region Pa. The pad
region Pa may be positioned at a central portion of an upper
surface of the semiconductor chip 100. Electrode pads (not shown)
may be arranged in the pad region Pa. A plurality of bumps 135 may
be arranged on the electrode pads in the pad region Pa. The bumps
135 may be directly/indirectly connected with the conductive layer
electrically connected to the semiconductor circuit. The conductive
layer may include a wiring line and a wiring contact connected
between the device layers. Alternatively, the pad region Pa may be
arranged at an edge portion of the upper surface of the
semiconductor chip 100.
[0028] FIG. 3 is a cross-sectional view illustrating a pad region
of the semiconductor chip in FIG. 2.
[0029] Referring to FIG. 3, a plurality of device layers 110 may be
formed on an upper surface of a semiconductor substrate 101. The
device layer 110 may include circuits, wirings (conductive layers)
connected between the circuits, and insulating layers arranged
between the circuits and the wirings. The electrode pad 115 may be
arranged in the pad region Pa on an upper surface of the device
layer 110. The electrode pad 115 may be electrically connected with
at least one conductive layer of the device layer 110. A
passivation layer 120 and a buffer layer 125 may be sequentially
formed on the electrode pad 115. The passivation layer 120 and the
buffer layer 125 may be partially etched to expose an upper surface
of the electrode pad 115. Thus, openings configured to expose the
electrode pad 115 may be formed through the passivation layer 120
and the buffer layer 125. The passivation layer 120 may include an
oxide layer for protecting the device layer 110 from external
environments. The buffer layer 125 may include an insulating
material, polyimide, or an epoxy resin. The buffer layer 125 may
absorb the weight of the bump to prevent the weight of the bump
from being transferred to the device layer 110.
[0030] The bump 135 may be formed in the openings of the
passivation layer 120 and the buffer layer 125. The bumps 135 may
be electrically connected to the electrode pad 115 exposed through
the openings. The bump 135 may include a spherical solder bump. An
under bump metal (UBM) 130 may be interposed between the bump 135
and the electrode pad 115 to prevent diffusions of solders, thereby
completing the semiconductor chip 100.
[0031] In example embodiments, a wafer level test such as a probe
test may be performed through the electrode pad 115 between opening
the electrode pad 115 and forming the bump 135.
[0032] In example embodiments, a substrate back grinding process
and a dicing process may be additionally performed after forming
the bump 135 to complete the semiconductor chip 100.
[0033] Bonding the Flip Chip (S2)
[0034] FIG. 4 is a cross-sectional view illustrating a bonding
process of a flip chip in accordance with example embodiments.
[0035] Referring to FIG. 4, bonding the flip chip (S2) may include
flipping the semiconductor chip to orient the bump 135 toward a
package substrate 200, and bonding the semiconductor chip 100 to
the package substrate 200.
[0036] The package substrate 200 may include a body layer 210, an
upper layer 220, and a lower layer 230. The upper layer 220 may
include a first connection terminal 220a electrically connected to
the bump 135. The lower layer 230 may include a second connection
terminal 230a. An electrical signal may be communicated between the
second connection terminal 230a and an external device.
[0037] The package substrate 200 may include a printed circuit
board (PCB), a glass substrate, a flexible film, etc. The body
layer 210 may include circuit patterns electrically connected
between the first connection terminals 220a and the second
connection terminals 220b. The first and second connection
terminals 220a and 220b may include a photo solder resist.
[0038] When the bump 135 of the semiconductor chip 100 is connected
to the first connection terminal 220a of the package substrate 200
by the flip chip bonding process, an internal signal of the
semiconductor chip 100 may be transmitted to the external device
through the first connection terminal 220a, the circuit pattern,
and the second connection terminal 220b of the package substrate
200. Further, an external signal of the external device may be
transmitted to the semiconductor device 100 through the first
connection terminal 220a, the circuit pattern, and the second
connection terminal 230a. The external device may include a system
having a logic circuit, a memory module, a system including the
logic circuit, and the memory module, etc.
[0039] Bonding the flip chip may be performed using a mechanical
pressure of the die bonding apparatus.
[0040] Electrically Testing the Flip Chip (S3)
[0041] FIG. 5 is a cross-sectional view illustrating an apparatus
for testing a flip chip in accordance with example embodiments.
[0042] The bare semiconductor chips 100 bonded to the package
substrate 200 may be electrically tested before the molding
process.
[0043] In the electrical test, various voltages or various currents
may be supplied to the second connection terminal 230a of the
package substrate 200 to detect whether the bump 135 of the
semiconductor chip 100 may be normally connected to the first
connection terminal 220a of the package substrate 200 or not. The
electrical test may further include a capacitance test, a
resistance test, etc.
[0044] The electrical test may be performed using the apparatus
illustrated in FIG. 5.
[0045] Referring to FIG. 5, the electrical test apparatus 300 may
include a loader 310, a tester 350, and an unloader 370.
[0046] The package substrate 200 with the semiconductor chips 100
may be on standby in the loader 310.
[0047] The tester 350 may include a test wall 352, a test board
354, a substrate-fixing member 356, and a protection member
360.
[0048] The test wall 352 may define a test space where the test
process may be performed. The test wall 352 may include gates G
connected to the loader 310 and the unloader 370. The package
substrate 200 may be transferred through the gates G.
[0049] The test board 354 may be arranged in the test space defined
by the test wall 352.
[0050] The test board 354 may include a substrate stage 354a and a
support 354b. The substrate stage 354a may have a size for
receiving the package substrate 200. The substrate stage 354a may
be configured to make contact with the lower surface 230 of the
package substrate 200. The substrate stage 354a may include a
plurality of test pins 355. The test pins 355 may be arranged on a
surface of the substrate stage 354a fronting the package substrate
200. The test pins 355 may make contact with the second connection
terminal 230a of the package substrate 200.
[0051] The support 354b may be configured to support a central
portion of a lower surface of the substrate stage 354a. The support
354b may be vertically moved. Thus, when the package substrate 200
with the semiconductor chips 100 may be loaded into the test space,
the support 354b may be upwardly moved to contact the test pins 355
with the second connection terminal 230a of the package substrate
200.
[0052] FIG. 6 is a plan view illustrating a substrate-fixing member
in accordance with example embodiments.
[0053] Referring to FIG. 6, the substrate-fixing member 356 may
have a frame shape. The substrate-fixing member 356 may primarily
fix the package substrate 200 in the test space. Although not
depicted in drawings, the substrate-fixing member 356 may be
mechanically connected to at least one portion of the test wall 352
or the test board 354 to fix the package substrate 200 with the
semiconductor chips 100.
[0054] FIG. 7 is a perspective view illustrating a protection
member in accordance with example embodiments.
[0055] Referring to FIG. 7, the protection member 360 may protect
the bare semiconductor chips 100 loaded into the test apparatus 300
during the electrical test. The protection member 360 may be
movably connected to an upper surface, also referred to as a
portion of the test wall 352, of the test space so that the
protection member 360 is able to move up and down in the vertical
direction. The protection member 360 may have a groove H configured
to receive the semiconductor chips 100 bonded to the package
substrate 200. The groove H of the protection member 360 may have a
size to form a gap between an inner surface 360a of the groove H
and any outer surface of the semiconductor chips 100 bonded to the
package substrate 200. Thus, the inner surface 360a of the groove H
might not make contact with any outer surface of the semiconductor
chips 100 bonded to the package substrate 200. For example, in
order to prevent a contact between the inner surface 360a of the
groove H and the outer surface of the semiconductor chip 100, the
groove H may have a depth d greater than a sum of a thickness of
the semiconductor chip 100 and a thickness of the bump 135 by about
1 mm to about 10 mm. Further, the protection member 360 may include
a conductive material or a dissipative material having a heat
dissipative property, easy workability and good durability.
[0056] FIG. 8 is a perspective view illustrating a protection
member in accordance with example embodiments, and FIG. 9 is a
cross-sectional view taken along a line VIII-VIII' in FIG. 8.
[0057] Referring to FIGS. 8 and 9, a protection member 360 may
further include partitions 365 arranged in the groove H to
individually receive each of the semiconductor chips 100. For
example, when eight semiconductor chips 100 are bonded to the
package substrate 200, the partitions 365 may define eight spaces
in the groove H. Further, vacuum holes 367 may be formed through
the protection member 360 and the partitions 365 to provide the
semiconductor chips 100 in the spaces defined by the partitions
365. Thus, vacuum may be supplied to each of the semiconductor
chips 100 through the vacuum holes 367 to firmly fix the
semiconductor chips 100, thereby reducing damages to the
semiconductor chips 100. The vacuum holes 367 may be connected to a
vacuum pump in the test apparatus.
[0058] Hereinafter, operations of the test apparatus in accordance
with this example embodiment are described in detail.
[0059] The package substrates 200 on which the flip chip bonding
process (S2) is performed may be received in a magazine before the
molding process. The package substrates 200 may be sequentially
loaded into the loader 310. The package substrate 200 in the
magazine may be sequentially loaded into the loader 310 by a
pusher.
[0060] The package substrate 200 in the loader 310 may be on
standby until a previous test process in the tester 350 is
finished. After the previous test process is finished, the package
substrate 200 in the loader 310 may be transferred to the tester
350. The package substrate 200 may be transferred to the tester 350
by a conveyor belt.
[0061] The substrate-fixing member 356 may primarily fix the
package substrate 200 in the tester 350. The protection member 360
or 360 may be moved downward to contact the edge portion of the
package substrate 200 fixed by the substrate-fixing member 356 with
the edge portion of the protection member 360. Thus, the package
substrate 200 and the protection member 360 may fully enclose the
semiconductor chip 100.
[0062] The support 354b of the test board 354 may be moved upward
so the test pins 355 of the substrate stage 354a contact the second
connection terminals 230a of the package substrate 200. The test
board 354 may provide the second connection terminals 230a of the
package substrate 200 with a current or a voltage through the test
pins 355. Therefore, a bonding failure between the semiconductor
chip 100 and the package substrate 200, i.e., between the bump 135
and the first connection terminal 220a, a contact failure between
the semiconductor chip 100 and the bump 135, etc., may be detected
based on electrical characteristics of current/voltage/resistance
transmitted from the package substrate 200 to the semiconductor
chip 100. Alternatively, the test process may use other test
techniques as well as the current/voltage test.
[0063] According to example embodiments, although the electrical
test may be performed on the semiconductor chips to which the
molding process has not yet been performed, the semiconductor chips
100 are not be damaged because the protection member 360 may fully
cover the semiconductor chips 100.
[0064] After the test process, the package substrate 200 may be
unloaded to the unloader 370 through a gate. Because the
semiconductor chips 100 is not yet molded, a semiconductor chip 100
determined to be abnormal in the electrical test (S3) may be
repaired.
[0065] Molding/Mounting and Singulating the Semiconductor Chips
[0066] FIG. 10 is a cross-sectional view illustrating a molding
process and a mounting process of a semiconductor chip in
accordance with example embodiments.
[0067] Referring to FIG. 10, an underfilling layer 150 may be
formed between the bump 135 of the semiconductor chip 100 to which
the electrical test (S3) and/or the repair process (S4) may be
performed and the package substrate 200. The underfilling layer 150
may protect the bump 135 from the external environments. The
underfilling layer 150 may be annealed to reinforce an adhesion
force between the bump 135 and the first connection terminal 220a
of the package substrate 200.
[0068] A molding member 160 may be formed on the package substrate
200 to cover the semiconductor chips 100. The molding member 160
may include an epoxy resin. After annealing the molding member 160,
a laser-marking process may be performed on the molding member
160.
[0069] An external terminal 240, such as a solder ball, may be
mounted on the second connection terminal 230 of the package
substrate 200. Here, the sequence of the molding process, the
laser-marking process, and the mounting process may be changed.
[0070] The semiconductor chips 100 may be singulated to complete
the flip chip package.
[0071] According to example embodiments, after bonding a
semiconductor chip to a package substrate, an electrical test may
be performed before a molding process. Thus, because the electrical
test is performed before the molding process is performed, any
contact failure between the semiconductor chip and the package
substrate may be repaired. The packaging process may then be
performed on the semiconductor chip and the package substrate
having the repaired contact.
[0072] Further, the protection member configured to cover the
semiconductor chip in the test process may be installed at the
tester to reduce the damage to the bare semiconductor chip. The
protection member may cover the semiconductor chips to prevent
influences of the semiconductor chips in the test process, thereby
reducing possible damage to the semiconductor chip.
[0073] The above described embodiments of the present teachings are
intended to illustrate and not to limit the present teachings.
Various alternatives and equivalents are possible. The present
teachings are not limited by the embodiments described herein. Nor
are the present teachings limited to any specific type of
semiconductor device. Other additions, subtractions, or
modifications are possible in view of the present disclosure and
are intended to fall within the scope of the appended claims.
* * * * *