U.S. patent application number 17/205055 was filed with the patent office on 2022-01-06 for semiconductor packages and method of manufacturing semiconductor packages.
The applicant listed for this patent is SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to Jingu KIM, Sangkyu LEE, Yongkoon LEE.
Application Number | 20220006173 17/205055 |
Document ID | / |
Family ID | 1000005565158 |
Filed Date | 2022-01-06 |
United States Patent
Application |
20220006173 |
Kind Code |
A1 |
LEE; Yongkoon ; et
al. |
January 6, 2022 |
SEMICONDUCTOR PACKAGES AND METHOD OF MANUFACTURING SEMICONDUCTOR
PACKAGES
Abstract
A semiconductor package includes a redistribution wiring layer
having redistribution wirings, a semiconductor chip on the
redistribution wiring layer, a frame on the redistribution wiring
layer, the frame surrounding the semiconductor chip, and the frame
having core connection wirings electrically connected to the
redistribution wirings, and an antenna structure on the frame, the
antenna structure including a ground pattern layer, a first antenna
insulation layer, a radiator pattern layer, a second antenna
insulation layer, and a director pattern layer sequentially stacked
on one another.
Inventors: |
LEE; Yongkoon; (Suwon-si,
KR) ; KIM; Jingu; (Suwon-si, KR) ; LEE;
Sangkyu; (Suwon-si, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRONICS CO., LTD. |
Suwon-si |
|
KR |
|
|
Family ID: |
1000005565158 |
Appl. No.: |
17/205055 |
Filed: |
March 18, 2021 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2924/173 20130101;
H01L 2224/2101 20130101; H01L 2224/214 20130101; H01L 2224/211
20130101; H01Q 1/2283 20130101; H01L 23/66 20130101; H01L 2223/6616
20130101; H01L 2924/1421 20130101; H01L 24/20 20130101; H01L
2924/172 20130101; H01L 2223/6677 20130101 |
International
Class: |
H01Q 1/22 20060101
H01Q001/22; H01L 23/66 20060101 H01L023/66; H01L 23/00 20060101
H01L023/00 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 3, 2020 |
KR |
10-2020-0082296 |
Claims
1. A semiconductor package, comprising: a redistribution wiring
layer having redistribution wirings; a semiconductor chip on the
redistribution wiring layer; a frame on the redistribution wiring
layer, the frame surrounding the semiconductor chip, and the frame
having core connection wirings electrically connected to the
redistribution wirings; and an antenna structure on the frame, the
antenna structure including a ground pattern layer, a first antenna
insulation layer, a radiator pattern layer, a second antenna
insulation layer, and a director pattern layer sequentially stacked
on one another.
2. The semiconductor package as claimed in claim 1, wherein the
first antenna insulation layer has a first thermal expansion
coefficient, and the second antenna insulation layer has a second
thermal expansion coefficient smaller than the first thermal
expansion coefficient.
3. The semiconductor package as claimed in claim 2, wherein the
second thermal expansion coefficient is within a range of 1/3 to
1/4 of the first thermal expansion coefficient.
4. The semiconductor package as claimed in claim 2, wherein the
second thermal expansion coefficient of the second antenna
insulation layer is a same as a thermal expansion coefficient of
the frame.
5. The semiconductor package as claimed in claim 1, wherein the
first antenna insulation layer has a first thickness, and the
second antenna insulation layer has a second thickness greater than
the first thickness.
6. The semiconductor package as claimed in claim 5, wherein the
first thickness of the first antenna insulation layer is in a range
of 100 .mu.m to 150 .mu.m, and the second thickness of the second
antenna insulation layer is in a range of 150 .mu.m to 350
.mu.m.
7. The semiconductor package as claimed in claim 1, wherein the
radiator pattern layer is electrically connected to the core
connection wirings by a transmission line.
8. The semiconductor package as claimed in claim 7, wherein the
transmission line extends through a via hole in the ground pattern
layer.
9. The semiconductor package as claimed in claim 1, wherein the
second antenna insulation layer includes a same material as the
frame.
10. The semiconductor package as claimed in claim 1, wherein the
semiconductor chip includes a radio frequency integrated circuit
(RFIC) for wireless communication.
11. A semiconductor package, comprising: a frame having a cavity; a
semiconductor chip in the cavity, the semiconductor chip including
chip pads; a redistribution wiring layer on a lower surface of the
frame, the redistribution wiring layer having redistribution
wirings electrically connected to the chip pads of the
semiconductor chip; and an antenna structure on an upper surface of
the frame, the antenna structure including a ground pattern layer,
a first antenna insulation layer, a radiator pattern layer, a
second antenna insulation layer, and a director pattern layer
sequentially stacked on one another, wherein the first antenna
insulation layer has a first thermal expansion coefficient, and the
second antenna insulation layer has a second thermal expansion
coefficient smaller than the first thermal expansion
coefficient.
12. The semiconductor package as claimed in claim 11, wherein the
second thermal expansion coefficient is in a range of 1/3 to 1/4 of
the first thermal expansion coefficient.
13. The semiconductor package as claimed in claim 11, wherein the
second thermal expansion coefficient of the second antenna
insulation layer is a same as a thermal expansion coefficient of
the frame.
14. The semiconductor package as claimed in claim 11, wherein the
first antenna insulation layer has a first thickness and the second
antenna insulation layer has a second thickness greater than the
first thickness.
15. The semiconductor package as claimed in claim 11, wherein: the
frame includes core connection wirings, and the radiator pattern
layer is electrically connected to the core connection wirings by a
transmission line, the transmission line extending through a via
hole in the ground pattern layer.
16. A semiconductor package, comprising: a semiconductor chip; a
frame surrounding the semiconductor chip, the frame having core
connection wirings; a redistribution wiring layer on a lower
surface of the frame, the redistribution wiring layer having
redistribution wirings electrically connected to chip pads of the
semiconductor chip; and an antenna structure on an upper surface of
the frame, the antenna structure including a ground pattern layer,
a first antenna insulation layer, a radiator pattern layer, a
second antenna insulation layer, and a director pattern layer
sequentially stacked on one another, wherein the radiator pattern
layer is electrically connected to the redistribution wirings
through the core connection wirings.
17. The semiconductor package as claimed in claim 16, wherein the
first antenna insulation layer has a first thermal expansion
coefficient, and the second antenna insulation layer has a second
thermal expansion coefficient smaller than the first thermal
expansion coefficient.
18. The semiconductor package as claimed in claim 17, wherein the
second thermal expansion coefficient is within a range of 1/3 to
1/4 of the first thermal expansion coefficient.
19. The semiconductor package as claimed in claim 17, wherein the
second thermal expansion coefficient of the second antenna
insulation layer is a same as a thermal expansion coefficient of
the frame.
20. The semiconductor package as claimed in claim 16, wherein the
first antenna insulation layer has a first thickness and the second
antenna insulation layer has a second thickness greater than the
first thickness.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] Korean Patent Application No. 10-2020-0082296, filed on Jul.
3, 2020, in the Korean Intellectual Property Office, and entitled:
"Semiconductor Packages and Method of Manufacturing the
Semiconductor Packages," is incorporated by reference herein in its
entirety.
BACKGROUND
1. Field
[0002] Example embodiments relate to a semiconductor package and a
method of manufacturing the semiconductor package. More
particularly, example embodiments relate to a semiconductor package
including a semiconductor chip mounted therein and a method of
manufacturing the same.
2. Description of the Related Art
[0003] In mobile communication, as a service frequency increases to
expand a bandwidth, an antenna in package (AiP) has been developed.
The AiP may include an antenna and a radio frequency integrated
circuit (RFIC) that are integrated together.
SUMMARY
[0004] According to example embodiments, a semiconductor package
includes a redistribution wiring layer having redistribution
wirings, a semiconductor chip arranged on the redistribution wiring
layer, a frame on the redistribution wiring layer to surround the
semiconductor chip and having core connection wirings electrically
connected to the redistribution wirings, and an antenna structure
provided on the frame and including a ground pattern layer, a first
antenna insulation layer, a radiator pattern layer, a second
antenna insulation layer and a director pattern layer sequentially
stacked on one another.
[0005] According to example embodiments, a semiconductor package
includes a frame having a cavity, a semiconductor chip arranged
within the cavity, a redistribution wiring layer arranged on a
lower surface of the frame and having redistribution wirings
electrically connected to chip pads of the semiconductor chip, and
an antenna structure provided on an upper surface of the frame and
including a ground pattern layer, a first antenna insulation layer,
a radiator pattern layer, a second antenna insulation layer and a
director pattern layer sequentially stacked on one another. The
first antenna insulation layer has a first thermal expansion
coefficient, and the second antenna insulation layer has a second
thermal expansion coefficient smaller than the first thermal
expansion coefficient.
[0006] According to example embodiments, a semiconductor package
includes a semiconductor chip, a frame surrounding the
semiconductor chip and having core connection wirings, a
redistribution wiring layer arranged on a lower surface of the
frame and having redistribution wirings electrically connected to
chip pads of the semiconductor chip, and an antenna structure
provided on an upper surface of the frame and including a ground
pattern layer, a first antenna insulation layer, a radiator pattern
layer, a second antenna insulation layer and a director pattern
layer sequentially stacked on one another. The radiator pattern
layer is electrically connected to the redistribution wiring
through the core connection wiring.
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Features will become apparent to those of skill in the art
by describing in detail exemplary embodiments with reference to the
attached drawings in which:
[0008] FIG. 1 is a cross-sectional view illustrating a
semiconductor package in accordance with example embodiments.
[0009] FIG. 2A is a plan view illustrating a ground pattern layer
of an antenna structure in FIG.1.
[0010] FIG. 2B is a plan view illustrating a radiator pattern layer
of the antenna structure in FIG. 1.
[0011] FIG. 2C is a plan view illustrating a director pattern layer
of the antenna structure in FIG. 1.
[0012] FIGS. 3 to 15 are views illustrating stages in a method of
manufacturing a semiconductor package in accordance with example
embodiments.
[0013] FIG. 16 is a cross-sectional view illustrating a
semiconductor package in accordance with example embodiments.
[0014] FIGS. 17 to 19 are cross-sectional views illustrating stages
in a method of manufacturing a semiconductor package in accordance
with example embodiments.
[0015] FIG. 20 is a cross-sectional view illustrating a
semiconductor package in accordance with example embodiments.
[0016] FIGS. 21 to 29 are cross-sectional views illustrating stages
in a method of manufacturing a semiconductor package in accordance
with example embodiments.
DETAILED DESCRIPTION
[0017] Hereinafter, example embodiments will be explained in detail
with reference to the accompanying drawings.
[0018] FIG. 1 is a cross-sectional view illustrating a
semiconductor package in accordance with example embodiments. FIG.
2A is a plan view illustrating a ground pattern layer of an antenna
structure in FIG.1, FIG. 2B is a plan view illustrating a radiator
pattern layer of the antenna structure in FIG. 1, and FIG. 2C is a
plan view illustrating a director pattern layer of the antenna
structure in FIG. 1.
[0019] Referring to FIGS. 1 to 2C, a semiconductor package 10 may
include a fan-out package 100 and an antenna structure 300 adhered
on the fan-out package 100. The fan-out package 100 may include a
frame 110, a semiconductor chip 200, and a redistribution wiring
layer 140. Additionally, the fan-out package 100 may further
include outer connection members 400. The antenna structure 300 may
include a ground pattern layer 310, a first antenna insulation
layer 320, a radiator pattern layer 330, a second antenna
insulation layer 340, and a director pattern layer 350 sequentially
stacked on one another.
[0020] In example embodiments, the fan-out package 100 may include
the frame 110 provided on a base substrate and surrounding the
semiconductor chip 200. The frame 110 may include core connection
wirings 122 which are provided in a fan-out region, i.e., a region
outside an area where the semiconductor chip is arranged, to
function as an electrical connection path with the semiconductor
chip 200. Accordingly, the semiconductor package 10 may be provided
as a fan-out panel level package.
[0021] Additionally, the semiconductor package 10 may be provided
as an Antenna in Package (AiP). For example, the semiconductor chip
200 may include a radio frequency (RF) integrated circuit (RFIC)
for wireless communication. The antenna structure 300 may be
disposed on the fan-out package 100 to serve as an antenna for
transmitting and receiving RF signals.
[0022] In example embodiments, the frame 110 may have a first
surface 112, e.g., an upper surface, and a second surface 114,
e.g., a lower surface, opposite to each other. The frame 110 may
have a cavity 116 in a middle region thereof. The cavity 116 may
extend from the first surface 112 to the second surface 114 of the
frame 110.
[0023] The frame 110 may include a plurality of stacked insulation
layers, e.g., first and second insulation layers 120a and 120b, and
the core connection wirings 122 provided in the insulation layers.
For example, the frame 110 may include the first insulation layer
120a and the second insulation layer 120b stacked on the first
insulation layer 120a. The core connection wiring 122 may include a
first metal wiring 122a, a first contact 122b, a second metal
wiring 122c, a second contact 122d, and a third metal wiring 122e.
The first metal wiring 122a may be provided in the second surface
114 of the frame 110, i.e., in a lower surface of the first
insulation layer 120a, and at least a portion of the first metal
wiring 122a may be exposed from the second surface 114. The third
metal wiring 112e may be provided in the first surface 112 of the
frame 110, i.e., in an upper surface of the second insulation layer
120b, and at least a portion of the third metal wiring 112e may be
exposed from the first surface 112. It may be understood that the
numbers and arrangements of the insulation layers and the core
connection wirings of the frame 110 may not be limited thereto.
[0024] The semiconductor chip 200 may be disposed within the cavity
116 of the frame 110. A sidewall of the semiconductor chip 200 may
be spaced apart from an inner sidewall of the cavity 116.
Accordingly, a gap may be formed between the sidewall of the
semiconductor chip 200 and the inner sidewall of the cavity
116.
[0025] The semiconductor chip 200 may include a first substrate and
chip pads 210 on an active surface, e.g., a first surface facing
the redistribution wiring layer 140, of the first substrate. The
semiconductor chip 200 may be arranged such that the first surface
on which the chip pads 210 are formed faces downward. Accordingly,
the chip pads 210 may be exposed from the second surface 114 of the
frame 110. The first surface of the semiconductor chip 200 may be
coplanar with the second surface 114 of the frame 110. The second
surface of the semiconductor chip 200, i.e., a surface opposite to
the first surface, may be located on a plane higher than the first
surface 112 of the frame 110, e.g., relative to the redistribution
wiring layer 140.
[0026] The molding layer 130 may be provided on the first surface
112 of the frame 110 to cover the semiconductor chip 200. The
molding layer 130 may be formed to fill the gap between the
sidewall of the semiconductor chip 200 and the inner sidewall of
the cavity 116. Accordingly, a first portion of the molding layer
130 may be formed on the first surface 112 of the frame 110, a
second portion of the molding layer 130 may be formed on the inner
sidewall of the cavity 116 of the frame 110 to fill the gap, and a
third portion of the molding layer 130 may be formed on a second
surface of the semiconductor chip 200 opposite to the first
surface. For example, the molding layer 130 may include an
insulation material, e.g., epoxy resin, a photo imageable
dielectric (PID) material, an insulation film, e.g., Ajinomoto
Build-up Film (ABF), etc.
[0027] In example embodiments, the redistribution wiring layer 140
may be arranged on the second surface 114 of the frame 110, and may
have redistribution wirings 152 electrically connected to the chip
pads 210 of the semiconductor chip 200 and the core connection
wirings 122 of the frame 110, respectively. The redistribution
wirings 152 may be provided on the second surface 114 of the frame
110 to function as a front side redistribution wiring.
[0028] In particular, the redistribution wiring layer 140 may
include a first lower insulation layer 150a provided on the second
surface 114 of the frame 110 and having first openings which expose
the chip pads 210 of the semiconductor chip 200 and the first metal
wiring 122a of the core connection wiring 122. First lower
redistribution wirings 152a may be provided on the first lower
insulation layer 150a and at least portions of which make contact
with the chip pads 210 and the first metal wiring 122a through the
first openings.
[0029] The redistribution wiring layer 140 may include a second
lower insulation layer 150b provided on the first lower insulation
layer 150a and having second openings which expose the first lower
redistribution wirings 152a. Second lower redistribution wirings
152b may be provided on the second lower insulation layer 150b and
at least portions of which make contact with the first lower
redistribution wirings 152a through the second openings.
[0030] The redistribution wiring layer 140 may include a third
lower insulation layer 150c provided on the second lower insulation
layer 150b and having third openings which expose the second lower
redistribution wirings 152b. Third lower redistribution wirings
152c may be provided on the third lower insulation layer 150c and
at least portions of which make contact with the second lower
redistribution wirings 152b through the third openings.
[0031] The redistribution wiring layer 140 may include a protective
layer on the third lower insulation layer 150c to expose at least a
portion of the third lower redistribution wiring 152c. In this
case, the portion of the third lower redistribution wiring 152c may
function as a landing pad, i.e., a package pad.
[0032] For example, the first to third lower insulation layers 150a
to 150c may include a polymer layer, a dielectric layer, etc. The
redistribution wirings 152 may include, e.g., aluminum (Al), copper
(Cu), tin (Sn), nickel (Ni), gold (Au), platinum (Pt) or an alloy
thereof.
[0033] Thus, the redistribution wiring layer 140 may be provided on
the second surface 114 of the frame 110 and may have the
redistribution wirings 152 electrically connected to the chip pads
210 and the core connection wirings 122, respectively. The
redistribution wiring layer 140 may cover the second surface 114 of
the frame 110 in a region outside the semiconductor chip 200. Some
of the redistribution wirings 152 may electrically connect the
semiconductor chip 200 and the core connection wiring 122 of the
frame 110. It may be understood that the number, sizes,
arrangements, etc. of the lower insulation layers of the
redistribution wirings are exemplarily illustrated, and thus, it
may not be limited thereto.
[0034] The outer connection members 400 may be disposed on the
package pads on an outer surface of the redistribution wiring layer
140. For example, the outer connection member 400 may include a
solder ball. For example, the solder ball may have a diameter of
300 .mu.m to 500 .mu.m. The semiconductor package 10 may be mounted
on a module substrate via the solder balls to constitute a memory
module. The semiconductor package 10 may be electrically connected
to an external device, e.g., a modem, through the solder balls to
transmit and receive data or voice signals.
[0035] Thus, the fan-out package 100 as the fan-out panel level
package may include the frame 110 provided in the region outside
the semiconductor chip 200 and the redistribution wiring layer 140
covering the second surface 114 of the frame 110. In example
embodiments, the antenna structure 300 may be provided as a patch
antenna adhered on the fan-out package 100.
[0036] As illustrated in FIG. 1, the antenna structure 300 may
include the ground pattern layer 310, the radiator pattern layer
330, and the director pattern layer 350 provided as backside
redistribution wirings on the first surface 112 of the frame 110.
The first antenna insulation layer 320 may be interposed between
the ground pattern layer 310 and the radiator pattern layer 330.
The second antenna insulation layer 340 may be interposed between
the radiator pattern layer 330 and the director pattern layer
350.
[0037] As illustrated in FIGS. 1 and 2A, the ground pattern layer
310 may include a ground pattern provided on the molding layer 130
to function as a shield layer. The ground pattern layer 310 may
include a plurality of via holes 311. A first transmission wiring
312b may be formed within the via hole 311. The first transmission
wiring 312b may be electrically connected to a first transmission
contact 312a formed in the molding layer 130. The first
transmission contact 312a may be electrically connected to the
third metal wiring 122e of the core connection wiring 122.
[0038] Thus, the first transmission contact 312a and the first
transmission wiring 312b may be electrically connected to the core
connection wiring 122. The ground pattern layer 310 may be
electrically insulated from the core connection wiring 122.
[0039] The first antenna insulation layer 320 may be provided on
the molding layer 130 to cover the ground pattern layer 310, e.g.,
the first antenna insulation layer 320 may contact a top surface of
the molding layer 130 and completely surround the ground pattern
layer 310. The first antenna insulation layer 320 may include an
insulation material having a first thermal expansion coefficient
(coefficient of linear expansion). The insulation material may
include, e.g., Ajinomoto Build-up Film (ABF) film, polyimide film,
epoxy resin, etc. The first thermal expansion coefficient may be
within a range of about 30 ppm (part per million)/.degree. C. to
about 50 ppm/.degree. C.
[0040] The first antenna insulation layer 320 may be formed to have
a first thickness T1. The first thickness T1 may be within a range
of about 100 .mu.m to about 150 .mu.m. The first antenna insulation
layer 320 may have a dissipation factor of about 0.020 to about
0.030 in a frequency of about 28 GHz to about 60 GHz.
[0041] As illustrated in FIG. 2B, a radiator pattern layer 330 may
be provided on the first antenna insulation layer 320. The radiator
pattern layer 330 may have a radiator antenna pattern 332 and a
radiator ground pattern 334. The radiator pattern layer 330 may be
electrically connected to a second transmission contact 312c formed
in the first antenna insulation layer 320. The first transmission
contact 312a, the first transmission wiring 312b, and the second
transmission contact 312c may be provided as a transmission line
312. Accordingly, the radiator pattern layer 330 may be
electrically connected to the core connection wiring 122 by the
transmission line 312.
[0042] As illustrated in FIGS. 1 and 2C, a second antenna
insulation layer 340 may be provided on the radiator pattern layer
330, and the director pattern layer 350 may be formed on an upper
surface of the second antenna insulation layer 340. The second
antenna insulation layer 340 having the director pattern layer 350
formed thereon may be adhered on the radiator pattern layer 330 in
the form of a core substrate. A first insulation layer 362 and a
second insulation layer 360 may be provided on the upper surface
and a lower surface of the second antenna insulation layer 340,
respectively.
[0043] The director pattern layer 350 may have a director antenna
pattern 352 and a director ground pattern 354. The director pattern
layer 350 may be electrically insulated from the radiator pattern
layer 330.
[0044] In example embodiments, the second antenna insulation layer
340 may include an insulation material having a second thermal
expansion coefficient. The insulation material may be formed using,
e.g., polypropylene glycol (PPG). The second antenna insulation
layer 340 having the director pattern layer 350 formed thereon may
include a material of copper clad laminates (CCL) using
prepreg.
[0045] The second thermal expansion coefficient of the second
antenna insulation layer 340 may be smaller than the first thermal
expansion coefficient of the first antenna insulation layer 320.
For example, the second thermal expansion coefficient may be 1/3 to
1/4 of the first thermal expansion coefficient. The second thermal
expansion coefficient may be within a range of about 5 ppm/.degree.
C. to about 15 ppm/.degree. C.
[0046] The second antenna insulation layer 340 may include the same
material as the frame 110. The second thermal expansion coefficient
of the second antenna insulation layer 340 may be substantially the
same as the thermal expansion coefficient of the frame 110.
[0047] The second antenna insulation layer 340 may be formed to
have a second thickness T2. The second thickness T2 of the second
antenna insulation layer 340 may be greater than the first
thickness T1 of the first antenna insulation layer 320. For
example, the second thickness T2 may be at least twice the first
thickness T1. For example, the second thickness T2 may be within a
range of about 150 .mu.m to about 350 .mu.m. In addition, the
second antenna insulation layer 340 may have a dielectric loss (Df,
dissipation factor) of about 0.001 to about 0.005 at about 28 GHz
to about 60 GHz.
[0048] In example embodiments, the transmission line 312 may
electrically connect the radiator pattern layer 330 of the antenna
structure 300 and the core connection wiring 122. The transmission
lines 312 electrically connected to the semiconductor chip 200 may
be vertically stacked through the via hole 311 of the ground
pattern layer 310 to match antenna impedance.
[0049] As mentioned above, the antenna structure 300 may be
disposed on and separated from the frame 110, in which the
semiconductor chip 200 is mounted, by the ground pattern layer 310.
The second thermal expansion coefficient of the second antenna
insulation layer 340 may be smaller than the first thermal
expansion coefficient of the first antenna insulation layer 320,
and the second thermal expansion coefficient of the second antenna
insulation layer 340 may be the same as or similar to the thermal
expansion coefficient of the frame 110. The second thickness T2 of
the second antenna insulation layer 340 may be greater than the
first thickness T1 of the first antenna insulation layer 320.
[0050] Accordingly, warpage due to a difference in thermal
expansion coefficient between the fan-out package 100 and the
antenna structure 300 may be prevented, and the thickness of the
antenna insulation layer may be increased. Thus, antenna radiation
gain may be improved.
[0051] Hereinafter, a method of manufacturing the semiconductor
package in FIG. 1 will be explained, with reference to FIGS. 3 to
15.
[0052] FIGS. 3 to 15 are views illustrating stages in a method of
manufacturing a semiconductor package in accordance with example
embodiments. FIGS. 3, 5 to 10, 12 and 14 are cross-sectional views
illustrating stages in the method of manufacturing a semiconductor
package in accordance with example embodiments. FIG. 4 is a
sectional view taken along the line A-A' in FIG. 3, as viewed in a
top view, FIG. 11 is a plan view of FIG. 10, and FIG. 15 is a plan
view of FIG. 14.
[0053] Referring to FIGS. 3 and 4, the frame 110 having the cavity
116 may be adhered on a barrier tape 20. In example embodiments,
the frame 110 may be used as a support frame for electrical
connection on which a plurality of semiconductor chips is arranged
to manufacture semiconductor packages having a fan-out panel level
package configuration.
[0054] The frame 110 may have the first surface 112 and the second
surface 114 opposite to each other. The frame 110 may have the
cavity 116 in a middle region thereof. As described later, the
cavity 116 may have an area for receiving the semiconductor chip
200.
[0055] The frame 110 may include the plurality of stacked
insulation layers 120a, 120b and core connection wirings 122
provided in the insulation layers. The core connection wirings 122
may be provided to penetrate through the frame 110 from the first
surface 112 to the second surface 114 of the frame 110 to function
as electrical connection paths. That is, the core connection
wirings 122 may be provided in a fan-out region outside an area
where the semiconductor chip (die) is disposed to be used for
electrical connection with the semiconductor chip mounted
therein.
[0056] For example, the frame 110 may include the first insulation
layer 120a and the second insulation layer 120b stacked on the
first insulation layer 120a. The core connection wiring 122 may
include the first metal wiring 122a, the first contact 122b, the
second metal wiring 122c, the second contact 122d, and the third
metal wiring 122e. The first metal wiring 122a may be provided in
the second surface 114 of the frame 110, i.e., a lower surface of
the first insulation layer 120a, and at least a portion of the
first metal wiring 122a may be exposed from the second surface 114.
The third metal wiring 122e may be provided in the first surface
112 of the frame 110, i.e., an upper surface of the second
insulation layer 120b, and at least a portion of the third metal
wiring 122e may be exposed from the first surface 112. It may be
understood that the numbers and arrangements of the insulation
layers and the core connection wirings may not be limited
thereto.
[0057] The frame 110 may be arranged on the barrier tape 20. The
second surface 114 of the frame 110 may be adhered on the barrier
tape 20. The barrier tape 20 may have a panel shape. For example,
dozens or hundreds of dies may be arranged in the cavities 116 of
the frame 110, respectively. As described later, a singulation
process may be performed to saw the frame 110 to complete a fan-out
panel level package.
[0058] Referring to FIGS. 5 and 6, the semiconductor chip 200 may
be arranged within the cavity 116 of the frame 110. The molding
layer 130 may be formed on the first surface 112 of the frame 110
to cover the semiconductor chip 200.
[0059] The semiconductor chip 200 may be disposed within the cavity
116 of the frame 110. A sidewall of the semiconductor chip 200 may
be spaced apart from an inner sidewall of the cavity 116.
Accordingly, a gap may be formed between the sidewall of the
semiconductor chip 200 and the inner sidewall of the cavity
116.
[0060] The semiconductor chip 200 may include a first substrate and
chip pads 210 on an active surface, i.e., a first surface of the
first substrate. The semiconductor chip 200 may be arranged such
that the first surface on which the chip pads 210 are formed faces
downward. For example, the semiconductor chip 200 may include an
RFIC for wireless communication.
[0061] The molding layer 130 may include an insulation material,
e.g., epoxy resin, a photo imageable dielectric (PID) material, an
insulation film, e.g., ABF, etc. The molding layer 130 may be
formed on the first surface 112 of the frame 110 to cover the
semiconductor chip 200. The molding layer 130 may be formed to fill
the gap between the sidewall of the semiconductor chip 200 and the
inner sidewall of the cavity 116. Accordingly, a first portion of
the molding layer 130 may be formed on the first surface 112 of the
frame 110, a second portion of the molding layer 130 may be formed
on the inner sidewall of the cavity 116 of the frame 110 to fill
the gap, and a third portion of the molding layer 130 may be formed
on a second surface of the semiconductor chip 200 opposite to the
first surface.
[0062] Referring to FIGS. 7 to 9, the redistribution wiring layer
140 having the redistribution wirings 152 electrically connected to
the chip pads 210 of the semiconductor chip 200 and the core
connection wirings 122, respectively, may be formed on the second
surface 114 of the frame 110.
[0063] As illustrated in FIG. 7, after the first lower insulation
layer 150a is formed on the second surface 114 of the frame 110,
the first lower insulation layer 150a may be patterned to form
first openings 151a which expose the chip pads 210 of the
semiconductor chip 200 and the first metal wiring 122a of the core
connection wiring 122, respectively. For example, the first lower
insulation layer 150a may include a polymer layer, a dielectric
layer, etc. The first lower insulation layer 150a may be formed by
a vapor deposition process, a spin coating process, etc.
[0064] As illustrated in FIG. 8, the first lower redistribution
wirings 152a may be formed on the first lower insulation layer 150a
to make contact with the chip pads 210 and the first metal wiring
122a through the first openings 151a, respectively. The first lower
redistribution wiring 152a may be formed by forming a seed layer on
a portion of the first lower insulation layer 150a and in the first
opening 151a, patterning the seed layer and performing an electro
plating process. Accordingly, at least a portion of the first lower
redistribution wiring 152a may make contact with the first metal
wiring 122a through the first opening. For example, the first lower
redistribution wiring 152a may include aluminum (Al), copper (Cu),
tin (Sn), nickel (Ni), gold (Au), platinum (Pt) or an alloy
thereof.
[0065] As illustrated in FIG. 9, after the second lower insulation
layer 150b is formed on the first lower insulation layer 150a to
cover the first lower redistribution wirings 152a, the second lower
insulation layer 150b may be patterned to form second openings
which expose the first lower redistribution wirings 152a,
respectively. The second lower redistribution wirings 152b may be
formed on the second lower insulation layer 150b to make contact
with the first lower redistribution wirings 152a through the second
openings, respectively.
[0066] Similarly, after the third lower insulation layer 150c is
formed on the second lower insulation layer 150b to cover the
second lower redistribution wirings 152b, the third lower
insulation layer 150c may be patterned to form third openings which
expose the second lower redistribution wirings 152b, respectively.
The third lower redistribution wirings 152c may be formed on the
third lower insulation layer 150c to make contact with the second
lower redistribution wirings 152b through the third openings,
respectively.
[0067] A protective layer pattern may be further formed on the
third lower insulation layer 150c to expose at least a portion of
the third lower redistribution wiring 152c. In this case, the
portion of the third lower redistribution wiring 152c may function
as a landing pad, i.e., a package pad.
[0068] Thus, the redistribution wiring layer 140 having the
redistribution wirings 152 electrically connected to the chip pads
210 and the core connection wirings 122, respectively, may be
formed on the second surface 114 of the frame 110. The
redistribution wiring layer 140 may cover the second surface 114 of
the frame 110 in a region outside the semiconductor chip 200. Some
of the redistribution wirings 152 may electrically connect the
semiconductor chip 200 and the core connection wiring 122 of the
frame 110. It may be understood that the number, sizes,
arrangements, etc. of the lower insulation layers of the
redistribution wirings are exemplarily illustrated, and thus, it
may not be limited thereto.
[0069] Referring to FIGS. 10 to 15, the antenna structure 300 may
be formed on the first surface 112 of the frame 110.
[0070] As illustrated in FIGS. 10 and 11, the ground pattern layer
310 may be formed on the molding layer 130 on the first surface 112
of the frame 110. For example, as illustrated in FIG. 10, the
ground pattern layer 310 may include the via holes 311 on the first
surface 112.
[0071] In example embodiments, a conductive layer may be formed on
the molding layer 130, e.g., to cover an entire top surface of the
molding layer 130, followed by patterning the conductive layer to
form the ground pattern layer 310. The ground pattern layer 310 may
have the via holes 311. The first transmission wiring 312b may be
formed within the via hole 311, such that the first transmission
wiring 312b may be electrically connected to the first transmission
contact 312a formed in the molding layer 130. The first
transmission contact 312a may be electrically connected to the
third metal wiring 122e of the core connection wiring 122.
[0072] Thus, the first transmission contact 312a and the first
transmission wiring 312b may be electrically insulated from the
ground pattern layer 310. Additionally, the first transmission
contact 312a and the first transmission wiring 312b may be
electrically connected to the core connection wiring 122.
[0073] As illustrated in FIG. 12, the first antenna insulation
layer 320 may be formed on the molding layer 130 to cover the
ground pattern layer 310. In example embodiments, the first antenna
insulation layer 320 may include an insulation material having a
first thermal expansion coefficient. The insulation material may
include, e.g., ABF film, polyimide film, epoxy resin, etc. The
first thermal expansion coefficient may be within a range of about
30 ppm/.degree. C. to about 50 ppm/.degree. C.
[0074] The first antenna insulation layer 320 may be formed to have
the first thickness T1. The first thickness T1 may be within a
range of about 100 .mu.m to about 150 .mu.m. The first antenna
insulation layer 320 may have a dissipation factor of about 0.020
to about 0.030 in a frequency of about 28 GHz to about 60 GHz.
[0075] As illustrated in FIG. 13, the radiator pattern layer 330
may be formed on the first antenna insulation layer 320. The
radiator pattern layer 330 may be electrically connected to the
second transmission contact 312c formed in the first antenna
insulation layer 320. The first transmission contact 312a, the
first transmission wiring 312b, and the second transmission contact
312c may be provided as the transmission line 312. Accordingly, the
radiator pattern layer 330 may be electrically connected to the
core connection wiring 122 by the transmission line 312.
[0076] As illustrated in FIGS. 14 and 15, the second antenna
insulation layer 340 may be formed on the radiator pattern layer
330. The director pattern layer 350 may be formed on an upper
surface of the second antenna insulation layer 340. The second
antenna insulation layer 340 having the director pattern layer 350
formed thereon may be adhered on the radiator pattern layer 330 in
the form of a core substrate.
[0077] The director pattern layer 350 may have the director antenna
pattern 352 and the director ground pattern 354. The director
pattern layer 350 may be electrically insulated from the radiator
pattern layer 330.
[0078] In example embodiments, the second antenna insulation layer
340 may include an insulation material having a second thermal
expansion coefficient. The insulation material may include
polypropylene glycol (PPG). The second antenna insulation layer 340
having the director pattern layer 350 formed thereon may be formed
of a copper clad laminates (CCL) using prepreg.
[0079] The second thermal expansion coefficient of the second
antenna insulation layer 340 may be smaller than the first thermal
expansion coefficient of the first antenna insulation layer 320.
For example, the second thermal expansion coefficient may be 1/3 to
1/4 of the first thermal expansion coefficient. The second thermal
expansion coefficient may be within a range of about 5 ppm/.degree.
C. to about 15 ppm/.degree. C.
[0080] The second antenna insulation layer 340 may include the same
material as the frame 110. The second thermal expansion coefficient
of the second antenna insulation layer 340 may be substantially the
same as the thermal expansion coefficient of the frame 110.
[0081] The second antenna insulation layer 340 may be formed to
have the second thickness T2. The second thickness T2 of the second
antenna insulation layer 340 may be greater than the first
thickness T1 of the first antenna insulation layer 320. For
example, the second thickness T2 may be at least twice the first
thickness T1. For example, the second thickness T2 may be within a
range of about 150 .mu.m to about 350 .mu.m. In addition, the
second antenna insulation layer 340 may have a dielectric loss (Df,
dissipation factor) of about 0.001 to about 0.005 at about 28 GHz
to about 60 GHz.
[0082] FIG. 16 is a cross-sectional view illustrating a
semiconductor package in accordance with example embodiments. The
semiconductor package may be substantially the same as or similar
to the semiconductor package described with reference to FIG. 1
except for a configuration of an antenna structure. Thus, same
reference numerals will be used to refer to the same or like
elements and any further repetitive explanation concerning the
above elements will be omitted.
[0083] Referring to FIG. 16, an antenna structure 300 of a
semiconductor package 11 may include antenna patterns, i.e., the
ground pattern layer 310, the radiator pattern layer 330, and a
director pattern layer 350a, provided as backside redistribution
wirings on the first surface 112 of the frame 110. The first
antenna insulation layer 320 may be interposed between the ground
pattern layer 310 and the radiator pattern layer 330. The second
antenna insulation layer 340 may be interposed between the radiator
pattern layer 330 and the director pattern layer 350a.
[0084] The ground pattern layer 310 may be provided on the molding
layer 130, and the first antenna insulation layer 320 may be
provided on a first upper insulation layer 160 to cover the ground
pattern layer 310.
[0085] The first transmission contact 312a, the first transmission
wiring 312b, the second transmission contact 312c, the second
transmission wiring 312d, and the third transmission contact 312e
may be provided as the transmission line 312. Accordingly, the
radiator pattern layer 330 may be electrically connected to the
core connection wiring 122 by the transmission line 312.
[0086] The second antenna insulation layer 340 may be provided on
the radiator pattern layer 330. The first director pattern layer
350a may be provided on an upper surface of the second antenna
insulation layer 340, and a second director pattern layer 350b may
be provided on a lower surface of the second antenna insulation
layer 340. The second antenna insulation layer 340 having the first
and second director pattern layers 350a and 350b formed thereon may
be adhered on the radiator pattern layer 330 in the form of a core
substrate.
[0087] The first and second director pattern layers 350a and 350b
may have shapes corresponding to each other, e.g., the first and
second director pattern layers 350a and 350b may completely overlap
each other along a vertical direction. Additionally, the radiator
pattern layer 330 may have a shape corresponding to, e.g.,
overlapping, the first and second director pattern layers 350a,
350b.
[0088] Hereinafter, a method of manufacturing the semiconductor
package in FIG. 16 will be explained.
[0089] FIGS. 17 to 19 are cross-sectional views illustrating a
method of manufacturing a semiconductor package in accordance with
example embodiments.
[0090] Referring to FIG. 17, first, processes the same as or
similar to the processes described with reference to FIGS. 3 to 10
may be performed to form the ground pattern layer 310 on the
molding layer 130 on the first surface 112 of the frame 110. Then,
the first upper insulation layer 160 and the first antenna
insulation layer 320 may be formed on the molding layer 130 to
cover the ground pattern layer 310.
[0091] In example embodiments, the first upper insulation layer 160
may be formed by a vapor deposition process, a spin coating
process, etc. The first upper insulation layer 160 may include a
polymer layer, a dielectric layer, etc. Alternatively, the first
upper insulation layer 160 may include a photo imageable dielectric
(PID) material.
[0092] After the first upper insulation layer 160 is patterned to
form the second transmission contact 312c, the second transmission
wiring 312d as an upper redistribution wiring may be formed on the
first upper insulation layer 160. The first antenna insulation
layer 320 may be formed on the first upper insulation layer 160 to
cover the second transmission wiring 312d. The first antenna
insulation layer 320 may be formed to have the first thickness T1.
The first thickness T1 may be within a range of about 100 .mu.m to
about 150 .mu.m.
[0093] Referring to FIG. 18, a radiator pattern layer 330 may be
formed on the first antenna insulation layer 320.
[0094] The radiator pattern layer 330 may be electrically connected
to the third transmission contact 312e formed in the first antenna
insulation layer 320. The first transmission contact 312a, the
first transmission wiring 312b, the second transmission contact
312c, the second transmission wiring 312d, and the third
transmission contact 312e may be provided as the transmission line
312. Accordingly, the radiator pattern layer 330 may be
electrically connected to the core connection wiring 122 by the
transmission line 312.
[0095] Referring to FIG. 19, the second antenna insulation layer
340 may be formed on the radiator pattern layer 330. The first
director pattern layer 350a may be formed on an upper surface of
the second antenna insulation layer 340, and the second director
pattern layer 350b may be formed on a lower surface of the second
antenna insulation layer 340. The second antenna insulation layer
340 having the first and second director pattern layers 350a an
350b formed thereon may be adhered on the radiator pattern layer
330 in the form of a core substrate.
[0096] The first and second director pattern layers 350a and 350b
may have shapes corresponding to each other. Additionally, the
radiator pattern layer 330 may have a shape corresponding to the
first and second director pattern layers 350a and 350b.
[0097] FIG. 20 is a cross-sectional view illustrating a
semiconductor package in accordance with example embodiments. The
semiconductor package may be substantially the same as or similar
to the semiconductor package described with reference to FIG. 16,
except for an upper redistribution wiring layer and an additional
second package. Thus, same reference numerals will be used to refer
to the same or like elements and any further repetitive explanation
concerning the above elements will be omitted.
[0098] Referring to FIG. 20, a fan-out package 500 of a
semiconductor package 12 may include a mold substrate 530 as a
frame surrounding a semiconductor chip 200. The fan-out package 500
may include a redistribution wiring layer 510, the semiconductor
chip 200 arranged on the redistribution wiring layer 510 and the
mold substrate 530 on the redistribution wiring layer to cover the
semiconductor chip 200. The mold substrate 530 may include
conductive connection members 532 as core connection wirings, which
are provided in a fan-out region outside an area where the
semiconductor chip is arranged, to function as an electrical
connection path with the semiconductor chip 200. Accordingly, the
semiconductor package 12 may be provided as a fan-out wafer level
package.
[0099] In example embodiments, the redistribution wiring layer 510
may include a plurality of redistribution wirings 522 electrically
connected to chip pads 210 of the semiconductor chip 200 and the
conductive connection members 532, respectively. The conductive
connection member 532 may include a conductive connection column
532a and a conductive connection pattern 532b.
[0100] The semiconductor chip 200 may be mounted on the
redistribution wiring layer 510 in a flip chip mounting manner. In
this case, the semiconductor chip 200 may be mounted on the
redistribution wiring layer 510 such that an active surface, on
which the chip pads 210 are formed, of the semiconductor chip 200
faces the redistribution wiring layer 510. The chip pads 210 of the
semiconductor chip 200 may be electrically connected to bonding
pads of fourth redistribution wirings 522d of the redistribution
wiring layer 510 by conductive bumps, e.g., solder bumps 220.
[0101] The mold substrate 530 may be provided on the redistribution
wiring layer 510 to cover the semiconductor chip 200. For example,
the mold substrate 530 may include epoxy molding compound
(EMC).
[0102] The first transmission contact 312a, the first transmission
wiring 312b, the second transmission contact 312c, the second
transmission wiring 312d, and the third transmission contact 312e
may be provided as the transmission line 312. Accordingly, the
radiator pattern layer 330 may be electrically connected to the
conductive connection member 532 as the core connection wiring by
the transmission line 312.
[0103] Hereinafter, a method of manufacturing the semiconductor
package in FIG. 20 will be explained.
[0104] FIGS. 21 to 29 are cross-sectional views illustrating stages
in a method of manufacturing a semiconductor package in accordance
with example embodiments.
[0105] Referring to FIGS. 21 and 22, the redistribution wiring
layer 510 may be formed on a dummy substrate 22. In example
embodiments, first, the first redistribution wirings 522a may be
formed on the dummy substrate 22, and then, the first lower
insulation layer 520a having first openings which expose portions
of the first redistribution wirings 522a may be formed on the dummy
substrate 22.
[0106] The dummy substrate 22 may be used as a base substrate on
which the redistribution wiring layer is formed. At least one
semiconductor chip is stacked on the redistribution wiring layer,
and a mold substrate is to be formed to cover the semiconductor
chip. The dummy substrate 22 may have a size corresponding to a
wafer on which a semiconductor fabrication process is performed.
The dummy substrate 22 may include, e.g., a silicon substrate, a
glass substrate, or a non-metal or metal plate.
[0107] Then, the second redistribution wirings 522b may be formed
on the first lower insulation layer 520a on the dummy substrate 22
to make contact with the first redistribution wirings 522a through
the first openings. Then, the second lower insulation layer 520b
having second openings which expose portions of the second
redistribution wirings 522b may be formed on the first lower
insulation layer 520a.
[0108] Then, the third redistribution wirings 522c may be formed on
the second lower insulation layer 520b to make contact with the
second redistribution wirings 522b through the second openings.
Then, the third lower insulation layer 520c having third openings
which expose portions of the third redistribution wirings 522c may
be formed on the second lower insulation layer 520b.
[0109] Then, the fourth redistribution wirings 522d may be formed
on the third lower insulation layer 520c to make contact with the
third redistribution wirings 522c through the third openings. Then,
the fourth lower insulation layer 520d having fourth openings which
expose portions of the fourth redistribution wirings 522d may be
formed on the third lower insulation layer 520c.
[0110] Thus, the redistribution wiring layer 510 having the
redistribution wirings 522 may be formed on the dummy substrate
22.
[0111] Referring to FIG. 23, the semiconductor chip 200 may be
stacked on the redistribution wiring layer 510. In example
embodiments, the semiconductor chip 200 may be mounted on the
redistribution wiring layer 510 in a flip chip bonding manner. In
this case, the semiconductor chip 200 may be mounted on the
redistribution wiring layer 510 such that an active surface,
including the chip pads 210, of the semiconductor chip 200 faces
the redistribution wiring layer 510. The chip pads 210 of the
semiconductor chip 200 may be electrically connected to bonding
pads of the fourth redistribution wirings 522d of the
redistribution wiring layer 510 by conductive bumps, e.g., solder
bumps 220. An underfill member may be filled between the active
surface of the semiconductor chip 200 and an upper surface of the
redistribution wiring layer 510.
[0112] Referring to FIG. 24, the mold substrate 530 may be formed
on the redistribution wiring layer 510 to cover the semiconductor
chip 200. In example embodiments, the mold substrate 530 covering
the semiconductor chip 200 may be formed by a molding process. For
example, the mold substrate 530 may include epoxy molding compound
(EMC).
[0113] Referring to FIGS. 25 and 26, openings 531 may be formed in
the mold substrate 530 to expose conductive connection column
regions, respectively. Then, the conductive connection members 532
as core connection wirings may be formed in the openings 531,
respectively. The conductive connection member 532 may include the
conductive connection column 532a and the conductive connection
pattern 532b.
[0114] For example, the openings 531 may be formed by a laser
drilling process. A plating process may be performed on the pad
exposed by the opening 531 to form the conductive connection column
532a. After a seed layer is formed on an upper surface of the mold
substrate 530, the seed layer may be patterned to form the
conductive connection pattern 532b.
[0115] Referring to FIGS. 27 and 28, a first upper insulation layer
540 may be formed on the mold substrate 530, and then, the ground
pattern layer 310 may be formed on the first upper insulation layer
540. Then, a second upper insulation layer 550 and the first
antenna insulation layer 320 may be formed on the first upper
insulation layer 540 to cover the ground pattern layer 310. Then,
the radiator pattern layer 330 may be formed on the first antenna
insulation layer 320.
[0116] In example embodiments, the first and second upper
insulation layers 540 and 550 may be formed by a vapor deposition
process, a spin coating process, etc. The first and second upper
insulation layers 540 and 550 may include, e.g., a polymer layer, a
dielectric layer, etc. Alternatively, the first and second upper
insulation layers 540 and 550 may include a photo imageable
dielectric (PID) material.
[0117] After the first upper insulation layer 540 is patterned to
form the first transmission contact 312a, the first transmission
wiring 312b as a first upper redistribution wiring may be formed on
the first upper insulation layer 540. After the second upper
insulation layer 550 is patterned to form the second transmission
contact 312c, the second transmission wiring 312d as a second upper
redistribution wiring may be formed on the second upper insulation
layer 550.
[0118] After the first antenna insulation layer 320 is patterned to
form the third transmission contact 312e, the radiator pattern
layer 330 as a third upper redistribution wiring may be formed on
the first antenna insulation layer 320. The radiator pattern layer
330 may be electrically connected to the third transmission contact
312e.
[0119] The first transmission contact 312a, the first transmission
wiring 312b, the second transmission contact 312c, the second
transmission wiring 312d, and the third transmission contact 312e
may be provided as the transmission line 312. Accordingly, the
radiator pattern layer 330 may be electrically connected to the
conductive connection member 532 as the core connection wiring by
the transmission line 312.
[0120] Referring to FIG. 29, the second antenna insulation layer
340 may be formed on the radiator pattern layer 330. The first
director pattern layer 350a may be formed on the upper surface of
the second antenna insulation layer 340, and the second director
pattern layer 350b may be formed on the lower surface of the second
antenna insulation layer 340. The second antenna insulation layer
340 having the first and second director pattern layers 350a and
350b formed thereon may be adhered on the radiator pattern layer
330 in the form of a core substrate.
[0121] The first and second director pattern layers 350a and 350b
may have shapes corresponding to each other. Additionally, the
radiator pattern layer 330 may have a shape corresponding to the
first and second director pattern layers 350a and 350b.
[0122] By way of summation and review, due to an increase in
thickness of a dielectric material in an antenna implemented in an
AiP, in which the RFIC is mounted, warpage due to a difference in
thermal expansion coefficients may occur, and new dielectric
material and antenna structure may be required in order to prevent
loss in a feed line and improve antenna radiation gain. Therefore,
example embodiments provide a semiconductor package capable of
preventing warpage and improving antenna radiation gain, and a
method of manufacturing the same.
[0123] That is, according to example embodiments, a semiconductor
package may include a fan-out package and an antenna structure on
the fan-out package. The antenna structure may include a ground
pattern layer, a first antenna insulation layer, a radiator pattern
layer, a second antenna insulation layer, and a director pattern
layer sequentially stacked on one another. The antenna structure
may be disposed on and separated from a frame in which a
semiconductor chip is mounted, by the ground pattern layer. A
second thermal expansion coefficient of the second antenna
insulation layer may be smaller than a first thermal expansion
coefficient of the first antenna insulation layer, and the second
thermal expansion coefficient of the second antenna insulation
layer may be the same as or similar to a thermal expansion
coefficient of the frame. Additionally, a thickness of the second
antenna insulation layer may be greater than a thickness of the
first antenna insulation layer. Accordingly, warpage due to a
difference in thermal expansion coefficient between the fan-out
package and the antenna structure may be prevented, the thickness
of the antenna insulation layer may be increased, and thus, antenna
radiation gain may be improved.
[0124] Example embodiments have been disclosed herein, and although
specific terms are employed, they are used and are to be
interpreted in a generic and descriptive sense only and not for
purpose of limitation. In some instances, as would be apparent to
one of ordinary skill in the art as of the filing of the present
application, features, characteristics, and/or elements described
in connection with a particular embodiment may be used singly or in
combination with features, characteristics, and/or elements
described in connection with other embodiments unless otherwise
specifically indicated. Accordingly, it will be understood by those
of skill in the art that various changes in form and details may be
made without departing from the spirit and scope of the present
invention as set forth in the following claims.
* * * * *