U.S. patent application number 16/667921 was filed with the patent office on 2021-05-06 for gate oxide forming process.
The applicant listed for this patent is UNITED MICROELECTRONICS CORP.. Invention is credited to Chun-Lin Chen, Sheng-Chen Chung, Chen-An Kuo, Chiu-Te Lee, Yi-Han Su, Chih-Chung Wang, Yuan-Cheng Yang.
Application Number | 20210134679 16/667921 |
Document ID | / |
Family ID | 1000005535225 |
Filed Date | 2021-05-06 |
United States Patent
Application |
20210134679 |
Kind Code |
A1 |
Yang; Yuan-Cheng ; et
al. |
May 6, 2021 |
GATE OXIDE FORMING PROCESS
Abstract
A gate oxide forming process includes the following steps. A
substrate including a first area and a second area is provided. A
first oxide layer, a silicon containing cap layer and a second
oxide layer on the substrate of the first area and the second area
are sequentially and blanketly formed. The silicon containing cap
layer and the second oxide layer in the first area are removed. An
oxidation process is performed to oxidize the silicon containing
cap layer and a gate oxide layer is formed in the second area.
Inventors: |
Yang; Yuan-Cheng; (Kaohsiung
City, TW) ; Su; Yi-Han; (Pingtung County, TW)
; Chung; Sheng-Chen; (Tainan City, TW) ; Kuo;
Chen-An; (Taoyuan City, TW) ; Chen; Chun-Lin;
(Tainan City, TW) ; Lee; Chiu-Te; (Hsinchu County,
TW) ; Wang; Chih-Chung; (Hsinchu City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
UNITED MICROELECTRONICS CORP. |
Hsin-chu City |
|
TW |
|
|
Family ID: |
1000005535225 |
Appl. No.: |
16/667921 |
Filed: |
October 30, 2019 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/823481 20130101;
H01L 21/823462 20130101; H01L 21/8249 20130101 |
International
Class: |
H01L 21/8234 20060101
H01L021/8234; H01L 21/8249 20060101 H01L021/8249 |
Claims
1. A gate oxide forming process, comprising: providing a substrate
comprising a first area and a second area; sequentially and
blanketly forming a first oxide layer, a silicon containing cap
layer and a second oxide layer on the substrate of the first area
and the second area; removing the silicon containing cap layer and
the second oxide layer in the first area; and performing an
oxidation process to oxidize the silicon containing cap layer
completely and thus forming a gate oxide layer in the second
area.
2. The gate oxide forming process according to claim 1, wherein the
first area is a low voltage area while the second area is a medium
voltage area.
3. The gate oxide forming process according to claim 1, wherein the
silicon containing cap layer comprises a silicon layer or a
polysilicon layer.
4. The gate oxide forming process according to claim 1, wherein the
oxidation process comprises a rapid thermal oxide process.
5. The gate oxide forming process according to claim 1, wherein the
steps of removing the silicon containing cap layer and the second
oxide layer in the first area comprise: forming a photoresist
covering the second oxide layer of the second area but exposing the
second oxide layer of the first area; and removing the silicon
containing cap layer and the second oxide layer in the first area;
and removing the photoresist.
6. The gate oxide forming process according to claim 1, further
comprising: forming a first well in the substrate of the first
area, and a second well in the substrate of the second area before
the oxidation process is performed.
7. The gate oxide forming process according to claim 6, wherein the
first well and the second well are both formed by performing an
implantation process and then a thermal process.
8. The gate oxide forming process according to claim 7, wherein the
thermal process comprises a rapid thermal processing (RTP)
process.
9. The gate oxide forming process according to claim 6, further
comprising: removing the first oxide layer in the first area after
the first well and the second well are formed; and forming a first
gate oxide layer on the substrate of the first area.
10. The gate oxide forming process according to claim 9, wherein
the first gate oxide layer is formed by performing the oxidation
process.
11. The gate oxide forming process according to claim 10, wherein
the first gate oxide layer is an input/output gate oxide layer in
an input/output area.
12. The gate oxide forming process according to claim 11, further
comprising: forming a second gate oxide layer in a logic area.
13. The gate oxide forming process according to claim 1, further
comprising: forming an isolation structure in the substrate before
the silicon containing cap layer and the second oxide layer are
formed.
14. The gate oxide forming process according to claim 13, wherein
the steps of forming the isolation structure comprise: sequentially
forming the first oxide layer and a nitride layer on the substrate;
etching the first oxide layer, the nitride layer and the substrate
to form a recess; forming the isolation structure in the recess;
and removing the nitride layer.
Description
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0001] The present invention relates generally to a gate oxide
forming process, and more specifically to a gate oxide forming
process in different areas.
2. Description of the Prior Art
[0002] In integrated circuits, applied voltage to transistors in a
high voltage component area is much higher than the applied voltage
to transistors in a logic circuit area. Thus, thicknesses of buffer
layers or dielectric layers of the transistors in the high voltage
component area should be larger than the thicknesses of buffer
layers or dielectric layers of the transistors in the logic circuit
area.
[0003] Fabricating transistors in the high voltage component area
and in the logic circuit area includes the following steps. A thick
oxide layer suited for usage in transistors in the high voltage
component area is formed on a substrate in the high voltage
component area and in the logic circuit area. Then, the thick oxide
layer in the logic circuit area is removed and a thinner oxide
layer suited for usage in transistors in the logic circuit area is
formed to replace the thick oxide layer. After the thick oxide
layer is formed in the high voltage component area and the thinner
oxide layer is formed in the logic circuit area, a polysilicon
layer is formed on the oxide layer in the two areas at the same
time. Thereafter, the polysilicon layer, the thick oxide layer and
the thinner oxide layer are sequentially patterned. Sequential
transistor processes are then performed.
SUMMARY OF THE INVENTION
[0004] The present invention provides a gate oxide forming process,
which integrates devices of two different voltage areas without
extra thermal budget impact.
[0005] The present invention provides a gate oxide forming process
including the following steps. A substrate including a first area
and a second area is provided. A first oxide layer, a silicon
containing cap layer and a second oxide layer on the substrate of
the first area and the second area are sequentially and blanketly
formed. The silicon containing cap layer and the second oxide layer
in the first area are removed. An oxidation process is performed to
oxidize the silicon containing cap layer and a gate oxide layer is
therefore formed in the second area.
[0006] According to the above, the present invention provides a
gate oxide forming process, which sequentially and blanketly forms
a first oxide layer, a silicon containing cap layer and a second
oxide layer on a substrate of a first area and a second area;
removes the silicon containing cap layer and the second oxide layer
in the first area; and performs an oxidation process to oxidize the
silicon containing cap layer and thus forms a gate oxide layer in
the second area. Thereby, gate oxide layers with different
thicknesses in the first area and the second area can be formed. By
using the method of the present invention, devices in the second
area can be integrated with devices in the first area without extra
thermal budget impact, and the uniformity of the breakdown voltage
of a formed device can be improved.
[0007] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0008] FIG. 1 schematically depicts a cross-sectional view of a
gate oxide forming process according to an embodiment of the
present invention.
[0009] FIG. 2 schematically depicts a cross-sectional view of a
gate oxide forming process according to an embodiment of the
present invention.
[0010] FIG. 3 schematically depicts a cross-sectional view of a
gate oxide forming process according to an embodiment of the
present invention.
[0011] FIG. 4 schematically depicts a cross-sectional view of a
gate oxide forming process according to an embodiment of the
present invention.
[0012] FIG. 5 schematically depicts a cross-sectional view of a
gate oxide forming process according to an embodiment of the
present invention.
[0013] FIG. 6 schematically depicts a cross-sectional view of a
gate oxide forming process according to an embodiment of the
present invention.
[0014] FIG. 7 schematically depicts a cross-sectional view of a
gate oxide forming process according to an embodiment of the
present invention.
[0015] FIG. 8 schematically depicts a cross-sectional view of a
gate oxide forming process according to an embodiment of the
present invention.
[0016] FIG. 9 schematically depicts a cross-sectional view of a
gate oxide forming process according to an embodiment of the
present invention.
DETAILED DESCRIPTION
[0017] FIGS. 1-9 schematically depict cross-sectional views of a
gate oxide forming process according to an embodiment of the
present invention. As shown in FIG. 1, a substrate 110 is provided.
The substrate 110 may be a semiconductor substrate such as a
silicon substrate, a silicon containing substrate, a III-V
group-on-silicon (such as GaN-on-silicon) substrate, a
graphene-on-silicon substrate, a silicon-on-insulator (SOI)
substrate or a substrate containing epitaxial layers etc. The
substrate 110 may include a first area A and a second area B, but
it is not limited thereto. The substrate 110 may further include
other areas (not shown). In this embodiment, the first area A is a
low voltage area while the second area B is a medium voltage area,
so that the thickness of a gate oxide layer on the substrate 110 of
the first area A is thinner than the thickness of a gate oxide
layer on the substrate 110 of the second area B. The method of the
present invention described as follows can be applied in a
bipolar-CMOS-DMOS (BCD) process or other processes of multiple
voltage areas.
[0018] Isolation structures 30 may be formed in the substrate 110.
The isolation structures 30 maybe shallow trench isolation
structures, which may be formed by a shallow trench isolation
process, but it is not limited thereto. Methods of forming the
isolation structures 30 may include the following. A first oxide
layer (not shown) and a nitride layer (not shown) maybe
sequentially formed on the substrate 110 of the first area A and
the second area B. The first oxide layer (not shown) and the
nitride layer (not shown) may be deposited by atomic layer
deposition (ALD) processes or chemical vapor deposition (CVD)
processes, but it is not restricted thereto. The first oxide layer
(not shown), the nitride layer (not shown) and the substrate 110
are etched to form recesses R in a first oxide layer 10, a nitride
layer 20 and the substrate 110. The isolation structures 30 fill in
the recesses R.
[0019] Then, the nitride layer 20 is removed, as shown in FIG. 2.
In this embodiment, the first oxide layer 10 is a pad oxide layer
for forming the isolation structures 30. In other embodiments, the
first oxide layer 10 maybe formed blanketly after the isolation
structures 30 are carried out. For example, the thickness of the
first oxide layer 10 is 110 angstroms.
[0020] As shown in FIG. 3, a silicon containing cap layer 120 is
formed on the substrate 110 of the first area A and the second area
B blanketly. The silicon containing cap layer 120 may include a
silicon layer, a polysilicon layer or etc. The silicon containing
cap layer 120 may be deposited by an atomic layer deposition (ALD)
processes or a chemical vapor deposition (CVD) process, but it is
not restricted thereto. For example, the thickness of the silicon
containing cap layer 120 is 10-20 angstroms.
[0021] As shown in FIG. 4, a second oxide layer 130 is formed on
the silicon containing cap layer 120 of the first area A and the
second area B blanketly. The second oxide layer 130 may be
deposited by an atomic layer deposition (ALD) processes or a
chemical vapor deposition (CVD) process, but it is not restricted
thereto. For example, the thickness of the second oxide layer 130
is 15-20 angstroms.
[0022] Please refer to FIGs.5-6, the second oxide layer 130 and the
silicon containing cap layer 120 are removed only in the first area
A, and the second oxide layer 130 and the silicon containing cap
layer 120 are reserved in the second area B. As shown in FIG. 5, a
photoresist P may be formed by coating and then patterning to cover
the second oxide layer 130 of the second area B but exposes the
second oxide layer 130 of the first area A. Thereafter, the silicon
containing cap layer 120 and the second oxide layer 130 in the
first area A are removed, and thus a silicon containing cap layer
120a and a second oxide layer 130a only in the second area B are
formed, and the first oxide layer 10 in the first area A is
exposed, as shown in FIG. 6. The photoresist P is then removed.
[0023] A first well 42 is formed on the substrate 110 of the first
area A, and a second well 44 is formed on the substrate 110 of the
second area B. The first well 42 and the second well 44 may be
formed on the substrate 110 of the first area A and the second area
B respectively by different implant processes. Due to the first
oxide layer 10 covering the substrate 110 of the first area A and
the first oxide layer 10, the silicon containing cap layer 120a and
the second oxide layer 130a covering the substrate 110 of the
second area B, the substrate 110 can be prevented from damage and
the performance of the first well 42 and the second well 44 is
improved. Then, a thermal process Q1 may be performed to active the
first well 42 and the second well 44. The thermal process Q1 may be
a rapid thermal processing (RTP) process, but it is not limited
thereto.
[0024] Thereafter, the first oxide layer 10 in the first area A is
removed after the first well 42 and the second well 44 are formed,
thereby a first oxide layer 10a only on the substrate 110 of the
second area B being formed and the substrate 110 in the first area
A being exposed, as shown in FIG. 7.
[0025] Please refer to FIGS. 7-8, a first gate oxide layer 140 is
formed on the substrate 110 of the first area A and a gate oxide
layer K1 is formed on the substrate 110 of the second area B. In
this embodiment, an oxidation process Q2 is performed to not only
form the first gate oxide layer 140 on the substrate 110 of the
first area A, but also oxidize the silicon containing cap layer
120a on the substrate 110 of the second area B, therefore forming
the gate oxide layer K1 in the second area B, wherein the gate
oxide layer K1 is constituted by the first oxide layer 10 in the
second area B, a silicon oxide layer 120b transferring from the
silicon containing cap layer 120a and the second oxide layer 130a.
Preferably, the oxidation process is a rapid thermal oxide (RTO)
process, but it is not limited thereto. Since the first area A is a
low voltage area while the second area B is a medium voltage area
in this case, a thickness t1 of the first gate oxide layer 140 on
the substrate 110 of the first area A is thinner than a thickness
t2 of the gate oxide layer K1 on the substrate 110 of the second
area B. By doing this, only one photoresist P is applied and one
oxidation process Q2 is processed to form the first gate oxide
layer 140 in first area A and the gate oxide layer K1 in the second
area B. Thus, devices in the second area B (meaning the medium
voltage area in this case) can be integrated with devices in the
first area A (meaning the low voltage area in this case) without
extra thermal budget impact, hence keeping the performance of the
devices in the low voltage area. Besides, the thickness t2 of the
gate oxide layer K1 is tunable, and the first oxide layer 10 in the
second area B can be prevented from damage because of the coverage
of the silicon containing cap layer 120a. As a result, the
uniformity of the breakdown voltage of a formed device can be
improved.
[0026] In one case, the first area A may include an input/output
area A1 and a logic area A2, as shown in FIG. 9. The first gate
oxide layer 140 of FIG. 8 is an input/output gate oxide layer, so
that the first gate oxide layer 140 in the logic area A2 is removed
to expose the substrate 110 while a first gate oxide layer 140a in
the input/output area A1 is reserved. Then, a second gate oxide
layer 140b is formed on the substrate 110 of the logic area A2. A
thickness t3 of the second gate oxide layer 140b is thinner than
the thickness t1 of the first gate oxide layer 140a.
[0027] In later processes, polysilicon gates may be disposed over
the gate oxide layer K1 in the second area B, the first gate oxide
layer 140a in the input/output area A1 and the second gate oxide
layer 140b in the logic area A2 at the same time or
respectively.
[0028] To summarize, the present invention provides a gate oxide
forming process, which sequentially and blanketly forms a first
oxide layer, a silicon containing cap layer and a second oxide
layer on a substrate of a first area and a second area; removes the
silicon containing cap layer and the second oxide layer in the
first area; and performs an oxidation process to oxidize the
silicon containing cap layer and therefore forms a gate oxide layer
in the second area. Thereby, gate oxide layers with different
thicknesses in the first area and the second area can be formed. By
using the method of the present invention, devices in the second
area can be integrated with devices in the first area A without
extra thermal budget impact, the performance of the devices in the
low voltage area can be kept, and the uniformity of the breakdown
voltage of a formed device can be improved.
[0029] Moreover, the first oxide layer in the first area may be
removed before the oxidation process is performed, so that a gate
oxide layer on the substrate of the first area can be formed while
the oxidation process is performed. A first well may be formed in
the substrate of the first area and a second well may be formed in
the substrate of the second area before the first oxide layer is
removed, thereby the substrate can being prevented from damage
while implanting.
[0030] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *