U.S. patent application number 17/070097 was filed with the patent office on 2021-02-18 for transistors with dual wells.
The applicant listed for this patent is TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Xiang-Zheng BO, Douglas T. GRIDER, Michelle N. NGUYEN.
Application Number | 20210050445 17/070097 |
Document ID | / |
Family ID | 1000005190682 |
Filed Date | 2021-02-18 |
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United States Patent
Application |
20210050445 |
Kind Code |
A1 |
BO; Xiang-Zheng ; et
al. |
February 18, 2021 |
TRANSISTORS WITH DUAL WELLS
Abstract
In some examples, a transistor includes a first well doped with
a first-type dopant having a first concentration. The transistor
also includes a gate oxide layer on a portion of the first well and
a gate layer on the gate oxide layer. The transistor further
includes a first segment of a second well doped with the first-type
dopant having a second concentration, the first segment
underlapping a first portion of the gate layer. The transistor also
includes a source region doped with a second-type dopant having a
third concentration, the source region in the first segment. The
transistor further includes a drain region doped with the
second-type dopant having a concentration that is substantially the
same as the third concentration.
Inventors: |
BO; Xiang-Zheng; (Plano,
TX) ; NGUYEN; Michelle N.; (Allen, TX) ;
GRIDER; Douglas T.; (McKinney, TX) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TEXAS INSTRUMENTS INCORPORATED |
Dallas |
TX |
US |
|
|
Family ID: |
1000005190682 |
Appl. No.: |
17/070097 |
Filed: |
October 14, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15871785 |
Jan 15, 2018 |
10811534 |
|
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17070097 |
|
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62611485 |
Dec 28, 2017 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 29/665 20130101;
H01L 29/66492 20130101; H01L 21/265 20130101; H01L 29/7835
20130101; H01L 29/66659 20130101; H01L 29/1045 20130101; H01L
29/6659 20130101 |
International
Class: |
H01L 29/78 20060101
H01L029/78; H01L 29/66 20060101 H01L029/66; H01L 21/265 20060101
H01L021/265; H01L 29/10 20060101 H01L029/10 |
Claims
1. A transistor comprising: a substrate having a first conductivity
type and a first dopant concentration; a gate dielectric layer over
a portion of the substrate and having first and second opposite
sidewalls; a gate electrode over the dielectric layer; a first
dielectric sidewall spacer on the first sidewall and a second
dielectric sidewall spacer on the second sidewall; a well having
the first conductivity type and a second dopant concentration, the
well underlapping first sidewall spacer; a first source/drain
region within the first well and having a second opposite
conductivity type; and a second source/drain region within the well
and adjacent the second sidewall spacer, having the second
conductivity type and having a third dopant concentration, the
second source/drain region extending toward the first source/drain
region no further than the second sidewall.
2. The transistor of claim 1, wherein the well is a first well and
further comprising a second well having the first conductivity type
and spaced apart laterally from the first well, the second
source/drain region located within the second well.
3. The transistor of claim 1, wherein the second well underlaps the
second sidewall spacer.
4. The transistor of claim 1, wherein the second well does not
underlap any portion of the gate electrode.
5. The transistor of claim 1, wherein the second source/drain
region touches the substrate.
6. The transistor of claim 1, wherein the first conductivity type
is p-type and the second conductivity type is n-type .
7. The transistor of claim 1, wherein the first-type dopant
comprises elements from group V and the second-type dopant
comprises elements from group III of the periodic table.
8. The transistor of claim 1, wherein the second concentration is
higher than the first concentration.
9. The transistor of claim 1 further comprising a corresponding
silicide layer formed on each of the first source/drain region, the
second source/drain region, and the gate layer electrode.
10. An integrated circuit, comprising: first and second doped
regions having a first conductivity type in a semiconductor
substrate region having the first conductivity type, the first and
second doped regions having a higher dopant concentration than the
semiconductor substrate region, the second doped region being
laterally offset from the first doped region, and an intervening
region of the semiconductor substrate region being located between
the first and second doped regions; a third doped region and first
extension both having a second opposite conductivity type within
the first doped region, and a fourth doped region and a second
extension both having the second conductivity type within the
second doped region, the first and second extensions being located
between and having a lower dopant concentration than the third and
fourth doped regions, the third doped region and the first
extension being isolated from the substrate region by the first
doped region, and the fourth doped region and the second extension
being isolated from the substrate region by the second doped
region; a dielectric layer directly on the intervening region; a
conductive structure between the third and fourth doped regions,
directly on the dielectric layer, and over at least one of the
first and second doped regions, the conductive structure having a
first sidewall and a second opposing sidewall; and a silicide layer
over the third and fourth doped regions, wherein the first
extension extends from the third doped region toward the conductive
structure no further than the first sidewall, and the second
extension extends from the fourth doped region toward the
conductive structure no further than the second sidewall.
11. The integrated circuit of claim 10, wherein the conductive
structure overlaps both the first and the second doped regions.
12. The integrated circuit of claim 10, wherein the conductive
structure overlaps only one of the first and the second doped
regions.
13. The integrated circuit of claim 10, wherein the third doped
region is configured to operate as a source of a MOSFET, the fourth
doped region is configured to operate as a drain of the MOSFET, and
the conductive structure is configured to operate as a gate
electrode of the MOSFET.
14. The integrated circuit of claim 10, wherein the first
conductivity type is p-type and the second conductivity type is
n-type.
15. The integrated circuit of claim 10, further comprising first
and second dielectric structures on opposing sidewalls of the
conductive structure, the first dielectric structure located over
the first extension, and the second dielectric structure located
over the second extension.
16. The integrated circuit of claim 10, wherein the third and
fourth doped regions have a higher dopant concentration than the
first and second doped regions.
17. An integrated circuit, comprising: a first doped region having
a first conductivity type in a semiconductor substrate region
having the first conductivity type, the first doped region having a
higher dopant concentration than the semiconductor substrate
region; a second doped region having a second different
conductivity type within the first doped region, the second doped
region including a first subregion having a higher dopant
concentration and a second subregion having a lower dopant
concentration, and the second doped region isolated from the
substrate region by the first doped region; a dielectric layer that
touches the first doped region and the second doped region; a
conductive structure and a sidewall dielectric structure, the
conductive structure touching the dielectric layer and overlapping
the first doped region and a portion of the semiconductor substrate
region that touches the dielectric layer, and the sidewall spacer
overlapping the second subregion; and a silicide layer over the
second doped region, wherein an interface between the second doped
region and the first doped region intersects a top surface of the
semiconductor substrate under the sidewall dielectric
structure.
18. The integrated circuit of claim 17, further comprising: a third
doped region having the first conductivity type within the
semiconductor substrate region; and a fourth doped region having
the second conductivity type within the third doped region, wherein
the portion of the semiconductor substrate region that touches the
dielectric layer is located between the first and third doped
regions.
19. The integrated circuit of claim 18, wherein the second doped
region has a higher dopant concentration than the first doped
region and the fourth doped region has a higher dopant
concentration than the third doped region.
20. The integrated circuit of claim 17, further comprising a
sidewall dielectric layer on the conductive structure over the
second subregion.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims priority to U.S. Provisional
Patent Application No. 62/611,485, which was filed Dec. 28, 2017,
is titled "Transistors With Dual Wells," and is hereby incorporated
herein by reference in its entirety. This application is a
divisional of U.S. patent application Ser. No. 15/871,785, issued
as U.S. Pat. No. 10,811,534, which is incorporated herein by
reference in its entirety
BACKGROUND
[0002] A transistor is the fundamental building block of modern day
electronic devices and is ubiquitously used in modern electronic
systems, such as smartphones, personal computers, etc. One of the
most common applications of a transistor is a switch. A transistor
that utilizes an electric field to control its switching ability is
known as a field effect transistor (FET).
SUMMARY
[0003] According to an example, a transistor comprises a first well
doped with a first-type dopant having a first concentration. The
transistor also includes a gate oxide layer on a portion of the
first well and a gate layer on the gate oxide layer. The transistor
further includes a first segment of a second well doped with the
first-type dopant having a second concentration, the first segment
underlapping a first portion of the gate layer. The transistor also
includes a source region doped with a second-type dopant having a
third concentration, the source region in the first segment. The
transistor further includes a drain region doped with the
second-type dopant having a concentration that is substantially the
same as the third concentration.
[0004] According to another example, a method to fabricate a
transistor comprises obtaining a substrate doped with a first-type
dopant having a first concentration, the substrate comprises a
first side and forms a first well. The method also includes
implanting the first-type dopant to form a second well with a first
segment and a second segment in the first well, the first and the
second segments having a second concentration that is substantially
equal to each other, the first segment interfacing with a first
portion of the first side, the second segment interfacing with a
second portion of the first side. The method further includes
growing a gate oxide layer on the first side, the gate oxide layer
having a second side interfacing the first side and further having
a third side opposite to the second side. The method also includes
depositing and patterning a gate layer on a third portion of the
third side, the third portion coincides with first portion to form
a first coinciding region under the gate layer and the third
portion coincides with the second portion to form a second
coinciding region under the gate layer. The method further includes
implanting a first lightly doped layer (LDL) in the first segment
and a second LDL in the second segment. The method then includes
implanting a source region in the first segment and a drain region
in the second segment, both the source and the drain regions doped
with a second type dopant, the source region overlaps with a fourth
portion of the first LDL layer and the first side, the drain region
overlaps with a fifth portion of the second LDL layer and the first
side.
[0005] According to yet another example, a transistor comprising a
first well doped with a first-type dopant having a first
concentration, the first well comprising a first side. The
transistor also includes a gate oxide layer having a second side
interfacing a first portion of the first side and further having a
third side opposite to the second side. The transistor also
includes a gate layer having a fourth side interfacing a second
portion of the third side. The transistor also includes a first
segment of a second well doped with the first-type dopant having a
second concentration, the first segment implanted in the first well
and overlapping a third portion of the first side, the third
portion coinciding with a fourth portion of the second side at a
first coinciding region below the gate layer. The transistor
further includes a second segment of the second well doped with the
first-type dopant having a concentration that is substantially the
same as the second concentration, the second segment implanted in
the first well and overlapping a fifth portion of the first side,
the fifth portion coinciding with a portion of the second side at a
second coinciding region below the gate layer. The transistor also
includes a source region doped with a second-type dopant having a
third concentration, the source region implanted in the first
segment. The transistor also includes a drain region doped with the
second-type dopant having a concentration that is substantially the
same as the third concentration, the drain region implanted in the
second segment.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] For a detailed description of various examples, reference
will now be made to the accompanying drawings in which:
[0007] FIG. 1 is a cross section of an illustrative transistor that
includes dual wells, in accordance with various examples.
[0008] FIG. 2(a)-2(b) depicts cross section of another illustrative
transistor that includes dual wells, in accordance with various
examples.
[0009] FIG. 3 is an illustrative method to fabricate an
illustrative transistor that includes dual wells, in accordance
with various examples.
[0010] FIG. 4(a)-FIG. 4(h) depict an illustrative step-by-step
fabrication process to fabricate an illustrative transistor that
includes dual wells, in accordance with various examples.
DETAILED DESCRIPTION
[0011] A FET typically includes a source region ("source"), a drain
region ("drain"), and a gate layer ("gate"). The source and drain
are fabricated in a substrate, and the gate is positioned on the
substrate. A FET controls the flow of carriers (electrons or holes)
from the source to the drain by affecting the size and/or the shape
of a conductive channel ("channel") generated by voltage (or lack
of voltage) applied at the gate. The channel is formed when the
voltage across the gate (or gate-to-source) is higher than a
threshold voltage. A FET is said to be "closed" or short-circuited
when the aforementioned channel exists, i.e., when the gate voltage
is higher than a threshold voltage and the channel provides a low
resistive path for the carriers to travel between the source and
the drain. A FET is said to be "open" or open-circuited when there
is no channel between the source and the drain, i.e., the voltage
applied across the gate and the source is below a threshold
voltage.
[0012] A FET can be characterized either as a p-type FET or an
n-type FET, depending on the type of dopant (p-type or n-type) used
to dope various portions (e.g., source, drain, and substrate) and
the type of majority carriers that form the channel in the FET. For
instance, an n-type FET forms a channel with electrons as the
majority carrier, and a p-type FET forms a channel with holes being
the majority carrier. A p-type FET typically includes a source and
a drain that is doped with a p-type dopant (e.g., group III
elements of the periodic table). The p-type FET further includes a
substrate that is doped with an n-type dopant (e.g., group V
elements of the periodic table.) However, an n-type FET includes a
source and a drain that is doped with an n-type dopant, and a
substrate that is doped with a p-type dopant.
[0013] For the sake of illustration, in the following description,
the case of an n-type FET is assumed. As a positive voltage is
applied to the gate layer of an n-type FET, a vertical electric
field is produced. This vertical electric field attracts electrons
from the body of the p-type substrate to the gate layer and repels
the holes present near the gate layer to the body of the substrate.
At a threshold voltage, the attracted electrons may move towards
the top surface of the substrate and become the dominant carrier in
a narrow layer at the surface, effectively making the narrow layer
n-type, i.e., dominant with electrons. This results in the
formation of a channel of electrons between the source and the
drain. The type of FET (n-type or p-type) dictates the carrier
(electron or hole) that may form the channel. For example, as
described above, an n-type FET may form a channel including
electrons as carriers. Using a similar principle, a p-type FET may
form a channel including holes as carriers.
[0014] In some cases, the length of the gate layer may be used as a
parameter to define the size of a transistor. In other cases, the
size of the transistor may be defined using other different
parameters (e.g., half pitch of the first metal). The size of a
transistor is an important parameter as it may dictate the
switching speed of an integrated circuit. Therefore, semiconductor
companies have been researching to scale down the size of a
transistor. A smaller transistor may assist in increasing the
overall performance of an integrated circuit (by increasing the
number of transistors that can be fabricated in the same amount of
area.) However, a small transistor size may bring about additional
challenges, such as sub-threshold leakage. For example, as
described above, a channel may form at the surface of a substrate
when a threshold voltage is applied to the gate layer. However, as
a transistor is scaled down in size, transistor threshold voltage
decreases as the due to merging of the source and drain depletion
regions. A leakage current may flow between the source and the
drain at the sub-threshold voltage.
[0015] Various techniques have been employed to reduce the
sub-threshold leakage. One of the techniques includes increasing
the channel doping concentration. However, increasing the channel
doping concentration lowers the mobility of the carriers in the
channel, and reduces the performance of a transistor. Other
techniques include using pocket implants at both the source and the
drain to increase the threshold voltage of the transistor. However,
pocket implants increase transistor mismatch and may further
degrade source/drain junction breakdown.
[0016] Accordingly, this disclosure uses dual well to improve
transistor performance. A relatively lower concentration dopant is
implanted into the substrate, making the substrate a first well. A
second well with relatively higher concentration dopant is
implanted in the source and/or the drain. In some examples, the
first well forming at least a portion of the channel improves the
carrier mobility, and the second well in the source and/or drain
regions may increase transistor threshold voltage and may further
reduce the transistor subthreshold voltage. Accordingly, at least
some of the examples in this disclosure are directed to a
transistor that has an improved (i.e., lower) sub-threshold
leakage, drive current and transconductance. In particular, the
examples disclosed herein are directed towards using dual wells,
with the substrate being the first well. The second well may be
implanted in the substrate such that the source region overlaps one
segment of the second well and the drain region overlaps the other
segment of the second well. Extensive correlation tests revealed
that transistors containing dual wells have a higher threshold
voltage relative to a transistor without the dual wells. The higher
the threshold voltage, the lower the sub-threshold leakage.
[0017] FIG. 1 is a cross section of an illustrative transistor 100
that includes dual wells. The transistor 100 includes a substrate
110 that may include silicon, which may be doped with an n-type
dopant or a p-type dopant. The doped substrate 110 may form the
first well. In some examples, the first well may be formed by
implanting dopants. For illustration's sake, it is assumed that the
transistor 100 is an n-type transistor, i.e., the substrate 110 is
doped with p-type dopants (e.g., elements from group III of the
periodic table of elements, such as boron) and a source region 140
and a drain region 150 are doped with n-type dopants (e.g.,
elements from group V of the periodic table of elements, such as
phosphorus). The scope of this disclosure is not limited to n-type
transistors. Similar principles, as described below, may be applied
to p-type transistors. In the case of p-type transistors, the first
well may, for example, be an n-type well formed in a p-type
substrate or an n-type substrate.
[0018] The illustrative transistor 100 includes a second well that
may include first segment 120 and a second segment 130. In this
disclosure, the combination of the first well (i.e., the substrate
110) and the second well (i.e., the first segment 120 and the
second segment 130) may sometimes be referred to as dual wells. The
transistor 100 further includes the source region 140, a source
contact layer 145, the drain region 150, a drain contact layer 155,
the source extension layer 143, the drain extension layer 153, a
gate layer 160, a gate contact layer 165, and a gate oxide layer
170. The transistor 100 also includes spacer regions 163, 164. The
substrate 110 includes a top side 112. The transistor 100 also
includes the gate oxide layer 170 having a bottom side 172 and a
top side 173, such that the bottom side 172 interfaces with the top
side 112.
[0019] The transistor 100 further depicts the gate layer 160 having
a bottom side 162 interfacing with the top side 172 along a portion
161, which may be referred to as the physical gate length. Stated
another way, the bottom side 162 of the gate layer 160 shares the
portion 161 with the top side 112. The substrate 110 further
includes the first segment 120 and the second segment 130, both of
which may be doped with the same type of dopant that is used to
dope the substrate 110. However, the doping concentration of the
first and the second segment 120, 130 may be high relative to the
doping concentration of the substrate 110. For example, the
substrate 110 may be doped with p-type dopants and may have a
concentration of 5.times.10.sup.15.about.1.times.10.sup.17
cm.sup.-3.The first and the second segment 120, 130 may be formed
by implanting additional p-type dopants in the substrate, such that
the doping concentrations of the first and the second segment may
be 5.times.10.sup.17.about.5.times.10.sup.18 cm.sup.-3. In some
examples, the concentration of first and the second segment may be
substantially (i.e., lie within a 10% range relative to each other)
equal. The first segment 120 may overlap a portion with the gate
16. This coinciding region is referred to as "CR1". The second
segment 130 may further overlap a portion 131 with the top side
112. The portion 131 may coincide with the portion 161 and this
coinciding region is referred to as "CR2". Stated another way, CR1
and CR2 are regions of the first segment 120 and the second segment
130 (respectively) that are present below the gate layer 160.
[0020] In some examples, the source region 140 and the drain region
150 are doped with a type of dopant that is complementary to the
dopant type used to dope the substrate 110, i.e., for an n-type
transistor, the substrate 110 is doped with a p-type dopant.
Complementary to the p-type dopants, the source and the drain
regions 140, 150 are doped with an n-type dopant. In some examples,
the source and the drain regions 140, 150 are highly doped and may
have a concentration of 1.times.10.sup.20.about.1.times.10.sup.21
cm.sup.-3. In some examples, the concentration of the source and
the drain regions 140, 150 may be substantially (i.e., lie within a
10% range relative to each other) equal. As depicted in FIG. 1, the
source region 140 is implanted such that the source region 140 is
positioned inside the first segment 120. The source region 140 may
also overlap along a portion 141 with the top side 112. Similar to
the source region 140, the drain region 150 may also be implanted
such that the drain region 150 is positioned in the second segment
120. The drain region 150 may also overlap along a portion 151 with
the top side 112. The source and drain extension layers 143, 153
are lightly doped with the same type of dopant that is used to dope
the source and the drain regions 140, 150, i.e., an n-type dopant.
The doping concentration of the extension layers 143, 153 may be
lower than the doping concentration of the source and the drain
regions 140, 150 and can be in the range of
5.times.10.sup.18.about.5.times.10.sup.19 cm.sup.-3. The first and
second extension layers 143, 153 may also overlap with the top side
112 and may also extend a portion 144 and a portion 154 to the
channel (CH) from the source 140 and the drain 150 (respectively).
In some examples, the channel CH extends from the source 140 to the
drain 150, respectively.
[0021] In some examples, the transistor 100 may be "symmetric",
i.e., the first and second segments 120, 130 may be of equal or
substantially equal (i.e., one within 10% of another) dimensions.
In such a case, the coinciding regions CR1 and CR2 may be of equal
or substantially equal lengths (i.e., one within 5%-10% of another)
and symmetric around the gate 160.
[0022] FIG. 2(a) depicts an illustrative transistor 100' that
includes the first and second segments 120, 130 of unequal
dimensions. Such transistors may also be referred to as
"asymmetric." In such example transistors, the coinciding regions
CR1 and CR2 may be of unequal lengths. In other examples, unequal
lengths of CR1, CR2 may include a portion 131 that may be smaller
than the portion 121 such that the portion 131 may not be
coincident with the portion 161 (as depicted in FIG. 2(a)). Stated
another way, unequal length may include a transistor 100' in which
there is no coinciding region CR2. In some examples, as depicted in
FIG. 2(b), the second segment 130 may not be present and in such a
case, there is no coinciding region CR2. In such examples, the
substrate 110 forming the first well improves the carrier mobility,
and the second well formed by the first segment 120 may increase
transistor threshold voltage and that may reduce the transistor
subthreshold voltage. The description of the transistor 100 (of
FIG. 1) may be valid for the transistors 100' of FIGS. 2(a) and
2(b).
[0023] As noted above, as a transistor is scaled down in size, a
sub-threshold leakage current may flow between the source and the
drain at the sub-threshold voltage. In this disclosure, the
sub-threshold leakage may improve due to the higher doping
concentration in the first segment 120. In some examples,
implanting the first segment 120 such that it overlaps the source
region 140 and is coincident with at least a portion (CR1) of the
gate layer 160 may improve the sub-threshold leakage by increasing
the threshold voltage. Referring now to FIG. 1, in operation, when
a gate voltage equal to or greater than a threshold voltage is
applied to the gate layer 160, a channel CH is formed in the
substrate 110. As depicted in FIG. 1, most of the channel CH is
formed in the substrate 110 (i.e., in the first well with lower
doping concentration relative to the second wells.) However, as the
size of a transistor decreases, the relative distance between the
source region 140, drain region 150, and the gate region 160 also
decreases. In such a case, the asymmetric transistor 100' (depicted
in FIG. 2(a) and FIG. 2(b)) may be used. The transistor 100'
includes the first segment 120 such that it completely overlaps the
source region 140 and shares some portion CR1 with the gate 160.
The second segment 130 in transistor 100' may overlap the drain
region 150, but the second segment 130 may not coincide with the
gate layer 160 under it, i.e., the CR2 region may not exist in the
transistor 100'.
[0024] FIG. 3 depicts an illustrative method 300 to fabricate a
transistor 100 (FIG. 1). For illustration's sake, it is assumed
that the transistor 100 is an n-type transistor. The method 300 is
described in tandem with FIG. 4(a)-FIG. 4(h), which illustrates the
step-by-step fabrication process that may be used to fabricate the
transistor 100. Step 310 includes obtaining a substrate 110 that is
doped with a first-type dopant. For clarity sake, FIG. 4(a) also
depicts the top side 112 and the length 111 of the substrate 110.
The substrate 110 (or the first well) may be implanted using ion
implantation with a p-type dopant. The doping concentration of the
substrate 110, as noted above, can be
5.times.10.sup.15.about.1.times.10.sup.17 cm.sup.-3. The method 300
further includes implanting the first-type dopants to form the
first segment 120 and the second segment 130 (step 320, FIG. 4(b)).
As noted above, the first and second segments 120, 130 are
implanted with the same dopant type as the type of dopant used to
dope the substrate 110. Therefore, the step 320 includes doping the
substrate with additional p-type dopants, i.e., the first and
second segments 120, 130 are areas in the substrate 110 that are
highly doped relative to the rest of the substrate 110. The first
and second segments 120, 130 depicted in FIG. 4(b) may be
symmetrical (as described above in FIG. 1). However, the step 320
may be adapted to include the first and second segments 120, 130
having unequal dimensions (as depicted in FIG. 2(a).) Similarly,
the step 320 may also be adapted to include just the first segment
120 (as depicted in FIG. 2(b).)
[0025] Completing the step 320 may include additional steps that
are not expressly recited in the method 300. The additional steps
may include first covering the substrate 110 with a photoresist and
then using masks/lithography techniques to pattern the photoresist.
Following the patterning step, additional p-type dopants may be
implanted using an ion implantation technique, which forms the
first segment 120 and the second segment 130. The depth of the
first and the second segments 120, 130 may depend on the
implantation energy, i.e., the more the implantation energy, the
deeper the wells. FIG. 4(b) also depicts the portion 121 and the
portion 131 that overlap with the top side 112.
[0026] The method 300 continues with growing a gate oxide layer
170(a) on the top side 112 of the substrate 110 (step 330, FIG.
4(c)). In some examples, the gate oxide layer 170(a) may be growing
by oxidizing the substrate 110 such that the top side 112 is
oxidized and forms the gate oxide layer 170(a). FIG. 4(c) also
depicts the bottom side 172 and the top side 173 of the gate oxide
layer 170(a). In other examples, other methods of oxidation, such
as in situ steam generation (ISSG) may be used. The method further
continues with depositing a gate layer 160 on a portion 161 of the
top side 173 (step 340, FIG. 4(d)). The deposition process may
include chemical vapor deposition that deposits materials such as
polysilicon to form the gate layer 160. The gate layer is then
patterned into the portion 161 by photo lithography and plasma dry
etch (step 340, FIG. 4(d)). FIG. 4(d) also depicts the coinciding
region CR1 between 120 and gate 160, and the coinciding region CR2
between 130 and gate 160, CR2.
[0027] The method 300 continues in step 350 (FIG. 4(e)) with
implanting a first lightly doped layer (LDL) 143(a) in the first
segment 120 and a second lightly doped layer (LDL) 153(a) in the
second segment 130. The first and the second LDLs 143(a) and 153(a)
are formed by implanting the type of dopant that is complementary
to the type of dopant used to dope the substrate 110, i.e., the LDL
143(a) and 153(a) are doped using n-type dopants, where each LDL
has a concentration of 5.times.10.sup.18.about.1.times.10.sup.20
cm.sup.-3. In some examples, the concentration of both the LDLs
143(a), 153(a) may be substantially (i.e., lie within a 2-10% range
relative to each other) equal. Different techniques may be used to
implant the LDLs, such as ion implantation. As noted above, the
implantation energy dictates the depth of the feature. Therefore,
while implanting the LDLs, the implantation energy may be such that
the LDLs form closer to the top side 112. FIG. 4(e) also depicts
the portion 144(a) and the portion 154(a) that overlaps with the
top side 112. In some examples, the step 350 may include oxidizing
the gate layer 160 such that a gate oxide layer similar to the gate
oxide layer 170(a) grows on the sides of the gate layer 160. The
method 300 may continue in step 360 (FIG. 4(f)) with depositing
spacer regions 163, 164, which may be done by chemical vapor
deposition and plasma spacer etch. Spacer region 163 may sometimes
be referred to as source spacer region and spacer region 164 may
sometimes be referred to as drain spacer region.
[0028] The method 300 then proceeds with implanting the source
region 140 and the drain region 150 in the first and second
segments 120, 130, respectively (step 370, FIG. 4(g)). As noted
above, the example described in this disclosure is of an n-type
transistor. Therefore, the source region 140 and the drain region
150 are implanted with the type of dopant that is complementary to
the type of dopant used to dope the substrate 110, i.e., an n-type
dopant. The doping concentration of both the source and the drain
regions 140, 150 may be 1.times.10.sup.20.about.1.times.10.sup.21
cm.sup.-3, which is relatively higher than the doping concentration
of the LDLs 143(a) and 143(b). FIG. 4(g) depicts a first extension
layer 143 and a second extension layer 153, which are parts of the
first and the second LDLs 143(a) and 153(a) (FIG. 4(e)),
respectively. Stated another way, because the doping concentrations
of the source and drain regions 140, 150 are substantially higher
than the doping concentrations of the LDLs 143(a) and 153(a), when
the source and the drain regions 140, 150 are implanted, portions
of the LDLs 143(a) and 153(a) are completely covered by the highly
concentrated source and drain regions 140, 150. Portions of the
LDLs 143(a) and 153(a) are not completely overlapped by the source
and the drain regions 140, 150 and they are referred to as
"extension regions" 143 and 153. The method 300 may also include
some additional steps that are not expressly shown in FIG. 3. The
method 300 may include etching the oxide layer 170(a) so as to
deposit on top of the source, the drain and the gate to form
silicide contact layers 145, 155, and 165 (FIG. 4(h)). Different
silicide, such as nickel-platinum silicide, titanium silicide,
cobalt silicide, may be used as the source, drain, and the gate
contact layers 145, 155, 165. The foregoing description is for an
n-type transistor 100. However, the scope of this disclosure is not
limited to n-type transistors. Similar principles may be applied
for different types of transistors, such as p-type transistors.
[0029] The above discussion is meant to be illustrative of the
principles and various embodiments of the present disclosure.
Numerous variations and modifications will become apparent to those
skilled in the art once the above disclosure is fully appreciated.
It is intended that the following claims be interpreted to embrace
all such variations and modifications.
* * * * *