Grider; Douglas T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Grider; Douglas T..The latest application filed is for "transistors with dual wells".

Company Profile

6.38.36

Grider; Douglas T. - McKinney TX
Grider; Douglas T - McKinney TX
Grider; Douglas T. - Pleasanton CA
Grider; Douglas T. - Raleigh NC

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Partially disposed gate layer into the trenches Grant 11,189,626 - Bo , et al. November 30, 2	2021-11-30
Integrated circuit including vertical capacitors Grant 11,152,068 - Bo , et al. October 19, 2	2021-10-19
Transistors With Dual Wells App 20210050445 - BO; Xiang-Zheng ; et al.	2021-02-18
Transistors with dual wells Grant 10,811,534 - Bo , et al. October 20, 2	2020-10-20
Integrated Circuit Including Vertical Capacitors App 20200219566 - BO; Xiang-Zheng ; et al.	2020-07-09
Integrated circuit including vertical capacitors Grant 10,622,073 - Bo , et al.	2020-04-14
Partially Disposed Gate Layer Into The Trenches App 20200006362 - BO; Xiang-Zheng ; et al.	2020-01-02
Integrated Circuit Including Vertical Capacitors App 20190348119 - BO; Xiang-Zheng ; et al.	2019-11-14
Partially disposed gate layer into the trenches Grant 10,446,563 - Bo , et al. Oc	2019-10-15
Partially Disposed Gate Layer Into The Trenches App 20190312045 - BO; Xiang-Zheng ; et al.	2019-10-10
Transistors With Dual Wells App 20190207025 - BO; Xiang-Zheng ; et al.	2019-07-04
High tilt angle plus twist drain extension implant for CHC lifetime improvement Grant 9,431,248 - Bo , et al. August 30, 2	2016-08-30
Three dimensional three semiconductor high-voltage capacitors Grant 9,318,337 - Bo , et al. April 19, 2	2016-04-19
High Tilt Angle Plus Twist Drain Extension Implant For Chc Lifetime Improvement App 20160027647 - Bo; Xiang-Zheng ; et al.	2016-01-28
High tilt angle plus twist drain extension implant for CHC lifetime improvement Grant 9,177,802 - Bo , et al. November 3, 2	2015-11-03
Three Dimensional Three Semiconductor High-Voltage Capacitors App 20150076577 - Bo; Xiangzheng ; et al.	2015-03-19
High performance CMOS transistors using PMD liner stress Grant 8,809,141 - Bu , et al. August 19, 2	2014-08-19
High Tilt Angle Plus Twist Drain Extension Implant For Chc Lifetime Improvement App 20140187008 - Bo; Xiang-Zheng ; et al.	2014-07-03
Polycrystalline Silicon Efuse And Resistor Fabrication In A Metal Replacement Gate Process App 20140011333 - McKee; Benjamin P. ; et al.	2014-01-09
Nitrogen based implants for defect reduction in strained silicon Grant 8,084,312 - Chakravarthi , et al. December 27, 2	2011-12-27
PMD liner nitride films and fabrication methods for improved NMOS performance Grant 8,084,787 - Bu , et al. December 27, 2	2011-12-27
Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps Grant 7,847,401 - Chidambaram , et al. December 7, 2	2010-12-07
Nitrogen Based Implants for Defect Reduction in Strained Silicon App 20100120215 - CHAKRAVARTHI; Srinivasan ; et al.	2010-05-13
Nitrogen based implants for defect reduction in strained silicon Grant 7,670,892 - Chakravarthi , et al. March 2, 2	2010-03-02
Methods, Systems and Structures for Forming Semiconductor Structures Incorporating High-Temperature Processing Steps App 20090224296 - Chidambaram; PR ; et al.	2009-09-10
Reliable high voltage gate dielectric layers using a dual nitridation process Grant 7,560,792 - Khamankar , et al. July 14, 2	2009-07-14
Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps Grant 7,553,718 - Chidambaram , et al. June 30, 2	2009-06-30
PMD Liner Nitride Films and Fabrication Methods for Improved NMOS Performance App 20080251850 - Bu; Haowen ; et al.	2008-10-16
Drive current improvement from recessed SiGe incorporation close to gate Grant 7,244,654 - Chidambaram , et al. July 17, 2	2007-07-17
High performance CMOS transistors using PMD liner stress App 20070128806 - Bu; Haowen ; et al.	2007-06-07
PMD liner nitride films and fabrication methods for improved NMOS performance Grant 7,226,834 - Bu , et al. June 5, 2	2007-06-05
Reliable high voltage gate dielectric layers using a dual nitridation process App 20070117331 - Khamankar; Rajesh ; et al.	2007-05-24
Nitrogen based implants for defect reduction in strained silicon App 20070105294 - Chakravarthi; Srinivasan ; et al.	2007-05-10
High performance CMOS transistors using PMD liner stress Grant 7,192,894 - Bu , et al. March 20, 2	2007-03-20
Reliable high voltage gate dielectric layers using a dual nitridation process Grant 7,183,165 - Khamankar , et al. February 27, 2	2007-02-27
Methods, systems and structures for forming semiconductor structures incorporating high-temperature processing steps App 20060172502 - Chidambaram; PR ; et al.	2006-08-03
High performance CMOS transistors using PMD linear stress App 20050245012 - Bu, Haowen ; et al.	2005-11-03
PMD liner nitride films and fabrication methods for improved NMOS performance App 20050233514 - Bu, Haowen ; et al.	2005-10-20
Method for transistor gate dielectric layer with uniform nitrogen concentration Grant 6,933,248 - Grider August 23, 2	2005-08-23
Method for transistor gate dielectric layer with uniform nitrogen concentration App 20050181625 - Grider, Douglas T.	2005-08-18
Drive current improvement from recessed SiGe incorporation close to gate App 20050139872 - Chidambaram, Pr ; et al.	2005-06-30
Semiconductor device isolation structure and method of forming App 20040238915 - Chen, Zhihao ; et al.	2004-12-02
Reliable high voltage gate dielectric layers using a dual nitridation process App 20040102010 - Khamankar, Rajesh ; et al.	2004-05-27
Semiconductor device isolation structure and method of forming Grant 6,737,333 - Chen , et al. May 18, 2	2004-05-18
Method of CMOS source/drain extension with the PMOS implant spaced by poly oxide and cap oxide from the gates Grant 6,737,354 - Miles , et al. May 18, 2	2004-05-18
Source/drain extension fabrication process with direct implantation Grant 6,709,938 - Miles , et al. March 23, 2	2004-03-23
Disposable spacer technology for reduced cost CMOS processing Grant 6,699,763 - Grider , et al. March 2, 2	2004-03-02
Multi-layered polysilicon process Grant 6,645,840 - Grider , et al. November 11, 2	2003-11-11
Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile Grant 6,632,747 - Niimi , et al. October 14, 2	2003-10-14
Disposable spacer technology for reduced cost CMOS processing Grant 6,632,718 - Grider , et al. October 14, 2	2003-10-14
Disposable spacer technology for reduced cost CMOS processing App 20030176033 - Grider, Douglas T. ; et al.	2003-09-18
Method for forming gate dielectrics of varying thicknesses on a wafer App 20030096466 - Eklund, Robert H. ; et al.	2003-05-22
Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile Grant 6,548,366 - Niimi , et al. April 15, 2	2003-04-15
Source/drain extension fabrication process with direct implantation App 20030040169 - Miles, Donald S. ; et al.	2003-02-27
Source/drain extension fabrication process App 20030017674 - Miles, Donald S. ; et al.	2003-01-23
Semiconductor device isolation structure and method of forming App 20030006476 - Chen, Zhihao ; et al.	2003-01-09
Temperature spike for uniform nitridization of ultra-thin silicon dioxide layers in transistor gates Grant 6,503,846 - Niimi , et al. January 7, 2	2003-01-07
Temperature Spike For Uniform Nitridization Of Ultra-thin Silicon Dioxide Layers In Transistor Gates App 20020197882 - Niimi, Hiroaki ; et al.	2002-12-26
Method of ammonia annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile App 20020197883 - Niimi, Hiroaki ; et al.	2002-12-26
Method of two-step annealing of ultra-thin silicon dioxide layers for uniform nitrogen profile App 20020197884 - Niimi, Hiroaki ; et al.	2002-12-26
Multi-thickness oxide growth with in-situ scanned laser heating App 20020098712 - Mavoori, Jaideep ; et al.	2002-07-25
Method for transistor gate dielectric layer with uniform nitrogen concentration App 20020072177 - Grider, Douglas T.	2002-06-13
Cost effective split-gate process that can independently optimize the low voltage(LV) and high voltage (HV) transistors to minimize reverse short channel effects App 20020052083 - Zhang, Xin ; et al.	2002-05-02
Multi-layered polysilicon process App 20020048918 - Grider, Douglas T. ; et al.	2002-04-25
Integrated circuit isolation Grant 6,326,281 - Violette , et al. December 4, 2	2001-12-04
Method of forming thin silicon nitride or silicon oxynitride gate dielectrics Grant 6,136,654 - Kraft , et al. October 24, 2	2000-10-24
Selective area halogen doping to achieve dual gate oxide thickness on a wafer Grant 6,093,659 - Grider , et al. July 25, 2	2000-07-25
Doped polysilicon to retard boron diffusion into and through thin gate dielectrics Grant 6,030,874 - Grider , et al. February 29, 2	2000-02-29
Product resulting from selective deposition of polysilicon over single crystal silicon substrate Grant 5,818,100 - Grider , et al. October 6, 1	1998-10-06
Implantation of a semiconductor substrate with controlled amount of noble gas ions to reduce channeling and/or diffusion of a boron dopant subsequently implanted into the substrate to form P- LDD region of a PMOS device Grant 5,585,286 - Aronowitz , et al. December 17, 1	1996-12-17
Selective deposition of doped silicon-germanium alloy on semiconductor substrate, and resulting structures Grant 5,336,903 - Ozturk , et al. August 9, 1	1994-08-09
Selective deposition of doped silion-germanium alloy on semiconductor substrate Grant 5,242,847 - Ozturk , et al. September 7, 1	1993-09-07

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