U.S. patent application number 17/000725 was filed with the patent office on 2020-12-10 for sinusoidal shaped capacitor architecture in oxide.
The applicant listed for this patent is Advanced Micro Devices, Inc.. Invention is credited to Richard T. Schultz.
Application Number | 20200388669 17/000725 |
Document ID | / |
Family ID | 1000005038089 |
Filed Date | 2020-12-10 |
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United States Patent
Application |
20200388669 |
Kind Code |
A1 |
Schultz; Richard T. |
December 10, 2020 |
SINUSOIDAL SHAPED CAPACITOR ARCHITECTURE IN OXIDE
Abstract
A system and method for fabricating metal insulator metal
capacitors while managing semiconductor processing yield and
increasing capacitance per area are described. A semiconductor
device fabrication process places an oxide layer on top of a metal
layer. A photoresist layer is formed on top of the oxide layer and
etched with repeating spacing. One of a variety of lithography
techniques is used to alter the distance between the spacings. The
process etches trenches into areas of the oxide layer unprotected
by the photoresist layer and strips the photoresist layer. The top
and bottom corners of the trenches are rounded. The process
deposits a bottom metal, a dielectric, and a top metal on the oxide
layer both on areas with the trenches and on areas without the
trenches. The process completes the metal insulator metal capacitor
with metal nodes contacting each of the top plate and the bottom
plate.
Inventors: |
Schultz; Richard T.; (Fort
Collins, CO) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Advanced Micro Devices, Inc. |
Santa Clara |
CA |
US |
|
|
Family ID: |
1000005038089 |
Appl. No.: |
17/000725 |
Filed: |
August 24, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15474043 |
Mar 30, 2017 |
10756164 |
|
|
17000725 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 28/90 20130101;
H01L 28/92 20130101; H01L 21/31111 20130101; H01L 21/02255
20130101; H01L 21/31144 20130101; H01L 28/84 20130101; H01L 23/5223
20130101; H01L 27/0755 20130101; H01L 28/40 20130101; H01L 21/76877
20130101; H01L 27/0777 20130101; H01L 21/32133 20130101; H01L 28/82
20130101; H01L 21/0223 20130101; H01L 21/0273 20130101; H01L
27/0716 20130101; H01L 21/32051 20130101; H01L 21/76802 20130101;
H01L 27/0788 20130101; H01L 27/0676 20130101; H01L 27/0805
20130101; H01L 27/0794 20130101 |
International
Class: |
H01L 49/02 20060101
H01L049/02; H01L 21/027 20060101 H01L021/027; H01L 21/311 20060101
H01L021/311; H01L 21/3205 20060101 H01L021/3205; H01L 21/02
20060101 H01L021/02; H01L 21/3213 20060101 H01L021/3213; H01L
21/768 20060101 H01L021/768; H01L 23/522 20060101 H01L023/522 |
Claims
1-20. (canceled)
21. A semiconductor device comprising: a first metal layer; an
oxide layer on top of the first metal layer, the oxide layer
comprising a first location that includes a plurality of trenches
and a second location that does not include trenches; and a
combination of layers on the oxide layer at the first location, the
combination of layers comprising a bottom metal layer, a dielectric
layer, and a top metal layer; wherein the second location has
formed thereon the bottom metal layer of the combination of layers
without the dielectric layer and the top metal layer.
22. The semiconductor device as recited in claim 21, wherein top
and bottom corners of the plurality of trenches are rounded.
23. The semiconductor device as recited in claim 21, further
comprising a first via at the second location creating contact with
the bottom metal layer.
24. The semiconductor device as recited in claim 23, wherein the
combination of layers at the first location form a
metal-insulator-metal (MIM) capacitor with an oscillating
pattern.
25. The semiconductor device as recited in claim 24, further
comprising a second via at a location creating contact with the top
metal layer.
26. The semiconductor device as recited in claim 25, further
comprising a second metal layer over the second via.
27. A semiconductor device fabrication process comprising: forming
a first metal layer; forming an oxide layer on top of the first
metal layer, the oxide layer comprising a first location that
includes a plurality of trenches and a second location that does
not include trenches; and forming a combination of layers on the
oxide layer at the first location, the combination of layers
comprising a bottom metal layer, a dielectric layer, and a top
metal layer; wherein the second location has formed thereon the
bottom metal layer of the combination of layers without the
dielectric layer and the top metal layer.
28. The semiconductor device fabrication process as recited in
claim 27, wherein top and bottom corners of the plurality of
trenches are rounded.
29. The semiconductor device fabrication process as recited in
claim 27, wherein a thickness of the oxide layer on top of the
first metal layer is at least an order of magnitude greater than a
thickness of a gate silicon dioxide layer formed for active
devices.
30. The semiconductor device fabrication process as recited in
claim 27, wherein the process further comprises placing a first via
at the second location creating contact with the bottom metal
layer.
31. The semiconductor device fabrication process as recited in
claim 27, wherein the combination of layers at the first location
form a metal-insulator-metal (MIM) capacitor with an oscillating
pattern.
32. The semiconductor device fabrication process as recited in
claim 31, wherein the process further comprises placing a second
via at a location creating contact with the top metal layer.
33. The semiconductor device fabrication process as recited in
claim 32, wherein the process further comprises placing a second
metal layer over the second via.
34. A method for fabricating a semiconductor device comprising:
depositing an oxide layer on top of a first metal layer, the oxide
layer having a first location and a second location; forming a
plurality of trenches in the oxide layer at the first location but
not the second location; depositing a bottom metal layer over the
oxide layer; depositing a dielectric layer on top of the bottom
metal layer; depositing a top metal layer on top of the dielectric
layer; and removing the top metal layer and the dielectric layer at
the second location of the oxide layer.
35. The method as recited in claim 34, further comprising rounding
top and bottom corners of the plurality of trenches.
36. The method as recited in claim 34, wherein a thickness of the
oxide layer on top of the first metal layer is at least an order of
magnitude greater than a thickness of a gate silicon dioxide layer
formed for active devices.
37. The method as recited in claim 34, further comprising placing a
first via at the second location creating contact with the bottom
metal layer.
38. The method as recited in claim 37, wherein the bottom metal
layer, dielectric layer, and top metal layer form a a
metal-insulator-metal (MIM) capacitor with an oscillating
pattern.
39. The method as recited in claim 38, further comprising placing a
second via at location creating contact with the top metal
layer.
40. The method as recited in claim 39, further comprising placing a
second metal layer over the second via.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of U.S. patent
application Ser. No. 15/474,043, entitled "SINUSOIDAL SHAPED
CAPACITOR ARCHITECTURE IN OXIDE", filed Mar. 30, 2017, the entirety
of which is incorporated herein by reference.
BACKGRUOUND
Description of the Relevant Art
[0002] As both semiconductor manufacturing processes advance and
on-die geometric dimensions reduce, semiconductor chips provide
more functionality and performance while consuming less space.
While many advances have been made, design issues still arise with
modern techniques in processing and integrated circuit design that
may limit potential benefits. For example, as the number and size
of passive components used in a design increase, the area consumed
by these components also increases. Impedance matching circuits,
harmonic filters, decoupling capacitors, bypass capacitors and so
on are examples of these components.
[0003] Many manufacturing processes use metal insulator metal (MIM)
capacitors to provide capacitance in both on-die integrated
circuits and off-chip integrated passive device (IPD) packages. A
MIM capacitor is formed with two parallel metal plates separated by
a dielectric layer. Generally speaking, each of the two metal
plates and the dielectric layer is parallel to a semiconductor
substrate surface. Such MIM capacitors are used in a variety of
integrated circuits, including oscillators and phase-shift networks
in radio frequency (RF) integrated circuits, as decoupling
capacitors to reduce noise in both mixed signal integrated circuits
and microprocessors as well as bypass capacitors near active
devices in microprocessors to limit the parasitic inductance, and
so on. MIM capacitors may also be used as memory cells in a dynamic
RAM.
[0004] Fabricating MIM capacitors is a challenging process. The
material selection for the dielectric layer is limited as many of
the materials used for the dielectric layer may diffuse with the
metal layers used for the parallel metal plates. This limited
selection can also reduce the capacitance per area that might
otherwise be achieved. Further, the dielectric layer is typically
larger than the gate oxide layer used for active devices such as
transistors. Therefore, the MIM capacitors are relatively large,
and at times, are larger than the transistors used on the die. When
the MIM capacitor sizes are increased to provide the necessary
capacitance per area (density), less space is available for other
components on the device. In addition, when etching to create space
for vias used for connecting the parallel metal plates of a MIM
capacitor, more insulating material is etched to reach the bottom
metal plate than to reach the top metal plate. Therefore, the
chance for etch stop problems increases.
[0005] In view of the above, efficient methods and systems for
fabricating metal insulator metal capacitors while managing
semiconductor processing yield and increasing capacitance per area
are desired.
BRIEF DESCRIPTION OF THE DRAWINGS
[0006] FIG. 1 is a generalized diagram of a cross-sectional view of
a portion of a semiconductor passive component being
fabricated.
[0007] FIG. 2 is a generalized diagram of a cross-sectional view of
a portion of a semiconductor passive component being
fabricated.
[0008] FIG. 3 is a generalized diagram of a cross-sectional view of
a portion of a semiconductor passive component being
fabricated.
[0009] FIG. 4 is a generalized diagram of a cross-sectional view of
a portion of a semiconductor passive component being
fabricated.
[0010] FIG. 5 is a generalized diagram of a cross-sectional view of
a portion of a semiconductor passive component being
fabricated.
[0011] FIG. 6 is a generalized diagram of a cross-sectional view of
a portion of a semiconductor passive component being
fabricated.
[0012] FIG. 7 is a generalized diagram of a cross-sectional view of
a portion of a semiconductor passive component being
fabricated.
[0013] FIG. 8 is a generalized diagram of a cross-sectional view of
a portion of a semiconductor passive component being
fabricated.
[0014] FIG. 9 is a generalized diagram of a cross-sectional view of
a portion of a semiconductor passive component being
fabricated.
[0015] FIG. 10 is a generalized diagram of a cross-sectional view
of a fabricated semiconductor metal-insulator-metal (MIM) capacitor
with an oscillating pattern.
[0016] FIG. 11 is a generalized diagram of a method for fabricating
a semiconductor metal-insulator-metal (MIM) capacitor with an
oscillating pattern.
[0017] While the invention is susceptible to various modifications
and alternative forms, specific embodiments are shown by way of
example in the drawings and are herein described in detail. It
should be understood, however, that drawings and detailed
description thereto are not intended to limit the invention to the
particular form disclosed, but on the contrary, the invention is to
cover all modifications, equivalents and alternatives falling
within the scope of the present invention as defined by the
appended claims.
DETAILED DESCRIPTION
[0018] In the following description, numerous specific details are
set forth to provide a thorough understanding of the present
invention. However, one having ordinary skill in the art should
recognize that the invention might be practiced without these
specific details. In some instances, well-known circuits,
structures, and techniques have not been shown in detail to avoid
obscuring the present invention. Further, it will be appreciated
that for simplicity and clarity of illustration, elements shown in
the figures have not necessarily been drawn to scale. For example,
the dimensions of some of the elements are exaggerated relative to
other elements.
[0019] Systems and methods for fabricating metal insulator metal
capacitors while managing semiconductor processing yield and
increasing capacitance per area are contemplated. In various
embodiments, a semiconductor device fabrication process places an
oxide layer on top of a metal layer. A photoresist layer is formed
on top of the oxide layer and etched with repeating spacing which
determines a frequency of an oscillating wave structure to be
formed later and used as a metal-insulator-metal (MIM) capacitor.
One of a variety of lithography techniques is used to reduce the
pitch (increase the frequency) of the trenches.
[0020] The process etches trenches into areas of the oxide layer
unprotected by the photoresist layer and then strips the
photoresist layer. The top and bottom corners of the trenches are
rounded to create a basis for the oscillating wave structure. In
some embodiments, the process uses relatively high temperature
oxidation steps to round the corners. The process deposits a
combination of layers including the bottom metal, dielectric and
top metal of the MIM capacitor on the oxide layer. The deposition
of the combination of layers is performed both on areas with the
trenches and on areas without the trenches. The process completes
the MIM capacitor with metal nodes contacting each of the top plate
and the bottom plate. As the frequency and depth of the trenches
increase, the density, such as the capacitance per area, of the MIM
capacitor also increases.
[0021] In the description of FIGS. 1-11 that follows, the
fabrication steps for a metal insulator metal capacitor with a
sinusoidal structure are described. Turning to FIG. 1, a
generalized block diagram of a cross-sectional view of a portion of
a semiconductor passive component being fabricated is shown. Unlike
active components, such as field effect transistors, passive
components are not turned on prior to controlling current flow by
means of another signal such as a voltage signal. There is no
threshold voltage for passive components. Here, a metal layer 102
is deposited on an inter-level dielectric (ILD), which is not
shown. In various embodiments, the ILD is used to insulate metal
layers which are used for interconnects. In some embodiments, the
ILD is silicon dioxide. In other embodiments, the ILD is one of a
variety of low-k dielectrics containing carbon or fluorine. The
low-k dielectrics provide a lower capacitance between the metal
layers, and thus, reduce performance loss, power consumption, and
cross talk between interconnect routes. A chemical mechanical
planarization (CMP) step is used to remove unwanted ILD and to
polish the remaining ILD. The CMP step achieves a near-perfect flat
and smooth surface upon which further layers are built.
[0022] Deposition of the metal layer 102 follows. In one
embodiment, the metal layer 102 is copper. In another embodiment,
the metal layer 102 is aluminum or a copper and aluminum mix. In
some embodiments, the metal layer 102 is formed by a dual damascene
process. In other embodiments the metal layer 102 formed by a
single damascene process. These and other techniques are
contemplated. In embodiments with copper used as the metal layer
102, a liner using a Ta based barrier material is deposited on the
dielectric before the metal layer 102 is formed. The liner prevents
the copper from diffusing into the dielectric and acts as an
adhesion layer for the copper. Next a thin copper seed layer is
deposited by physical vapor diffusion (PVD) followed by
electroplating of copper. Next the excess copper metal layer 102 is
chemical-mechanical-polished and a capping layer typically SiN
(silicon mononitride) is deposited. Afterward, an oxide layer 104
of a controlled thickness is formed. In various embodiments, the
oxide layer 104 is silicon dioxide.
[0023] In various embodiments, a plasma-enhanced chemical vapor
deposition (PECVD) process is used to deposit a thin film of
silicon dioxide from a gas state (vapor) to a solid state on the
metal layer 102. The PECVD process introduces reactant gases
between a grounded electrode and a parallel radio frequency (RF)
energized electrode. The capacitive coupling between the electrodes
excites the reactant gases into a plasma, which induces a chemical
reaction and results in the reaction product being deposited on the
metal layer 102.
[0024] In some embodiments, the oxide layer 104 is deposited using
a combination of gasses such as dichlorosilane or silane with
oxygen precursors, such as oxygen and nitrous oxide, typically at
pressures from a few millitorr to a few torr. The thickness of the
oxide layer 104 is relatively thick. For example, the thickness of
the oxide layer 104 is at least an order of magnitude greater than
a thickness of a thin gate silicon dioxide layer formed for active
devices such as transistors. After the oxide layer 104 is
deposited, a photoresist 106 is placed on the oxide layer 104 with
a pattern removed for initially defining the non-planar shape of
the metal insulator metal (MIM) capacitor.
[0025] The spacing of the etchings in the photoresist layer 106 is
set by the technique used to remove the photoresist layer 106. In
some embodiments, the extreme ultraviolet lithography (EUV)
technique is used to provide the resolution of each of the width
110 and the pitch 120. The EUV technique uses an extreme
ultraviolet wavelength to reach resolution below 40 nanometers. The
extreme ultraviolet wavelength is approximately 13.5 nanometers.
Relatively high temperature and high density plasma is used to
provide the EUV beam. In other embodiments, the directed
self-assembly (DSA) lithography technique used to provide the
resolution of each of the width 110 and the pitch 120. The DSA
technique takes advantage of the self-assembling properties of
materials to reach nanoscale dimensions.
[0026] In yet other embodiments, the immersion lithography
technique is used to provide the resolution of each of the width
110 and the pitch 120. Immersion lithography uses a liquid medium,
such as purified water, between the lens of the imaging equipment
and the wafer surface. Previously, the gap space was simply air.
The resolution achieved by this technique is the resolution of the
imaging equipment increased by the refractive index of the liquid
medium. In some examples, the increased resolution falls above 80
nanometers.
[0027] In further embodiments, the double patterning technique is
used to provide the resolution of each of the width 110 and the
pitch 120. The double patterning technique uses immersion optical
lithography systems to define features with resolution between 80
and 40 nanometers. Either of the self-aligned doubled patterning
(SADP) technique or the litho-etch-litho-etch technique (LELE) is
used. The double patterning technique counteracts the effects of
diffraction in optical lithography, which occurs when the minimum
dimensions of features on a wafer are less than the 193 nanometer
wavelength of the illuminating light source. Other examples of
techniques used to counteract the effects of diffraction in optical
lithography are phase-shift masks, optical-proximity correction
(OPC) techniques, optical equipment improvements and computational
lithography.
[0028] When selecting between immersion lithography, double
patterning, EUV and DSA techniques, and other techniques, cost is
considered as the cost increases from immersion lithography to EUV.
However, over time, the costs of these techniques adjust as well as
additional and newer techniques are developed for providing
relatively high resolution for the width 110 and the pitch 120.
Accordingly, one of a variety of lithography techniques is used to
provide relatively high resolution for the width 110 and the pitch
120. As described later, the relatively high resolution for the
width 110 and the pitch 120 provides a higher capacitance per area
density for a MIM capacitor being fabricated.
[0029] Referring to FIG. 2, a generalized block diagram of another
cross-sectional view of a portion of a semiconductor passive
component being fabricated is shown. Materials and layers described
earlier are numbered identically. As shown, regions of the oxide
layer 104 are etched. The etched trenches 210 are placed in regions
where the oxide layer 104 is unprotected by the photoresist 106. In
some embodiments, a dry etch process is used to provide the etched
trenches 210. A reactive-ion etching (RIE) process generates a
plasma by an electromagnetic field under a relatively low pressure
to remove material. The RIE process is a relatively high
anisotropic etch process for creating trenches. Portions of the
oxide layer 104 not protected by the photoresist layer 106 are
immersed in plasma, which is a reactive gas. The unprotected
portions of the oxide layer 104 are removed by chemical reactions
and/or ion bombardment. The reaction products are carried away in
the gas stream.
[0030] Plasma etching processes can operate in one of multiple
modes by adjusting the parameters of the etching process. Some
plasma etching processes operate with a pressure between 0.1 torr
and 5 torr. In various embodiments, the source gas for the plasma
contains chlorine or fluorine. For example, trifluoromethane (CHF3)
is used to etch silicon dioxide. As shown, the etched trenches 210
have sharp corners. However, in other embodiments, the parameters
used for the plasma etching process are adjusted to provide rounded
corners for the etched trenches 210. The rounded corners aid in
providing conformity in later processing steps where metal and
dielectric are deposited on the surfaces of the trenches for
building a MIM capacitor. These deposition steps are described
shortly.
[0031] Turning now to FIG. 3, a generalized block diagram of
another cross-sectional view of a portion of a semiconductor
passive component being fabricated is shown. Here, the photoresist
layer 106 is removed. A source gas for plasma containing oxygen is
used to oxidize ("ash") photoresist, which facilitates the removal
of the photoresist. Referring to FIG. 4, a generalized block
diagram of another cross-sectional view of a portion of a
semiconductor passive component being fabricated is shown. As
shown, the trenches have rounded corners. As described earlier, the
rounded corners of the trenches aid in providing conformity in
later processing steps where metal and dielectric are deposited on
the surfaces of the trenches for building a MIM capacitor. In
addition, sharp corners cause a concentration of the electric field
for the later-fabricated MIM capacitor, so the rounded corners aid
in reducing this effect.
[0032] In some embodiments, as described earlier, the rounded
corners of the trenches are already created or partially created by
adjusting the parameters used for the earlier plasma etching
process on the oxide layer 104. In other embodiments, relatively
high temperature oxidation is also used. For example, a relatively
high temperature oxidation step followed by removal of the oxide
with dry etching rounds the corners. In some embodiments, a
tetraethyl orthosilicate (TEOS) film is placed along both the top
surfaces and the trench surfaces of the oxide layer 104 and then
removed.
[0033] In yet other embodiments, fluorosilicate glass (FSG), which
is fluorine containing silicon dioxide, is formed over the top
surfaces and the trench surfaces of the oxide layer 104 with high
temperature reflow. A variety of other techniques for rounding the
top corners and the bottom corners of the trenches are possible and
contemplated.
[0034] The rounded trench corners (both top corners and bottom
corners) provide a sinusoidal-like waveform in the oxide layer 104.
In various embodiments, the waveform is not a symmetrical shape. In
some embodiments, the top of the wave has a different width than
the bottom of the wave. In other embodiments, the left slope of the
wave has a different angle than the right slope of the wave.
Although the waveform is not an exact sinusoidal shape, or even
symmetrical at times, as used herein, the waveform with the rounded
corners is described as being a sinusoidal shape or waveform. The
"frequency" of this sinusoidal shape is based on the width 110 and
the pitch 120 described earlier in FIG. 1. As described earlier,
one of a variety of lithography techniques is used to define the
width 110 and the pitch 120 of the trenches such as immersion
lithography, double patterning, EUV and DSA techniques, and so on.
The sinusoidal waveform is used to create a sinusoidal structure to
be used as a MIM capacitor with relatively high density
(capacitance per area). It is noted that in other embodiments, the
systems and methods described herein can be used to oscillating
structures that are not sinusoidal. For example, given a suitable
process a saw tooth or square wave structure may be generated. Such
alterative embodiments are contemplated as well.
[0035] Turning now to FIGS. 5-6, block diagrams of cross-sectional
views of a portion of a semiconductor passive component being
fabricated are shown. In particular, the metal-insulator-metal
layers are deposited for the MIM capacitor. As shown in FIG. 5, the
bottom metal is formed for the MIM capacitor. In some embodiments,
the bottom metal 510 is tantalum nitride (TaN), whereas in other
embodiments, the bottom metal 510 is titanium nitride (TiN). In
various embodiments, the bottom metal 510 is placed by atomic layer
deposition (ALD). In other embodiments, the bottom metal 510 is
placed by physical vapor deposition (PVD) such as a sputter
technique.
[0036] Following this, as shown in FIG. 6, a relatively high-K
oxide dielectric 610 is formed on the bottom metal 510. Examples of
the oxide 610 are hafnium oxide (Hf02) and other rare earth metal
oxides. In various embodiments, an atomic layer deposition (ALD) is
used to place the dielectric 610. The top metal 620 is deposited on
the dielectric 610 using a same metal compound and similar
technique to deposit the bottom metal 510. The combination of the
bottom metal 510, the dielectric 610 and the top metal 620 provides
the metal-insulator-metal (MIM) capacitor.
[0037] Turning now to FIGS. 7-9, block diagrams of cross-sectional
views of a portion of a semiconductor passive component being
fabricated are shown. In particular, the top metal 620 and the
dielectric 610 are removed in a particular region for later
placement of a connecting via. The bottom metal 510 remains in the
particular region. FIG. 7 shows a relatively thin, uniform coating
of the photoresist layer 710 formed on the top metal 620. As
described earlier, UV light is transmitted through a photomask
which contains the pattern for the placement of the vias. In these
regions, the photoresist layer 710 is removed. Following this, each
of the top metal 620 and the dielectric 610 are etched in this
region as shown in FIG. 8. In FIG. 9, the photoresist layer 710 is
removed. Each of the etching steps for the top metal 620 and the
dielectric 610 and the removal of the photoresist layer 710 is done
by one of a variety of methods. For example, in some embodiments,
at least one of the methods previously described is used.
[0038] Referring to FIG. 10, a generalized block diagram of a
cross-sectional view of a fabricated semiconductor MIM capacitor
with an oscillating pattern is shown. As shown, the oxide layer
1010 is deposited over the oscillating top metal layer 620 and the
oscillating bottom metal layer 510 where there is no top metal
layer 620. Examples of the oxide layer 1010 are TEOS, silicon
dioxide, or one of a variety of low-k dielectrics containing carbon
or fluorine. In embodiments with aluminum used for metal layers,
each of the vias 1020 and 1022 are formed by etching trenches into
the oxide layer 1010, filling the trenches with copper or other
conductive metal, and performing a chemical mechanical
planarization (CMP) step to polish the surface. Following this,
each of the metal 1030 and 1032 is formed on the vias 1020 and
2022. As via 1020 makes contact with the bottom metal layer 510 and
the via 1022 makes contact with the top metal layer 620, the MIM
capacitor is formed with the metal layers 1030 and 1032 providing
the voltage nodes.
[0039] In embodiments with copper used for metal layers, a dual
damascene process is used. Trenches for the metal layers 1030 and
1032 are etched into the oxide layer 1010, photoresist is placed in
the trenches, patterns for the vias 1020 and 1022 are etched, the
oxide layer 1010 is etched using these patterns to create space for
the vias 1020 and 1022, the photoresist is removed and copper is
used to fill the created spaces. Again, as via 1020 makes contact
with the bottom metal layer 510 and the via 1022 makes contact with
the top metal layer 620, the MIM capacitor is formed with the metal
layers 1030 and 1032 providing the voltage nodes.
[0040] Turning now to FIG. 11, one embodiment of a method 1100 for
fabricating a semiconductor metal-insulator-metal (MIM) capacitor
with an oscillating pattern is shown. For purposes of discussion,
the steps in this embodiment are shown in sequential order.
However, in other embodiments some steps occur in a different order
than shown, some steps are performed concurrently, some steps are
combined with other steps, and some steps are absent. In the
example shown, an oxide layer is grown on top of a metal layer
(block 1102). In various embodiments, the oxide layer is silicon
dioxide grown on top of copper. In some embodiments, a
plasma-enhanced chemical vapor deposition (PECVD) process is used
to place the oxide layer on the copper. In other embodiments, the
metal layer is a mix of copper and aluminum. A photoresist layer is
then formed on top of the oxide layer (block 1104). Subsequently,
the photoresist layer is etched (block 1106). The etching occurs
with repeating spacing which generally determines a frequency of an
oscillating wave to be formed later and used in a MIM capacitor.
One of a variety of lithography techniques may be used to reduce or
increase the pitch (increase the frequency) of the trenches. For
example, one of immersion lithography, double patterning, EUV and
DSA techniques, and other techniques, may be used for creating the
spacing in the photoresist layer.
[0041] Trenches are etched into areas of the oxide layer
unprotected by the photoresist layer (block 1108). Following this,
the photoresist layer is stripped (block 1110). The top and bottom
corners of the trenches are rounded to create a basis for the
oscillating wave (block 1112). In some embodiments, relatively high
temperature oxidation steps are used to round the corners. The
bottom metal, dielectric and top metal of the MIM capacitor are
deposited on the oxide layer both on areas with the trenches and on
areas without the trenches (block 1114). The MIM capacitor is
completed with metal nodes contacting each of the top plate and the
bottom plate (block 1116). An insulating oxide is deposited over
the MIM capacitor and in some embodiments, a dual damascene process
is used for placement of copper metal layers in addition to vias.
One via makes contact with the bottom metal and a second via makes
contact with the top metal of the MIM capacitor.
[0042] It is noted that one or more of the above-described
embodiments include software. In such embodiments, the program
instructions that implement the methods and/or mechanisms are
conveyed or stored on a computer readable medium. For example,
program steps describing and controlling fabrication equipment may
be stored on a non-transitory computer readable medium. Numerous
types of media which are configured to store program instructions
are available and include hard disks, floppy disks, CD-ROM, DVD,
flash memory, Programmable ROMs (PROM), random access memory (RAM),
and various other forms of volatile or non-volatile storage.
Generally speaking, a computer accessible storage medium includes
any storage media accessible by a computer during use to provide
instructions and/or data to the computer. For example, a computer
accessible storage medium includes storage media such as magnetic
or optical media, e.g., disk (fixed or removable), tape, CD-ROM, or
DVD-ROM, CD-R, CD-RW, DVD-R, DVD-RW, or Blu-Ray. Storage media
further includes volatile or non-volatile memory media such as RAM
(e.g. synchronous dynamic RAM (SDRAM), double data rate (DDR, DDR2,
DDR3, etc.) SDRAM, low-power DDR (LPDDR2, etc.) SDRAM, Rambus DRAM
(RDRAM), static RAM (SRAM), etc.), ROM, Flash memory, non-volatile
memory (e.g. Flash memory) accessible via a peripheral interface
such as the Universal Serial Bus (USB) interface, etc. Storage
media includes microelectromechanical systems (MEMS), as well as
storage media accessible via a communication medium such as a
network and/or a wireless link.
[0043] Additionally, in various embodiments, program instructions
include behavioral-level descriptions or register-transfer level
(RTL) descriptions of the hardware functionality in a high level
programming language such as C, or a design language (HDL) such as
Verilog, VHDL, or database format such as GDS II stream format
(GDSII). In some cases the description is read by a synthesis tool,
which synthesizes the description to produce a netlist including a
list of gates from a synthesis library. The netlist includes a set
of gates, which also represent the functionality of the hardware
including the system. The netlist is then placed and routed to
produce a data set describing geometric shapes to be applied to
masks. The masks are then used in various semiconductor fabrication
steps to produce a semiconductor circuit or circuits corresponding
to the system. Alternatively, the instructions on the computer
accessible storage medium are the netlist (with or without the
synthesis library) or the data set, as desired. Additionally, the
instructions are utilized for purposes of emulation by a hardware
based type emulator from such vendors as Cadence.RTM., EVE.RTM.,
and Mentor Graphics.RTM..
[0044] Although the embodiments above have been described in
considerable detail, numerous variations and modifications will
become apparent to those skilled in the art once the above
disclosure is fully appreciated. It is intended that the following
claims be interpreted to embrace all such variations and
modifications.
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