Schultz; Richard T.

Patent Applications and Registrations

Patent applications and USPTO patent grants for Schultz; Richard T..The latest application filed is for "standard cell layout architectures and drawing styles for 5nm and beyond".

Company Profile

9.48.41

Schultz; Richard T. - Fort Collins CO
Schultz; Richard T. - Ft. Collins CO
Schultz; Richard T - Fort Collins CO

*profile and listings may contain filings by different individuals or companies with the same name. Review application materials to confirm ownership/assignment.

Patent Activity

Patent	Date
Folded cell layout for 6T SRAM cell Grant 11,437,316 - Schultz , et al. September 6, 2	2022-09-06
Gate contact over active region in cell Grant 11,424,336 - Schultz August 23, 2	2022-08-23
Power grid architecture and optimization with EUV lithography Grant 11,347,925 - Schultz May 31, 2	2022-05-31
Standard Cell Layout Architectures And Drawing Styles For 5nm And Beyond App 20220102275 - Schultz; Richard T.	2022-03-31
Folded Cell Layout For 6t Sram Cell App 20220093504 - Schultz; Richard T. ; et al.	2022-03-24
Dual-track Bitline Scheme For 6t Sram Cells App 20220093503 - Wuu; John J. ; et al.	2022-03-24
Metal Zero Power Ground Stub Route To Reduce Cell Area And Improve Cell Placement At The Chip Level App 20210406439 - Schultz; Richard T.	2021-12-30
Standard cell layout architectures and drawing styles for 5nm and beyond Grant 11,211,330 - Schultz December 28, 2	2021-12-28
Power grid layout designs for integrated circuits Grant 11,189,569 - Schultz , et al. November 30, 2	2021-11-30
Metal zero power ground stub route to reduce cell area and improve cell placement at the chip level Grant 11,120,190 - Schultz September 14, 2	2021-09-14
Gate Contact Over Active Region In Cell App 20210028288 - Schultz; Richard T.	2021-01-28
Sinusoidal Shaped Capacitor Architecture In Oxide App 20200388669 - Schultz; Richard T.	2020-12-10
Gate contact over active region in cell Grant 10,818,762 - Schultz October 27, 2	2020-10-27
Standard cell and power grid architectures with EUV lithography Grant 10,796,061 - Schultz October 6, 2	2020-10-06
Double spacer immersion lithography triple patterning flow and method Grant 10,784,154 - Schultz Sept	2020-09-22
Sinusoidal shaped capacitor architecture in oxide Grant 10,756,164 - Schultz A	2020-08-25
Metal zero contact via redundancy on output nodes and inset power rail architecture Grant 10,651,164 - Schultz	2020-05-12
Oscillating capacitor architecture in polysilicon for improved capacitance Grant 10,608,076 - Schultz	2020-03-31
Metal Zero Contact Via Redundancy On Output Nodes And Inset Power Rail Architecture App 20200035662 - Schultz; Richard T.	2020-01-30
Gate Contact Over Active Region In Cell App 20190363167 - Schultz; Richard T.	2019-11-28
Metal Zero Contact Via Redundancy On Output Nodes And Inset Power Rail Architecture App 20190333911 - Schultz; Richard T.	2019-10-31
Metal zero contact via redundancy on output nodes and inset power rail architecture Grant 10,438,937 - Schultz O	2019-10-08
Double Spacer Immersion Lithography Triple Patterning Flow And Method App 20190295885 - Schultz; Richard T.	2019-09-26
Double spacer immersion lithography triple patterning flow and method Grant 10,304,728 - Schultz	2019-05-28
Metal Zero Power Ground Stub Route To Reduce Cell Area And Improve Cell Placement At The Chip Level App 20190155979 - Schultz; Richard T.	2019-05-23
Metal density distribution for double pattern lithography Grant 10,283,437 - Schultz , et al.	2019-05-07
Vertical gate all around library architecture Grant 10,186,510 - Schultz Ja	2019-01-22
Standard Cell Layout Architectures And Drawing Styles For 5nm And Beyond App 20180315709 - Schultz; Richard T.	2018-11-01
Power Grid Architecture And Optimization With Euv Lithography App 20180314785 - Schultz; Richard T.	2018-11-01
Vertical Gate All Around Library Architecture App 20180315751 - Schultz; Richard T.	2018-11-01
Double Spacer Immersion Lithography Triple Patterning Flow And Method App 20180315645 - Schultz; Richard T.	2018-11-01
Sinusoidal Shaped Capacitor Architecture In Oxide App 20180286942 - Schultz; Richard T.	2018-10-04
Oscillating Capacitor Architecture In Polysilicon For Improved Capacitance App 20180277624 - Schultz; Richard T.	2018-09-27
Gate all around device architecture with hybrid wafer bond technique Grant 10,068,794 - Schultz September 4, 2	2018-09-04
Gate All Around Device Architecture With Hybrid Wafer Bond Technique App 20180218938 - Schultz; Richard T.	2018-08-02
Power Grid Layout Designs For Integrated Circuits App 20180090440 - Schultz; Richard T. ; et al.	2018-03-29
Gate all around device architecture with local oxide Grant 9,704,995 - Schultz July 11, 2	2017-07-11
Trench silicide and gate open with local interconnect with replacement gate process Grant 9,006,834 - Schultz April 14, 2	2015-04-14
Trench Silicide And Gate Open With Local Interconnect With Replacement Gate Process App 20140197494 - Schultz; Richard T.	2014-07-17
Metal Density Distribution For Double Pattern Lithography App 20140145342 - Schultz; Richard T. ; et al.	2014-05-29
Trench silicide and gate open with local interconnect with replacement gate process Grant 8,716,124 - Schultz May 6, 2	2014-05-06
Process for forming fins for a FinFET device Grant 8,624,320 - Schultz January 7, 2	2014-01-07
Selective local interconnect to gate in a self aligned local interconnect process Grant 8,563,425 - Schultz October 22, 2	2013-10-22
Self-aligned trench contact and local interconnect with replacement gate process Grant 8,564,030 - Schultz October 22, 2	2013-10-22
Trench Silicide And Gate Open With Local Interconnect With Replacement Gate Process App 20130119474 - Schultz; Richard T.	2013-05-16
Self-aligned Trench Contact And Local Interconnect With Replacement Gate Process App 20120313148 - Schultz; Richard T.	2012-12-13
Sram Bit Cell With Self-aligned Bidirectional Local Interconnects App 20120037996 - Schultz; Richard T. ; et al.	2012-02-16
Process for Forming FINS for a FinFET Device App 20120025316 - Schultz; Richard T.	2012-02-02
SRAM bit cell with self-aligned bidirectional local interconnects Grant 8,076,236 - Schultz , et al. December 13, 2	2011-12-13
Methods for fabricating FinFET structures having different channel lengths Grant 7,960,287 - Johnson , et al. June 14, 2	2011-06-14
Methods For Fabricating Finfet Structures Having Different Channel Lengths App 20110014791 - JOHNSON; Frank S. ; et al.	2011-01-20
Selective Local Interconnect To Gate In A Self Aligned Local Interconnect Process App 20100304564 - Schultz; Richard T.	2010-12-02
Sram Bit Cell With Self-aligned Bidirectional Local Interconnects App 20100301482 - Schultz; Richard T. ; et al.	2010-12-02
N cell height decoupling circuit Grant 7,829,973 - Schultz , et al. November 9, 2	2010-11-09
Methods for fabricating FinFET structures having different channel lengths Grant 7,829,466 - Johnson , et al. November 9, 2	2010-11-09
Instantaneous voltage drop sensitivity analysis tool (IVDSAT) Grant 7,818,157 - Schultz October 19, 2	2010-10-19
Cad Flow For 15nm/22nm Multiple Fine Grained Wimpy Gate Lengths In Sit Gate Flow App 20100248481 - Schultz; Richard T.	2010-09-30
Methods For Fabricating Finfet Structures Having Different Channel Lengths App 20100197096 - JOHNSON; Frank S. ; et al.	2010-08-05
N Cell Height Decoupling Circuit App 20090051006 - Schultz; Richard T. ; et al.	2009-02-26
Interconnect integrity verification Grant 7,424,690 - Schultz , et al. September 9, 2	2008-09-09
Device For Avoiding Timing Violations Resulting From Process Defects In A Backfilled Metal Layer Of An Integrated Circuit App 20080155488 - SCHULTZ; RICHARD T. ; et al.	2008-06-26
Device for avoiding timing violations resulting from process defects in a backfilled metal layer of an integrated circuit Grant 7,392,496 - Schultz , et al. June 24, 2	2008-06-24
Reliability circuit for applying an AC stress signal or DC measurement to a transistor device Grant 7,183,791 - Walker , et al. February 27, 2	2007-02-27
Static timing and risk analysis tool Grant 7,181,713 - Schultz February 20, 2	2007-02-20
Interconnect integrity verification App 20060123377 - Schultz; Richard T. ; et al.	2006-06-08
Reliability circuit for applying an AC stress signal or DC measurement to a transistor device App 20060076972 - Walker; John D. ; et al.	2006-04-13
Floor plan development electromigration and voltage drop analysis tool Grant 7,016,794 - Schultz March 21, 2	2006-03-21
Static timing and risk analysis tool App 20050114811 - Schultz, Richard T.	2005-05-26
Thick traces from multiple damascene layers Grant 6,830,984 - Schultz , et al. December 14, 2	2004-12-14
Floor plan-based power bus analysis and design tool for integrated circuits Grant 6,675,139 - Jetton , et al. January 6, 2	2004-01-06
Method of automatically generating schematic and waveform diagrams for isolating faults from multiple failing paths in a circuit using input signal predictors and transition times Grant 6,671,846 - Schultz December 30, 2	2003-12-30
Instantaneous voltage drop sensitivity analysis tool (IVDSAT) App 20030237059 - Schultz, Richard T.	2003-12-25
Process, voltage and temperature independent clock tree deskew circuitry-temporary driver method Grant 6,653,883 - Schultz November 25, 2	2003-11-25
Power redistribution bus for a wire bonded integrated circuit Grant 6,653,726 - Schultz , et al. November 25, 2	2003-11-25
Method of automatically generating schematic and waveform diagrams for relevant logic cells of a circuit using input signal predictors and transition times Grant 6,625,770 - Schultz September 23, 2	2003-09-23
Thick traces from multiple damascene layers App 20030157805 - Schultz, Richard T. ; et al.	2003-08-21
Floor Plan Development Electromigration And Voltage Drop Analysis Tool App 20030014201 - SCHULTZ, RICHARD T.	2003-01-16
Process, voltage and temperature independent clock tree deskew circuitry-temporary driver method App 20020196067 - Schultz, Richard T.	2002-12-26
Method of automatically generating schematic and waveform diagrams for analysis of timing margins and signal skews of relevant logic cells using input signal predictors and transition times Grant 6,442,741 - Schultz August 27, 2	2002-08-27
Process, voltage and temperature independent clock tree deskew circuitry-active drive method Grant 6,433,598 - Schultz August 13, 2	2002-08-13
Process, Voltage And Temperature Independent Clock Tree Deskew Circuitry -temporary Driver Method App 20020105366 - Schultz, Richard T.	2002-08-08
Process, voltage and temperature independent clock tree deskew circuitry-temporary driver method Grant 6,429,714 - Schultz August 6, 2	2002-08-06
Metastability risk simulation analysis tool and method Grant 6,408,265 - Schultz , et al. June 18, 2	2002-06-18
Meta-hardened flip-flop Grant 5,999,029 - Nguyen , et al. December 7, 1	1999-12-07

uspto.report is an independent third-party trademark research tool that is not affiliated, endorsed, or sponsored by the United States Patent and Trademark Office (USPTO) or any other governmental organization. The information provided by uspto.report is based on publicly available data at the time of writing and is intended for informational purposes only.

While we strive to provide accurate and up-to-date information, we do not guarantee the accuracy, completeness, reliability, or suitability of the information displayed on this site. The use of this site is at your own risk. Any reliance you place on such information is therefore strictly at your own risk.

All official trademark data, including owner information, should be verified by visiting the official USPTO website at www.uspto.gov. This site is not intended to replace professional legal advice and should not be used as a substitute for consulting with a legal professional who is knowledgeable about trademark law.