U.S. patent application number 16/877990 was filed with the patent office on 2020-11-26 for extreme ultraviolet mask with embedded absorber layer.
This patent application is currently assigned to Applied Materials, Inc.. The applicant listed for this patent is Applied Materials, Inc.. Invention is credited to Vibhu Jindal, Wen Xiao.
Application Number | 20200371431 16/877990 |
Document ID | / |
Family ID | 1000004883353 |
Filed Date | 2020-11-26 |
United States Patent
Application |
20200371431 |
Kind Code |
A1 |
Xiao; Wen ; et al. |
November 26, 2020 |
EXTREME ULTRAVIOLET MASK WITH EMBEDDED ABSORBER LAYER
Abstract
Extreme ultraviolet (EUV) mask blanks, methods for their
manufacture and production systems therefor are disclosed. The EUV
mask blanks comprise a substrate; a multilayer stack of reflective
layers on the substrate; a capping layer on the multilayer stack of
reflecting layers; and an absorber layer embedded in the multilayer
stack of reflective layers.
Inventors: |
Xiao; Wen; (Singapore,
SG) ; Jindal; Vibhu; (San Jose, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Applied Materials, Inc. |
Santa Clara |
CA |
US |
|
|
Assignee: |
Applied Materials, Inc.
Santa Clara
CA
|
Family ID: |
1000004883353 |
Appl. No.: |
16/877990 |
Filed: |
May 19, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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62851404 |
May 22, 2019 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G03F 1/54 20130101; G03F
1/24 20130101 |
International
Class: |
G03F 1/54 20060101
G03F001/54; G03F 1/24 20060101 G03F001/24 |
Claims
1. A method of manufacturing an extreme ultraviolet (EUV) mask
blank comprising: forming on a substrate a multilayer stack which
reflects EUV radiation, the multilayer stack comprising a plurality
of reflective layer pairs; forming a capping layer on the
multilayer stack, the capping layer having a capping layer top
surface; and forming an absorber layer embedded in the capping
layer and the multilayer stack.
2. The method of claim 1, wherein the absorber layer is formed in a
trench in the capping layer and the multilayer stack.
3. The method of claim 2, wherein the trench is formed by masking
and etching a portion of the capping layer and multilayer
stack.
4. The method of claim 3, wherein the masking comprises forming a
hard mask on the capping layer, forming an anti-reflection coating
on the hard mask and forming a photoresist on the anti-reflection
coating.
5. The method of claim 4, further comprising exposing the
photoresist through a mask pattern to radiation and curing a
portion of the photoresist to form a trench in the photoresist to
provide an exposed antireflective coating portion.
6. The method of claim 5, further comprising etching the exposed
antireflective coating portion and etching a portion of the hard
mask, the capping layer and the multilayer underlying the exposed
antireflective coating portion to form a trench in the capping
layer and the multilayer stack.
7. The method of claim 6, further comprising removing remaining
photoresist and antireflective coating and depositing an absorber
layer in the trench in the capping layer and the multilayer
stack.
8. The method of claim 2, wherein the trench in the capping layer
and the multilayer stack comprises vertical sidewalls.
9. The method of claim 2, wherein the trench in the capping layer
and the multilayer stack comprises angled sidewalls forming an
angle greater than ninety degrees with the capping layer top
surface.
10. The method of claim 3, wherein the trench in the capping layer
and the multilayer stack comprises angled sidewalls forming an
angle less than ninety degrees with the capping layer top
surface.
11. An extreme ultraviolet (EUV) mask blank comprising: a
substrate; a multilayer stack which reflects EUV radiation, the
multilayer stack comprising a plurality of reflective layer pairs;
a capping layer on the multilayer stack of reflecting layers, the
capping layer having a capping layer top surface; and an absorber
layer embedded in the capping layer and the multilayer stack.
12. The extreme ultraviolet (EUV) mask blank of claim 11, wherein
the absorber layer comprises an absorber layer top surface, and the
absorber layer top surface is flush with the capping layer top
surface.
13. The extreme ultraviolet (EUV) mask blank of claim 11, wherein
the absorber layer is formed in a trench in the capping layer and
the multilayer stack.
14. The extreme ultraviolet (EUV) mask blank of claim 13, wherein
the trench in the capping layer and the multilayer stack comprises
vertical sidewalls.
15. The extreme ultraviolet (EUV) mask blank of claim 14, wherein
the absorber layer comprises vertical sidewalls.
16. The extreme ultraviolet (EUV) mask blank of claim 13, wherein
the trench in the capping layer and the multilayer stack comprises
angled sidewalls forming an angle greater than ninety degrees with
the capping layer top surface.
17. The extreme ultraviolet (EUV) mask blank of claim 16, wherein
the absorber layer angled sidewalls forming an angle greater than
ninety degrees with the capping layer top surface.
18. The extreme ultraviolet (EUV) mask blank of claim 11, wherein
the trench in the capping layer and the multilayer stack comprises
angled sidewalls forming an angle less than ninety degrees with the
capping layer top surface.
19. The extreme ultraviolet (EUV) mask blank of claim 18, wherein
the absorber layer comprises angled sidewalls forming an angle less
than ninety degrees with the capping layer top surface.
20. An extreme ultraviolet (EUV) mask blank comprising: a
substrate; a multilayer stack which reflects EUV radiation, the
multilayer stack comprising a plurality of reflective layer pairs
including molybdenum (Mo) and silicon (Si); a capping layer on the
multilayer stack of reflecting layers having a capping layer top
surface; and an absorber layer embedded in the capping layer and
the multilayer stack, the absorber layer having an absorber layer
top surface that is flush with the capping layer top surface.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims priority to U.S. Provisional
Application No. 62/851,404, filed May 22, 2019, the entire
disclosure of which is hereby incorporated by reference herein.
TECHNICAL FIELD
[0002] The present disclosure relates generally to extreme
ultraviolet lithography, and more particularly extreme ultraviolet
mask blanks with an absorber layer embedded in a reflective
multilayer stack and methods of manufacture.
BACKGROUND
[0003] Extreme ultraviolet (EUV) lithography, also known as soft
x-ray projection lithography, is used for the manufacture of 0.0135
micron and smaller minimum feature size semiconductor devices.
However, extreme ultraviolet light, which is generally in the 5 to
100 nanometer wavelength range, is strongly absorbed in virtually
all materials. For that reason, extreme ultraviolet systems work by
reflection rather than by transmission of light. Through the use of
a series of mirrors, or lens elements, and a reflective element, or
mask blank, coated with a non-reflective absorber mask pattern, the
patterned actinic light is reflected onto a resist-coated
semiconductor substrate.
[0004] The lens elements and mask blanks of extreme ultraviolet
lithography systems are coated with reflective multilayer coatings
of materials such as molybdenum and silicon. Reflection values of
approximately 65% per lens element, or mask blank, have been
obtained by using substrates that are coated with multilayer
coatings that strongly reflect light within an extremely narrow
ultraviolet bandpass, for example, 12.5 to 14.5 nanometer bandpass
for 13.5 nanometer ultraviolet light.
[0005] FIG. 1 shows a conventional EUV reflective mask 10, which is
formed from an EUV mask blank, which includes a reflective
multilayer stack 12 on a substrate 14, which reflects EUV radiation
at unmasked portions by Bragg interference. Masked (non-reflective)
areas 16 of the conventional EUV reflective mask 10 are formed by
etching buffer layer 18 and an absorber layer 20 to provide a
patterned absorber layer 20. A capping layer 22 is formed over the
reflective multilayer stack 12 and protects the reflective
multilayer stack 12 during the etching process. As will be
discussed further below, EUV mask blanks are made of a low thermal
expansion material substrate coated with multilayers, a capping
layer and an absorber layer, which is then patterned by etching to
provide reflective areas 24 and the masked (non-reflective) areas
16 comprising the patterned absorber layer 20.
[0006] The International Technology Roadmap for Semiconductors
(ITRS) specifies a node's overlay requirement as some percentage of
a technology's minimum half-pitch feature size. Due to the impact
on image placement and overlay errors inherent in all reflective
lithography systems, EUV reflective masks will need to adhere to
more precise flatness specifications for future production.
Additionally, EUV mask blanks have a very low tolerance to defects
on the working area of the blank. Furthermore, the thickness or
height of patterned absorber causes what is referred to as the mask
3D effect, which deteriorates the resolution of EUV lithography.
For example, TaN-based or other absorber layers on top of the
multilayer stack 12 require a thickness of at least 40 nm,
typically in a range of from 51 nm to 77 nm, which is very thick.
EUV mask blanks with current thick absorbers on top of the
multilayer stack cannot be used for node 5 nm integrated circuit
manufacturing and next-generation high numerical aperture ("high
NA") EUV scanners. Embodiments of the disclosure provide improved
structural design of EUV mask blanks and methods therefor to
minimize the mask 3D effect.
SUMMARY
[0007] One or more embodiments of the disclosure are directed to a
method of manufacturing an extreme ultraviolet (EUV) mask blank
comprising forming on a substrate a multilayer stack which reflects
EUV radiation, the multilayer stack comprising a plurality of
reflective layer pairs; forming a capping layer on the multilayer
stack, the capping layer having a capping layer top surface; and
forming an absorber layer embedded in the capping layer and the
multilayer stack.
[0008] Additional embodiments of the disclosure are directed to an
EUV mask blank comprising a substrate; a multilayer stack which
reflects EUV radiation, the multilayer stack comprising a plurality
of reflective layer pairs; a capping layer on the multilayer stack
of reflecting layers, the capping layer having a capping layer top
surface; and an absorber layer embedded in the capping layer and
the multilayer stack. In some embodiments, an EUV mask blank
comprises a substrate; a multilayer stack which reflects EUV
radiation, the multilayer stack comprising a plurality of
reflective layer pairs including molybdenum (Mo) and silicon (Si);
a capping layer on the multilayer stack of reflecting layers having
a capping layer top surface; and an absorber layer embedded in the
capping layer and the multilayer stack, the absorber layer having
an absorber layer top surface that is flush with the capping layer
top surface
BRIEF DESCRIPTION OF THE DRAWINGS
[0009] So that the manner in which the above recited features of
the present disclosure can be understood in detail, a more
particular description of the disclosure, briefly summarized above,
may be had by reference to embodiments, some of which are
illustrated in the appended drawings. It is to be noted, however,
that the appended drawings illustrate only typical embodiments of
this disclosure and are therefore not to be considered limiting of
its scope, for the disclosure may admit to other equally effective
embodiments.
[0010] FIG. 1 schematically illustrates a background art EUV
reflective mask employing a conventional absorber;
[0011] FIG. 2 schematically illustrates an embodiment of an extreme
ultraviolet lithography system;
[0012] FIG. 3 illustrates an embodiment of an extreme ultraviolet
reflective element production system;
[0013] FIGS. 4A-C illustrate embodiments of an extreme ultraviolet
reflective element such as an EUV mask blank;
[0014] FIGS. 5A-H illustrate an embodiment of a method of forming
an extreme ultraviolet reflective element such as an EUV mask
blank; and
[0015] FIG. 6 illustrates an embodiment of a multi-cathode physical
deposition chamber.
DETAILED DESCRIPTION
[0016] Before describing several exemplary embodiments of the
disclosure, it is to be understood that the disclosure is not
limited to the details of construction or process steps set forth
in the following description. The disclosure is capable of other
embodiments and of being practiced or being carried out in various
ways.
[0017] The term "horizontal" as used herein is defined as a plane
parallel to the plane or surface of a mask blank, regardless of its
orientation. The term "vertical" refers to a direction
perpendicular to the horizontal as just defined. Terms, such as
"above", "below", "bottom", "top", "side" (as in "sidewall"),
"higher", "lower", "upper", "over", and "under", are defined with
respect to the horizontal plane, as shown in the figures.
[0018] The term "on" indicates that there is direct contact between
elements. The term "directly on" indicates that there is direct
contact between elements with no intervening elements.
[0019] Those skilled in the art will understand that the use of
ordinals such as "first" and "second" to describe process regions
do not imply a specific location within the processing chamber, or
order of exposure within the processing chamber.
[0020] As used in this specification and the appended claims, the
term "substrate" refers to a surface, or portion of a surface, upon
which a process acts. It will also be understood by those skilled
in the art that reference to a substrate refers to only a portion
of the substrate, unless the context clearly indicates otherwise.
Additionally, reference to depositing on a substrate means both a
bare substrate and a substrate with one or more films or features
deposited or formed thereon.
[0021] Referring now to FIG. 2, an exemplary embodiment of an
extreme ultraviolet lithography system 100 is shown. The extreme
ultraviolet lithography system 100 includes an extreme ultraviolet
light source 102 for producing extreme ultraviolet light 112, a set
of reflective elements, and a target substrate 110. The reflective
elements include a condenser 104, an EUV reflective mask 106, an
optical reduction assembly 108, a mask blank, a mirror, or a
combination thereof.
[0022] The extreme ultraviolet light source 102 generates the
extreme ultraviolet light 112. The extreme ultraviolet light 112 is
electromagnetic radiation having a wavelength in a range of 5 to 50
nanometers (nm). For example, the extreme ultraviolet light source
102 includes a laser, a laser produced plasma, a discharge produced
plasma, a free-electron laser, synchrotron radiation, or a
combination thereof.
[0023] The extreme ultraviolet light source 102 generates the
extreme ultraviolet light 112 having a variety of characteristics.
The extreme ultraviolet light source 102 produces broadband extreme
ultraviolet radiation over a range of wavelengths. For example, the
extreme ultraviolet light source 102 generates the extreme
ultraviolet light 112 having wavelengths ranging from 5 to 50
nm.
[0024] In one or more embodiments, the extreme ultraviolet light
source 102 produces the extreme ultraviolet light 112 having a
narrow bandwidth. For example, the extreme ultraviolet light source
102 generates the extreme ultraviolet light 112 at 13.5 nm. The
center of the wavelength peak is 13.5 nm.
[0025] The condenser 104 is an optical unit for reflecting and
focusing the extreme ultraviolet light 112. The condenser 104
reflects and concentrates the extreme ultraviolet light 112 from
the extreme ultraviolet light source 102 to illuminate the EUV
reflective mask 106.
[0026] Although the condenser 104 is shown as a single element, it
is understood that in some embodiments, the condenser 104 includes
one or more reflective elements such as concave mirrors, convex
mirrors, flat mirrors, or a combination thereof, for reflecting and
concentrating the extreme ultraviolet light 112. For example, the
condenser 104 according to some embodiments is a single concave
mirror or an optical assembly having convex, concave, and flat
optical elements.
[0027] The EUV reflective mask 106 is an extreme ultraviolet
reflective element having a mask pattern 114. The EUV reflective
mask 106 creates a lithographic pattern to form a circuitry layout
to be formed on the target substrate 110. The EUV reflective mask
106 reflects the extreme ultraviolet light 112. The mask pattern
114 defines a portion of a circuitry layout.
[0028] The optical reduction assembly 108 is an optical unit for
reducing the image of the mask pattern 114. The reflection of the
extreme ultraviolet light 112 from the EUV reflective mask 106 is
reduced by the optical reduction assembly 108 and reflected on to
the target substrate 110. The optical reduction assembly 108 of
some embodiments includes mirrors and other optical elements to
reduce the size of the image of the mask pattern 114. For example,
the optical reduction assembly 108 of some embodiments includes
concave mirrors for reflecting and focusing the extreme ultraviolet
light 112.
[0029] The optical reduction assembly 108 reduces the size of the
image of the mask pattern 114 on the target substrate 110. For
example, the mask pattern 114 is imaged at a 4:1 ratio by the
optical reduction assembly 108 on the target substrate 110 to form
the circuitry represented by the mask pattern 114 on the target
substrate 110. The extreme ultraviolet light 112 of some embodiment
scans the EUV reflective mask 106 synchronously with the target
substrate 110 to form the mask pattern 114 on the target substrate
110.
[0030] Referring now to FIG. 3, an embodiment of of an extreme
ultraviolet reflective element production system 200 is shown. The
extreme ultraviolet reflective element includes an EUV mask blank
204, an extreme ultraviolet mirror 205, or other reflective element
such as an EUV reflective mask 106.
[0031] The extreme ultraviolet reflective element production system
200 in some embodiments produces mask blanks, mirrors, or other
elements that reflect the extreme ultraviolet light 112 of FIG. 2.
The extreme ultraviolet reflective element production system 200
fabricates the reflective elements by applying thin coatings to
source substrates 203.
[0032] The EUV mask blank 204 is a multilayered structure for
forming the EUV reflective mask 106 of FIG. 2. In some embodiments,
the EUV mask blank 204 is formed using semiconductor fabrication
techniques. In some embodiments, the EUV reflective mask 106 has
the mask pattern 114 of FIG. 2 formed on the EUV mask blank 204 by
etching and other processes.
[0033] The extreme ultraviolet mirror 205 is a multilayered
structure reflective in a range of extreme ultraviolet light. In
some embodiments, the extreme ultraviolet mirror 205 is formed
using semiconductor fabrication techniques. The EUV mask blank 204
and the extreme ultraviolet mirror 205 in some embodiment are
similar structures with respect to the layers formed on each
element, however, the extreme ultraviolet mirror 205 does not have
the mask pattern 114.
[0034] The reflective elements are efficient reflectors of the
extreme ultraviolet light 112. In an embodiment, the EUV mask blank
204 and the extreme ultraviolet mirror 205 has an extreme
ultraviolet reflectivity of greater than 60%. The reflective
elements are efficient if they reflect more than 60% of the extreme
ultraviolet light 112.
[0035] The extreme ultraviolet reflective element production system
200 includes a substrate loading and carrier handling system 202
into which the source substrates 203 are loaded and from which the
reflective elements are unloaded. An atmospheric handling system
206 provides access to a substrate handling vacuum chamber 208. The
substrate loading and carrier handling system 202 in some
embodiments include substrate transport boxes, loadlocks, and other
components to transfer a substrate from atmosphere to vacuum inside
the system. Because the EUV mask blank 204 is used to form devices
at a very small scale, the source substrates 203 and the EUV mask
blank 204 are processed in a vacuum system to prevent contamination
and other defects.
[0036] In some embodiments, the substrate handling vacuum chamber
208 contains two vacuum chambers, a first vacuum chamber 210 and a
second vacuum chamber 212. The first vacuum chamber 210 includes a
first substrate handling system 214 and the second vacuum chamber
212 includes a second substrate handling system 216. Although the
substrate handling vacuum chamber 208 is described with two vacuum
chambers, it is understood that the system of one or more
embodiments has any number of vacuum chambers.
[0037] The substrate handling vacuum chamber 208 shown has a
plurality of ports around its periphery for attachment of various
other systems. The first vacuum chamber 210 has a degas system 218,
a first physical vapor deposition system 220, a second physical
vapor deposition system 222, and a pre-clean system 224. The degas
system 218 is for thermally desorbing moisture from the substrates.
The pre-clean system 224 is for cleaning the surfaces of the
substrates, mask blanks, mirrors, or other optical components.
[0038] The physical vapor deposition systems, such as the first
physical vapor deposition system 220 and the second physical vapor
deposition system 222, are used to form thin films of conductive
materials on the source substrates 203. For example, the physical
vapor deposition systems of one or more embodiments include vacuum
deposition system such as magnetron sputtering systems, ion
sputtering systems, pulsed laser deposition, cathode arc
deposition, or a combination thereof. The physical vapor deposition
systems, such as the magnetron sputtering system, form thin layers
on the source substrates 203 including the layers of silicon,
metals, alloys, compounds, or a combination thereof.
[0039] The physical vapor deposition system forms reflective
layers, capping layers, and absorber layers. For example, the
physical vapor deposition systems in some embodiments forms layers
of silicon, molybdenum, titanium oxide, titanium dioxide, ruthenium
oxide, niobium oxide, ruthenium tungsten, ruthenium molybdenum,
ruthenium niobium, chromium, antimony, nitrides, compounds, or a
combination thereof. Although some compounds are described as an
oxide, it is understood that the compounds in some embodiments
include oxides, dioxides, atomic mixtures having oxygen atoms, or a
combination thereof.
[0040] The second vacuum chamber 212 has a first multi-cathode
source 226, a chemical vapor deposition system 228, a cure chamber
230, and an ultra-smooth deposition chamber 232 connected to it.
For example, the chemical vapor deposition system 228 of some
embodiments includes a flowable chemical vapor deposition system
(FCVD), a plasma assisted chemical vapor deposition system (CVD),
an aerosol assisted CVD, a hot filament CVD system, or a similar
system. In another example, the chemical vapor deposition system
228, the cure chamber 230, and the ultra-smooth deposition chamber
232 are in a separate system from the extreme ultraviolet
reflective element production system 200.
[0041] The chemical vapor deposition system 228 forms thin films of
material on the source substrates 203. For example, the chemical
vapor deposition system 228 is used to form layers of materials on
the source substrates 203 including mono-crystalline layers,
polycrystalline layers, amorphous layers, epitaxial layers, or a
combination thereof. The chemical vapor deposition system 228 is
configured in some embodiments to form layers of silicon, silicon
oxides, silicon oxycarbide, carbon, tungsten, silicon carbide,
silicon nitride, titanium nitride, metals, alloys, and other
materials suitable for chemical vapor deposition. For example, the
chemical vapor deposition system is configured to form
planarization layers.
[0042] The first substrate handling system 214 is capable of moving
the source substrates 203 between the atmospheric handling system
206 and the various systems around the periphery of the first
vacuum chamber 210 in a continuous vacuum. The second substrate
handling system 216 is capable of moving the source substrates 203
around the second vacuum chamber 212 while maintaining the source
substrates 203 in a continuous vacuum. The extreme ultraviolet
reflective element production system 200 is configured to transfer
the source substrates 203 and the EUV mask blank 204 between the
first substrate handling system 214, the second substrate handling
system 216 in a continuous vacuum.
[0043] Referring now to FIGS. 4A-C, various embodiments of an
extreme ultraviolet reflective element 302 are shown. In one or
more embodiments, the exemplary extreme ultraviolet reflective
elements 302 shown in FIGS. 4A-C each are used as the EUV mask
blank 204 shown in FIG. 3 or the extreme ultraviolet mirror 205
shown FIG. 3. The EUV mask blank 204 and the extreme ultraviolet
mirror 205 are structures for reflecting the extreme ultraviolet
light 112 as depicted in FIG. 2. The EUV mask blank 204 is used to
form the EUV reflective mask 106 shown in FIG. 2.
[0044] The extreme ultraviolet reflective element 302 includes a
substrate 304, a multilayer stack 306 of reflective layers, and a
capping layer 308. In one or more embodiments, the extreme
ultraviolet mirror 205 is used to form reflecting structures for
use in the condenser 104 of FIG. 2 or the optical reduction
assembly 108 of FIG. 2.
[0045] The extreme ultraviolet reflective element 302 shown in
FIGS. 4A-C, which in some embodiments is an EUV mask blank 204,
includes the substrate 304, the multilayer stack 306 of reflective
layers, the capping layer 308, and an absorber layer 310a, 310b of
310c. The extreme ultraviolet reflective element 302 in some
embodiments is an EUV mask blank 204, which is used to form the EUV
reflective mask 106 of FIG. 2 by patterning the absorber layer 310
with the layout of the circuitry required.
[0046] In the following sections, the term for the EUV mask blank
204 is used interchangeably with the term of the extreme
ultraviolet mirror 205 for simplicity. In one or more embodiments,
the EUV mask blank 204 includes the components of the extreme
ultraviolet mirror 205 with the absorber layer 310 added in
addition to form the mask pattern 114 of FIG. 2.
[0047] The EUV mask blank 204 is an optically flat structure used
for forming the EUV reflective mask 106 having the mask pattern
114. In one or more embodiments, the reflective surface of the EUV
mask blank 204 forms a flat focal plane for reflecting the incident
light, such as the extreme ultraviolet light 112 of FIG. 2.
[0048] The substrate 304 is an element for providing structural
support to the extreme ultraviolet reflective element 302. In one
or more embodiments, the substrate 304 is made from a material
having a low coefficient of thermal expansion (CTE) to provide
stability during temperature changes. In one or more embodiments,
the substrate 304 has properties such as stability against
mechanical cycling, thermal cycling, crystal formation, or a
combination thereof. The substrate 304 according to one or more
embodiments is formed from a material such as silicon, glass,
oxides, ceramics, glass ceramics, or a combination thereof.
[0049] The multilayer stack 306 is a structure that is reflective
to the extreme ultraviolet light 112. The multilayer stack 306
includes alternating reflective layers of a first reflective layer
312 and a second reflective layer 314. The first reflective layer
312 and the second reflective layer 314 form a reflective layer
pair 316 of FIGS. 4A-C. In a non-limiting embodiment, the
multilayer stack 306 includes a range of 20-60 of the reflective
layer pairs 316 for a total of up to 120 reflective layers.
[0050] The first reflective layer 312 and the second reflective
layer 314 are formed from a variety of materials. In an embodiment,
the first reflective layer 312 and the second reflective layer 314
are formed from silicon and molybdenum, respectively. Although the
layers are shown as silicon and molybdenum, it is understood that
the alternating layers are formed from other materials or have
other internal structures.
[0051] The first reflective layer 312 and the second reflective
layer 314 in some embodiments have a variety of structures. In an
embodiment, both the first reflective layer 312 and the second
reflective layer 314 are formed with a single layer, multiple
layers, a divided layer structure, non-uniform structures, or a
combination thereof.
[0052] Because most materials absorb light at extreme ultraviolet
wavelengths, the optical elements used are reflective instead of
the transmissive as used in other lithography systems. The
multilayer stack 306 forms a reflective structure by having
alternating thin layers of materials with different optical
properties to create a Bragg reflector or mirror.
[0053] In an embodiment, each of the alternating layers has
dissimilar optical constants for the extreme ultraviolet light 112.
The alternating layers provide a resonant reflectivity when the
period of the thickness of the alternating layers is one half the
wavelength of the extreme ultraviolet light 112. In an embodiment,
for the extreme ultraviolet light 112 at a wavelength of 13 nm, the
alternating layers are about 6.5 nm thick. It is understood that
the sizes and dimensions provided are within normal engineering
tolerances for typical elements.
[0054] The multilayer stack 306 in some embodiments is formed in a
variety of ways. In an embodiment, the first reflective layer 312
and the second reflective layer 314 are formed with magnetron
sputtering, ion sputtering systems, pulsed laser deposition,
cathode arc deposition, or a combination thereof.
[0055] In an illustrative embodiment, the multilayer stack 306 is
formed using a physical vapor deposition technique, such as
magnetron sputtering. In an embodiment, the first reflective layer
312 and the second reflective layer 314 of the multilayer stack 306
have the characteristics of being formed by the magnetron
sputtering technique including precise thickness, low roughness,
and clean interfaces between the layers. In an embodiment, the
first reflective layer 312 and the second reflective layer 314 of
the multilayer stack 306 have the characteristics of being formed
by the physical vapor deposition including precise thickness, low
roughness, and clean interfaces between the layers.
[0056] The physical dimensions of the layers of the multilayer
stack 306 formed using the physical vapor deposition technique in
some embodiments is precisely controlled to increase reflectivity.
In an embodiment, the first reflective layer 312, such as a layer
of silicon, has a thickness of 4.1 nm. The second reflective layer
314, such as a layer of molybdenum, has a thickness of 2.8 nm. The
thickness of the layers dictates the peak reflectivity wavelength
of the extreme ultraviolet reflective element. If the thickness of
the layers is incorrect, the reflectivity at the desired wavelength
13.5 nm in some embodiments is reduced.
[0057] In an embodiment, the multilayer stack 306 has a
reflectivity of greater than 60%. In an embodiment, the multilayer
stack 306 formed using physical vapor deposition has a reflectivity
in a range of 66%-67%. In one or more embodiments, forming the
capping layer 308 over the multilayer stack 306 formed with harder
materials improves reflectivity. In some embodiments, reflectivity
greater than 70% is achieved using low roughness layers, clean
interfaces between layers, improved layer materials, or a
combination thereof.
[0058] In one or more embodiments, the capping layer 308 is a
protective layer allowing the transmission of the extreme
ultraviolet light 112. In an embodiment, the capping layer 308 is
formed directly on the multilayer stack 306. In one or more
embodiments, the capping layer 308 protects the multilayer stack
306 from contaminants and mechanical damage. In one embodiment, the
multilayer stack 306 is sensitive to contamination by oxygen,
carbon, hydrocarbons, or a combination thereof. The capping layer
308 according to an embodiment interacts with the contaminants to
neutralize them.
[0059] In one or more embodiments, the capping layer 308 is an
optically uniform structure that is transparent to the extreme
ultraviolet light 112. The extreme ultraviolet light 112 passes
through the capping layer 308 to reflect off of the multilayer
stack 306. In one or more embodiments, the capping layer 308 has a
total reflectivity loss of 1% to 2%. In one or more embodiments,
each of the different materials has a different reflectivity loss
depending on thickness, but all of them will be in a range of 1% to
2%.
[0060] In one or more embodiments, the capping layer 308 has a
smooth surface. For example, the surface of the capping layer 308
in some embodiments has a roughness of less than 0.2 nm RMS (root
mean square measure). In another example, the surface of the
capping layer 308 has a roughness of 0.08 nm RMS for a length in a
range of 1/100 nm and 1/1 .mu.m. The RMS roughness will vary
depending on the range it is measured over. For the specific range
of 100 nm to 1 micron that roughness is 0.08 nm or less. Over a
larger range the roughness will be higher.
[0061] The capping layer 308 in some embodiments is formed in a
variety of methods. In an embodiment, the capping layer 308 is
formed on or directly on the multilayer stack 306 with magnetron
sputtering, ion sputtering systems, ion beam deposition, electron
beam evaporation, radio frequency (RF) sputtering, atomic layer
deposition (ALD), pulsed laser deposition, cathode arc deposition,
or a combination thereof. In one or more embodiments, the capping
layer 308 has the physical characteristics of being formed by the
magnetron sputtering technique including precise thickness, low
roughness, and clean interfaces between the layers. In an
embodiment, the capping layer 308 has the physical characteristics
of being formed by the physical vapor deposition including precise
thickness, low roughness, and clean interfaces between the
layers.
[0062] In one or more embodiments, the capping layer 308 is formed
from a variety of materials having a hardness sufficient to resist
erosion during cleaning. In one embodiment, ruthenium is used as a
capping layer material because it is a good etch stop and is
relatively inert under the operating conditions. However, it is
understood that other materials in some embodiments are used to
form the capping layer 308. In specific embodiments, the capping
layer 308 has a thickness in a range of 2.5 and 5.0 nm.
[0063] In one or more embodiments, the absorber layer 310a, 310b or
310c is a layer that absorbs the extreme ultraviolet light 112. In
an embodiment, the absorber layer 310a, 310b or 310c is used to
form the pattern on the EUV reflective mask 106 by providing areas
that do not reflect the extreme ultraviolet light 112. The absorber
layer 310, according to one or more embodiments, comprises a
material having a high absorption coefficient for a particular
frequency of the extreme ultraviolet light 112, such as about 13.5
nm. In an embodiment, the absorber layer 310a, 310b, or 310c is
formed directly on the capping layer 308, and the absorber layer
310a, 310b or 310c is etched using a photolithography process to
form the pattern of the EUV reflective mask 106.
[0064] According to one or more embodiments, the extreme
ultraviolet reflective element 302, such as the extreme ultraviolet
mirror 205, is formed with the substrate 304, the multilayer stack
306, and the capping layer 308. The extreme ultraviolet mirror 205
has an optically flat surface and in some embodiments efficiently
and uniformly reflects the extreme ultraviolet light 112.
[0065] According to one or more embodiments, the extreme
ultraviolet reflective element 302, such as the EUV mask blank 204,
is formed with the substrate 304, the multilayer stack 306, the
capping layer 308, and the absorber layer 310a, 310b or 310c. The
mask blank 204 has an optically flat surface and in some
embodiments efficiently and uniformly reflects the extreme
ultraviolet light 112. In an embodiment, the mask pattern 114 is
formed with the absorber layer 310 of the EUV mask blank 204.
[0066] Referring now to FIG. 4A, according to one or more
embodiments, an EUV mask blank comprises a substrate 304, a
multilayer stack 306 which reflects EUV radiation, the multilayer
stack 306 comprising a plurality of reflective layer pairs 316. A
capping layer 308 is on the multilayer stack 306 of reflecting
layers, the capping layer 308 comprising a capping layer top
surface 309. An absorber layer 310a is embedded in the capping
layer 308 and the multilayer stack 306. According to one or more
embodiments, reference to an absorber layer as being "embedded" in
the capping layer 308 and the multilayer stack 306, means that a
portion of the absorber layer 310a is beneath the capping layer top
surface 309. In the embodiment shown, the absorber layer 310a has a
thickness such that a portion of the absorber layer beneath
reflective layer pairs 316 of the multilayer stack 306.
[0067] In the embodiments shown, the absorber layer 310a comprises
an absorber layer top surface 311, and the absorber layer top
surface 311 is flush with the capping layer top surface 309. In
other words, the absorber layer top surface 311 and the capping
layer top surface 309 form a continuous plane or an unbroken
surface. Stated another way, the absorber layer 310a is formed in a
trench 315 (shown in FIG. 5E) in the capping layer 308 and the
multilayer stack 306. In some embodiments, the trench 315 in the
capping layer 308 and the multilayer stack 306 comprises vertical
sidewalls 317. In some embodiments such as the exemplary embodiment
shown in FIG. 4A, the absorber layer 310a comprises vertical
sidewalls 319a.
[0068] In some embodiments such as the exemplary embodiment shown
in FIG. 4B, the trench in the capping layer 308 and the multilayer
stack 306 comprises angled sidewalls forming an angle .beta. less
than ninety degrees with the capping layer top surface 309. It will
be appreciated that the trench is filled by the absorber layer 310b
and therefore, angled sidewalls of the trench and the angled
sidewalls of the absorber layer 310b are in direct contact. Thus,
in some embodiments, the absorber layer 310b comprises angled
sidewalls 319b forming an angle .beta. less than ninety degrees
with the capping layer top surface 309. In specific embodiments,
the angle .beta. is in a range of from 80 degrees to 90
degrees.
[0069] In one or more embodiments such as the exemplary embodiment
shown in FIG. 4C, the trench in the capping layer 308 and the
multilayer stack 306 comprises angled sidewalls forming an angle a
greater than ninety degrees with the capping layer top surface 309.
It will be appreciated that the trench is filled by the absorber
layer 310c and therefore, angled sidewalls of the trench and the
angled sidewalls of the absorber layer 310c are in direct contact.
Thus, in the embodiment shown in FIG. 4C, the absorber layer angled
sidewalls 319c form an angle .alpha. greater than ninety degrees
with the capping layer top surface 309. In specific embodiments,
the angle .alpha. is in a range of from 90 degrees to 100
degrees.
[0070] In a specific embodiment, an extreme ultraviolet (EUV) mask
blank 302 comprises a substrate 304, a multilayer stack 306 which
reflects EUV radiation, the multilayer stack 306 comprising a
plurality of reflective layer pairs 316 including molybdenum (Mo)
and silicon (Si), a capping layer 308 on the multilayer stack 306
of reflecting layers having a capping layer top surface 309, and an
absorber layer 310a, 310b or 310c embedded in the capping layer 308
and the multilayer stack 306, the absorber layer having an absorber
layer top surface 311 that is flush with the capping layer top
surface 309.
[0071] One or more embodiments provide a solution to mitigate the
mask 3D effect by to embedding the absorber layer beneath the
capping layer and within multilayers, so that the surface of the
patterned mask is smooth because the top surface of the absorber
layer and the capping layer top surface are flush or coplanar.
Incident EUV light from an angle (e.g. 6.degree.) in some
embodiments reaches the multilayer and get reflected without being
blocked by the absorber layer, which can occur when the absorber
layer is disposed on top of the capping layer. The embedded
absorber layer in some embodiments is single material which absorbs
EUV light by attenuation or stacking a multilayer absorber which
absorbs EUV light by both attenuation and phase shift mechanisms.
The embedded absorber layer in some embodiments is in the form of a
multilayer absorber which generates 180.degree. phase shift of EUV
light compared to the underlying multilayer for destructive
interference based on the material (n and k) and thickness.
[0072] In one or more embodiments, the absorber layer 310 is etch
selective to the capping layer 308. In some embodiments, the
capping layer 308 comprises ruthenium, and the absorber layer 310a,
310b or 310c is etch selective to ruthenium.
[0073] In an embodiment, the absorber layer 310a, 310b, or 310c
comprises a material comprising tantalum, for example, tantalum
nitride. In some embodiments, the absorber layer 310a, 310b, or
310c is an alloy of carbon and antimony, an alloy of bismuth and
iron, an alloy of copper and tellurium, an alloy of boron and
nickel, an alloy of copper and hafnium, an alloy of iron and
tellurium, an alloy of antimony and tellurium or an alloy of
tellurium and germanium. In some embodiments the absorber layer
comprises SiOC, Al, Ge, Z, Te, Mg, Ni, Sn, Ag, Fe, Ta, W, C, B, or
their alloys, carbides, borides, nitrides, silicides, and
oxides.
[0074] In some embodiments the absorber has a thickness of less
than about 45 nm. In some embodiments, the absorber layer has a
thickness of less than about 45 nm, including less than about 40
nm, less than about 35 nm, less than about 30 nm, less than about
25 nm, less than about 20 nm, less than about 15 nm, less than
about 10 nm, less than about 5 nm, less than about 1 nm, or less
than about 0.5 nm. In other embodiments, the absorber layer 310 has
a thickness in a range of about 0.5 nm to about 45 nm, including a
range of about 1 nm to about 44 nm, 1 nm to about 40 nm, and 15 nm
to about 40 nm. It will be understood that in embodiments in which
the absorber layer is embedded in the capping layer and the
multilayer stack, the absorber layer has a thickness greater than
the capping layer.
[0075] Without intending to be bound by theory, it is thought that
an absorber layer 310 having a thickness of less than about 45 nm
advantageously results in an absorber layer having a reflectively
of less than about 2%, reducing and mitigating 3D mask effects in
the extreme ultraviolet (EUV) mask blank.
[0076] In another specific method embodiment, the different
absorber layers are formed in a physical deposition chamber having
a first cathode comprising a first absorber material and a second
cathode comprising a second absorber material. Referring now to
FIG. 6 an upper portion of a multi-cathode source chamber 500 is
shown in accordance with an embodiment. The multi-cathode chamber
500 includes a base structure 501 with a cylindrical body portion
502 capped by a top adapter 504. The top adapter 504 has provisions
for a number of cathode sources, such as cathode sources 506, 508,
510, 512, and 514, positioned around the top adapter 504.
[0077] In one or more embodiments, the method forms an absorber
layer that has a thickness in a range of 5 nm and 60 nm. In one or
more embodiments, the absorber layer has a thickness in a range of
51 nm and 57 nm. In one or more embodiments, the materials used to
form the absorber layer are selected to effect etch properties of
the absorber layer. In one or more embodiments, The alloy of the
absorber layer is formed by co-sputtering an alloy absorber
material formed in a physical deposition chamber, which can provide
much thinner absorber layer thickness (less than 30 nm) and
achieving less than 2% reflectivity and desired etch properties. In
an embodiment, the etch properties and other desired properties of
the absorber layer in some embodiments are tailored to
specification by controlling the alloy percentage of each absorber
material. In an embodiment, the alloy percentage in some
embodiments is precisely controlled by operating parameters such
voltage, pressure, flow etc., of the physical vapor deposition
chamber.
[0078] The multi-cathode source chamber 500 in some embodiments is
part of the system shown in FIG. 3. In an embodiment, an extreme
ultraviolet (EUV) mask blank production system comprises a
substrate handling vacuum chamber for creating a vacuum, a
substrate handling platform, in the vacuum, for transporting a
substrate loaded in the substrate handling vacuum chamber, and
multiple sub-chambers, accessed by the substrate handling platform,
for forming an EUV mask blank, including a multilayer stack of
reflective layers on the substrate, the multilayer stack including
a plurality of reflective layer pairs, a capping layer on the
multilayer stack of reflective layers, and an absorber layer on the
capping layer. The system in some embodiments is used to make the
EUV mask blanks shown with respect to FIG. 4A-C and have any of the
properties described with respect to the EUV mask blanks described
with respect to FIG. 4A-C above.
[0079] Referring now to FIGS. 5A-H, an embodiment of a method of
making an EUV mask blank is shown. In one or more embodiments, the
method comprises forming on a substrate 304 a multilayer stack 306
which reflects EUV radiation, the multilayer stack 306 comprising a
plurality of reflective layer pairs 316. The method further
comprises forming a capping layer 308 on the multilayer stack 306,
the capping layer having a capping layer top surface 309. The
method further comprises forming an absorber layer such as the
absorber layer 310a, 310b or 310c embedded in the capping layer 308
and the multilayer stack 306. As shown in FIGS. 4A-C and 5A-H, the
absorber layer is embedded in only a portion of the multilayer
stack 306, for example, the first reflective layer pair 316 or the
first and second reflective layer pair 316. In some embodiments,
the absorber layer is embedded in three, four, five, six, seven,
eight, nine, ten, eleven, twelve, thirteen, fourteen, fifteen,
sixteen, seventeen, eighteen, ninety, or twenty or more reflective
layer pairs 316.
[0080] In some embodiments of the method, the absorber layer 310a
is formed in a trench 315 in the capping layer 308 and the
multilayer stack 306. In some embodiments, the trench 315 is formed
by masking and etching a portion of the capping layer and
multilayer stack. In specific embodiments, the masking comprises
forming a hard mask 322 on the capping layer, forming an
antireflective coating 324 on the hard mask 322 and forming a
photoresist 326 on the antireflective coating 324 as shown in FIG.
5B.
[0081] The hard mask and photoresist in some embodiments are any
suitable material. In one embodiment, the hard mask comprises a
carbon hard mask, a metal oxide hard mask layer, a metal nitride
hard mask layer, a silicon nitride hard mask layer, a silicon oxide
hard mask layer, a carbide hard mask layer, or other hard mask
layer known to one of ordinary skill in the art of microelectronic
device manufacturing. In one embodiment, the photoresist is
deposited using one or more mask layer deposition techniques known
to one of ordinary skill in the art of microelectronic device
manufacturing. In one embodiment, photoresist is deposited using
one of deposition techniques, such as but not limited to a CVD,
PVD, MBE, NOCVD, spin-on, or other insulating layer deposition
techniques known to one of ordinary skill in the art of
microelectronic device manufacturing. In one embodiment, the
opening is formed using one or more of the patterning and etching
techniques known to one of ordinary skill in the art of
microelectronic device manufacturing.
[0082] Referring now to FIG. 5C, the method further comprises
exposing the photoresist 326 through a mask pattern to radiation
and curing a portion of the photoresist to form a trench 327 in the
photoresist 326 to provide an exposed antireflective coating
portion 329. Referring now to FIG. 5D, the method of some
embodiments further comprises etching the exposed antireflective
coating portion 329 and etching a portion of the hard mask 322, the
capping layer 308 and the multilayer stack 306 underlying the
exposed antireflective coating portion 329 to form a trench 315 in
the capping layer 308 and the multilayer stack 306.
[0083] Referring now to FIGS. 5E and 5F, some embodiment further
comprise removing remaining photoresist 326 and antireflective
coating 324 and depositing an absorber layer 310 in the trench 315
in the capping layer 308 and at least of portion the multilayer
stack 306. In the embodiment shown, the trench 315 in the capping
layer and the multilayer stack comprises vertical sidewalls 317. In
some embodiments, the trench in the capping layer and the
multilayer stack comprises angled sidewalls forming an angle
greater than ninety degrees with the capping layer top surface. In
some embodiments, the trench in the capping layer and the
multilayer stack comprises angled sidewalls forming an angle less
than ninety degrees with the capping layer top surface.
[0084] Referring now to FIG. 5F and G, in some embodiments,
deposition of the absorber layer or multilayer stack absorber
layers in in some embodiments are formed using a flowable CVD
(FCVD) or spin coating based process. In some embodiments the
absorber layer comprises SiOC, Al, Ge, Z, Te, Mg, Ni, Sn, Ag, Fe,
Ta, W, C, B, or their alloys, carbides, borides, nitrides,
silicides, and oxides. In embodiments which comprise SiOC,
exemplary precursors such as octamethylcyclotetrasiloxane (OMCTS),
tetraethyl orthosilicate (TEOS) and other suitable precursors are
utilized to form SiOC.
[0085] Etching and an optional cleaning process to remove the
deposited FCVD layer are performed in some embodiments by reactive
ion etching or by chemical mechanical polishing and cleaning.
Referring to FIG. 5H, removal of the hard mask is achieved by
etching and cleaning using microelectronic fabrication techniques.
The process according to some embodiments, does not require etching
of absorber materials, removing the constraint of etchability for
selecting absorber materials.
[0086] Processes may generally be stored in the memory as a
software routine that, when executed by the processor, causes the
process chamber to perform processes of the present disclosure. The
software routine may also be stored and/or executed by a second
processor (not shown) that is remotely located from the hardware
being controlled by the processor. Some or all of the method of the
present disclosure may also be performed in hardware. As such, the
process may be implemented in software and executed using a
computer system, in hardware as, e.g., an application specific
integrated circuit or other type of hardware implementation, or as
a combination of software and hardware. The software routine, when
executed by the processor, transforms the general purpose computer
into a specific purpose computer (controller) that controls the
chamber operation such that the processes are performed.
[0087] Reference throughout this specification to "one embodiment,"
"certain embodiments," "one or more embodiments" or "an embodiment"
means that a particular feature, structure, material, or
characteristic described in connection with the embodiment is
included in at least one embodiment of the disclosure. Thus, the
appearances of the phrases such as "in one or more embodiments,"
"in certain embodiments," "in one embodiment" or "in an embodiment"
in various places throughout this specification are not necessarily
referring to the same embodiment of the disclosure. Furthermore,
the particular features, structures, materials, or characteristics
may be combined in any suitable manner in one or more
embodiments.
[0088] Although the disclosure herein has been described with
reference to particular embodiments, it is to be understood that
these embodiments are merely illustrative of the principles and
applications of the present disclosure. It will be apparent to
those skilled in the art that various modifications and variations
can be made to the method and apparatus of the present disclosure
without departing from the spirit and scope of the disclosure.
Thus, it is intended that the present disclosure include
modifications and variations that are within the scope of the
appended claims and their equivalents.
* * * * *