U.S. patent application number 16/800343 was filed with the patent office on 2020-06-18 for power converter having a conductive clip.
The applicant listed for this patent is TEXAS INSTRUMENTS INCORPORATED. Invention is credited to Rajeev Dinkar Joshi, Jie Mao.
Application Number | 20200194359 16/800343 |
Document ID | / |
Family ID | 67906034 |
Filed Date | 2020-06-18 |
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United States Patent
Application |
20200194359 |
Kind Code |
A1 |
Joshi; Rajeev Dinkar ; et
al. |
June 18, 2020 |
POWER CONVERTER HAVING A CONDUCTIVE CLIP
Abstract
A power supply module includes a metallic clip including a plate
having an area and a first and a second ridge on opposite sides of
the plate. The ridges bent in the same direction away from the
plate. The first and the second ridges conductively attached to the
substrate, where the substrate is of insulating material integral
with metal traces, the plate roofing over the substrate between the
ridges. A first MOS field-effect transistor (FET) chip and,
horizontally side-by-side, a second MOSFET chip are attached and
wire bonded to the substrate under the plate. The drain of the
first MOSFET is connected to the input terminal of the module, the
source of the first MOSFET is tied to the drain of the second
MOSFET, and the source of the second MOSFET, together with the
second ridge, is connected to ground. A driver and controller chip
is attached to the substrate under the plate and wire bonded to the
gates of the first and second MOSFET. A capacitor is attached to
the substrate under the clip plate and conductively connected to
the first clip ridge and to the drain of the first MOSFET.
Inventors: |
Joshi; Rajeev Dinkar;
(Cupertino, CA) ; Mao; Jie; (San Jose,
CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
TEXAS INSTRUMENTS INCORPORATED |
Dallas |
TX |
US |
|
|
Family ID: |
67906034 |
Appl. No.: |
16/800343 |
Filed: |
February 25, 2020 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15925191 |
Mar 19, 2018 |
10573585 |
|
|
16800343 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2924/1033 20130101;
H01L 2224/48091 20130101; H01L 23/49551 20130101; H01L 25/18
20130101; H01L 23/492 20130101; H01L 24/48 20130101; H01L
2224/37147 20130101; H01L 2224/48227 20130101; H01L 24/32 20130101;
H01L 2924/14 20130101; H01L 2224/48247 20130101; H01L 24/37
20130101; H01L 24/73 20130101; H01L 2224/40245 20130101; H01L
2924/10271 20130101; H01L 24/40 20130101; H01L 25/16 20130101; H01L
2924/181 20130101; H01L 23/642 20130101; H01L 2924/16251 20130101;
H01L 2924/30107 20130101; H01L 23/4334 20130101; H01L 2924/19041
20130101; H02M 3/158 20130101; H01L 2924/15192 20130101; H01L
23/49575 20130101; H01L 2924/19105 20130101; H01L 23/49589
20130101; H01L 2224/48137 20130101; H01L 2224/73265 20130101; H01L
2224/32225 20130101; H01L 2224/73221 20130101; H01L 2924/10329
20130101; H01L 2924/13091 20130101; H01L 2224/83801 20130101; H01L
2924/10253 20130101; H01L 2224/49111 20130101; H01L 24/41 20130101;
H02M 1/44 20130101; H01L 2224/73265 20130101; H01L 2224/32225
20130101; H01L 2224/48227 20130101; H01L 2924/00012 20130101; H01L
2224/48091 20130101; H01L 2924/00014 20130101 |
International
Class: |
H01L 23/495 20060101
H01L023/495; H01L 23/64 20060101 H01L023/64; H01L 23/00 20060101
H01L023/00; H01L 23/492 20060101 H01L023/492 |
Claims
1. A method of manufacturing a semiconductor package comprising:
assembling a passive component on a substrate of insulating
material with metal traces; assembling on the substrate,
horizontally and side-by-side a chip, a chip with a first MOS
field-effect transistor (FET), a chip with a second MOSFET, and a
chip with a driver and controller circuit; connecting by wire
bonding and traces, a drain of a first MOSFET to an input terminal
of the semiconductor package, a source of the first MOSFET to a
drain of a second MOSFET, a source of the second MOSFET to a ground
terminal, and gates of the first MOSFET and the second MOSFET to
the driver-and-controller terminals; connecting the passive
component to the drain of the first MOSFET and the input terminal
of the semiconductor package; providing a plate having an area and
a first and a second ridge on opposite sides of the plate, the
first ridge and the second ridge bent in the same direction away
from the plate; and attaching the first ridge and the second ridge
conductively to the substrate, the first ridge coupled to the
passive component and the second ridge coupled to the ground
terminal.
2. The method of claim 1, wherein the plate and the first and
second ridges together form a clip.
3. The method of claim 2 further comprising filling the space
between the substrate and the clip with a packaging material,
thereby covering the assembled chips and passive components while
leaving the outer surfaces of the clip and the substrate free of
packaging material.
4. The method of claim 1, wherein the passive component is a
capacitor.
5. The method of claim 1, wherein the first ridge and the second
ridge are at acute angles with respect to the plane along the
surface of the plate.
6. The method of claim 1, wherein the plate roofs over a portion of
the substrate between the first ridge and the second ridge.
7. The method of claim 1, wherein the driver chip and the
controller chip are located horizontally side-by-side.
8. The method of claim 1, wherein the insulating material is
ceramic material.
9. A method for fabricating a semiconductor package comprising:
assembling a capacitor on a substrate with metal traces; assembling
on the substrate a chip with a first MOS field-effect transistor
(FET), a chip with a second MOSFET, and a chip with a driver and
controller circuit; connecting by wire bonding and traces, a drain
of the first MOSFET to an input terminal of the semiconductor
package, a source of the first MOSFET to a drain of the second
MOSFET, a source of the second MOSFET to a ground, and gates of
MOSFET to driver-and-controller terminals; connecting the capacitor
to the drain of the first MOSFET and the input terminal of the
semiconductor package; providing a clip including a plate having an
area and a first and a second ridge on opposite sides of the plate,
the first and a second ridges bent in the same direction away from
the plate; and attaching the ridges conductively to the substrate
so that the area of the plate forms a roof over the assembled chips
and passive components, the first ridge is tied to the capacitor
and the second ridge is tied to ground;
10. The method of claim 9 further comprising filling the space
between the substrate and the clip with a packaging material,
thereby covering the assembled chips and passive components while
leaving the outer surfaces of the clip and the substrate free of
packaging material.
11. The method of claim 9 wherein the first and the second MOSFETs
are made of gallium nitride.
12. The method of claim 9 wherein the substrate is made of a
ceramic material including at least one patterned conductive
layer.
13. The method of claim 9 wherein the clip is of metal.
14. The method of claim 9 wherein the clip is selected from a group
consisting of copper, copper alloy, aluminum, silver, graphene, and
material of high thermal conductivity.
15. The method of claim 9, wherein the plate roofs over a portion
of the substrate between the first ridge and the second ridge.
16. The semiconductor package of claim 9, wherein the semiconductor
package functions as a power supply module.
Description
[0001] This application is a division of U.S. application Ser. No.
15/925,191, filed Mar. 19, 2018, the contents of which are herein
incorporated by reference in its entirety.
TECHNICAL FIELD
[0002] Embodiments of the invention are related in general to the
field of semiconductor devices and processes, and more specifically
to a system structure and fabrication method of a high voltage
power supply module having a conductive clip.
DESCRIPTION OF RELATED ART
[0003] Among power switching devices are the DC-DC converters
including Switched Mode Power Supply circuits. Particularly
suitable for the emerging power delivery requirements are the
synchronous Buck converters with two power MOS field effect
transistors (FETs) connected in series and coupled together by a
common switch node. In the Buck converter, a control FET chip, also
called the high side switch, is connected between the supply
voltage V.sub.IN and an LC output filter, and a synchronous (sync)
FET chip, also called the low side switch, is connected between the
LC output filter and ground potential.
[0004] The gates of the control FET chip and the sync FET chip are
connected to a semiconductor chip including an integrated circuit
(IC) acting as the driver of the converter, and the driver, in
turn, is connected to a controller IC. Preferably, both ICs are
integrated on a single chip.
[0005] The inductor of the output circuitry serves as the energy
storage of the power supply circuit. Consequently, the inductor has
to be a large enough component (typical sizes are 300 to 400 nH) to
reliably function for maintaining a constant output voltage
V.sub.OUT.
[0006] For many of today's power switching devices, the chips of
the power MOSFETs and the chip of the driver and controller IC are
made of silicon and assembled as individual components. Each chip
is typically attached to a rectangular shaped pad of a metallic
leadframe; the pad is surrounded by leads as output terminals. The
leads are commonly shaped without cantilever extensions, and
arranged in the manner of Quad Flat No-Lead (QFN) or Small Outline
No-Lead (SON) devices. The electrical connections from the chips to
the leads are provided by bonding wires, which add, due to their
lengths and resistances, significant parasitic inductance into the
circuit. Each assembly is typically packaged in a plastic
encapsulation, and the packaged components are employed as discrete
building blocks for board assembly of power supply systems.
[0007] In other power switching devices, the power MOSFET chips and
the driver-and-controller IC are assembled horizontally
side-by-side on a leadframe pad, which in turn is surrounded on all
four sides by leads serving as device terminals. The leads are
shaped in QFN or SON fashion. The electrical connections between
the chips and the leads may be provided by bonding wires; in some
recently introduced advanced assemblies, clips made of copper
substitute for many connecting wires. These clips add less
parasitic inductance than do wires.
[0008] In another recently introduced scheme, the control FET chip
and the sync FET chip, both made of silicon, are assembled
vertically on top of each other in a stack, with the physically
larger-area chip of the two attached to the leadframe pad, and with
clips providing the connections to the switch node and the stack
top tied to input supply V.sub.IN. Usually, the sync FET chip is
assembled onto the leadframe pad and the control FET chip is tied
to the input supply V.sub.IN. The pad may be connected to ground
potential and serves as a spreader of operationally generated heat.
It has been observed, however, that during the initial on-stages
the voltage at the switch node may display a ringing mode up to 25
V, which may last about 50 ns.
[0009] In order to alleviate this ringing disturbance, another
recent proposal (U.S. Pat. No. 8,431,979, issued Apr. 30, 2013,
"Power Converter Having Integrated Capacitor" by J. Herbsommer et
al.) inserts a capacitor between the top clip tied to the input
terminal and the leadframe pad tied to ground potential. Since the
root cause of the ringing was found to be the exchange of energy
between parasitic inductances mainly associated with the top clip
at input node and the capacitance across the sync FET, the
capacitor network connected between V.sub.IN and ground in parallel
with the converter helps to channel the ringing energies from the
capacitor associated with the converter's sync transistor at the
output switch node through the capacitor network into the ground
node.
[0010] Recently the III-V compound gallium nitride (GaN) became
commercially available as a base semiconductor material. Due to the
wide band gap, the compound has a special appeal for optoelectronic
applications such as blue light-emitting diodes. Furthermore,
transistors made of GaN can operate at high voltages and high
temperature, making them attractive for power converters operating
at high frequencies. The cost of GaN-based devices has come down
significantly, since thin films of GaN can be deposited on zinc
oxide, silicon carbide, and silicon wafers.
SUMMARY
[0011] One example provides a power supply module. The power supply
module includes a metallic clip including a plate having an area
and a first and a second ridge on opposite sides of the plate. The
ridges bent in the same direction away from the plate. The first
and the second ridges conductively attached to the substrate, where
the substrate is of insulating material integral with metal traces,
the plate roofing over the substrate between the ridges. A first
MOS field-effect transistor (FET) chip and, horizontally
side-by-side, a second MOSFET chip are attached and wire bonded to
the substrate under the plate. The drain of the first MOSFET is
connected to the input terminal of the module, the source of the
first MOSFET is tied to the drain of the second MOSFET, and the
source of the second MOSFET, together with the second ridge, is
connected to ground. A driver and controller chip is attached to
the substrate under the plate and wire bonded to the gates of the
first and second MOSFET. A capacitor is attached to the substrate
under the clip plate and conductively connected to the first clip
ridge and to the drain of the first MOSFET.
[0012] Another example provides a method for fabricating a power
supply module. Passive electronic components including a capacitor
are assembled on a substrate of insulating material integral with
metal traces. Then, a first MOS field-effect transistor (FET), a
chip with a second MOSFET, and a chip with a driver and controller
circuit are assembled on the substrate, horizontally and
side-by-side a chip. The drain of the first MOSFET is connected, by
wire bonding and traces, to the input terminal of the power supply
module, the source of the first MOSFET to the drain of the second
MOSFET, the source of the second MOSFET to ground, and the MOSFET
gates to the driver-and-controller terminals. Then the capacitor is
connected to the drain of the first MOSFET and the input terminal
of the module. A metallic clip is provided including a plate having
an area and a first and a second ridge on opposite sides of the
plate, the ridges bent in the same direction away from the plate.
Then, the ridges are conductively attached to the substrate so that
the area of the plate forms a roof over the assembled chips and
passive components, the first ridge is tied to the capacitor and
the second ridge is tied to ground. The space between the substrate
and the clip is filled with a packaging material, thereby
encapsulating the assembled chips and passive components while
leaving the outer surfaces of the clip and the substrate free of
packaging material.
BRIEF DESCRIPTION OF THE DRAWINGS
[0013] FIG. 1 illustrates a perspective view of a packaged
synchronous Buck converter with a decoupling capacitor and
low-inductance clip according to the invention.
[0014] FIG. 2 shows a cross section of the synchronous Buck
converter with a decoupling capacitor and low-inductance clip
according of FIG. 1.
[0015] FIG. 3 is a circuit diagram of a synchronous Buck converter
according to the invention.
[0016] FIG. 4 is a flow diagram of a process for the fabrication of
a power converter module.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0017] Building on the experience with power converters using
silicon chips, attempts in incorporating capacitor networks on the
circuit board are ineffective in reducing the ringing when the
parasitic inductance associated with the traces that connect the
capacitor to the power module are too high; this is especially true
when the capacitor is connected with bond wires to the transistor
terminals.
[0018] Due to their lateral construction, field effect transistors
made of GaN cannot be stacked or flip-chip assembled; consequently,
they have to be wire bonded. In contrast, the one or more
capacitors for reducing the ringing problem can utilize
low-inductance traces of the board metallization.
[0019] The ringing problem is solved at the switch node of power
modules using GaN chips, using a method of structuring and
fabricating the power loop, the control loop, and the decoupling
capacitor so that not only a low-value for the parasitic inductance
of the capacitor loop is achieved, but also concurrently
cross-coupling and cross-talk of the power and control loops are
dissolved, and the heat dissipation for high-frequency power
switching is enhanced.
[0020] One power module has a synchronous Buck converter using two
GaN chips with filed effect transistors (FETs) horizontally
side-by-side assembled on an insulating substrate made of ceramic
with good heat dissipation and electrical insulation; metal traces
are integral with the substrate. The FET terminals are wire bonded
to the substrate traces. The module further includes a driver and
control chip assembled on the substrate and wire bonded to the FET
gates. In addition, at least one capacitor, attached to the
substrate, is inserted between the input terminal and ground. The
connection to ground is constructed as a metallic clip with a flat
plate portion of an area flanked by two ridges bent an angle in the
same direction from the plate; one ridge is tied to the capacitor,
the other ridge to ground, while the flat plate spans like a roof
over the assembled synchronous Buck converter, control loop and
capacitor. The clip has inherently low parasitic inductance,
effectively isolates cross coupling between power loop and control
loop, and acts, when made of high thermal conductivity material
such as copper, as an additional heat sink.
[0021] Various examples of the disclosure use MOSFETs in a
source-down configuration, but the invention may be implemented in
other configurations such as with the FETs in a drain-down
configuration, in which the terminal polarities of the FETs are
reversed. Persons skilled in the art may also substitute the
MOSFETs with bipolar transistors to implement the invention without
undue experiments.
[0022] FIGS. 1 and 2 illustrate an exemplary embodiment of the
invention, a high frequency power supply converter generally
designated 100. Assembled on an insulating substrate 120 is a
plurality of active and passive electronic components including a
metallic clip 110. Substrate 120 is preferably made of a ceramic
material of high thermal conductivity, and clip 110 is selected
from a material of high thermal conductivity including metals such
as copper, copper alloy, aluminum, and silver, and graphene. The
outer surface 110a of clip 110 may have a metallurgical
configuration to facilitate solderability or thermal radiation. The
assembly is encapsulated in a plastic package 160 preferably so
that the top surface 110a of the clip and the bottom surface 120a
of the substrate remain un-encapsulated and thus available to
conduct thermal energy away from converter 100. For clarity
purposes, the material for package 160 is shown transparent in
FIGS. 1 and 2; in reality, however, package 160 is preferably made
of an opaque compound such as an epoxy-based molding
formulation.
[0023] Substrate 120 includes metal pads and traces preferably made
from at least one metal layer patterned into traces and pads. In
FIG. 1, the metal pads and traces are indicated by contact areas
121, and in FIG. 2 by portions of layer 122. For some devices,
substrate 120 may also include metal barriers; FIGS. 1 and 2
display barrier 123 and barrier 124. The pads and barriers may be
at electrical potentials; for instance, in the embodiment of FIGS.
1 and 2, barrier 124 may be connected to ground potential.
[0024] As FIG. 1 indicates, clip 110 includes a plate 111 with an
outer surface 110a. The plate 111 has an area bordered by length
112, first side 113 and second side 114. Preferably second side 114
has the same length as first side 113. As further shown in FIGS. 1
and 2, clip 110 includes a ridge 115 (first ridge) connected to
first side 113, and a ridge 116 connected to second side 114. The
ridges may have the same area or different areas. Both ridge 115
and ridge 116 are bent in the same direction away from plate 111;
in FIGS. 1 and 2, both ridges are bent away from plate 111 by an
acute angle.
[0025] FIGS. 1 and 2 indicate that ridge 115 and ridge 116 are
attached to substrate 120. To facilitate the attachment, metallic
barriers 123 and 124 may have solderable surfaces so that ridge 115
can be soldered to barrier 123 and ridge 116 can be soldered to
barrier 124. As mentioned, for the embodiment on FIGS. 1 and 2,
barrier 124 is tied to ground. As a result of the attachment of
clip 110 on substrate 120, plate 111 is roofing over the substrate
area between the attached ridges. It is preferred that plate 111 is
approximately parallel to substrate 120; consequently, the distance
117 between plate 111 and substrate 120 is substantially constant
and provides space for assembling components on the substrate under
the roof of the clip.
[0026] FIG. 2 illustrates that a plurality of components are
assembled on substrate 120 and interconnected by traces 122. In the
exemplary embodiment, as parts of a synchronous Buck converter, a
first MOS field effect transistor (FET) chip 131 and, horizontally
side-by-side, a second MOS FET chip 132 are attached and bonded by
wires 140 to substrate 120 under plate 111. In the example, chips
131 and 132 are made of gallium nitride; in other embodiments, they
may be made of silicon, silicon germanium, gallium arsenide or
other semiconductor compounds used for semiconductor devices. Chip
131 includes the control transistor and chip 132 includes the
synchronous (sync) transistor of the converter. In electrical
terms, the drain 131c of first (control) FET 131 is connected to
the input terminal V.sub.IN, which may coincide with barrier 123.
The source 131a of first (control) FET 131 is tied to the drain
132c of the second (sync) FET 132. The source 132a of the second
FET is connected to ground, which may coincide with barrier
124.
[0027] FIGS. 1 and 2 further indicate that a first capacitor 150 is
attached to substrate 120 under the plate 111 and conductively
connected to the ridge 115 and to the drain 131c of first FET 131.
The capacitor is integrated into the synchronous Buck converter
using clip 110, which is formed to have a low inductance. Capacitor
150 is sized so that it can divert, in conjunction with the
inductance of clip 110, a large portion of the energy between input
inductance and output capacitor, which causes oscillations at the
onset of converter operation (so called ringing) from the converter
switch node to ground. As a result of this decoupling action,
ringing oscillations of within the control loop of the converter
are significantly reduced.
[0028] It should be pointed out that in certain embodiments a
second or even more capacitors may be employed in parallel to first
capacitor 150. The additional capacitors may be positioned under
the roofing clip plate at various locations of the substrate
area.
[0029] FIG. 1 shows that the integrated circuit chip 170 including
the driver and controller functions of the converter, together with
the connecting network of traces to the converter, is assembled on
the substrate area under the roof of plate 111. The terminals of
the chip 170 are wire bonded to the gates first FET 131 and second
FET 132. Due to the arrangement of the control loop under the
inductance of roofing plate 111 and thus inside of the package of
the converter, the control loop of the converter is largely
decoupled from the power loop. Consequently, cross talk between the
control loop and power loop is largely suppressed.
[0030] As FIGS. 1 and 2 show, the distance 117 between substrate
120 and plate 110 roofing over the substrate after clip attachment
is greater than the heights of the capacitor 150 and the bonding
wire loops 140. In addition, since clip 110 is formed to roof over
the network of the converter as well as over the network of driver
and controller, power loop and control loop are largely decoupled.
The converter network, the driver/controller network, and the
ringing-suppressing capacitor/inductance network are summarized in
the circuit diagram of FIG. 3.
[0031] In FIG. 3, electrical energy may exchange between the input
inductance L.sub.IN (301) and the parasitic output capacitance
C.sub.OS (133) of the sync FET (132). This is the root cause of the
ringing phenomenon. By introducing decoupling capacitor C.sub.DEC
(150), the ringing energies may be diverted through the C.sub.DEC
(150) to ground, thus reducing the oscillations of voltage at
switch node 340. Decoupling inductance L.sub.DEC is the parasitic
inductance associated with clip 110, especially the plate 111,
connected to capacitor C.sub.DEC (150). The converter network
listed in FIG. 3 includes the sync FET (132) and the control FET
(131). Further listed in FIG. 3 are the input capacitor C.sub.IN
(302), the input inductance L.sub.IN (303), and the inductance
L.sub.SUB (304) associated with the ceramic substrate 120.
[0032] As FIG. 3 shows, an input current flowing from supply
V.sub.IN (360) to the drain 131c of control FET 131 encounters a
substrate inductance L.sub.SUB (304) and the input inductance (wire
bond inductance of drain connection) L.sub.IN (301). Gate 131b is
connected to a respective wire bond with inductance L.sub.GATE 331b
to driver 390. The parasitic inductance L.sub.SOURCE (331a)
originates in conjunction with wire bonding of source 131a. FIG. 3
further lists the electrical parasitics in conjunction with the
source-down connection of sync FET 132 to the substrate pad at
ground potential 350. The connection of source 132a to the pad is
performed by wire bonding and the parasitic inductance is
L.sub.SOURCE (332a). The parasitic inductance of drain 132c is
L.sub.DRAIN (332c) and determined by wire bonding. Gate 132b is
connected by wire bond to driver 391 and creates inductance
L.sub.GATE (332b). In FIG. 3, the load current I.sub.LOAD of the
converter flows from switch node 340 through wire bond to an output
inductor L.sub.OUT (371) and V.sub.OUT (370).
[0033] In the exemplary power module of FIGS. 1 and 2, several
components can be designed for the control of the voltage ringing
at the switch node. They include the size of the (one or more)
capacitors C.sub.DEC (150) and the geometries of clip 110 that
connects the capacitors to ground. Electrical simulations were
performed on exemplary gallium nitride half bridge power modules
with identical component layouts. The simulations compared a first
module assembled on an aluminum-nitride substrate integral with a
single-sided patterned copper metallization (100 .mu.m layer
thickness) and a copper clip (layout-sized, 250 .mu.m thickness),
to a second module assembled on an aluminum-nitride substrate
integral with double-sided copper metallization (100 .mu.m
thickness) and metal-filled via holes extending through the
substrate thickness and connecting the copper metallizations.
[0034] The results showed for the first module a power loop
inductance of 8.5 nH and for the second module a power loop
inductance of 9.1 nH. From this result it can be concluded that
both module structures deliver similar inductances. Actually, a
copper clip may deliver a somewhat smaller inductance and is thus a
preferred configuration. In addition, a copper clip as a
stand-alone piece part is a preferred solution due to its lower
cost compared to a backside metal layer deposited on the ceramic
substrate, coupled with the need for a plurality of metal-filled
via holes through the substrate for connecting the back-sider
metallization to the half bridge power module assembled on the
front-side of the substrate. Further, a copper clip offers itself
as an additional heat spreader for dissipating the thermal energy
created by the power module operating at high frequency.
[0035] The same solution of using a metal clip and its small
parasitic inductance can be scaled for other high power modules
which require multi-metal layer substrates.
[0036] Another embodiment of the invention is a method for
fabricating a power converter based on chips made of gallium
nitride (GaN). DC-DC converters using field effect transistors made
in chips of GaN, a wide band gap semiconducting III-V compound,
offer operation at high voltage, high switching frequency, and high
temperature. The cost of GaN-based devices has come down
significantly, since thin films of GaN can be deposited on zinc
oxide, silicon carbide, and silicon wafers.
[0037] The flow of certain processes of the fabrication method is
summarized in FIG. 4. To insure effective heat dissipation from
high output power modules, an insulating substrate of high thermal
conductivity is selected for the fabrication. A preferred material
is a ceramic compound of high thermal conductivity integral with at
least one conductive layer, such as a metal layer which can be
patterned into conductive traces.
[0038] In process 401 of FIG. 4, passive electronic components are
assembled on the substrate. For reducing or suppressing any voltage
ringing at switching, at least one capacitor is among the passive
components. In process 402, a GaN chip with a first MOS
field-effect transistor (FET), a second GaN chip with a second FET,
and a chip (preferably silicon) with a driver and controller
circuitry are horizontally and side-by-side assembled on the
substrate and wire bonded to the substrate.
[0039] In order to create the connections for the power loop and
the driver-and-controller loop of a synchronous Buck converter, the
connections among the chips, summarized in process 403 of FIG. 4,
are performed so that the drain of the first MOSFET is tied to the
input terminal of the module, the source of the first MOSFET is
tied to the drain of the second MOSFET, and the source of the
second MOSFET is tied to ground. Furthermore, the gates of the FETs
are tied to the driver-and-controller terminals.
[0040] In process 404 of FIG. 4, one terminal of the capacitor is
connected, preferably by substrate traces, to the drain of the
first MOSFET and thus also to the input terminal of the module. The
other terminal of the capacitor is tied to the clip (see
below).
[0041] In process 405, a conductive clip is provided which includes
a flat plate portion having an area and a first and a second ridge
on opposite sides of the plate. Both ridges are bent in the same
direction away from the plate, preferably by an acute angle. The
material of the clip is selected from a group including copper,
copper alloy, aluminum, silver, graphene, and materials of high
electrical and thermal conductivity.
[0042] In the next process 406, both clip ridges are attached to
the substrate so that the area of the plate forms a roof over the
assembled chips and passive components, the first ridge is tied to
the capacitor and the second ridge is tied to ground. In the
configuration after the clip attachment, the distance between the
substrate and the plate roofing over the substrate is greater than
the heights of the capacitor and the bonding wire loops. With this
arrangement, a space is defined, which physically includes the
power loop as well as the control loop, and in which the
low-inductance clip can electrically act to isolate the coupling
between the power loop and the control loop, effectively resolving
any cross-coupling between the two loops.
[0043] In the next process 407, the space between the substrate and
the clip is filled with a packaging material. A preferred method is
a transfer molding process using an epoxy-based molding compound.
By this filling process, the assembled chips, passive components,
and wire bonds are encapsulated while the outer surfaces of the
metallic clip as well as the ceramic substrate remain free of
packaging material so that they can serve to enhance external heat
sinking.
[0044] It is a technical advantage that compared to conventional
power modules using silicon MOSFET chips and lateral or stacked
chip designs, the power module of FIGS. 1, 2, and 3 based on
gallium nitride MOSFET chips has smaller power loop inductance and
thus offers reduced voltage ringing at power switching.
[0045] It is another technical advantage that compared to
multilayer printed circuit board structures, the use of a ceramic
substrate offers significantly improved heat dissipation.
[0046] It is another advantage that compared to multilayer ceramic
structures, the use of a metallic clip together with a patterned
single-layer ceramic substrate is significantly less expensive.
[0047] While this invention has been described in reference to
illustrative embodiments, this description is not intended to be
construed in a limiting sense. Various modifications and
combinations of the illustrative embodiments, as well as other
embodiments of the invention, will be apparent to persons skilled
in the art upon reference to the description. As an example, the
invention applies not only to field effect transistors, but also to
other suitable power transistors.
[0048] As another example, the invention applies to power
converters using MOSFET chips made of any semiconductor material,
including silicon, germanium, silicon germanium, III-V compounds
and II-VI compounds used in semiconductor manufacturing.
[0049] As yet another example, two or more capacitors C.sub.DEC may
be integrated into the power supply module, together with
respective parasitic inductances L.sub.DEC.
[0050] As yet another example, the conductive clips may have a
variety of geometrical configurations, including a variety of
configurations for the ridges.
[0051] It is therefore intended that the appended claims encompass
any such modifications or embodiments.
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