U.S. patent application number 16/666288 was filed with the patent office on 2020-02-27 for interface substrate and method of making the same.
The applicant listed for this patent is QUALCOMM Incorporated. Invention is credited to Jon Gregory ADAY, Steve Joseph BEZUK, Nicholas Ian BUCHAN, Hong Bok WE.
Application Number | 20200066964 16/666288 |
Document ID | / |
Family ID | 60244054 |
Filed Date | 2020-02-27 |
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United States Patent
Application |
20200066964 |
Kind Code |
A1 |
ADAY; Jon Gregory ; et
al. |
February 27, 2020 |
INTERFACE SUBSTRATE AND METHOD OF MAKING THE SAME
Abstract
A package may include a substrate and a semiconductor die with
the substrate having a smaller width than the semiconductor die and
encapsulated in a mold compound. In one example, the package may be
a wafer level package that allows an external connection on the
backside of the package to enable manufacturing in a panel or wafer
form.
Inventors: |
ADAY; Jon Gregory;
(Escondido, CA) ; WE; Hong Bok; (San Diego,
CA) ; BEZUK; Steve Joseph; (Saint Augustine, FL)
; BUCHAN; Nicholas Ian; (San Jose, CA) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
QUALCOMM Incorporated |
San Diego |
CA |
US |
|
|
Family ID: |
60244054 |
Appl. No.: |
16/666288 |
Filed: |
October 28, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15256501 |
Sep 2, 2016 |
10516092 |
|
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16666288 |
|
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|
62333038 |
May 6, 2016 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/81815
20130101; H01L 2224/92125 20130101; H01L 2224/16225 20130101; H01L
24/81 20130101; H01L 24/09 20130101; H01L 24/17 20130101; H01L
23/49838 20130101; H01L 24/11 20130101; H01L 41/1132 20130101; H01L
23/3114 20130101; H01L 21/76877 20130101; H01L 21/563 20130101;
H01L 2224/73204 20130101; H01L 24/95 20130101; H01L 24/73 20130101;
H01L 24/03 20130101; H01L 41/053 20130101; H01L 2224/0401 20130101;
H01L 2224/16235 20130101; H01L 24/96 20130101; H01L 2224/13101
20130101; H01L 23/3135 20130101; H01L 24/94 20130101; H01L 21/561
20130101; H01L 21/78 20130101; H01L 2224/83855 20130101; H01L 24/05
20130101; H01L 24/13 20130101; H01L 24/14 20130101; H01L 2224/81193
20130101; H01L 2224/97 20130101; H01L 24/16 20130101; H01L
2224/32225 20130101; H01L 23/49827 20130101; H01L 2224/83851
20130101; H01L 23/49866 20130101; H01L 24/32 20130101; H01L 2224/94
20130101; H01L 2924/15311 20130101; H01L 23/49816 20130101; H01L
24/83 20130101; H01L 2224/83001 20130101; H01L 23/3128 20130101;
H01L 2224/94 20130101; H01L 2224/81 20130101; H01L 2224/97
20130101; H01L 2224/81 20130101; H01L 2224/73204 20130101; H01L
2224/16225 20130101; H01L 2224/32225 20130101; H01L 2924/00012
20130101; H01L 2924/15311 20130101; H01L 2224/73204 20130101; H01L
2224/16225 20130101; H01L 2224/32225 20130101; H01L 2924/00012
20130101; H01L 2224/13101 20130101; H01L 2924/014 20130101; H01L
2924/00014 20130101 |
International
Class: |
H01L 41/113 20060101
H01L041/113; H01L 21/768 20060101 H01L021/768; H01L 21/56 20060101
H01L021/56; H01L 23/00 20060101 H01L023/00; H01L 21/78 20060101
H01L021/78; H01L 23/31 20060101 H01L023/31; H01L 23/498 20060101
H01L023/498; H01L 41/053 20060101 H01L041/053 |
Claims
1. A package comprising: a semiconductor die with a perimeter
defined by sidewalls and a width; a package substrate with
sidewalls, the package substrate located vertically below the
semiconductor die within the perimeter; a mold compound with
sidewalls and a width configured to encapsulate the package
substrate, the mold compound width is approximately the same as the
semiconductor die width and each sidewall of the mold compound is
co-planar with a respective sidewall of the semiconductor die; a
first plurality of pads on a first side of the package substrate; a
second plurality of pads on a second side of the package substrate;
a plurality of interconnects that extend from the first plurality
of pads to the second plurality of pads; and a redistribution layer
embedded in the package substrate proximate the second side of the
package substrate and embedded in the mold compound wherein the
second side of the package substrate faces the semiconductor
die.
2. The package of claim 1, wherein the sidewalls of the package
substrate are not exposed and the package substrate is completely
underneath the semiconductor die.
3. The package of claim 1, wherein the mold compound is completely
underneath the semiconductor die within the perimeter of the
semiconductor die.
4. The package of claim 1, further comprising: a plurality of first
contacts on the first plurality of pads; and a plurality of second
contacts on the second plurality of pads, the plurality of second
contacts coupled to the semiconductor die.
5. The package of claim 4, wherein the plurality of first contacts
are solder bumps or solder balls and the plurality of second
contacts are solder bumps or solder balls.
6. The package of claim 1, wherein the plurality of interconnects
are copper pillars or conductive vias.
7. The package of claim 1, wherein the sidewalls of the package
substrate are parallel to sidewalls of the mold compound.
8. The package of claim 1, wherein the package is incorporated into
a device selected from a group consisting of a music player, a
video player, an entertainment unit, a navigation device, a
communications device, a mobile device, a mobile phone, a
smartphone, a personal digital assistant, a fixed location
terminal, a tablet computer, a computer, a wearable device, a
laptop computer, a server, and a device in an automotive vehicle,
and further including the device.
9. The package of claim 1, wherein the mold compound includes a
width sized to approximately match the semiconductor die width.
10. The package of claim 1, wherein the package substrate is
smaller in size than the semiconductor die.
11. A method for forming a package, comprising: forming a plurality
of substrates, each of the plurality of substrates has a first
width; forming a plurality of semiconductor dies on a wafer, each
of the plurality of semiconductor dies has a second width larger
than the first width; placing the plurality of substrates on the
plurality of semiconductor dies; attaching each of the plurality of
substrates to a corresponding one of the plurality of semiconductor
dies; applying a mold compound to the wafer, the mold compound
configured to encapsulate the plurality of substrates, wherein each
semiconductor die has a perimeter defined by sidewalls and a width,
each substrate has sidewalls and is vertically below one of the
plurality of semiconductor dies within the perimeter, and the mold
compound has sidewalls and a width configured to encapsulate one of
the plurality of substrates and is approximately the same as the
semiconductor die width and each sidewall of the mold compound is
co-planar with a respective sidewall of the semiconductor die; and
singulating the wafer to form a plurality of packages, each of the
plurality of packages comprises one of the plurality of substrates
and one of the plurality of semiconductor dies and each of the
plurality of packages has a third width approximately equal to the
second width.
12. The method of claim 11, wherein the forming each of the
plurality of substrates comprises: forming a plurality of
interconnects that extend from a first side of the substrate to a
second side of the substrate opposite the first side of the
substrate; forming a redistribution layer embedded in the substrate
proximate the second side of the substrate; forming a first
plurality of pads on the first side of the substrate, the first
plurality of pads connected to the plurality of interconnects;
forming a plurality of first contacts on the first plurality of
pads; forming a second plurality of pads on the second side of the
substrate, the second plurality of pads connected to the plurality
of interconnects; forming a plurality of second contacts on the
second plurality of pads; and applying a mold compound configured
to encapsulate the substrate.
13. The method of claim 12, wherein sidewalls of each of the
plurality of substrates are not exposed.
14. The method of claim 12, wherein each of the plurality of
substrates is completely underneath a corresponding one of the
plurality of semiconductor dies.
15. The method of claim 12, wherein, after the singulating, the
mold compound is completely underneath each of the plurality of
semiconductor dies within a perimeter of each of plurality of
semiconductor dies.
16. The method of claim 12, wherein the plurality of first contacts
are solder bumps or solder balls and the plurality of second
contacts are solder bumps or solder balls.
17. The method of claim 12, wherein the plurality of interconnects
are copper pillars or conductive vias.
18. The method of claim 12, wherein each of the plurality of
substrates is composed of ceramic or organic materials.
19. The method of claim 12, wherein at least one of the plurality
of packages is incorporated into a device selected from a group
consisting of a music player, a video player, an entertainment
unit, a navigation device, a communications device, a mobile
device, a mobile phone, a smartphone, a personal digital assistant,
a fixed location terminal, a tablet computer, a computer, a
wearable device, a laptop computer, a server, and a device in an
automotive vehicle, and further including the device.
20. The method of claim 11, wherein the attaching each of the
plurality of substrates to the corresponding one of the plurality
of semiconductor dies comprises a solder reflow process or a curing
process.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application for patent claims the benefit of
U.S. Provisional Patent Application No. 62/333,038, entitled
"INTERFACE SUBSTRATE AND METHOD OF MAKING THE SAME," filed May 6,
2016, pending, assigned to the assignee hereof, and expressly
incorporated herein by reference in its entirety.
[0002] The present application for patent is a continuation of
patent application Ser. No. 15/256,501 entitled "INTERFACE
SUBSTRATE AND METHOD OF MAKING THE SAME" filed Sep. 2, 2016,
pending, assigned to the assignee hereof, and expressly
incorporated by reference in its entirety.
FIELD OF DISCLOSURE
[0003] This disclosure relates generally to substrates, and more
specifically, but not exclusively, to wafer level package
substrates.
BACKGROUND
[0004] Conventional wafer level package (WLP) use photo-dielectric
material for layer to layer passivation and connection. However,
photo-dielectric material is a thinner and physically weaker
material than that used for substrate cores. In addition,
conventional substrate based and leadframe based packages are
bigger in size than semiconductor dies coupled to the WLPs. This
creates a problem when the package size is critical, such as when
the package size must be the same as the semiconductor die coupled
to the package. In addition, certain sensor applications require
alternative interconnection methods than can be provided with a WLP
since the materials and processes used would impact the performance
of the sensing components.
[0005] Accordingly, there is a need for systems, apparatus, and
methods that overcome the deficiencies of conventional approaches
including the methods, system and apparatus provided hereby.
SUMMARY
[0006] The following presents a simplified summary relating to one
or more aspects and/or examples associated with the apparatus and
methods disclosed herein. As such, the following summary should not
be considered an extensive overview relating to all contemplated
aspects and/or examples, nor should the following summary be
regarded to identify key or critical elements relating to all
contemplated aspects and/or examples or to delineate the scope
associated with any particular aspect and/or example. Accordingly,
the following summary has the sole purpose to present certain
concepts relating to one or more aspects and/or examples relating
to the apparatus and methods disclosed herein in a simplified form
to precede the detailed description presented below.
[0007] In one aspect, a semiconductor package comprises: a
semiconductor die; a substrate; a mold compound configured to
encapsulate the substrate; a first plurality of pads on a first
side of the substrate; a plurality of first contacts on the first
plurality of pads; a second plurality of pads on a second side of
the substrate; a plurality of second contacts on the second
plurality of pads, the plurality of second contacts coupled to the
semiconductor die; a plurality of interconnects 180 that extend
from the first plurality of pads to the second plurality of pads;
and a redistribution layer embedded in the substrate proximate the
second side of the substrate.
[0008] In another aspect, a sensor package comprises: a sensor
configured to receive an input and transmit an output; a thin film
transistor connected to the sensor; a piezoelectric layer on a
first side of the thin film transistor opposite the sensor; a first
metal layer configured to encapsulate the piezoelectric layer; a
first mold compound configured to encapsulate the first metal
layer; a second metal layer proximate to the first metal layer; a
conductive layer proximate to the second metal layer; a substrate
connected to the conductive layer opposite the second metal layer;
and an external connection coupled to the substrate opposite the
conductive layer.
[0009] In still another aspect, a method for forming a
semiconductor package comprises: forming a plurality of substrates,
each of the plurality of substrates has a first width; forming a
plurality of semiconductor dies on the wafer, each of the plurality
of semiconductor dies has a second width larger than the first
width; placing the plurality of substrates on the plurality of
semiconductor dies; attaching each of the plurality of substrates
to a corresponding one of the plurality of semiconductor dies;
applying a mold compound to the wafer, the mold compound configured
to encapsulate the plurality of substrates; and singulating the
wafer to form a plurality of semiconductor packages, each of the
plurality of semiconductor packages comprises one of the plurality
of substrates and one of the plurality of semiconductor dies and
each of the plurality of semiconductor packages has a third width
approximately equal to the second width.
[0010] Other features and advantages associated with the apparatus
and methods disclosed herein will be apparent to those skilled in
the art based on the accompanying drawings and detailed
description.
BRIEF DESCRIPTION OF THE DRAWINGS
[0011] A more complete appreciation of aspects of the disclosure
and many of the attendant advantages thereof will be readily
obtained as the same becomes better understood by reference to the
following detailed description when considered in connection with
the accompanying drawings which are presented solely for
illustration and not limitation of the disclosure, and in
which:
[0012] FIG. 1 illustrates an exemplary semiconductor package
structure in accordance with some examples of the disclosure.
[0013] FIG. 2 illustrates an exemplary sensor application of a
substrate in accordance with some examples of the disclosure.
[0014] FIGS. 3A-D illustrate an exemplary method for fabrication of
a WLP with a substrate in accordance with some examples of the
disclosure.
[0015] FIG. 4 illustrates an exemplary method for fabrication of a
WLP in accordance with some examples of the disclosure.
[0016] FIG. 5 illustrates various electronic devices that may be
integrated with any of the aforementioned interface substrate,
integrated device, semiconductor device, integrated circuit, die,
interposer, package or package-on-package (PoP) in accordance with
some examples of the disclosure.
[0017] In accordance with common practice, the features depicted by
the drawings may not be drawn to scale. Accordingly, the dimensions
of the depicted features may be arbitrarily expanded or reduced for
clarity. In accordance with common practice, some of the drawings
are simplified for clarity. Thus, the drawings may not depict all
components of a particular apparatus or method. Further, like
reference numerals denote like features throughout the
specification and figures.
DETAILED DESCRIPTION
[0018] The exemplary methods, apparatus, and systems disclosed
herein address the industry needs, as well as other previously
unidentified needs, and mitigate shortcomings of the conventional
methods, apparatus, and systems. For example, an interface
substrate according to some examples of the disclosure may include
a thinner, smaller interface substrate assembly that is equal to or
smaller in size than a semiconductor die coupled to the assembly.
In another example, an interface substrate assembly process may use
conventional die bonding and reflow processes or laser assist
bonding to manufacture the thinner, smaller interface substrate
assembly. This may allow the interface substrate to replace a
conventional redistribution layer (RDL) manufacturing process so
that known-good substrates can be assembled with semiconductor dies
to minimize die loss and substrate loss. Furthermore, an interface
substrate package may be molded to increase the assembly
reliability and ball reliability better than WLPs. Benefits of the
examples described herein include processing in wafer form that
allows a higher throughput process than conventional individual and
strip based structures, manufacturing process may use conventional
wafer handling infrastructure without the need for a RDL process
step, may provide a more robustness package for low k wafer nodes,
a packaged part may have the same form factor as a WLP, may provide
an interconnection with the package backside for applications (such
as sensor applications) where part of the package surface needs to
be free of other materials thus avoiding single unit processing
necessitated by interconnections on the side of the package, and
minimize manufacturing process costs and failure costs by using
known-good substrates and known-good die assemblies in the
package.
[0019] FIG. 1 illustrates an exemplary semiconductor package
structure in accordance with some examples of the disclosure. As
shown in FIG. 1, a semiconductor package 100 (e.g. a wafer level
chip scale package) may include a semiconductor die 110 (e.g. a
logic die, memory die, or integrated circuit), a substrate 120, and
a mold compound 130 encapsulating the substrate 120. The
semiconductor die has an outer perimeter 112 shown with dashed
lines in FIG. 1 and a width 114. The substrate 120 may include a
first sidewall 121, a second sidewall 123, a first plurality of
pads 140 on a first side 122 of substrate 120 opposites a second
side 124 of the substrate 120, a plurality of first contacts 150
(e.g. solder bumps or solder balls) on the first plurality of pads
140 for enabling an external connection (not shown), a second
plurality of pads 160 on the second side 124, a plurality of second
contacts 170 (e.g. solder bumps or solder balls) on the second
plurality of pads 160 for enabling connection to the semiconductor
die 110, a plurality of interconnects 180 (e.g. copper pillars or
electrically conductive vias) extending from the first plurality of
pads 140 to the second plurality of pads 160 for connecting the
first plurality of pads 140 to the second plurality of pads 160,
and a redistribution layer 190 embedded in the substrate 120 near
the second side 124. The substrate 120 may be composed of ceramic
and/or organic materials, for example, and may have a smaller width
than the semiconductor die 110. The mold compound 130 may
encapsulate the substrate 120 only with a width 132 sized to match
the width 114 of the semiconductor die 110 such that the
semiconductor package 100 has the same width as the semiconductor
die 110 and the sidewalls 121 and 123 of the substrate 120 are not
exposed.
[0020] FIG. 2 illustrates an exemplary sensor application of a
substrate in accordance with some examples of the disclosure. As
shown in FIG. 2, a sensor package 200 may include a platen 210
(e.g. for a finger print sensor), a thin film transistor (TFT) 220
(e.g. a silicon TFT) connected to the platen 210, a piezoelectric
layer 230, a first metal layer 240 (e.g. a copper layer), a mold
compound 250, a second metal layer 260 (e.g. a copper layer), a
conductive layer 270 (e.g. anisotropic conductive film (ACF) or
solder), and the substrate package 100 with an external connection
280 on a backside 201 of the sensor package 200. This will allow
wafer level processing because the external connection 280 does not
extend to either side of the package and will not be compromised by
a singulation process of the wafer. The TFT 220, piezoelectric
layer 230 and the first metal layer 240 comprise an active
circuitry area of the sensor 210 and are located on one side of the
sensor package 200 opposite the semiconductor package 100. This
will allow the active circuitry area to be separate from the
semiconductor package 100 without interference or loss of area
under the sensor 210. The piezoelectric layer 230 may comprise, for
example, piezoelectric materials that may be employed according to
various implementations include piezoelectric polymers having
appropriate acoustic properties. For example, an acoustic impedance
between about 2.5 MRayls and 5 MRayls. Specific examples of
piezoelectric materials that may be employed include ferroelectric
polymers such as polyvinylidene fluoride (PVDF) and polyvinylidene
fluoride-trifluoroethylene (PVDF-TrFE) copolymers. Examples of PVDF
copolymers include 60:40 (molar percent) PVDF-TrFE, 70:30
PVDF-TrFE, 80:20 PVDF-TrFE, and 90:10 PVDR-TrFE. Other examples of
piezoelectric materials that may be employed include Teflon.RTM.
and other PTFE polymers, polyvinylidene chloride (PVDC)
homopolymers and copolymers, polytetrafluoroethylene (PTFE)
homopolymers and copolymers, and diisopropylammonium bromide
(DIPAB).
[0021] FIGS. 3A-D illustrate an exemplary method for fabrication of
a WLP with a substrate in accordance with some examples of the
disclosure. As shown in FIG. 3A, a substrate 120 is formed. The
substrate 120 may be one of several configurations depending on the
intended application. For example, a substrate 120A may include the
first plurality of pads 140 on the first side 122 of substrate 120A
opposites the second side 124 of the substrate 120A, the second
plurality of pads 160 on the second side 124, the plurality of
second contacts 170 (e.g. solder bumps or solder balls) on the
second plurality of pads 160, and the plurality of interconnects
180 extending from the first plurality of pads 140 to the second
plurality of pads 160 for connecting the first plurality of pads
140 to the second plurality of pads 160, and the redistribution
layer 190 embedded in the substrate 120A. In another example, a
substrate 120B may include the first plurality of pads 140 on the
second plurality of pads 160, and the plurality of interconnects
180 extending from the first plurality of pads 140 to the second
plurality of pads 160 for connecting the first plurality of pads
140 to the second plurality of pads 160 and the redistribution
layer 190. In yet another example, a substrate 120C may include the
first plurality of pads 140, the plurality of first contacts 150
(e.g. solder bumps or solder balls) on the first plurality of pads
140, the second plurality of pads 160, the plurality of second
contacts 170 (e.g. solder bumps or solder balls) on the second
plurality of pads 160, the plurality of interconnects 180 extending
from the first plurality of pads 140 to the second plurality of
pads 160 for connecting the first plurality of pads 140 to the
second plurality of pads 160, and the redistribution layer 190.
Next in FIG. 3B, a wafer 300 is formed with appropriate surface
finish and/or pad stack. The wafer 300 may include a plurality of
semiconductor dies 310 (e.g. semiconductor die 110) and, as in this
example, a plurality of second contacts 170 for each of the
corresponding plurality of semiconductor dies 310.
[0022] Next in FIG. 3C, a plurality of substrates 120A, for
example, are placed on a corresponding one of the plurality of
semiconductor dies 310 and a solder reflow process is applied to
connect one of the plurality of substrates 120A to a corresponding
one of the plurality of semiconductor dies 310. Alternatively, a
curing process may be used to connect one of the plurality of
substrates 120A to a corresponding one of the plurality of
semiconductor dies 310 if a ACF layer is used instead of the
plurality of second contacts 170. Next in FIG. 3D, a wafer level
mold compound 330 is applied to encapsulate the plurality of
substrates 120A such that the plurality of semiconductor dies 310
are free of mold compound 330. Then, an optional pad cleaning
process may be applied the wafer 300 if desired and an optional
solder ball attachment process may be applied to the plurality of
substrates 120A for a ball grid array (BGA) application, for
instance, or an optional organic solderability protectant (OSP) may
be added for a land grid array (LGA) application. Last, the wafer
300 may be singulated to form individual semiconductor packages
100.
[0023] FIG. 4 illustrates an exemplary method for fabrication of a
WLP in accordance with some examples of the disclosure. As shown in
FIG. 4, a method for forming a semiconductor package begins in
block 410 with forming a plurality of substrates, each of the
plurality of substrates has a first width. Next in block 420, the
method continues with forming a plurality of semiconductor dies on
a wafer, each of the plurality of semiconductor dies has a second
width larger than the first width. Next in block 430, the method
continues with placing the plurality of substrates on the plurality
of semiconductor dies. Next in block 440, the method continues with
attaching each of the plurality of substrates to a corresponding
one of the plurality of semiconductor dies. Next in block 450, the
method continues with applying a mold compound to the wafer, the
mold compound configured to encapsulate the plurality of
substrates. Next in block 460, the method concludes with
singulating the wafer to form a plurality of semiconductor
packages, each of the plurality of semiconductor packages comprises
one of the plurality of substrates and one of the plurality of
semiconductor dies and each of the plurality of semiconductor
packages has a third width approximately equal to the second
width.
[0024] FIG. 5 illustrates various electronic devices that may be
integrated with any of the aforementioned substrates, integrated
device, semiconductor device, integrated circuit, die, interposer,
package or package-on-package (PoP) in accordance with some
examples of the disclosure. For example, a mobile phone device 502,
a laptop computer device 504, and a fixed location terminal device
506 may include an integrated device 500 as described herein. The
integrated device 500 may be, for example, any of the integrated
circuits, dies, integrated devices, integrated device packages,
integrated circuit devices, device packages, integrated circuit
(IC) packages, package-on-package devices described herein. The
devices 502, 504, 506 illustrated in FIG. 5 are merely exemplary.
Other electronic devices may also feature the integrated device 500
including, but not limited to, a group of devices (e.g., electronic
devices) that includes mobile devices, hand-held personal
communication systems (PCS) units, portable data units such as
personal digital assistants, global positioning system (GPS)
enabled devices, navigation devices, set top boxes, music players,
video players, entertainment units, fixed location data units such
as meter reading equipment, communications devices, smartphones,
tablet computers, computers, wearable devices, servers, routers,
electronic devices implemented in automotive vehicles (e.g.,
autonomous vehicles), or any other device that stores or retrieves
data or computer instructions, or any combination thereof.
[0025] One or more of the components, processes, features, and/or
functions illustrated in FIGS. 1, 2, 3A-D, 4 and/or 5 may be
rearranged and/or combined into a single component, process,
feature or function or embodied in several components, processes,
or functions. Additional elements, components, processes, and/or
functions may also be added without departing from the disclosure.
It should also be noted that FIGS. 1, 2, 3A-D, 4 and/or 5 and its
corresponding description in the present disclosure is not limited
to dies and/or ICs. In some implementations, FIGS. 1, 2, 3A-D, 4
and/or 5 and its corresponding description may be used to
manufacture, create, provide, and/or produce integrated devices. In
some implementations, a device may include a die, an integrated
device, a die package, an integrated circuit (IC), a device
package, an integrated circuit (IC) package, a wafer, a
semiconductor device, a package on package (PoP) device, and/or an
interposer.
[0026] In this description, certain terminology is used to describe
certain features. The term "mobile device" can describe, and is not
limited to, a music player, a video player, an entertainment unit,
a navigation device, a communications device, a mobile device, a
mobile phone, a smartphone, a personal digital assistant, a fixed
location terminal, a tablet computer, a computer, a wearable
device, a laptop computer, a server, an automotive device in an
automotive vehicle, and/or other types of portable electronic
devices typically carried by a person and/or having communication
capabilities (e.g., wireless, cellular, infrared, short-range
radio, etc.). Further, the terms "user equipment" (UE), "mobile
terminal," "mobile device," and "wireless device," can be
interchangeable.
[0027] The wireless communication between electronic devices can be
based on different technologies, such as code division multiple
access (CDMA), W-CDMA, time division multiple access (TDMA),
frequency division multiple access (FDMA), Orthogonal Frequency
Division Multiplexing (OFDM), Global System for Mobile
Communications (GSM), 3GPP Long Term Evolution (LTE) or other
protocols that may be used in a wireless communications network or
a data communications network.
[0028] The word "exemplary" is used herein to mean "serving as an
example, instance, or illustration." Any details described herein
as "exemplary" is not to be construed as advantageous over other
examples. Likewise, the term "examples" does not mean that all
examples include the discussed feature, advantage or mode of
operation. Furthermore, a particular feature and/or structure can
be combined with one or more other features and/or structures.
Moreover, at least a portion of the apparatus described hereby can
be configured to perform at least a portion of a method described
hereby.
[0029] The terminology used herein is for the purpose of describing
particular examples and is not intended to be limiting of examples
of the disclosure. As used herein, the singular forms "a," "an,"
and "the" are intended to include the plural forms as well, unless
the context clearly indicates otherwise. It will be further
understood that the terms "comprises", "comprising," "includes,"
and/or "including," when used herein, specify the presence of
stated features, integers, actions, operations, elements, and/or
components, but do not preclude the presence or addition of one or
more other features, integers, actions, operations, elements,
components, and/or groups thereof.
[0030] It should be noted that the terms "connected," "coupled," or
any variant thereof, mean any connection or coupling, either direct
or indirect, between elements, and can encompass a presence of an
intermediate element between two elements that are "connected" or
"coupled" together via the intermediate element.
[0031] Any reference herein to an element using a designation such
as "first," "second," and so forth does not limit the quantity
and/or order of those elements. Rather, these designations are used
as a convenient method of distinguishing between two or more
elements and/or instances of an element. Also, unless stated
otherwise, a set of elements can comprise one or more elements.
[0032] Nothing stated or illustrated depicted in this application
is intended to dedicate any component, action, feature, benefit,
advantage, or equivalent to the public, regardless of whether the
component, action, feature, benefit, advantage, or the equivalent
is recited in the claims.
[0033] In the detailed description above it can be seen that
different features are grouped together in examples. This manner of
disclosure should not be understood as an intention that the
claimed examples have more features than are explicitly mentioned
in the respective claim. Rather, the situation is such that
inventive content may reside in fewer than all features of an
individual example disclosed. Therefore, the following claims
should hereby be deemed to be incorporated in the description,
wherein each claim by itself can stand as a separate example.
Although each claim by itself can stand as a separate example, it
should be noted that--although a dependent claim can refer in the
claims to a specific combination with one or a plurality of
claims--other examples can also encompass or include a combination
of said dependent claim with the subject matter of any other
dependent claim or a combination of any feature with other
dependent and independent claims. Such combinations are proposed
herein, unless it is explicitly expressed that a specific
combination is not intended. Furthermore, it is also intended that
features of a claim can be included in any other independent claim,
even if said claim is not directly dependent on the independent
claim.
[0034] It should furthermore be noted that methods disclosed in the
description or in the claims can be implemented by a device
comprising means for performing the respective actions of this
method.
[0035] Furthermore, in some examples, an individual action can be
subdivided into a plurality of sub-actions or contain a plurality
of sub-actions. Such sub-actions can be contained in the disclosure
of the individual action and be part of the disclosure of the
individual action.
[0036] While the foregoing disclosure shows illustrative examples
of the disclosure, it should be noted that various changes and
modifications could be made herein without departing from the scope
of the disclosure as defined by the appended claims. The functions
and/or actions of the method claims in accordance with the examples
of the disclosure described herein need not be performed in any
particular order. Additionally, well-known elements will not be
described in detail or may be omitted so as to not obscure the
relevant details of the aspects and examples disclosed herein.
Furthermore, although elements of the disclosure may be described
or claimed in the singular, the plural is contemplated unless
limitation to the singular is explicitly stated.
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