U.S. patent application number 16/199189 was filed with the patent office on 2020-01-23 for split-gate non-volatile memory and fabrication method thereof.
This patent application is currently assigned to NEXCHIP SEMICONDUCTOR CO., LTD. The applicant listed for this patent is NEXCHIP SEMICONDUCTOR CO., LTD. Invention is credited to GEENG-CHUAN CHERN.
Application Number | 20200027888 16/199189 |
Document ID | / |
Family ID | 69161337 |
Filed Date | 2020-01-23 |
![](/patent/app/20200027888/US20200027888A1-20200123-D00000.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00001.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00002.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00003.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00004.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00005.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00006.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00007.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00008.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00009.png)
![](/patent/app/20200027888/US20200027888A1-20200123-D00010.png)
View All Diagrams
United States Patent
Application |
20200027888 |
Kind Code |
A1 |
CHERN; GEENG-CHUAN |
January 23, 2020 |
SPLIT-GATE NON-VOLATILE MEMORY AND FABRICATION METHOD THEREOF
Abstract
A split-gate non-volatile memory and a fabrication method
thereof. The method comprises the following steps: 1) forming a
plurality of shallow trench isolation structures in a semiconductor
substrate; 2) forming word lines on the semiconductor substrate; 3)
forming a source and a drain in the semiconductor substrate, and
forming a floating gate on a sidewall of the word line on a side
close to the source, a portion of the floating gate that contacts
with the word lines presents as a sharp tip; 4) removing part of
the word lines by adopting an etching process such that the sharp
tip of the top portion of the floating gate is higher than the word
lines; 5) forming a tunneling dielectric layer and an erasing gate
at the top portion of the floating gate; and 6) forming a
conductive plug on the drain and forming metal bit lines on the
conductive plug.
Inventors: |
CHERN; GEENG-CHUAN; (Hefei
City, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
NEXCHIP SEMICONDUCTOR CO., LTD |
Hefei City |
|
CN |
|
|
Assignee: |
NEXCHIP SEMICONDUCTOR CO.,
LTD
Hefei City
CN
|
Family ID: |
69161337 |
Appl. No.: |
16/199189 |
Filed: |
November 25, 2018 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/11519 20130101;
H01L 29/42328 20130101; H01L 29/40114 20190801; H01L 21/76897
20130101; H01L 21/76224 20130101; H01L 27/11521 20130101 |
International
Class: |
H01L 27/11521 20060101
H01L027/11521; H01L 27/11519 20060101 H01L027/11519; H01L 21/768
20060101 H01L021/768; H01L 21/762 20060101 H01L021/762; H01L 21/28
20060101 H01L021/28; H01L 29/423 20060101 H01L029/423 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 19, 2018 |
CN |
2018107962778 |
Claims
1. A method for fabricating a split-gate non-volatile memory,
characterized in that the method for fabricating the split-gate
type non-volatile memory comprises the following steps: 1)
providing a semiconductor substrate and forming a plurality of
shallow trench isolation structures in the semiconductor substrate,
wherein the plurality of shallow trench isolation structures
isolate a plurality of spaced active regions in the semiconductor
substrate; 2) forming a plurality of spaced word lines on the
semiconductor substrate; 3) forming at least one source and at
least one drain in the semiconductor substrate, and forming a
floating gate on a sidewall of the word lines on a side close to
the source, wherein the source and the drain are respectively
located on two opposite sides of the word lines, a width of the
floating gate gradually decreases from a bottom portion to a top
portion, such that a portion of the top portion of the floating
gate that contacts with the word lines presents as a sharp tip; 4)
removing part of the word lines by adopting an etching process,
such that the sharp tip of the top portion of the floating gate is
higher than an upper edge of a top portion of the word lines; 5)
forming a tunneling dielectric layer and an erasing gate at the top
portion of the floating gate, wherein the tunneling dielectric
layer at least covers part of the sharp tip of the top portion of
the floating gate, and the erasing gate is located on an upper
surface of the tunneling dielectric layer; and 6) forming a
conductive plug on the drain, and forming a plurality of spaced
metal bit lines on the conductive plug, wherein the metal bit lines
are electrically connected to the drain through the conductive
plug.
2. The method for fabricating the split-gate non-volatile memory
according to claim 1, characterized in that, in step 5), the
tunneling dielectric layer at least covers part of an upper surface
of the word lines.
3. The method for fabricating the split-gate non-volatile memory
according to claim 1, characterized in that, in step 4), the
thickness of the word lines removed by the etching process is in a
range of 10 nm-50 nm.
4. The method for fabricating the split-gate non-volatile memory
according to claim 1, characterized in that step 2) comprises the
following steps: 2-1) sequentially forming a first gate dielectric
layer, a first polycrystalline silicon layer and an insulating
layer which are stacked from top to bottom on the semiconductor
substrate; 2-2) etching the insulating layer and the first
polycrystalline silicon layer to form a plurality of spaced word
line conductive layers and a top insulating layer located on an
upper surface of the word line conductive layers; 2-3) forming a
sidewall dielectric layer on the exposed first gate dielectric
layer, sidewalls of the word line conductive layers, and a sidewall
and an upper surface of the top insulating layer; and 2-4) etching
the sidewall dielectric layer and the first gate dielectric layer
to form a stacked structure comprising a bottom dielectric layer,
the word line conductive layers and the top insulating layer which
are sequentially stacked from bottom to top, and word line
sidewalls located on both sides of the stacked structure.
5. The method for fabricating the split-gate non-volatile memory
according to claim 1, characterized in that step 3) comprises the
following steps: 3-1) forming a second gate dielectric layer on a
surface of the exposed semiconductor substrate; 3-2) forming a
second polycrystalline silicon layer on a surface of the structure
obtained in step 3-1), the second polycrystalline silicon layer
covers a surface of the second gate dielectric layer and the
sidewall and the upper surface of the word lines; 3-3) etching the
second polycrystalline silicon layer to form a polycrystalline
silicon sidewall on outer walls of the word line sidewalls; 3-4)
performing ion implantation in the semiconductor substrate
according to the polycrystalline silicon sidewall to form the
source and the drain in the semiconductor substrate; and 3-5)
removing the polycrystalline silicon sidewall of the word lines and
the second gate dielectric layer on a side close to the drain, and
removing part of the polycrystalline silicon sidewall of the word
lines on a side close to the source and in a region above the
shallow trench isolation structures, the reserved polycrystalline
silicon sidewall and the reserved second gate dielectric layer
below the reserved polycrystalline silicon sidewall form the
floating gate.
6. The method for fabricating the split-gate non-volatile memory
according to claim 5, characterized in that after step 3-5),
further comprising the following step: removing the second gate
dielectric layer above the drain, and the word line sidewalls on a
side close to the drain.
7. The method for fabricating the split-gate non-volatile memory
according to claim 1, characterized in that, in step 5), after the
tunneling dielectric layer and the erasing gate are formed, the
method further comprises the following steps: forming a sidewall
structure on a sidewall of the erasing gate, a sidewall of the
floating gate and a sidewall of the stacked structure close to the
drain; and forming a heavily doped region in the source and the
drain according to the sidewall structure, and forming a lightly
doped diffusion region on a periphery of the heavily doped
region.
8. The method for fabricating the split-gate non-volatile memory
according to claim 7, characterized in that, in step 5), after the
heavily doped region and the lightly doped diffusion region are
formed, the method further comprises the following steps: forming a
silicide barrier layer on part of an upper surface of the erasing
gate, a surface of the sidewall structure of the erasing gate on a
side close to the source, a surface of the sidewall structure
located on the sidewall of the floating gate and an upper surface
of the source; and forming a self-aligned silicide layer on an
upper surface of the exposed erasing gate, an upper surface of the
word lines and an upper surface of the drain.
9. The method for fabricating the split-gate non-volatile memory
according to claim 7, characterized in that the semiconductor
substrate comprises a substrate of a first doping type, the first
polycrystalline silicon layer comprises a polycrystalline silicone
layer of a second doping type, the second polycrystalline silicon
layer comprises a polycrystalline silicon layer of the second
doping type, the source and the drain both are regions of the
second doping type, the erasing gate comprises a polycrystalline
silicon layer of the second doping type, the heavily doped region
and the lightly doped diffusion region both are regions of the
second doping type; and the first doping type is different from the
second doping type.
10. The method for fabricating the split-gate non-volatile memory
according to claim 1, characterized in that step 5) comprises the
following steps: 5-1) forming a tunneling dielectric material layer
on a surface of the structure obtained in step 4), wherein the
tunneling dielectric material layer covers the exposed
semiconductor substrate, the word lines and the floating gate; 5-2)
forming a third polycrystalline silicon layer on the tunneling
dielectric material layer; and 5-3) etching the third
polycrystalline silicon layer and the tunneling dielectric material
layer to form the tunneling dielectric layer and the erasing
gate.
11. The method for fabricating the split-gate non-volatile memory
according to claim 1, characterized in that, in step 6), before the
conductive plug is formed, the method further comprises the
following steps: forming an interlayer dielectric layer on a
surface of the structure obtained in step 5); and forming a
connecting via in the interlayer dielectric layer, wherein the
connecting via exposes the drain.
12. The method for fabricating the split-gate non-volatile memory
according to claim 11, characterized in that, in step 6), a
conductive material layer is filled into the connecting via to is
form the conductive plug; and metal bit lines are formed on the
interlayer dielectric layer.
13. A split-gate non-volatile memory, characterized in that the
split-gate non-volatile memory at least comprises: a semiconductor
substrate, wherein a plurality of shallow trench isolation
structures are formed in the semiconductor substrate, the plurality
of shallow trench isolation structures isolate a plurality of
spaced active regions in the semiconductor substrate; a plurality
of spaced word lines; a source; a drain, the source and the drain
are respectively located on two opposite sides of the word lines; a
floating gate located on a sidewall of the word lines close to the
source, wherein a longitudinal section width of the floating gate
gradually decreases from a bottom portion to a top portion, the top
portion of the floating gate presents as a sharp tip, the sharp tip
of the top portion of the floating gate is higher than an upper
edge of a top portion of the word lines and has a preset distance
to the top portion of the word lines; a tunneling dielectric layer
at least covers part of the sharp tip of the top portion of the
floating gate; an erasing gate located on the tunneling dielectric
layer; a conductive plug located on the drain and electrically
connected to the drain; and a plurality of spaced metal bit lines
located on the conductive plug and electrically connected to the
drain through the conductive plug.
14. The split-gate non-volatile memory according to claim 13,
characterized in that the tunneling dielectric layer at least
covers part of an upper surface of the word lines.
15. The split-gate non-volatile memory according to claim 13,
characterized in that the preset distance between the sharp tip of
the top portion of the floating gate and the top portion of the
word lines is in a range of 10 nm-50 nm.
16. The split-gate non-volatile memory according to claim 13,
characterized in that the word lines comprise a stacked structure
and word line sidewalls on both sides of the stacked structure,
wherein the stacked structure comprises a bottom dielectric layer,
a word line conductive layer and a top insulating layer which are
sequentially stacked from bottom to top.
17. The split-gate non-volatile memory according to claim 13,
characterized in that the floating gate comprises a floating gate
dielectric layer and a floating gate conductive layer, wherein the
floating gate dielectric layer is located on the semiconductor
substrate, and the floating gate conductive layer is located on the
floating gate dielectric layer.
18. The split-gate non-volatile memory according to claim 13,
characterized in that a thickness of the tunneling dielectric layer
is in a range of 8 nm-15 nm.
19. The split-gate non-volatile memory according to claim 13,
characterized in that the split-gate non-volatile memory further
comprises a sidewall structure, wherein the sidewall structure is
located on a sidewall of the tunneling dielectric layer, a sidewall
of the erasing gate and a sidewall of the floating gate.
20. The split-gate non-volatile memory according to claim 19,
characterized in that the split-gate non-volatile memory further
comprises: a silicide barrier layer located on part of an upper
surface of the erasing gate, a surface of the sidewall structure of
the erasing gate on a side close to the source, a surface of the
sidewall structure of the sidewall of the floating gate and an
upper surface of the source; and a self-aligned silicide layer
located on an upper surface of the exposed erasing gate, an upper
surface of the word lines and an upper surface of the drain, the
conductive plug is located on the self-aligned silicide layer on
the upper surface of the drain.
21. The split-gate non-volatile memory according to claim 13,
characterized in that the split-gate non-volatile memory further
comprises a heavily doped region and a lightly doped diffusion
region, wherein the heavily doped region is located in the source
and the drain, the heavily doped region in the drain extends to an
outer side of the drain, and the lightly doped diffusion region is
located on a periphery of the heavily doped region.
22. The split-gate non-volatile memory according to claim 21,
characterized in that the semiconductor substrate comprises a
substrate of a first doping type, the floating gate comprises a
polycrystalline silicone layer of a second doping type, the erasing
gate comprises a polycrystalline silicon layer of the second doping
type, the source, the drain, the heavily doped region and the
lightly doped diffusion region all are regions of the second doping
type; and the second doping type is different from the first doping
type.
23. The split-gate non-volatile memory according to claim 13,
characterized in that the split-gate non-volatile memory further
comprises an interlayer dielectric layer, the interlayer dielectric
layer covers a surface of the semiconductor substrate and covers
the word lines, the floating gate and the erasing gate; the
conductive plug is located in the interlayer dielectric is layer,
and the metal bit lines are located on the interlayer dielectric
layer.
Description
BACKGROUND OF THE PRESENT INVENTION
Field of Invention
[0001] The present invention relates to the technical field of
semiconductors, in particular to a split-gate non-volatile memory
and a fabrication method thereof.
Description of Related Arts
[0002] In the existing split-gate memories, since a tunneling
effect between a floating gate and an erasing gate is limited, in
order to facilitate implementing quick erasing under a situation of
small power, a thickness of a tunneling dielectric layer between
the floating gate and the erasing gate is generally small. However,
a material of the existing tunneling dielectric layer is generally
silicon oxide or silicon nitride, but silicon oxide and silicon
nitride are not complete insulators, when the thickness of the
tunneling dielectric layer is small, leakage current is very easily
caused, charges stored in the floating gate leak into the erasing
gate and are erased, and consequently the problem of poor data
retention is caused.
SUMMARY OF THE PRESENT INVENTION
[0003] In view of the above-mentioned disadvantages of the prior
art, the purpose of the present invention is to provide a
split-gate non-volatile memory and a fabrication method thereof,
which are used for solving the problems that, since the thickness
of the tunneling dielectric layer in the split-gate memory in the
prior art is relatively small in order to guarantee erasing,
current leakage is easily caused and consequently the problem of
poor data retention of the memory is caused.
[0004] In order to realize the above-mentioned purpose and other
related purposes, the present invention provides a method for
fabricating a split-gate non-volatile memory. The method for
fabricating the split-gate non-volatile memory comprises the
following steps:
[0005] 1) providing a semiconductor substrate and forming a
plurality of shallow trench isolation structures in the
semiconductor substrate, wherein the plurality of shallow trench
isolation structures isolate a plurality of spaced active regions
in the semiconductor substrate;
[0006] 2) forming a plurality of spaced word lines on the
semiconductor substrate;
[0007] 3) forming at least one source and at least one drain in the
semiconductor substrate, and forming a floating gate on a sidewall
of the word lines on a side close to the source, wherein the source
and the drain are respectively located on two opposite sides of the
word lines, a longitudinal section width of the floating gate
gradually decreases from a bottom portion to a top portion such
that a portion of the top portion of the floating gate that
contacts with the word lines presents as a sharp tip;
[0008] 4) removing part of the word lines by adopting an etching
process such that the sharp tip of the top portion of the floating
gate is higher than an upper edge of a top portion of the word
lines;
[0009] 5) forming a tunneling dielectric layer and an erasing gate
at the top portion of the floating gate, wherein the tunneling
dielectric layer at least covers part of the sharp tip of the top
portion of the floating gate, and the erasing gate is located on an
upper surface of the tunneling dielectric layer; and
[0010] 6) forming a conductive plug on the drain and forming a
plurality of spaced metal bit lines on the conductive plug, wherein
the metal bit lines are electrically connected to the drain through
the conductive plug.
[0011] Preferably, in step 5), the tunneling dielectric layer at
least covers part of an upper surface of the word lines.
[0012] Preferably, in step 4), the thickness of the word lines
removed by adopting the etching process is in a range of 10 nm-50
nm.
[0013] Preferably, step 2) comprises the following steps:
[0014] 2-1) sequentially forming a first gate dielectric layer, a
first polycrystalline silicon layer and an insulating layer which
are stacked from top to bottom on the semiconductor substrate;
[0015] 2-2) etching the insulating layer and the first
polycrystalline silicon layer to form a plurality of spaced word
line conductive layers and a top insulating layer located on an
upper surface of the word line conductive layers;
[0016] 2-3) forming a sidewall dielectric layer on the exposed
first gate dielectric layer, sidewalls of the word line conductive
layers and a sidewall and an upper surface of the top insulating
layer; and
[0017] 2-4) etching the sidewall dielectric layer and the first
gate dielectric layer to form a stacked structure comprising a
bottom dielectric layer, the word line conductive layers and the
top insulating layer which are sequentially stacked from bottom to
top, and word line sidewalls located on both sides of the stacked
structure.
[0018] Preferably, step 3) comprises the following steps:
[0019] 3-1) forming a second gate dielectric layer on a surface of
the exposed semiconductor substrate;
[0020] 3-2) forming a second polycrystalline silicon layer on a
surface of the structure obtained in step 3-1), the second
polycrystalline silicon layer covers a surface of the second gate
dielectric layer and the sidewall and the upper surface of the word
lines;
[0021] 3-3) etching the second polycrystalline silicon layer to
form a polycrystalline silicon sidewall on outer walls of the word
line sidewalls;
[0022] 3-4) performing ion implantation in the semiconductor
substrate according to the polycrystalline silicon sidewall to form
the source and the drain in the semiconductor substrate; and
[0023] 3-5) removing the polycrystalline silicon sidewall of the
word lines and the second gate dielectric layer on a side close to
the drain, and removing part of the polycrystalline silicon
sidewall of the word lines on a side close to the source and in a
region above the shallow trench isolation structures, the reserved
polycrystalline silicon sidewall and the reserved second gate
dielectric layer below the reserved polycrystalline silicon
sidewall form the floating gate.
[0024] Preferably, after step 3-5), further comprising the
following step: removing the second gate dielectric layer above the
drain and the word line sidewalls on a side close to the drain.
[0025] Preferably, in step 5), the tunneling dielectric layer at
least covers part of the upper surface of the word lines.
[0026] Preferably, in step 5), after the tunneling dielectric layer
and the erasing gate are formed, the method further comprises the
following steps:
[0027] forming a sidewall structure on a sidewall of the erasing
gate, a sidewall of the floating gate and a sidewall of the stacked
structure close to the drain; and
[0028] forming a heavily doped region in the source and the drain
according to the sidewall structure, and forming a lightly doped
diffusion region on a periphery of the heavily doped region.
[0029] Preferably, in step 5), after the heavily doped region and
the lightly doped diffusion region are formed, the method further
comprises the following steps:
[0030] forming a silicide barrier layer on part of an upper surface
of the erasing gate, a surface of the sidewall structure of the
erasing gate on a side close to the source, a surface of the
sidewall structure located on the sidewall of the floating gate and
an upper surface of the source; and
[0031] forming a self-aligned silicide layer on an upper surface of
the exposed erasing gate, an upper surface of the word lines and an
upper surface of the drain.
[0032] Preferably, the semiconductor substrate comprises a
substrate of a first doping type, the first polycrystalline silicon
layer comprises a polycrystalline silicone layer of a second doping
type, the second polycrystalline silicon layer comprises a
polycrystalline silicon layer of the second doping type, the source
and the drain both are regions of the second doping type, the
erasing gate comprises a polycrystalline silicon layer of the
second doping type, the heavily doped region and the lightly doped
diffusion region both are regions of the second doping type; and
the first doping type is different from the second doping type.
[0033] Preferably, step 5) comprises the following steps:
[0034] 5-1) forming a tunneling dielectric material layer on a
surface of the structure obtained in step 4), wherein the tunneling
dielectric material layer covers the exposed semiconductor
substrate, the word lines and the floating gate;
[0035] 5-2) forming a third polycrystalline silicon layer on the
tunneling dielectric material layer; and
[0036] 5-3) etching the third polycrystalline silicon layer and the
tunneling dielectric material layer to form the tunneling
dielectric layer and the erasing gate.
[0037] Preferably, in step 6), before the conductive plug is
formed, the method further comprises the following steps:
[0038] forming an interlayer dielectric layer on a surface of the
structure obtained in step 5); and
[0039] forming a connecting via in the interlayer dielectric layer,
wherein the connecting via exposes the drain.
[0040] Preferably, in step 6),
[0041] a conductive material layer is filled into the connecting
via to form the conductive plug; and metal bit lines are formed on
the interlayer dielectric layer.
[0042] The present invention further provides a split-gate
non-volatile memory. The split-gate non-volatile memory at least
comprises:
[0043] a semiconductor substrate, wherein a plurality of shallow
trench isolation structures are formed in the semiconductor
substrate, the shallow trench isolation structures isolate a
plurality of spaced active regions in the semiconductor
substrate;
[0044] a plurality of spaced word lines;
[0045] a source;
[0046] a drain, the source and the drain are respectively located
on two opposite sides of the word lines;
[0047] a floating gate located on a sidewall of the word lines
close to the source, wherein a longitudinal section width of the
floating gate gradually decreases from a bottom portion to a top
portion such that a top portion of the floating gate presents as a
sharp tip, the sharp tip of the top portion of the floating gate is
higher than an upper edge of a top portion of the word lines and
has a preset distance to the top portion of the word lines;
[0048] a tunneling dielectric layer at least covering part of the
sharp tip of the top of the floating gate;
[0049] an erasing gate located on the tunneling dielectric
layer;
[0050] a conductive plug located on the drain and electrically
connected with the drain; and
[0051] a plurality of spaced metal bit lines located on the
conductive plug and electrically connected with the drain through
the conductive plug.
[0052] Preferably, the tunneling dielectric layer at least covers
part of an upper surface of the word lines.
[0053] Preferably, the preset distance between the sharp tip of the
top of the floating gate and the top of the word lines is in a
range of 10 nm-50 nm.
[0054] Preferably, the word lines comprise a stacked structure and
word line sidewalls on two sides of the stacked structure, wherein
the stacked structure comprises a bottom dielectric layer, a word
line conductive layer and a top insulating layer which are
sequentially stacked from bottom to top.
[0055] Preferably, the floating gate comprises a floating gate
dielectric layer and a floating gate conductive layer, wherein the
floating gate dielectric layer is located on the semiconductor
substrate and the floating gate conductive layer is located on the
floating gate dielectric layer.
[0056] Preferably, a thickness of the tunneling dielectric layer is
in a range of 8 nm-15 nm.
[0057] Preferably, the tunneling dielectric layer at least covers
part of the upper surface of the word lines.
[0058] Preferably, the split-gate non-volatile memory further
comprises a sidewall structure, wherein the sidewall structure is
located on a sidewall of the tunneling dielectric layer, a sidewall
of the erasing gate and a sidewall of the floating gate.
[0059] Preferably, the split-gate non-volatile memory further
comprises:
[0060] a silicide barrier layer located on part of an upper surface
of the erasing gate, a surface of the sidewall structure on one
side, close to the source, of the erasing gate, a surface of the
sidewall structure located on the floating gate sidewall and an
upper surface of the source; and
[0061] a self-aligned silicide layer located on an upper surface of
the exposed erasing gate, an upper surface of the word lines and an
upper surface of the drain, the conductive plug being located on
the self-aligned silicide layer on the upper surface of the
drain.
[0062] Preferably, the split-gate non-volatile memory further
comprises a heavily doped region and a lightly doped diffusion
region, the heavily doped region is located in the source and the
drain, wherein the heavily doped region in the drain extends to an
outer side of the drain, and the lightly doped diffusion region is
located on a periphery of the heavily doped region.
[0063] Preferably, the semiconductor substrate comprises a
substrate of a first doping type, the floating gate comprises a
polycrystalline silicone layer of a second doping type, the erasing
gate comprises a polycrystalline silicon layer of the second doping
type, and the source, the drain, the heavily doped region and the
lightly doped diffusion region all are regions of the second doping
type; and the second doping type is different from the first doping
type.
[0064] Preferably, the split-gate non-volatile memory further
comprises an interlayer dielectric layer, the interlayer dielectric
layer covers the surface of the semiconductor substrate and covers
the word lines, the floating gate and the erasing gate; and the
conductive plug is located in the interlayer dielectric layer and
the metal bit lines are located on the interlayer dielectric
layer.
[0065] As described above, the split-gate non-volatile memory and
fabrication method thereof provided by the present invention have
the following beneficial effects: by designing the top portion of
the floating gate to be the sharp tip, the FN tunneling effect
between the floating gate and the erasing gate can be obviously
increased; since the top portion of the floating gate is the sharp
tip, the thickness of the tunneling dielectric layer between the
erasing gate and the floating gate can be increased, thus leakage
current is avoided and the split-gate non-volatile memory is
enabled to have better data retention.
BRIEF DESCRIPTION OF THE DRAWINGS
[0066] FIG. 1 illustrates a flowchart of a method for fabricating a
split-gate non-volatile memory provided in embodiment 1 of the
present invention.
[0067] FIG. 2 illustrates a top structural schematic view of a
split-gate non-volatile memory provided by the present
invention.
[0068] FIG. 3 to FIG. 4 illustrate structural schematic views of a
structure obtained in step 1) of the method for fabricating the
split-gate non-volatile memory provided in embodiment 1 of the
present invention, wherein
[0069] FIG. 3 illustrates a sectional structural schematic view
along AA' direction in FIG. 2, and
[0070] FIG. 4 illustrates a sectional structural schematic view
along BB' direction in FIG. 2.
[0071] FIG. 5 to FIG. 11 illustrate schematic views of a structure
obtained in step 2) of the method for fabricating the split-gate
non-volatile memory provided in embodiment 1 of the present
invention, wherein
[0072] FIG. 5 illustrates a sectional structural schematic view of
a structure obtained after sequentially forming a first gate
dielectric layer, a first polycrystalline silicon layer and an
insulating layer which are stacked from top to bottom on a
semiconductor substrate,
[0073] FIG. 6 illustrates a sectional structural schematic view
along AA' direction in FIG. 2,
[0074] FIG. 7 illustrates a sectional structural schematic view
along BB' direction in FIG. 2,
[0075] FIG. 8 illustrates a sectional structural schematic view of
a structure obtained after etching to form a word line conductive
layer and a top insulating layer along AA' direction in FIG. 2,
[0076] FIG. 9 illustrates a sectional structural schematic view of
a structure obtained after forming a sidewall dielectric layer
along AA' direction in FIG. 2,
[0077] FIG. 10 illustrates a sectional structural schematic view
along AA' direction in FIG. 2, and
[0078] FIG. 11 illustrates a sectional structural schematic view
along BB' direction in FIG. 2.
[0079] FIG. 12 to FIG. 18 illustrate schematic views of a structure
obtained in step 3) of the method for fabricating the split-gate
non-volatile memory provided in embodiment 1 of the present
invention, wherein
[0080] FIG. 12 illustrates a sectional structural schematic view of
a structure obtained after forming a second gate dielectric layer
and a second polycrystalline silicon layer on a surface of the
structure obtained in step 2) along AA' direction in FIG. 2,
[0081] FIG. 13 illustrates a sectional structural schematic view
along AA' direction in FIG. 2,
[0082] FIG. 14 illustrates a sectional structural schematic view
along BB' direction in FIG. 2,
[0083] FIG. 15 and FIG. 16 respectively illustrate sectional
structural schematic views after forming a source and a drain along
AA' direction and BB' direction in FIG. 2,
[0084] FIG. 17 illustrates a sectional structural schematic view
along AA' direction in FIG. 2, and
[0085] FIG. 18 illustrates a sectional structural schematic view
along BB' direction in FIG. 2.
[0086] FIG. 19 illustrate a partial sectional structural schematic
view of a structure obtained in step 4) of the method for
fabricating the split-gate non-volatile memory provided in
embodiment 1 of the present invention.
[0087] FIG. 20 to FIG. 24 illustrate schematic views of a structure
obtained in step 3) of the method for fabricating the split-gate
non-volatile memory provided in embodiment 1 of the present
invention, wherein
[0088] FIG. 20 illustrates a sectional structural schematic view
along AA' direction in FIG. 2,
[0089] FIG. 21 illustrates a sectional structural schematic view
along BB' direction in FIG. 2,
[0090] FIG. 22 illustrates a sectional structural schematic view of
a structure obtained after etching a third polycrystalline silicon
layer and a tunneling dielectric material layer according to a
third patterned photoresist layer,
[0091] FIG. 23 illustrates a sectional structural schematic view
along AA' direction in FIG. 2, and
[0092] FIG. 24 illustrates a sectional structural schematic view
along BB' direction in FIG. 2.
[0093] FIG. 25 illustrate a sectional structural schematic view of
a structure obtained after forming a heavily doped region and a
lightly doped diffusion region in the method for fabricating the
split-gate non-volatile memory provided in embodiment 1 of the
present invention.
[0094] FIG. 26 to FIG. 27 illustrate sectional schematic views of a
structure obtained in step 6) of the method for fabricating the
split-gate non-volatile memory provided in embodiment 1 of the
present invention, wherein
[0095] FIG. 26 illustrates a sectional structural schematic view
along AA' direction in FIG. 2, and
[0096] FIG. 27 illustrates a sectional structural schematic view
along BB' direction in FIG. 2.
[0097] FIG. 28 illustrates an equivalent circuit diagram of the
split-gate non-volatile memory provided by the present
invention.
[0098] FIG. 29 and FIG. 30 illustrate schematic diagrams of the
split-gate non-volatile memory provided by the present
invention.
DESCRIPTION OF COMPONENT NUMBERS
[0099] 10 Semiconductor substrate [0100] 11 Shallow trench
isolation structure [0101] 12 Active region [0102] 13 Word line
[0103] 131 First gate dielectric layer [0104] 132 First
polycrystalline silicon layer [0105] 133 Insulating layer [0106]
134 Stacked structure [0107] 1341 Word line conductive layer [0108]
1342 Top insulating layer [0109] 1343 Bottom dielectric layer
[0110] 135 Word line sidewall [0111] 1351 Sidewall dielectric layer
[0112] 14 Source [0113] 141 Source line [0114] 15 Drain [0115] 16
Floating gate [0116] 161 Second gate dielectric layer [0117] 162
Second polycrystalline silicon layer [0118] 163 Polycrystalline
silicon sidewall [0119] 164 Floating gate dielectric layer [0120]
165 Floating gate conductive layer [0121] 166 Sharp tip [0122] 17
Tunneling dielectric layer [0123] 171 Tunneling dielectric material
layer [0124] 18 Erasing gate [0125] 181 Third polycrystalline
silicon layer [0126] 19 Sidewall structure [0127] 20 Heavily doped
region [0128] 21 Lightly doped diffusion region [0129] 22 Silicide
barrier layer [0130] 23 Self-aligned silicide layer [0131] 24
Interlayer dielectric layer [0132] 25 Conductive plug [0133] 26
First patterned photoresist layer [0134] 27 Second patterned
photoresist layer [0135] 28 Third patterned photoresist layer
[0136] 29 Metal bit line [0137] .alpha. First angle [0138] d
Distance from sharp tip of top portion of floating gate to top
portion of word line [0139] S1-S6 Steps
DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS
[0140] The implementation modes of the present invention will be
described below through specific examples. One skilled in the art
can easily understand other advantages and effects of the present
invention according to content disclosed in the description. The
present invention may also be implemented or applied through other
different specific implementation modes. Various modifications or
variations may be made to all details in the description based on
different points of view and applications without departing from
the spirit of the present invention.
[0141] Please refer to FIG. 2 to FIG. 30. It needs to be stated
that the drawings provided in this embodiment are just used for
schematically describing the basic concept of the present
invention, thus only illustrate components only related to the
present invention and are not drawn according to the numbers,
shapes and sizes of components during actual implementation, the
configuration, number and scale of each component during actual
implementation thereof may be freely changed, and the component
layout configuration thereof may be more complex.
Embodiment 1
[0142] Please refer to FIG. 1, the present invention provides a
method for fabricating a split-gate non-volatile memory. The method
for fabricating the split-gate non-volatile memory comprises the
following steps:
[0143] 1) providing a semiconductor substrate and forming a
plurality of shallow trench isolation structures in the
semiconductor substrate, wherein the plurality of shallow trench
isolation structures isolate a plurality of spaced active regions
in the semiconductor substrate;
[0144] 2) forming a plurality of spaced word lines on the
semiconductor substrate;
[0145] 3) forming at least one source and at least one drain in the
semiconductor substrate, and forming a floating gate on a sidewall
of the word lines on a side close to the source, wherein the source
and the drain are respectively located on two opposite sides of the
word lines, a longitudinal section width of the floating gate
gradually decreases from a bottom portion to a top portion such
that a portion of the top portion of the floating gate that
contacts with the word lines presents as a sharp tip;
[0146] 4) removing part of the word lines by adopting an etching
process such that the sharp tip of the top portion of the floating
gate is higher than an upper edge of a top portion of the word
lines;
[0147] 5) forming a tunneling dielectric layer and an erasing gate
at the top portion of the floating gate, wherein the tunneling
dielectric layer at least covers part of the sharp tip of the top
portion of the floating gate, and the erasing gate is located on an
upper surface of the tunneling dielectric layer; and
[0148] 6) forming a conductive plug on the drain and forming a
plurality of spaced metal bit lines on the conductive plug, wherein
the metal bit lines are electrically connected to the drain through
the conductive plug.
[0149] A top view of the split-gate non-volatile memory fabricated
by adopting the method for fabricating the split-gate non-volatile
memory provided by the present invention is as illustrated in FIG.
2, the split-gate non-volatile memory at least comprises: metal bit
lines 29, word lines 13, a source line 141, a floating gate 16, an
erasing gate 18, active regions 12 and a conductive plug 25. FIG. 2
further illustrates two section directions by using dashed lines,
including a first dashed line from A to A' and a second dashed line
from B to B'.
[0150] In step 1), please refer to step S1 in FIG. 1 and FIG. 3 to
FIG. 4, a semiconductor substrate 10 is provided and a plurality of
shallow trench isolation structures 11 are formed in the
semiconductor substrate 10, the shallow trench isolation structures
11 isolate a plurality of spaced active regions 12 in the
semiconductor substrate.
[0151] As an example, a material of the semiconductor substrate 10
may include, but is not limited to, a monocrystalline or
polycrystalline semiconductor material, the semiconductor substrate
10 may further comprise an intrinsic monocrystalline silicon
substrate or doped silicon substrate; preferably, the semiconductor
substrate 10 comprises a substrate of a first doping type, the
first doping type may be P-type and may also be N-type, and in this
embodiment, the situation that the first doping type is P-type is
taken as an example, i.e., in this embodiment, the situation that
the semiconductor substrate 10 is a P-type substrate is only taken
as an example.
[0152] As an example, the shallow trench isolation structures 11
may be formed by forming trenches (not shown) in the semiconductor
substrate 10 and then filling an isolation material into the
trenches. A material of the shallow trench isolation structures 11
may comprise silicon nitride, silicon oxide, silicon oxynitride or
the like, and preferably, in this embodiment, the material of the
shallow trench isolation structures 11 comprises silicon oxide. A
shape of a longitudinal section of the shallow trench isolation
structures 11 may be configured according to actual needs, FIG. 4
takes the situation that the shape of the longitudinal section of
the shallow trench isolation structures 11 comprises an inverted
trapezoid shape as an example; of course, in other examples, the
shape of the longitudinal section of the shallow trench isolation
structures 11 may also be a U shape, etc.
[0153] It needs to be stated that, the specific number of the
active regions 12 isolated by the shallow trench isolation
structures 11 in the semiconductor substrate 10 may be configured
according to actual needs and is not limited herein. FIG. 3 only
takes the situation that two active regions 12 are illustrated in
the semiconductor substrate 10 as an example.
[0154] It needs to be further stated that the plurality of active
regions 12 may be spaced in parallel and may also be freely
arranged according to actual needs.
[0155] In step 2), please refer to step S2 in FIG. 1 and FIG. 5 to
FIG. 11, a plurality of spaced word lines 13 are formed on the
semiconductor substrate 10.
[0156] As an example, forming the plurality of spaced word lines 13
on the semiconductor substrate 10 specifically comprises the
following steps:
[0157] 2-1) sequentially forming a first gate dielectric layer 131,
a first polycrystalline silicon layer 132 and an insulating layer
133 which are stacked from top to bottom on the semiconductor
substrate 10, as illustrated in FIG. 5;
[0158] 2-2) etching the insulating layer 133 and the first
polycrystalline silicon layer 132 to form a plurality of spaced
word line conductive layers 1341 and a top insulating layer 1342
located on an upper surface of the word line conductive layers
1341;
[0159] 2-3) forming a sidewall dielectric layer 1351 on the exposed
first gate dielectric layer 131, sidewalls of the word line
conductive layers 1341 and a sidewall and an upper surface of the
top insulating layer 1342, i.e., the sidewall dielectric layer 1351
covers the exposed first gate dielectric layer 131, the sidewalls
of the word line conductive layers 1341 and the sidewall and the
upper surface of the top insulating layer 1342, as illustrated in
FIG. 9; and
[0160] 2-4) etching the sidewall dielectric layer 1351 and the
first gate dielectric layer 131 to form a stacked structure 134
comprising a bottom dielectric layer 1343, the word line conductive
layers 1341 and the top insulating layer 1342 which are
sequentially stacked from bottom to top, and word line sidewalls
135 located on both sides of the stacked structure 134, as
illustrated in FIG. 10 to FIG. 11.
[0161] As an example, in step 2-1), a material of the first gate
dielectric layer 131 may include, but is not limited to, silicon
oxide, silicon oxynitride or the like; a thickness of the first
gate dielectric layer 131 may be configured according to actual
needs, preferably, in this embodiment, the thickness of the first
gate dielectric layer 131 may be in a range of 2 nm-18 nm; the
first polycrystalline silicon layer 131 may be a polycrystalline
silicon layer of a second doping type, i.e., the doping type of the
first polycrystalline silicon layer 132 is different from the
doping type of the semiconductor substrate 10; the second doping
type may be P-type and may also be N-type, when the first doping
type is P-type, the second doping type is N-type, and when the
first doping type is N-type, the second doping type is P-type; a
thickness of the first polycrystalline silicon layer 132 may be
configured according to actual needs, preferably, in this
embodiment, the thickness of the first polycrystalline silicon
layer 132 may be in a range of 200 nm-500 nm; a material of the
insulating layer 133 may include, but is not limited to, silicon
oxide or silicon nitride, a thickness of the insulating layer 133
may be configured according to actual needs, preferably, in this
embodiment, the thickness of the insulating layer 133 may be in a
range of 50 nm-200 nm.
[0162] As an example, in step 2-2), firstly a first patterned
photoresist layer 26 is formed on the insulating layer 133, the
first patterned photoresist layer 26 defines positions and shapes
of the word lines 13, as illustrated in FIG. 6 and FIG. 7, and then
the insulating layer 133 and the first polycrystalline silicon
layer 132 are sequentially etched according to the first patterned
photoresist layer 26 to form the word line conductive layers 1341
and the top insulating layer 1342, as illustrated in FIG. 8; the
insulating layer 133 and the first polycrystalline silicon layer
132 may be sequentially etched by adopting a dry etching process, a
wet etching process or a combination of the dry etching process and
the wet etching process, preferably the insulating layer 133 and
the first polycrystalline silicon layer 132 are sequentially and
anisotropically etched by adopting the dry etching process, and a
vertically downward arrow in FIG. 8 expresses a direction of
plasmas in a dry etching process; etching gas and related etching
process conditions for etching the insulating layer 133 and the
first polycrystalline silicon layer 132 are well-known by those
skilled in the art and thus are not repetitively described
herein.
[0163] As an example, in step 2-3), a material of the sidewall
dielectric layer 1351 may include, but is not limited to, at least
one of silicon oxide and silicon nitride; and a thickness of the
sidewall dielectric layer 1351 may be configured according to
actual needs, preferably, in this embodiment, the thickness of the
sidewall dielectric layer 1351 may be in a range of 10 nm-40
nm.
[0164] As an example, in step 2-4), part of the sidewall dielectric
layer 1351 between the stacked structures 134 and part of the first
gate dielectric layer 131 may be removed through etching by
adopting a photolithographic-etching process to form the stacked
structure 134 comprising the bottom dielectric layer 1343, the word
line conductive layers 1341 and the top insulating layer 1342 which
are sequentially stacked from bottom to top, and the word line
sidewalls 135 on both sides of the stacked structure 134.
Preferably, the sidewall dielectric layer 1351 and the first gate
dielectric layer 131 are sequentially and anisotropically etched by
adopting a dry etching process, a vertically downward arrow in FIG.
10 and FIG. 11 expresses a direction of plasmas in the dry etching
process.
[0165] As an example, the word lines 13 in the present embodiment
are simultaneously used as a gate structure of a memory cell, i.e.,
the word lines 13 comprise a word line gate structure. The
plurality of word lines 13 may be spaced in parallel.
[0166] As an example, an extending direction of the word lines 13
is intersected with an extending direction of the active regions
12, preferably, the extending direction of the word lines 13 and
the extending direction of the active regions 12 have a first angle
.alpha., a numerical value range of the first angle .alpha. may be
any value in a range of 0.degree.-90.degree., preferably, in this
embodiment, the first angle .alpha. is equal to 90.degree., i.e.,
the extending direction of the word lines 13 is perpendicular to
the extending direction of the active regions 12.
[0167] It needs to be stated that the above-mentioned and
below-mentioned "in a range of" refers to a numerical value range
comprising two numerical value endpoints.
[0168] In step 3), please refer to step S3 in FIG. 1 and FIG. 12 to
FIG. 18, at least one source 14 and at least one drain 15 are
formed in the semiconductor substrate 10, and a floating gate 16 is
formed on a sidewall of the word lines 13 on a side close to the
source 14, the source 14 and the drain 15 are respectively located
on two opposite sides of the word lines, a longitudinal section
width of the floating gate 16 gradually decreases from a bottom
portion to a top portion such that a portion of a top portion of
the floating gate 16 that contacts with the word lines 13 presents
as a sharp tip.
[0169] As an example, forming the source 14 and the drain 15 in the
semiconductor substrate 10, and forming the floating gate 16 on a
sidewall of the word lines 13 on a side close to the source 14
specifically comprises the following steps:
[0170] 3-1) forming a second gate dielectric layer 161 on a surface
of the exposed semiconductor substrate 10;
[0171] 3-2) forming a second polycrystalline silicon layer 162 on a
surface of the structure obtained in step 3-1), the second
polycrystalline silicon layer 162 covers a surface of the second
gate dielectric layer 161 and the sidewall and the upper surface of
the word lines 13, as illustrated in FIG. 12;
[0172] 3-3) etching the second polycrystalline silicon layer 162 to
form a polycrystalline silicon sidewall 163 on outer walls of the
word line sidewalls 135; preferably, anisotropically etching the
second polycrystalline silicon layer 162 by adopting a dry etching
process, an outer sidewall, far away from the word lines 13, of the
polycrystalline silicon sidewall 163 formed after etching presents
an arc extending from bottom to top, i.e., the longitudinal section
width of the polycrystalline silicon sidewall 163 gradually
decreases from a bottom portion to a top portion such that the top
portion of the polycrystalline silicon sidewall 163 presents a
sharp tip 166 in contact with the word lines 13, as illustrated in
FIG. 13;
[0173] 3-4) performing ion implantation in the semiconductor
substrate 10 according to the polycrystalline silicon sidewall 163
to form the source 14 and the drain 15 in the semiconductor
substrate 10, as illustrated in FIG. 14; and
[0174] 3-5) removing the polycrystalline silicon sidewall 163 of
the word lines 13 and the second gate dielectric layer 161 on a
side close to the drain 15, and removing part of the
polycrystalline silicon sidewall 163 of the word lines 13 on a side
close to the source 14 and in a region above the shallow trench
isolation structures 11, the reserved polycrystalline silicon
sidewall 163 and the reserved second gate dielectric layer 161
below the reserved polycrystalline silicon sidewall 163 form the
floating gate 16, as illustrated in FIG. 15 to FIG. 18; and
specifically, the reserved polycrystalline silicon sidewall 163 is
used as a floating gate conductive layer 165, and the reserved
second gate dielectric layer 161 below the floating gate conductive
layer 165 is used as a floating gate dielectric layer 164.
[0175] As an example, in step 3-1), a material of the second gate
dielectric layer 161 may include, but is not limited to, silicon
oxide, silicon oxynitride or the like; and a thickness of the
second gate dielectric layer 161 may be configured according to
actual needs, preferably, in this embodiment, the thickness of the
second gate dielectric layer 161 may be in a range of 5 nm-12
nm.
[0176] As an example, in step 3-2), the second polycrystalline
silicon layer 162 may be a polycrystalline silicon layer of the
second doping type, i.e., the doping type of the second
polycrystalline silicon layer 162 is the same as the doping type of
the first polycrystalline silicon layer 132 and is different from
the doping type of the semiconductor substrate 10; a thickness of
the second polycrystalline silicon layer 162 may be configured
according to actual needs, preferably, in this embodiment, the
thickness of the second polycrystalline silicon layer 162 may be in
a range of 200 nm-500 nm.
[0177] As an example, in step 3-4), implantation of ions of the
second doping type is performed in the semiconductor substrate 10
to form the source 14 and the drain 15 of the second doping type;
and the ions of the second doping type may include, but are not
limited to, phosphorus (P) ions or arsenic (As) ions. Specific
methods for performing ion implantation in the semiconductor
substrate 10 to form the source 14 and the drain 15 are well-known
by those skilled in the art and thus are not repetitively described
herein. It needs to be stated that a vertically downward arrow in
FIG. 13 expresses a direction of ion implantation.
[0178] As an example, in step 3-5), firstly, a second patterned
photoresist layer 27 is formed on a surface of the structure
obtained in step 3-4), and the second patterned photoresist layer
27 at least covers the polycrystalline silicon sidewall 163 and the
second gate dielectric layer 161 which need to be reserved to form
the floating gate 16, as illustrated in FIG. 15 and FIG. 16;
secondly, the polycrystalline silicon sidewall 163 of the word
lines 13 on a side close to the drain 15 is etched and removed, and
part of the polycrystalline silicon sidewall 163 of the word lines
14 on a side close to the source 14 and in a region above the
shallow trench isolation structures 11 is removed according to the
second patterned photoresist layer 27, as illustrated in FIG. 15
and FIG. 16, specifically, the polycrystalline silicon sidewall 163
is removed through anisotropic etching by adopting a dry etching
process, wherein vertically downward arrows in FIG. 15 and FIG. 16
express directions of plasmas in the dry etching process; finally,
the second patterned photoresist layer 27 is removed, and the
exposed second gate dielectric layer 161 (the exposed second gate
dielectric layer 161 comprises the second gate dielectric layer 161
above the drain 15 and the second gate dielectric layer 161 between
the adjacent floating gates 13) is removed to obtain the floating
gate 16, as illustrated in FIG. 17 to FIG. 18. It needs to be
stated that the word line sidewall 135 on a side close to the drain
15 is removed while the second gate dielectric layer 161 which
needs to be removed is removed.
[0179] As an example, a length of the floating gate 16 may be
configured according to actual needs, preferably, in this
embodiment, the length of the floating gate 16 is greater than the
width of the metal bit lines which are formed subsequently and is
smaller than a sum of the width of the metal bit lines and the
distance between the adjacent metal bit lines, so as to guarantee
that there is a distance between the floating gates 16 crossing the
adjacent metal bit lines such that electrical isolation is realized
between the floating gates and the metal bit lines.
[0180] In step 4), please refer to step S4 in FIG. 1 and FIG. 19,
part of the word lines 13 is removed by adopting an etching process
such that the sharp tip 166 of the top portion of the floating gate
16 is higher than the upper edge of the top portion of the word
lines 13.
[0181] As an example, the part which can be removed by adopting the
wet etching process is specifically part of the top insulating
layer 1342 in the word lines 13. Since the material of the top
insulating layer 1342 is preferably silicon oxide, in this
embodiment, part of the top insulating layer 1342 may be removed by
adopting hydrofluoric acid. Of course, in other examples, any one
of wet etching solutions which can remove the top insulating layer
1342 without causing etching removal to the floating gate
conductive layer 165 may also be adopted. In the wet etching
process, temperature of the hydrofluoric acid, time of wet etching
and the like are not specifically limited. In the present
embodiment, after wet etching, it is only required that the sharp
tip 166 of the top portion of the floating gate 16 is exposed,
i.e., after wet etching, the sharp tip 166 of the top portion of
the floating gate 16 is required to have a distance d to the upper
surface of the reserved top insulating layer 1342; preferably, a
thickness of the top insulating layer 1342 in the word lines 13
removed by adopting the wet etching process is in a range of 10
nm-50 nm, i.e., after wet etching, the distance d between the sharp
tip 166 of the top portion of the floating gate 16 and the upper
surface of the reserved top insulating layer 1342 is in a range of
10 nm-50 nm; more preferably, in this embodiment, the thickness of
the top insulating layer 1342 in the word lines 13 removed by
adopting the wet etching process may be 10 nm, 20 nm, 30 nm, 40 nm
or 50 nm.
[0182] In other examples, part of the word lines 13 may also be
etched and removed by adopting any one of dry etching processes
which can remove the top insulating layer 1342 without causing
etching to the floating gate conductive layer 165, and part of the
word lines 13 may also be removed by adopting a wet etching and dry
etching combined process, but it is required to guarantee that the
top insulating layer 1342 is removed without causing etching to the
floating gate conductive layer 165 at the same time.
[0183] It needs to be stated that this step, regardless of adopting
the wet etching process, the dry etching process or a combined
process, is only for the purpose of removing part of the top
insulating layer 1342 to release the sharp tip 166, and in the
etching process, any processing is not performed to the floating
gate 16 and the sharp tip 166.
[0184] In step 5), please refer to step S5 in FIG. 1 and FIG. 20 to
FIG. 24, a tunneling dielectric layer 17 and an erasing gate 18 are
formed at the top portion of the floating gate 16, the tunneling
dielectric layer 17 at least covers part of the sharp tip 166 of
the top portion of the floating gate 16, and the erasing gate 18 is
located on an upper surface of the tunneling dielectric layer 17;
preferably, the tunneling dielectric layer 17 at least covers part
of the upper surface of the word lines 13.
[0185] As an example, forming the tunneling dielectric layer 17 and
the erasing gate 18 at the top portion of the word lines 13 and the
top portion of the floating gate 16 specifically comprises the
following steps:
[0186] 5-1) forming a tunneling dielectric material layer 171 on a
surface of the structure obtained in step 4), wherein the tunneling
dielectric material layer 171 covers the exposed semiconductor
substrate 10, the word lines 13 and the floating gate 16;
[0187] 5-2) forming a third polycrystalline silicon layer 181 on
the tunneling dielectric material layer 171; and
[0188] 5-3) etching the third polycrystalline silicon layer 181 and
the tunneling dielectric material layer 171 to form the tunneling
dielectric layer 17 and the erasing gate 18, as illustrated in FIG.
20 to FIG. 24.
[0189] As an example, in step 5-1), a material of the tunneling
dielectric material layer 171 may include, but is not limited to,
silicon oxide. Specifically, the tunneling dielectric material
layer 171 may be formed by adopting a High Temperature Oxidation
(HTO) and thermal oxidation combined process, and the formed
tunneling dielectric material layer 171 is placed at an NO or
N.sub.2O atmosphere to perform annealing treatment. A thickness of
the tunneling dielectric material layer 171 may be configured
according to actual needs; preferably, the thickness of the
tunneling dielectric material layer 171 may be in a range of 8
nm-15 nm; more preferably, in the present embodiment, the thickness
of the tunneling dielectric material layer 171 is 12 nm. Since the
top portion of the floating gate 16 in the present invention is the
sharp tip 166, due to the tip discharge effect, the FN
(Flowler-Nordheim) tunneling effect between the floating gate 16
and the erasing gate 18 can be greatly improved, and thus on the
premise that the performance of the split-gate non-volatile memory
is guaranteed, the thickness of the tunneling dielectric material
layer 171 can be notably increased (the thickness of the tunneling
dielectric layer in the prior art is generally 7 nm-9 nm, while the
thickness of the tunneling dielectric material layer 171 in the
present application can reach 8 nm-15 nm). Since the material of
the tunneling dielectric layer 17 between the floating gate 16 and
the erasing gate 18 is generally silicon oxide or silicon nitride,
but silicon oxide and silicon nitride cannot realize absolute
insulation, current leakage is very easily caused if the thickness
of the tunneling dielectric layer 17 is small, and thus the
performance of the device is influenced. In the present
application, by increasing the thickness of the tunneling
dielectric material layer 171, occurrence of leakage current can be
effectively avoided, the split-gate non-volatile memory is enabled
to have better data retention and thus the performance of the
split-gate non-volatile memory is improved.
[0190] As an example, in step 5-2), the third polycrystalline
silicon layer 181 may be a polycrystalline silicon layer of the
second doping type, i.e., the doping type of the third
polycrystalline silicon layer 181 is the same as the doping type of
the second polycrystalline silicon layer 162 and the first
polycrystalline silicon layer 132, and is different from the doping
type of the semiconductor substrate 10; the second doping type may
be P-type and may also be N-type; a thickness of the third
polycrystalline silicon layer 181 may be configured according to
actual needs, preferably, in the present embodiment, the thickness
of the third polycrystalline silicon layer 181 may be in a range of
200 nm-500 nm.
[0191] As an example, step 5-3) specifically comprises the
following steps: firstly a third patterned photoresist layer 28 is
formed on an upper surface of the third polycrystalline silicon
layer 181, the third patterned photoresist layer 28 defines
positions and shapes of the erasing gate 18 and the tunneling
dielectric layer 17, as illustrated in FIG. 20 to FIG. 21;
secondly, the third polycrystalline silicon layer 181 and the
tunneling dielectric material layer 17 are sequentially etched
according to the third patterned photoresist layer 28, preferably,
in the present embodiment, the third polycrystalline silicon layer
181 and the tunneling dielectric material layer 17 are sequentially
and isotropically etched by adopting a dry etching process, as
illustrated in FIG. 22, a vertically downward arrow in FIG. 22
expresses a direction of plasmas in the dry etching process; and
then, the third patterned photoresist layer 28 is removed to obtain
the tunneling dielectric layer 17 and the erasing gate 18, as
illustrated in FIG. 23 to FIG. 24.
[0192] As an example, in step 5), after the tunneling dielectric
layer 17 and the erasing layer 18 are formed, the method further
comprises the following steps:
[0193] forming a sidewall structure 19 on a sidewall of the erasing
gate 18, a sidewall of the floating gate 16 and a sidewall of the
stacked structure 134 close to the drain 15, specifically, a
material of the sidewall structure 19 may include, but is not
limited to, at least one of silicon oxide and silicon nitride;
[0194] forming a heavily doped region 20 in the source 14 and the
drain 15 according to the sidewall structure 19, and forming a
lightly doped diffusion region 21 on a periphery of the heavily
doped region 20, as illustrated in FIG. 25. The doping type of the
heavily doped region 20 and the lightly doped diffusion region 21
may be the second doping type, i.e., the heavily doped region 20
and the lightly doped diffusion region 21 both are regions of the
second doping type which is the same as the doping type of the
first polycrystalline silicon layer 132, the second polycrystalline
silicon layer 162 and the third polycrystalline silicon layer 181.
It needs to be stated that the so-called "heavily doped" and
"lightly doped" herein are relative concepts, i.e., it can be
called "heavily doped" when a doping amount is greater than the
doping amount of the source 14 and the drain 15, and it can be
called "lightly doped" when the doping amount is smaller than the
doping amount of the source 14 and the drain 15. Specific methods
for forming the heavily doped region 20 and the lightly doped
diffusion region 21 are well-known by those skilled in the art and
thus are not repetitively described herein.
[0195] As an example, in step 5), after the heavily doped region 20
and the lightly doped diffusion region 21 are formed, the method
further comprises the following steps:
[0196] forming a silicide barrier layer 22 on part of an upper
surface of the erasing gate 18, a surface of the sidewall structure
19 of the erasing gate 18 on a side close to the source 14, a
surface of the sidewall structure 19 located on the sidewall of the
floating gate 16 and an upper surface of the source 14, the
silicide barrier layer 22 defines a position and a shape of a
self-aligned silicide layer which is subsequently formed; and
[0197] forming a self-aligned silicide layer 23 on an upper surface
of the exposed erasing gate 16, an upper surface of the word lines
13 and an upper surface of the drain 15, as illustrated in FIG. 26.
A material of the self-aligned silicide layer 23 may comprise metal
silicide such as tungsten silicide and so on, and the self-aligned
silicide layer 23 is used for reducing a contact resistance that
forms the device structure (such as the drain, the word lines and
the erasing gate) and the metal leading-out structure (such as the
conductive plug).
[0198] In step 6), please refer to step S1 in FIG. 1 and FIG. 26 to
FIG. 27, a conductive plug 25 is formed on the drain 15 and a
plurality of spaced metal bit lines 29 are formed on the conductive
plug 25, the metal bit lines 29 are electrically connected to the
drain 15 through the conductive plug 25.
[0199] As an example, in step 6), before the conductive plug 25 is
formed, the method further comprises the following steps:
[0200] forming an interlayer dielectric layer 24 on a surface of
the structure obtained in step 5), a material of the interlayer
dielectric layer 24 may include, but is not limited to, silicon
oxide, silicon nitride or silicon oxynitride, an upper surface of
the interlayer dielectric layer 24 is higher than the upper surface
of the erasing gate 18 to guarantee that the interlayer dielectric
layer 24 can fully cover the erasing gate 18, the word lines 13 and
the floating gate 16; and
[0201] forming a connecting via (not shown) in the interlayer
dielectric layer 24, the connecting via exposes the drain 14,
specifically the connecting via may be formed by adopting a
photolithographic etching process and the connecting via is used as
a leading-out via of the drain 14.
[0202] As an example, a conductive material layer is filled into
the connecting via to form the conductive plug 25; and metal bit
lines 29 are formed on the interlayer dielectric layer 24. The
conductive plug 25 may comprise a tungsten plug or a copper plug.
The plurality of metal bit lines 29 may be spaced in parallel.
[0203] As an example, an extending direction of the metal bit lines
29 is intersected with an extending direction of the active regions
12, preferably the extending direction of the metal bit lines 29
and the extending direction of the active regions 12 have a second
angle, the second angle may be any numerical value in a range of
0.degree.-90.degree., preferably, in the present embodiment, the
second angle is 0.degree., i.e., the extending direction of the
metal bit lines 29 and the extending direction of the active
regions 12 are the same.
Embodiment 2
[0204] In combination with FIG. 2 to FIG. 25, continuously refer to
FIG. 26 to FIG. 27, the present invention further provides a
split-gate non-volatile memory. The split-gate non-volatile memory
may be obtained by adopting, but not limited to, the method for
fabricating the split-gate non-volatile memory in embodiment 1. The
split-gate non-volatile memory at least comprises: a semiconductor
substrate 10, a plurality of shallow trench isolation structures 11
are formed in the semiconductor substrate 10, the shallow trench
isolation structures 11 isolate a plurality of spaced active
regions 12 in the semiconductor substrate 10; a plurality of spaced
word lines 13; a source 14; a drain 15, the source 14 and the drain
15 are respectively located on two opposite sides of the word lines
13; a floating gate 16 located on a sidewall of the word lines 13
close to the source 14, a longitudinal section width of the
floating gate 16 gradually decreases from a bottom portion to a top
portion such that a top portion of the floating gate 16 presents as
a sharp tip 166, the sharp tip 166 of the top portion of the
floating gate 16 is higher than an upper edge of a top portion of
the word lines 13 and has a preset distance to the top portion of
the word lines 13; a tunneling dielectric layer 17, the tunneling
dielectric layer 17 at least covers part of the sharp tip 166 of
the top portion of the floating gate 16; an erasing gate 18 located
on the tunneling dielectric layer 17; a conductive plug 25 located
on the drain 15 and electrically connected to the drain 15; a
plurality of spaced metal bit lines 29 located on the conductive
plug 25 and electrically connected to the drain 15 through the
conductive plug 25.
[0205] As an example, a material of the semiconductor substrate 10
may include, but is not limited to, a monocrystalline or
polycrystalline semiconductor material, the semiconductor substrate
10 may further comprise an intrinsic monocrystalline silicon
substrate or doped silicon substrate; preferably, the semiconductor
substrate 10 comprises a substrate of a first doping type, the
first doping type may be P-type and may also be N-type, in this
embodiment the situation that the first doping type is P-type is
taken as an example, i.e., in the present embodiment, the situation
that the semiconductor substrate 10 is a P-type substrate is only
taken as an example.
[0206] As an example, the shallow trench isolation structures 11
may be formed by forming trenches (not shown) in the semiconductor
substrate 10 and then filling an isolation material into the
trenches. A material of the shallow trench isolation structures 11
may comprise silicon nitride, silicon oxide, silicon oxynitride or
the like, preferably, in the present embodiment, the material of
the shallow trench isolation structures 11 comprises silicon oxide.
A shape of a longitudinal section of the shallow trench isolation
structures 11 may be configured according to actual needs, FIG. 4
takes the situation that the shape of the longitudinal section of
the shallow trench isolation structures 11 comprises an inverted
trapezoid shape as an example; of course, in other examples, the
shape of the longitudinal section of the shallow trench isolation
structures 11 may also be a U shape, etc.
[0207] It needs to be stated that, the specific number of the
active regions 12 isolated by the shallow trench isolation
structures 11 in the semiconductor substrate 10 may be configured
according to actual needs and is not limited herein. FIG. 3 takes
the situation that two said active regions 12 in the semiconductor
substrate 10 are only illustrated as an example.
[0208] It needs to be further stated that the plurality of active
regions 12 may be spaced in parallel and may also be freely
arranged according to actual needs.
[0209] As an example, the word lines 13 comprise a stacked
structure 134 and word line sidewalls 135 on both sides of the
stacked structure 134, wherein the stacked structure 134 comprises
a bottom dielectric layer 1343, a word line conductive layer 1341
and a top insulating layer 1342 which are sequentially stacked from
bottom to top.
[0210] As an example, a material of the bottom dielectric layer
1343 may include, but is not limited to, silicon oxide, silicon
oxynitride or the like, a thickness of the bottom dielectric layer
1343 may be configured according to actual needs, preferably, in
the present embodiment, the thickness of the bottom dielectric
layer 1343 may be in a range of 2 nm-18 nm; a material of the word
line conductive layer 1341 may comprise polycrystalline silicon of
a second doping type, i.e., the doping type of the word line
conductive layer 1341 is different form the doping type of the
semiconductor substrate 10, the second doping type may be P-type
and may also be N-type, when the first doping type is P-type, the
second doping type is N-type, when the first doping type is N-type,
the second doping type is P-type, a thickness of the word line
conductive layer 1341 may be configured according to actual needs,
preferably, in the present embodiment, the thickness of the word
line conductive layer 1341 may be in a range of 200 nm-500 nm; a
material of the top insulating layer 1342 may include, but is not
limited to, silicon oxide or silicon nitride, a thickness of the
top insulating layer 1342 may be configured according to actual
needs, preferably, in the present embodiment, the thickness of the
top insulating layer 1342 may be in a range of 50 nm-200 nm.
[0211] As an example, a material of the word line sidewall 135 may
include, but is not limited to, at least one of silicon oxide and
silicon nitride; a thickness of the word line sidewall 135 may be
configured according to actual needs, preferably, in the present
embodiment, the thickness of the word line sidewall 135 may be in a
range of 10 nm-40 nm.
[0212] As an example, the word lines 13 in the present embodiment
are simultaneously used as a gate structure of a memory cell, i.e.,
the word lines 13 comprise a word line gate structure. The
plurality of word lines 13 may be spaced in parallel.
[0213] As an example, an extending direction of the word lines 13
is intersected with an extending direction of the active regions
12, preferably the extending direction of the word lines 13 and the
extending direction of the active regions 12 have a first angle
.alpha., a numerical value range of the first angle .alpha. may be
in a range of 0.degree.-90.degree., and preferably, in the present
embodiment, the first angle .alpha. is equal to 90.degree., i.e.,
the extending direction of the word lines 13 is perpendicular to
the extending direction of the active regions 12.
[0214] It needs to be stated that the above-mentioned and
subsequent "in a range of" refers to a numerical value range
comprising two numerical value endpoints.
[0215] As an example, the floating gate 16 comprises a floating
gate dielectric layer 164 and a floating gate conductive layer 165,
wherein the floating gate dielectric layer 164 is located on the
semiconductor substrate 10 and the floating gate conductive layer
165 is located on the floating gate dielectric layer 164.
[0216] As an example, a material of the floating gate dielectric
layer 164 may include, but is not limited to, silicon oxide,
silicon oxynitride or the like; a thickness of the floating gate
dielectric layer 164 may be configured according to actual needs,
preferably, in the present embodiment, the thickness of the
floating gate dielectric layer 164 may be in a range of 5 nm-12 nm;
a material of the floating gate conductive layer 165 may comprise
polycrystalline silicon of the second doping type, i.e., the doping
type of the floating gate conductive layer 165 is the same as the
doping type of the word line conductive layer 134 and is different
from the doping type of the semiconductor substrate 10; a thickness
of the floating gate conductive layer 165 may be configured
according to actual needs, preferably, in the present embodiment,
the thickness of the floating gate conductive layer 165 may be in a
range of 200 nm-500 nm.
[0217] As an example, the source 14 and the drain 15 both are
regions of the second doping type, the source 14 and the drain 14
are doped with phosphorus ions or arsenic ions.
[0218] As an example, a length of the floating gate 16 may be
configured according to actual needs, preferably, in the present
embodiment, the length of the floating gate 16 is greater than the
width of the metal bit lines 29 and is smaller than a sum of the
width of the metal bit lines 29 and the distance between the
adjacent metal bit lines 29, so as to guarantee that there is a
distance between the floating gates 16 crossing the adjacent metal
bit lines 29 such that electrical isolation is realized between the
floating gates and the metal bit lines.
[0219] As an example, the distance d between the sharp tip 166 of
the top portion of the floating gate 16 and the upper surface of
the reserved top insulating layer 1342 is in a range of 10 nm-50
nm; preferably, in the present embodiment, the distance d between
the sharp tip 166 of the top portion of the floating gate 16 and
the upper surface of the reserved top insulating layer 1342 may
comprise 10 nm, 20 nm, 30 nm, 40 nm or 50 nm.
[0220] As an example, a material of the tunneling dielectric layer
17 may include, but is not limited to, silicon oxide, a thickness
of the tunneling dielectric layer 17 may be configured according to
actual needs; preferably, the thickness of the tunneling dielectric
layer 17 may be in a range of 8 nm-15 nm, more preferably, in the
present embodiment, the thickness of the tunneling dielectric layer
17 is 12 nm. Since the top portion of the floating gate 16 in the
present invention is the sharp tip 166, due to the tip discharge
effect, the FN (Flowler-Nordheim) tunneling effect between the
floating gate 16 and the erasing gate 18 can be greatly improved,
and thus on the premise that the performance of the split-gate
non-volatile memory is guaranteed, the thickness of the tunneling
dielectric layer 17 can be notably increased (the thickness of the
tunneling dielectric layer in the prior art is generally 7 nm-9 nm,
while the thickness of the tunneling dielectric layer 17 in the
present application can reach 8 nm-15 nm). Since the material of
the tunneling dielectric layer 17 between the floating gate 16 and
the erasing gate 18 is generally silicon oxide or silicon nitride,
but silicon oxide and silicon nitride cannot realize absolute
insulation, small thickness of the tunneling dielectric layer 17
easily causes current leakage, thus influencing the performance of
the device. In the present application, by increasing the thickness
of the tunneling dielectric layer 17, occurrence of leakage current
can be effectively avoided, the split-gate non-volatile memory is
enabled to have better data retention and thus the performance of
the split-gate non-volatile memory is improved.
[0221] As an example, the tunneling dielectric layer 17 at least
covers part of the upper surface of the word lines 13.
[0222] As an example, a material of the erasing gate 18 may
comprise polycrystalline silicon of the second doping type, a
thickness of the erasing gate 18 may be configured according to
actual needs, preferably, in the present embodiment, the thickness
of the erasing gate 18 may be in a range of 200 nm-500 nm.
[0223] As an example, the split-gate non-volatile memory further
comprises a sidewall structure 19, the sidewall structure 19 is
located on a sidewall of the tunneling dielectric layer 17, a
sidewall of the erasing gate 18 and a sidewall of the floating gate
16. A material of the sidewall structure 19 may include, but is not
limited to, at least one of silicon oxide and silicon nitride.
[0224] As an example, the split-gate non-volatile memory further
comprises a heavily doped region 20 and a lightly doped diffusion
region 21, the heavily doped region 20 is located in the source 14
and the drain 15, the heavily doped region 19 in the drain 15
extends to an outer side of the drain 15, and the lightly doped
diffusion region 20 is located on a periphery of the heavily doped
region 19. The doping type of the heavily doped region 20 and the
lightly doped diffusion region 21 may be the second doping type,
i.e., the heavily doped region 20 and the lightly doped diffusion
region 21 both are regions of the second doping type. It needs to
be stated that the so-called "heavily doped" and "lightly doped"
herein are relative concepts, i.e., it can be called "heavily
doped" when a doping amount is greater than the doping amount of
the source 14 and the drain 15, and it can be called "lightly
doped" when a doping amount is smaller than the doping amount of
the source 14 and the drain 15.
[0225] As an example, the split-gate non-volatile memory further
comprises: a silicide barrier layer 22 located on part of an upper
surface of the erasing gate 18, a surface of the sidewall structure
19 of the erasing gate 18 on a side close to the source 14, a
surface of the sidewall structure 19 located on the sidewall of the
floating gate 16 and an upper surface of the source 14, the
silicide barrier layer 22 defines a shape and a position of the
self-aligned silicide layer 23; and a self-aligned silicide layer
23 located on an upper surface of the exposed erasing gate 18, an
upper surface of the word lines 13 and an upper surface of the
drain 15, the conductive plug 25 is located on the self-aligned
silicide layer 23 on the upper surface of the drain 15; a material
of the self-aligned silicide layer 23 may comprise metal silicide
such as tungsten silicide and so on, and the self-aligned silicide
layer 23 is used for reducing a contact resistance that forms the
device structure (such as the drain, the word lines and the erasing
gate) and the metal leading-out structure (such as the conductive
plug).
[0226] As an example, the split-gate non-volatile memory further
comprises an interlayer dielectric layer 24, the interlayer
dielectric layer 24 covers the surface of the semiconductor
substrate 10 and covers the word lines 13, the floating gate 16 and
the erasing gate 18; the conductive plug 25 is located in the
interlayer dielectric layer 24 and the metal bit lines 29 are
located on the interlayer dielectric layer 24. A material of the
interlayer dielectric layer 24 may include, but is not limited to,
silicon oxide, silicon nitride or silicon oxynitride, and an upper
surface of the interlayer dielectric layer 24 is higher than the
upper surface of the erasing gate 18.
[0227] As an example, the conductive plug 25 may comprise a
tungsten plug or a copper plug. The plurality of metal bit lines 29
may be spaced in parallel.
[0228] As an example, an extending direction of the metal bit lines
29 is intersected with an extending direction of the active regions
12, preferably the extending direction of the metal bit lines 29
and the extending direction of the active regions 12 have a second
angle, the second angle may be any numerical value in a range of
0.degree.-90.degree., preferably, in the present embodiment, the
second angle is 0.degree., i.e., the extending direction of the
metal bit lines 29 and the extending direction of the active
regions 12 are the same.
[0229] In the present invention, the word lines 13, the floating
gate 16 on one side of the word lines 13, the erasing gate 18 above
the word lines 13 and the floating gate 16, and the source 14 and
the drain 15 on both sides of the word lines 13 jointly form a
memory cell, the split-gate non-volatile memory provided by the
present invention comprises a plurality of memory cells, the
plurality of memory cells are arranged in a multi-line multi-row
array, the drains 15 of all memory cells in the same row are
sequentially connected in series through one said metal bit line
29, the word lines 13 of all memory cells in the same line are
sequentially connected in series, the erasing gates 18 of all
memory cells in the same line are sequentially connected in series,
and the sources of all memory cells in two adjacent lines are
sequentially connected in series to form a source line 141.
[0230] An equivalent circuit diagram of the split-gate non-volatile
memory provided by the present invention is as illustrated in FIG.
28. From FIG. 28, it can be seen that the split-gate non-volatile
memory comprises a plurality of memory transistors arranged in
multiple lines and multiple rows, a plurality of metal bit lines 29
spaced in parallel, a plurality of word lines 13 spaced in parallel
and a plurality of source lines 141 spaced in parallel, wherein the
word lines 13 are connected to the gates of all memory transistors
in the same line, the erasing gates 18 of all memory transistors in
the same line are sequentially connected in series, the source
lines 141 are connected to the sources 14 of all memory transistors
in the same line, and the metal bit lines 29 are connected to the
drains 15 of all memory transistors in the same row.
[0231] Please refer to FIG. 29 and FIG. 30, during programming,
taking a situation that a memory unit on a left side in FIG. 29 is
selected and a memory unit on a right side in FIG. 29 is not
selected as an example, the working principle of the split-gate
non-volatile memory provided by the present invention is as follow:
during programming, as illustrated in FIG. 29, charges are
implanted into the floating gate conductive layer 165 in the
floating gate 16 from the channels formed at the bottom portion of
the word lines 13 by means of thermal ion implantation to realize
storing, arrows in FIG. 29 express a moving direction of charges,
and reference sign "e" in FIG. 29 expresses charges; and during
erasing, as illustrated in FIG. 30, charges stored in the floating
gate conductive layer 165 penetrate through the tunneling
dielectric layer 17 by means of FN tunneling to enter the erasing
gate 18 to realize erasing, arrows in FIG. 30 express a moving
direction of charges and a reference sign "e" in FIG. 30 expresses
charges.
[0232] To sum up, the present invention provides a split-gate
non-volatile memory and a fabrication method thereof. The method
for fabricating the split-gate non-volatile memory comprises the
following steps: 1) providing a semiconductor substrate and forming
a plurality of shallow trench isolation structures in the
semiconductor substrate, the plurality of shallow trench isolation
structures isolate a plurality of spaced active regions in the
semiconductor substrate; 2) forming a plurality of spaced word
lines on the semiconductor substrate; 3) forming a source and a
drain in the semiconductor substrate, and forming a floating gate
on a sidewall of the word lines on a side close to the source, the
source and the drain are respectively located on two opposite sides
of the word lines, a longitudinal section width of the floating
gate gradually decreases from a bottom portion to a top portion
such that a portion of the top portion of the floating gate that
contacts with the word lines presents as a sharp tip; 4) removing
part of the word lines by adopting a wet etching process such that
the sharp tip of the top portion of the floating gate is higher
than an upper edge of a top portion of the word lines; 5) forming a
tunneling dielectric layer and an erasing gate at the top portion
of the floating gate, the tunneling dielectric layer at least
covers part of the sharp tip of the top portion of the floating
gate, and the erasing gate is located on an upper surface of the
tunneling dielectric layer; and 6) forming a conductive plug on the
drain and forming a plurality of spaced metal bit lines on the
conductive plug, the metal bit lines are electrically connected to
the drain through the conductive plug. By designing the top portion
of the floating gate to be the sharp tip, the FN tunneling effect
between the floating gate and the erasing gate can be notably
increased; since the top portion of the floating gate is the sharp
tip, the thickness of the tunneling dielectric layer between the
erasing gate and the floating gate can be increased, thus
occurrence of leakage current is avoided and the split-gate
non-volatile memory is enabled to have better data retention.
[0233] The above-mentioned embodiments are just used for
exemplarily describing the principle and effects of the present
invention instead of limiting the present invention. One skilled in
the art may make modifications or changes to the above-mentioned
embodiments without departing from the spirit and scope of the
present invention. Therefore, all equivalent modifications or
changes made by those who have common knowledge in the art without
departing from the spirit and technical thought disclosed by the
present invention shall be still covered by the claims of the
present invention.
* * * * *