U.S. patent application number 16/378568 was filed with the patent office on 2020-01-02 for semiconductor structure and method of forming the same.
The applicant listed for this patent is Yangtze Memory Technologies Co., Ltd.. Invention is credited to Weihua CHENG, Taotao DING, Ziqun HUA, Xianjin WAN, Jiawen WANG, Xinsheng WANG, Shining YANG, Gaosheng ZHANG, Li ZHANG, Hongbin ZHU.
Application Number | 20200006285 16/378568 |
Document ID | / |
Family ID | 68984585 |
Filed Date | 2020-01-02 |
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United States Patent
Application |
20200006285 |
Kind Code |
A1 |
WANG; Xinsheng ; et
al. |
January 2, 2020 |
SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME
Abstract
The present invention relates to a semiconductor structure and a
manufacturing method thereof. The semiconductor structure includes
a first substrate, and a bonding layer located on a surface of the
first substrate. The material of the first bonding layer is a
dielectric material containing element carbon (C). C atomic
concentration of a surface layer of the first bonding layer away
from the first substrate is higher than or equal to 35%. The first
bonding layer of the semiconductor structure may be used to enhance
bonding strength during bonding.
Inventors: |
WANG; Xinsheng; (Wuhan City,
CN) ; ZHANG; Li; (Wuhan City, CN) ; ZHANG;
Gaosheng; (Wuhan City, CN) ; WAN; Xianjin;
(Wuhan City, CN) ; HUA; Ziqun; (Wuhan City,
CN) ; WANG; Jiawen; (Wuhan City, CN) ; DING;
Taotao; (Wuhan City, CN) ; ZHU; Hongbin;
(Wuhan City, CN) ; CHENG; Weihua; (Wuhan City,
CN) ; YANG; Shining; (Wuhan City, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Yangtze Memory Technologies Co., Ltd. |
Wuhan City |
|
CN |
|
|
Family ID: |
68984585 |
Appl. No.: |
16/378568 |
Filed: |
April 9, 2019 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
PCT/CN2018/093690 |
Jun 29, 2018 |
|
|
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16378568 |
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/05684
20130101; H01L 2224/80357 20130101; H01L 24/08 20130101; H01L
2224/05186 20130101; H01L 24/03 20130101; H01L 2224/05023 20130101;
H01L 21/02326 20130101; H01L 24/09 20130101; H01L 24/27 20130101;
H01L 2224/05073 20130101; H01L 2224/05076 20130101; H01L 2224/27452
20130101; H01L 2224/05686 20130101; H01L 2224/03452 20130101; H01L
21/02107 20130101; H01L 24/05 20130101; H01L 21/76251 20130101;
H01L 2224/05568 20130101; H01L 21/0234 20130101; H01L 2224/05576
20130101; H01L 24/83 20130101; H01L 24/80 20130101; H01L 2224/05647
20130101; H01L 2224/335 20130101; H01L 2224/80896 20130101; H01L
2224/05573 20130101; H01L 2224/80895 20130101; H01L 21/02126
20130101; H01L 2224/08145 20130101; H01L 24/33 20130101; H01L
2224/05686 20130101; H01L 2924/0504 20130101; H01L 2924/01006
20130101; H01L 2224/05186 20130101; H01L 2924/0504 20130101; H01L
2924/01006 20130101; H01L 2224/05186 20130101; H01L 2924/05042
20130101; H01L 2224/05686 20130101; H01L 2924/05042 20130101; H01L
2224/05686 20130101; H01L 2924/05042 20130101; H01L 2924/05442
20130101; H01L 2224/05186 20130101; H01L 2924/05042 20130101; H01L
2924/05442 20130101; H01L 2224/05647 20130101; H01L 2924/00014
20130101; H01L 2224/05684 20130101; H01L 2924/00014 20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00 |
Claims
1. A semiconductor structure, comprising: a first substrate; and a
first bonding layer located on a surface of the first substrate,
wherein a material of the first bonding layer is a dielectric
material containing element carbon (C), and C atomic concentration
of a surface layer of the first bonding layer away from the first
substrate is higher than or equal to 35%.
2. The semiconductor structure according to claim 1, wherein C
atomic concentration distributes uniformly in the first bonding
layer.
3. The semiconductor structure according to claim 1, wherein C
atomic concentration in the first bonding layer increases gradually
with increasing thickness of the first bonding layer.
4. The semiconductor structure according to claim 1, wherein the
thickness of the surface layer ranges from 20 angstroms (.ANG.) to
50 angstroms.
5. The semiconductor structure according to claim 1, further
comprising: a second substrate, wherein a second bonding layer is
formed on a surface of the second substrate, and the second bonding
layer is bonded to and fixed on the first bonding layer with a
surface of the second bonding layer facing a surface of the first
bonding layer.
6. The semiconductor structure according to claim 5, wherein a
material of the second bonding layer is a dielectric material
containing element C, and C atomic concentration of a surface layer
of the second bonding layer away from the second substrate is
higher than or equal to 35%.
7. The semiconductor structure according to claim 5, wherein the
material of the second bonding layer is identical to the material
of the first bonding layer.
8. The semiconductor structure according to claim 5, further
comprising: a first bonding pad penetrating the first bonding
layer; and a second bonding pad penetrating the second bonding
layer, wherein the first bonding pad and the second bonding pad are
bonded to each other correspondingly.
9. A semiconductor structure, comprising: a first substrate; and a
bonding stack layer located on a surface of the first substrate,
wherein the bonding stack layer comprises bonding layers bonded to
one another, and a material of the bonding stack layer is a
dielectric material containing silicon (Si), nitrogen (N), carbon
(C), and oxygen (O).
10. The semiconductor structure according to claim 9, wherein the
bonding stack layer is formed by oxidizing two bonding layers
having CH.sub.3 bonds and bonding the two bonding layers after the
oxidizing.
11. The semiconductor structure according to claim 9, wherein C
atomic concentration of surface layers in the bonding layers
adjacent to a bonding surface is higher than or equal to 35%.
12. The semiconductor structure according to claim 9, further
comprising: a second substrate located on a side of the bonding
stack layer away from the first substrate.
13. The semiconductor structure according to claim 9, further
comprising: bonding pads penetrating the bonding layers, wherein
the bonding pads in two of the bonding layer are bonded to each
other correspondingly.
14. A method of forming a semiconductor structure, comprising:
providing a first substrate; forming a first bonding layer on a
surface of the first substrate, wherein a material of the first
bonding layer is a dielectric material containing element carbon
(C) and a CH.sub.3 bond; providing a second substrate; forming a
second bonding layer on a surface of the second substrate, wherein
a material of the second bonding layer is a dielectric material
containing element C and a CH.sub.3 bond; oxidizing a surface layer
of the first bonding layer and a surface layer of the second
bonding layer, wherein the CH.sub.3 bonds are oxidized to be OH
bonds; and bonding the first bonding layer and the second bonding
layer to each other correspondingly.
15. The method of forming the semiconductor structure according to
claim 14, wherein C atomic concentration within the surface layer
of the first bonding layer and C atomic concentration within the
surface layer of the second bonding layer are higher than or equal
to 35%.
16. The method of forming the semiconductor structure according to
claim 14, wherein the first bonding layer is formed by a
plasma-enhanced chemical vapor deposition process.
17. The method of forming the semiconductor structure according to
claim 14, wherein C atomic concentration in the first bonding layer
distributes uniformly in the first bonding layer or increases
gradually with increasing thickness of the first bonding layer, and
C atomic concentration in the second bonding layer distributes
uniformly in the second bonding layer or increases gradually with
increasing thickness of the second bonding layer.
18. The method of forming the semiconductor structure according to
claim 14, wherein the thickness of the surface layer of the first
bonding layer and the thickness of the surface layer of the second
bonding layer range from 10 angstroms (.ANG.) to 50 angstroms.
Description
CROSS REFERENCE TO RELATED APPLICATIONS
[0001] This application is a continuation of International
Application No. PCT/CN2018/093690, filed Jun. 29, 2018, which is
incorporated by reference herein in its entirety.
BACKGROUND OF THE INVENTION
1. Field of the Invention
[0002] The present invention relates to a field of semiconductor
technology, and more particularly, to a semiconductor structure and
a method of forming the same.
2. Description of the Prior Art
[0003] In the 3D wafer technology platform, two or more wafers
having semiconductor devices formed thereon are usually bonded to
one another by wafer bonding technology for enhancing the
integration of the wafer. In the current wafer bonding technique, a
bonding film is formed on a wafer bonding surface for bonding.
[0004] In the current technology, a silicon oxide film and a
silicon nitride film are generally used as the bonding film.
However, the bonding strength is not enough, defects are generated
in the manufacturing process easily, and the production yield is
affected.
[0005] Additionally, metal connection structures are formed in the
bonding film. In the hybrid bonding process, the metal connection
structures tend to diffuse at the bonding interface, and the
product performance is affected accordingly.
[0006] Therefore, how to improve the quality of the wafer bonding
is an urgent problem to be solved.
SUMMARY OF THE INVENTION
[0007] The technical problem to be solved in the present invention
is providing a semiconductor structure and a method of forming the
same.
[0008] A semiconductor structure is provided by the present
invention. The semiconductor structure includes a first substrate;
and a first bonding layer located on a surface of the first
substrate. A material of the first bonding layer is a dielectric
material containing element carbon (C), and C atomic concentration
of a surface layer of the first bonding layer away from the first
substrate is higher than or equal to 35%.
[0009] Selectively, C atomic concentration distributes uniformly in
the first bonding layer.
[0010] Selectively, C atomic concentration in the first bonding
layer distributes uniformly in the first bonding layer or increases
gradually with increasing thickness of the first bonding layer.
[0011] Selectively, the thickness of the surface layer ranges from
20 angstroms (.ANG.) to 50 angstroms.
[0012] Selectively, the semiconductor structure further includes a
second substrate. A second bonding layer is formed on a surface of
the second substrate, and the second bonding layer is bonded to and
fixed on the first bonding layer with a surface of the second
bonding layer facing a surface of the first bonding layer.
[0013] Selectively, a material of the second bonding layer is a
dielectric material containing element C, and C atomic
concentration of a surface layer of the second bonding layer away
from the second substrate is higher than or equal to 35%.
[0014] Selectively, the material of the second bonding layer is
identical to the material of the first bonding layer.
[0015] Selectively, the semiconductor structure further includes: a
first bonding pad penetrating the first bonding layer; and a second
bonding pad penetrating the second bonding layer. The first bonding
pad and the second bonding pad are bonded to each other
correspondingly.
[0016] A semiconductor structure is provided by the technical
solution of the present invention. The semiconductor structure
includes a first substrate; and a bonding stack layer located on a
surface of the first substrate. The bonding stack layer includes
bonding layers bonded to one another, and a material of the bonding
stack layer is a dielectric material containing silicon (Si),
nitrogen (N), carbon (C), and oxygen (O).
[0017] Selectively, the bonding stack layer is formed by oxidizing
two bonding layers having CH.sub.3 bonds and bonding the two
bonding layers after the oxidizing.
[0018] Selectively, C atomic concentration of surface layers in the
bonding layers adjacent to a bonding surface is higher than or
equal to 35%.
[0019] Selectively, the semiconductor structure further includes a
second substrate located on a side of the bonding stack layer away
from the first substrate.
[0020] Selectively, the semiconductor structure further includes
bonding pads penetrating the bonding layers. The bonding pads in
two of the bonding layer are bonded to each other
correspondingly.
[0021] A method of forming a semiconductor structure is further
provided by the technical solution of the present invention. The
method includes: providing a first substrate; forming a first
bonding layer on a surface of the first substrate, wherein a
material of the first bonding layer is a dielectric material
containing element C and a CH.sub.3 bond; providing a second
substrate; forming a second bonding layer on a surface of the
second substrate, wherein a material of the second bonding layer is
a dielectric material containing element C and a CH.sub.3 bond;
oxidizing a surface layer of the first bonding layer and a surface
layer of the second bonding layer, wherein the CH.sub.3 bonds are
oxidized to be OH bonds; and bonding the first bonding layer and
the second bonding layer to each other correspondingly.
[0022] Selectively, C atomic concentration within the surface layer
of the first bonding layer and C atomic concentration within the
surface layer of the second bonding layer are higher than or equal
to 35%.
[0023] Selectively, the first bonding layer is formed by a
plasma-enhanced chemical vapor deposition (PECVD) process.
[0024] Selectively, C atomic concentration in the first bonding
layer distributes uniformly in the first bonding layer or increases
gradually with increasing thickness of the first bonding layer, and
C atomic concentration in the second bonding layer distributes
uniformly in the second bonding layer or increases gradually with
increasing thickness of the second bonding layer.
[0025] Selectively, the thickness of the surface layer of the first
bonding layer and the thickness of the surface layer of the second
bonding layer range from 10 angstroms (.ANG.) to 50 angstroms.
[0026] The first bonding layer of the semiconductor structure of
the present invention may have higher bonding strength during the
bonding process and may be used to block metal materials from
diffusing at the bonding interface, and the performance of the
semiconductor structure formed by the method of the present
invention may be enhanced accordingly.
[0027] These and other objectives of the present invention will no
doubt become obvious to those of ordinary skill in the art after
reading the following detailed description of the preferred
embodiment that is illustrated in the various figures and
drawings.
BRIEF DESCRIPTION OF THE DRAWINGS
[0028] FIGS. 1-4 are structural schematic drawings illustrating
processes of forming a semiconductor structure according to an
embodiment of the present invention.
[0029] FIG. 5 is a schematic drawing illustrating a semiconductor
structure according to an embodiment of the present invention.
[0030] FIG. 6 is a schematic drawing illustrating a semiconductor
structure according to an embodiment of the present invention.
DETAILED DESCRIPTION
[0031] Embodiments of semiconductor structures and methods of
forming the same provided by the present invention are described in
detail by the following contents and figures.
[0032] Please refer to FIGS. 1-4. FIGS. 1-4 are structural
schematic drawings illustrating processes of forming a
semiconductor structure according to an embodiment of the present
invention.
[0033] Please refer to FIG. 1, a first substrate 100 is
provided.
[0034] The first substrate 100 includes a first semiconductor
substrate 101 and a first device layer 102 formed on a surface of
the first semiconductor substrate 101.
[0035] The first semiconductor substrate 101 may be a single
crystal silicon substrate, a germanium (Ge) substrate, a silicon
germanium (SiGe) substrate, a silicon-on-insulator (SOI) substrate,
a germanium-on-insulator (GOI) substrate, and so forth. Suitable
types of the first semiconductor substrate 101 may be used in
accordance with the actual requirements of the devices and are not
limited to the above descriptions. In the embodiment, the first
semiconductor substrate 101 is a single crystal silicon
substrate.
[0036] The first device layer 102 includes a semiconductor device,
a metal interconnection structure connected with the semiconductor
device, and a medium layer covering the semiconductor device and
the metal interconnection structure. The first device layer 102 may
be a multiple layer structure or a single layer structure. In an
embodiment, the first device layer 102 includes a medium layer and
a 3D NAND structure formed in the medium layer.
[0037] Please refer to FIG. 2. A first bonding layer 200 is formed
on the surface of the first substrate 100. The material of the
first bonding layer is a dielectric material containing element
carbon (C). C atomic concentration of a surface layer having a
certain thickness from the surface of the first bonding layer to
the inside of the first bonding layer is higher than or equal to
35%.
[0038] The first bonding layer 200 may be formed by a chemical
vapor deposition process. In the embodiment, the first bonding
layer 200 is formed by a plasma-enhanced chemical vapor deposition
process.
[0039] The material of the first bonding layer 200 is a dielectric
material containing element C. In one embodiment, the first bonding
layer 200 mainly includes silicon (Si), nitrogen (N), and carbon
(C). In another embodiment, the first bonding layer 200 may be
further doped with at least one element of Si, N, oxygen (O),
hydrogen (H), phosphorus (P), or fluorine (F) in accordance with
reactive gases used in the chemical vapor deposition process and
requirements of specific products. The material of the first
bonding layer 200 may be carbon-doped silicon nitride, carbon-doped
silicon oxynitride, nitrogen-doped silicon oxycarbide, and so
forth.
[0040] In one embodiment, the first bonding layer 200 is formed by
a plasma-enhanced chemical vapor deposition process. A reactive gas
used in the plasma-enhanced chemical vapor deposition process
includes one of trimethylsilane or tetramethylsilane and includes
NH.sub.3. The flow ratio of trimethylsilane to NH.sub.3 or the flow
ratio of tetramethylsilane to NH.sub.3 is 2:1, and the power is 800
W.
[0041] By controlling the process parameters of forming the first
bonding layer 200, concentration of each composition in the first
bonding layer 200 may be adjusted for modifying the adhesion
between the first bonding layer 200 and the first device layer 102,
the dielectric constant of the first bonding layer 200, and the
bonding strength between the first bonding layer 200 and another
bonding layer after bonding.
[0042] The element carbon in the first bonding layer 200 may be
used to effectively enhance the bonding strength between the first
bonding layer 200 and other bonding layers during the bonding
process. The higher the C atomic concentration, the higher the
bonding strength between the first bonding layer 200 and other
bonding layers during the bonding process. The higher the C atomic
concentration at the surface of the first bonding layer 200, the
higher the bonding strength between the first bonding layer 200 and
other bonding layers during the bonding process. The element carbon
in the first bonding layer 200 may exist in the form of methyl
group (--CH.sub.3), the methyl group (--CH.sub.3) may be oxidized
to be hydroxyl group (--OH) after treatments, such as an oxidation
treatment and a plasma activation treatment, performed before the
bonding process, and the amount of hydroxyl increases accordingly.
Finally in the bonding process, the amount of Si--O bonds at the
bonding interface is increased for enhancing the bonding strength.
Therefore, in the process of forming the first boding layer 200,
the C atomic concentration of the surface layer of the first
bonding layer 200 away from the first substrate is higher than or
equal to 35% by adjusting the process parameters, and the surface
of the first bonding layer 200 has a higher C atomic concentration
accordingly. In one embodiment, the thickness of the surface layer
may range from 10 angstroms (.ANG.) to 50 angstroms. In another
embodiment, the C atomic concentration of the surface layer having
a thickness equal to 30 angstroms in the first bonding layer 200 is
higher than 40%.
[0043] The adhesion between different material layers relates to
the material compositions at two sides of the interface. The closer
the material composition is, the higher the adhesion. For
increasing the adhesion between the first bonding layer 200 and the
first device layer 102, the process parameters may be adjusted
gradually in the process of forming the first bonding layer 200 for
forming composition having concentration varying gradually in the
first bonding layer and making the material compositions at the two
sides of the interface between the first bonding layer 200 and the
first device layer 200 similar to each other. In one embodiment,
the C atomic concentration in the first bonding layer 200 increases
gradually with increasing thickness of the first bonding layer 200
by adjusting the process parameters of the deposition process as
the thickness of the first bonding layer 200 increases in the
process of forming the first bonding layer 200, and the C atomic
concentration is highest at the surface of the first bonding layer
200. In another embodiment, the process parameters of the
deposition process may be fixed during the process of forming the
first bonding layer 200, and the concentration of each element in
the first bonding layer 200 distributes uniformly at different
thickness locations in the first bonding layer 200. For example,
the C atomic concentration is consistent at each thickness location
in the first bonding layer 200.
[0044] In another embodiment, the density of the first bonding
layer 200 may change gradually with increasing thickness of the
first bonding layer 200 by adjusting the parameters of the forming
process. For example, the density of the first bonding layer 200
gradually increases, gradually decreases, or increases first and
then decreases from the surface of the first device layer 102. The
density of the first bonding layer 200 is close to the density of
the first device layer 102 at the interface.
[0045] The first bonding layer 200 cannot be too thin for ensuring
an enough bonding thickness of the first bonding layer 200 in the
process of bonding the first bonding layer 200 to other bonding
layers. In one embodiment, the thickness of the first bonding layer
200 is larger than 100 angstroms.
[0046] The first bonding layer 200 may include two or more sub
bonding layers stacked with one another. The element compositions
of different sub bonding layers may be different from one another.
The composition concentration in each sub bonding layer may not
vary with thickness or may change gradually with thickness. The
composition concentration in the whole sub bonding layer may be
adjusted for modifying the adhesion between the first bonding layer
200 and the first device layer 102, the adhesion at the interface
between the sub bonding layers, and the dielectric constant of the
first bonding layer 200.
[0047] Please refer to FIG. 3. In another embodiment, the method
further includes providing a second substrate 300 and forming a
second bonding layer 400 on the surface of the second substrate
300.
[0048] The second substrate 300 includes a second semiconductor
substrate 301 and a second device layer 302 located on the surface
of the second semiconductor substrate 301.
[0049] The second bonding layer 400 is formed on the surface of the
second device layer 302 by a chemical vapor deposition process. The
material of the second bonding layer 400 may be silicon oxide or
silicon nitride.
[0050] In the embodiment, the material of the second bonding layer
400 may be a dielectric material containing element carbon. In one
embodiment, the second bonding layer 400 mainly includes Si, N, and
C. In another embodiment, the second bonding layer 400 may be
further doped with at least one element of Si, N, O, H, P, or F in
accordance with reactive gases used in the chemical vapor
deposition process and requirements of specific products. The
second bonding layer may be formed by the same method of forming
the first bonding layer 200. Please refer to the description about
the first bonding layer 200 in the embodiments mentioned above, and
that will not be redundantly described here. In one embodiment, the
material of the second bonding layer 400 may be the same as the
material of the first bonding layer 200 described above.
[0051] Please refer to FIG. 4. The second bonding layer 400 is
bonded to and fixed on the first bonding layer 200 with a surface
of the second bonding layer 400 facing a surface of the first
bonding layer 200.
[0052] A part of the element carbon in the first bonding layer 200
and the second bonding layer 400 exists in the form of CH.sub.3.
The method further includes performing an oxidation treatment and a
plasma treatment in sequence to the surface of the second bonding
layer 400 and the surface of the first bonding layer 200 before the
bonding process. The oxidation treatment can be used to oxidize
--CH3 or other carbon-containing groups in the second bonding layer
400 and the first bonding layer 200. The plasma treatment is used
to activate chemical bonds on the surface of the first bonding
layer 200 and the surface of the second bonding layer 400 for
increasing the surface energy of the first bonding layer 200 and
the second bonding layer 400. Finally, the --CH3 or other
carbon-containing groups are oxidized to be --OH. In one
embodiment, oxygen is used as an oxidation gas, the temperature
ranges from 25.degree. C. to 80.degree. C., and the treatment time
ranges from 20 minutes to 200 minutes in the oxidation treatment.
In one embodiment, N2 is used as a plasma source gas, the power
ranges from 75 W to 300 W, and the treatment time ranges from 15
seconds to 45 seconds in the plasma treatment.
[0053] The C atomic concentration is higher at the surface of the
first bonding layer 200 and the surface of the second bonding layer
400, and the amount of hydroxyl formed by oxidation at the surfaces
is larger. The hydroxyl and Si in the first bonding layer 200 and
the second bonding layer 400 form silicon-oxide bonds in the
bonding process for enhancing the bonding strength at the bonding
interface. In one embodiment, the bonding strength between the
second bonding layer 400 and the first bonding layer 200 is higher
than 1.7 J/M.sup.2. The bonding strength is generally lower than
1.5 J/M.sup.2 by using carbon-free bonding layers in the
conventional bonding technology.
[0054] In one embodiment, the first substrate 100 is a substrate
having a 3D NAND memory structure formed therein, and the second
substrate 200 is a substrate having a peripheral circuit formed
therein.
[0055] In another embodiment, the above-mentioned bonding layer may
be formed on two opposite surfaces of the substrate for realizing
multiple layer bonding.
[0056] Please refer to FIG. 5. In another embodiment, the method
further includes forming a first bonding pad 501 penetrating the
first bonding layer 200; forming a second bonding pad 502
penetrating the second bonding layer 400; and bonding the first
bonding pad 501 to the second bonding pad 502 correspondingly as
bonding the second bonding layer 400 to the first bonding layer 200
and fixing the second bonding layer 400 on the first bonding layer
200 with the surface of the second bonding layer 400 facing the
surface of the first bonding layer 200.
[0057] The first bonding pad 501 and the second bonding pad 502 may
be connected to the semiconductor devices and the metal
interconnection layers in the first device layer 102 and the second
device layer 302 respectively.
[0058] The method of forming the first bonding pad 501 may include
patterning the first bonding layer 200; forming an opening
penetrating the first bonding layer 200; filling the opening with
metal material; and performing a planarization process for forming
the first bonding pad 501 which the opening is filled with. The
second bonding pad 502 is formed in the second bonding layer 400 by
the same method. The first bonding pad 501 and the second bonding
pad 502 are bonded to and connected with each other for realizing
electrical connection between semiconductor devices in the first
device layer 102 and the second device layer 302.
[0059] The material of the first bonding pad 501 and the second
bonding pad 502 may be a metal material such as copper (Cu) or
tungsten (W). The first bonding layer 200 and the second bonding
layer 400 may both contain carbon for effectively blocking the
materials of the first bonding pad 501 and the second bonding pad
502 from diffusing at the bonding interface, and the performance of
the semiconductor structure is enhanced accordingly.
[0060] In the embodiment mentioned above, the first bonding layer
is formed on the surface of the first substrate, and the material
of the first bonding layer is a dielectric material containing
element carbon for providing higher bonding strength at the bonding
interface after the bonding process and blocking metal materials
from diffusing at the bonding interface. The performance of the
semiconductor structure formed by the method is enhanced
accordingly.
[0061] The above-mentioned method is further applied in bonding a
plurality of substrates.
[0062] Please refer to FIG. 6. In an embodiment of the present
invention, the method further include providing a third substrate
600; forming a third bonding layer 700 and a fourth bonding layer
800 on two opposite surfaces of the third substrate 600
respectively; bonding the third bonding layer 700 to the first
bonding layer 200 and fixing the third bonding layer 700 on the
first bonding layer 200 with the surface of the third bonding layer
700 facing the surface of the first bonding layer 200; and bonding
the fourth bonding layer 800 to the second bonding layer 400 and
fixing the fourth bonding layer 800 on the second bonding layer 400
with the surface of the fourth bonding layer 800 facing the surface
of the second bonding layer 400 for forming a tri-layer bonding
structure.
[0063] Please refer to the material and the forming method of the
first bonding layer 200 in the embodiments described above for the
material and the forming method of the third bonding layer 700 and
the fourth bonding layer 800, and those will not be redundantly
described here.
[0064] In the embodiment, the method further includes forming a
third bonding pad 701 in the third bonding layer 700; forming a
fourth bonding pad 801 in the fourth bonding layer 800; bonding the
third bonding pad 701 to the first bonding pad 501; and bonding the
fourth bonding pad 801 to the second bonding pad 502.
[0065] In another embodiment, a bonding structure including four or
more layers may be formed by the method described above.
[0066] It must be stated that, in the technical solution of the
present invention, the types of the semiconductor devices in each
substrate of the semiconductor structure are not limited to the
given embodiments. Apart from 3D NAND, the semiconductor device may
be a CMOS circuit, a CIS circuit, a TFT circuit, and so forth.
[0067] A semiconductor structure is further provided by embodiments
of the present invention.
[0068] Please refer to FIG. 2. FIG. 2 is a structural schematic
drawing illustrating a semiconductor structure according to an
embodiment of the present invention.
[0069] The semiconductor structure includes a first substrate 100;
and a first bonding layer 200 located on the surface of the first
substrate 100. The material of the first bonding layer 200 is a
dielectric material containing element carbon.
[0070] The first substrate 100 includes a first semiconductor
substrate 101 and a first device layer 102 formed on the surface of
the first semiconductor substrate 101.
[0071] The first semiconductor substrate 101 may be a single
crystal silicon substrate, a Ge substrate, a SiGe substrate, a SOI
substrate, a GOI substrate, and so forth. Suitable types of the
first semiconductor substrate 101 may be used in accordance with
the actual requirements of the devices and are not limited to the
above descriptions. In the embodiment, the first semiconductor
substrate 101 is a single crystal silicon substrate.
[0072] The first device layer 102 includes a semiconductor device,
a metal interconnection structure connected with the semiconductor
device, and a medium layer covering the semiconductor device and
the metal interconnection structure. The first device layer 102 may
be a multiple layer structure or a single layer structure. In an
embodiment, the first device layer 102 includes a medium layer and
a 3D NAND structure formed in the medium layer.
[0073] The material of the first bonding layer 200 is a dielectric
material containing element C. In one embodiment, the first bonding
layer 200 mainly includes Si, N, and C. In another embodiment, the
first bonding layer 200 maybe further doped with at least one
element of Si, N, O, H, P, or F in accordance with the forming
process and the requirements of the specific products. The material
of the first bonding layer 200 may be carbon-doped silicon nitride,
carbon-doped silicon oxynitride, nitrogen-doped silicon oxycarbide,
and so forth.
[0074] By controlling the process parameters of forming the first
bonding layer 200, the concentration of each composition in the
first bonding layer 200 may be adjusted for modifying the adhesion
between the first bonding layer 200 and the first device layer 102,
the dielectric constant of the first bonding layer 200, and the
bonding strength between the first bonding layer 200 and another
bonding layer after bonding.
[0075] The element carbon in the first bonding layer 200 may be
used to effectively enhance the bonding strength between the first
bonding layer 200 and other bonding layers during the bonding
process. The higher the C atomic concentration, the higher the
bonding strength between the first bonding layer 200 and other
bonding layers during the bonding process. The higher the C atomic
concentration at the surface of the first bonding layer 200, the
higher the bonding strength between the first bonding layer 200 and
other bonding layers during the bonding process. The element carbon
in the first bonding layer 200 may exist in the form of unstable
methyl group (--CH.sub.3), the methyl group (--CH.sub.3) maybe
oxidized to be hydroxyl group (--OH) after treatments, such as a
native oxidation and a plasma activation treatment, performed
before the bonding process, and the amount of hydroxyl increases
accordingly. Finally in the bonding process, the amount of Si--O
bonds at the bonding interface is increased for enhancing the
bonding strength.
[0076] The adhesion between different material layers relates to
the material compositions at two sides of the interface. The closer
the material composition is, the higher the adhesion. For further
increasing the adhesion between the first bonding layer 200 and the
first device layer 102, the composition concentration in the first
bonding layer 200 may vary gradually with increasing thickness for
making the material compositions at the two sides of the interface
between the first bonding layer 200 and the first device layer 200
similar to each other. In one embodiment, the C atomic
concentration in the first bonding layer 200 increases gradually
with increasing thickness of the first bonding layer 200, and the C
atomic concentration is highest at the surface of the first bonding
layer 200. In another embodiment, the concentration of each element
in the first bonding layer 200 distributes uniformly at different
thickness locations in the first bonding layer 200. For example,
the C atomic concentration is consistent at each thickness location
in the first bonding layer 200.
[0077] In another embodiment, the density of the first bonding
layer 200 changes gradually with increasing thickness. For example,
the density of the first bonding layer 200 gradually increases,
gradually decreases, or increases first and then decreases from the
surface of the first device layer 102. The density of the first
bonding layer 200 is close to the density of the first device layer
102 at the interface.
[0078] The first bonding layer 200 cannot be too thin for ensuring
an enough bonding thickness of the first bonding layer 200 in the
process of bonding the first bonding layer 200 to other bonding
layers. In one embodiment, the thickness of the first bonding layer
200 is larger than 100 angstroms. For having enough C atomic
concentration near the surface of the first bonding layer 200, in
an embodiment, the C atomic concentration of the surface layer
having a certain thickness from the surface of the first bonding
layer 200 to the inside of the first bonding layer 200 is higher
than or equal to 35%. The thickness of the surface layer may range
from 10 angstroms to 50 angstroms. In one embodiment, the C atomic
concentration within a thickness equal to 30 angstroms from the
surface of the first bonding layer 200 to the inside of the first
bonding layer 200 is higher than 40%.
[0079] The first bonding layer 200 may include two or more sub
bonding layers stacked with one another. The element compositions
of different sub bonding layers may be different from one another.
The composition concentration in each sub bonding layer may not
vary with thickness or may change gradually with thickness. The
composition concentration in the whole sub bonding layer may be
adjusted for modifying the adhesion between the first bonding layer
200 and the first device layer 102, the adhesion at the interface
between the sub bonding layers, and the dielectric constant of the
first bonding layer 200.
[0080] Please refer to FIG. 4. FIG. 4 is a structural schematic
drawing illustrating a semiconductor structure according to an
embodiment of the present invention.
[0081] In the embodiment, the semiconductor structure further
includes a second substrate 300. A second bonding layer 400 is
formed on the surface of the second substrate 300. The second
bonding layer 400 is bonded to and fixed on the first bonding layer
200 with the surface of the second bonding layer 400 facing the
surface of the first bonding layer 200.
[0082] The second substrate 300 includes a second semiconductor
substrate 301 and a second device layer 302 located on the surface
of the second semiconductor substrate 301. The material of the
second bonding layer 400 maybe silicon oxide or silicon nitride.
The material of the second bonding layer 400 maybe a dielectric
material containing element C also. For details, please refer to
the description of the first bonding layer 200 in the embodiments
described above, and that will not be redundantly described here.
In one embodiment, the material of the second bonding layer 400 is
the same as the material of the first bonding layer 200 described
above.
[0083] The second bonding layer 400 is bonded to and fixed on the
first bonding layer 200 with the surface of the second bonding
layer 400 facing the surface of the first bonding layer 200. The C
atomic concentration is higher at the surface of the first bonding
layer 200 and the surface of the second bonding layer 400. The
amount of hydroxyl formed by oxidation at the surfaces is larger
during the bonding process, and more silicon-oxide bonds are formed
at the bonding interface for enhancing the bonding strength at the
bonding interface.
[0084] In one embodiment, the first substrate 100 is a substrate
having a 3D NAND memory structure formed therein, and the second
substrate 200 is a substrate having a peripheral circuit formed
therein.
[0085] In another embodiment, the semiconductor structure may
include three or more substrates, and the adjacent substrates are
bonded to one another by the bonding layers in the embodiments of
the present invention.
[0086] Please refer to FIG. 5. FIG. 5 is a structural schematic
drawing illustrating a semiconductor structure according to another
embodiment of the present invention.
[0087] In the embodiment, the semiconductor structure further
includes a first bonding pad 501 penetrating the first bonding
layer 200 and a second bonding pad 502 penetrating the second
bonding layer 400. The second bonding layer 400 is bonded to and
fixed on the first bonding layer 200 with the surface of the second
bonding layer 400 facing the surface of the first bonding layer
200, and the first bonding pad 501 is bonded to the second bonding
pad 502 correspondingly.
[0088] The first bonding pad 501 and the second bonding pad 502 may
be connected to the semiconductor devices and the metal
interconnection layers in the first device layer 102 and the second
device layer 302 respectively.
[0089] The material of the first bonding pad 501 and the second
bonding pad 502 may be a metal material such as Cu or W. The first
bonding layer 200 and the second bonding layer 400 may both contain
carbon, and the C atomic concentration is higher at the bonding
interface for effectively blocking the materials of the first
bonding pad 501 and the second bonding pad 502 from diffusing at
the bonding interface. The performance of the semiconductor
structure is enhanced accordingly.
[0090] In one embodiment, the first substrate 100 is a substrate
having a 3D NAND memory structure formed therein, and the second
substrate 200 is a substrate having a peripheral circuit formed
therein.
[0091] Please refer to FIG. 6. FIG. 6 is a schematic drawing
illustrating a semiconductor structure according to another
embodiment of the present invention.
[0092] In the embodiment, the semiconductor structure further
includes a third substrate 600, a third bonding layer 700 located
on a surface at one side of the third substrate 600, and a fourth
bonding layer 800 located on an opposite surface at another side of
the third substrate 600. The third bonding layer 700 is bonded to
and fixed on the first bonding layer 200 with the surface of the
third bonding layer 700 facing the surface of the first bonding
layer 200, and the fourth bonding layer 800 is bonded to and fixed
on the second bonding layer 400 with the surface of the fourth
bonding layer 800 facing the surface of the second bonding layer
400 for forming a tri-layer bonding structure.
[0093] Please refer to the material and the structure of the first
bonding layer 200 in the embodiments described above for the
material and the structure of the third bonding layer 700 and the
fourth bonding layer 800, and those will not be redundantly
described here.
[0094] In the embodiment, the semiconductor structure further
includes a third bonding pad 701 penetrating the third bonding
layer 700 and a fourth bonding pad 801 penetrating the fourth
bonding layer 800. The third bonding pad 701 is bonded to the first
bonding pad 501, and the fourth bonding pad 801 is bonded to the
second bonding pad 502.
[0095] In another embodiment, a bonding structure including four or
more layers may be formed by the method described above.
[0096] The above descriptions are only preferred embodiments of the
present invention, and it should be noted that those skilled in the
art can also make several improvements and embellishments without
departing from the principles of the present invention. These
improvements and embellishments should also be regarded as the
protection scope of the present invention.
[0097] Those skilled in the art will readily observe that numerous
modifications and alterations of the device and method may be made
while retaining the teachings of the invention. Accordingly, the
above disclosure should be construed as limited only by the metes
and bounds of the appended claims.
* * * * *