U.S. patent application number 15/859388 was filed with the patent office on 2019-02-28 for technologies for migrating virtual machines.
The applicant listed for this patent is Intel Corporation. Invention is credited to Mohan J. Kumar, Murugasamy K. Nachimuthu, Slawomir Putyrski, Mark A. Schmisseur, Dimitrios Ziakas.
Application Number | 20190065231 15/859388 |
Document ID | / |
Family ID | 65434219 |
Filed Date | 2019-02-28 |
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United States Patent
Application |
20190065231 |
Kind Code |
A1 |
Schmisseur; Mark A. ; et
al. |
February 28, 2019 |
TECHNOLOGIES FOR MIGRATING VIRTUAL MACHINES
Abstract
Technologies for migrating virtual machines (VMs) includes a
plurality of compute sleds and a memory sled each communicatively
coupled to a resource manager server. The resource manager server
is configured to identify a compute sled of a for a virtual machine
instance, allocate a first set of resources of the identified
compute sled for the VM instance, associate a region of memory in a
memory pool of a memory sled with the compute sled, and create the
VM instance on the compute sled. The resource manager server is
further configured to migrate the VM instance to another compute
sled, associate the region of memory in the memory pool with the
other compute sled, and start-up the VM instance on the other
compute sled. Other embodiments are described herein.
Inventors: |
Schmisseur; Mark A.;
(Phoenix, AZ) ; Kumar; Mohan J.; (Aloha, OR)
; Nachimuthu; Murugasamy K.; (Beaverton, OR) ;
Putyrski; Slawomir; (Gdynia, PL) ; Ziakas;
Dimitrios; (Hillsboro, OR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Intel Corporation |
Santa Clara |
CA |
US |
|
|
Family ID: |
65434219 |
Appl. No.: |
15/859388 |
Filed: |
December 30, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
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62584401 |
Nov 10, 2017 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
G06F 9/44 20130101; H04L
41/0816 20130101; G06F 1/183 20130101; G06F 9/5088 20130101; G06F
11/3466 20130101; H04L 41/14 20130101; H04L 41/044 20130101; H04L
41/5019 20130101; H04L 43/0876 20130101; G06F 2200/201 20130101;
G06F 9/5061 20130101; G06F 11/3006 20130101; H05K 7/1489 20130101;
G06F 1/20 20130101; G06F 11/3409 20130101; H04L 41/5025 20130101;
H04L 41/0896 20130101; G06Q 30/0283 20130101; H04L 67/1008
20130101; B25J 15/0014 20130101; G06F 2201/86 20130101; H04L 43/065
20130101; G06F 9/505 20130101; G06F 2201/885 20130101; H05K 7/20736
20130101; G06F 11/3442 20130101; H05K 7/18 20130101; Y02D 10/00
20180101; G06F 15/7807 20130101; G06N 3/063 20130101; H04L 43/16
20130101; G06Q 10/0631 20130101; Y02D 30/00 20180101; H04L 49/40
20130101; G06F 9/4856 20130101; G06F 21/105 20130101; H04L 63/0428
20130101; H05K 7/1498 20130101; G06F 13/4022 20130101; G06F 15/7867
20130101 |
International
Class: |
G06F 9/455 20060101
G06F009/455; G06F 9/48 20060101 G06F009/48 |
Foreign Application Data
Date |
Code |
Application Number |
Aug 30, 2017 |
IN |
201741030632 |
Claims
1. A resource manager server for migrating virtual machines, the
resource manager server comprising: a communication circuit; and a
compute engine to: identify a compute sled of a plurality of
compute sleds for a virtual machine (VM) instance, wherein each of
the compute sleds is communicatively coupled to the resource
manager server; allocate a first set of resources of the identified
compute sled for the VM instance; associate a region of memory in a
memory pool of a memory sled with the compute sled, wherein the
memory sled is communicatively coupled to the resource manager
server; create the VM instance on the compute sled; allocate, in
response to determined determination that the VM instance is to be
migrated, a second set of resources of another compute sled of the
plurality of compute sleds for the VM instance; migrate the VM
instance to the other compute sled; associate the region of memory
in the memory pool with the other compute sled; and start-up the VM
instance on the other compute sled.
2. The resource manager server of claim 1, wherein to allocate the
first set of resources of the compute sled comprises to (i)
determine a set of resources required by a workload to be processed
by the VM instance and (ii) allocate the first set of resources of
the compute sled as a function of the determined required set of
resources.
3. The resource manager server of claim 2, wherein to allocate the
first set of resources of the compute sled further comprises to (i)
identify available resources of each of the plurality of compute
sleds and (ii) allocate the first set of resources of the compute
sled as a function of the identified available resources.
4. The resource manager server of claim 1, wherein to associate the
region of memory in the memory pool of the memory sled with the
compute sled comprises to transmit a memory allocation request to a
memory pool controller of the memory pool that is usable to
allocate the region of memory and map the allocated region of
memory to the compute sled.
5. The resource manager server of claim 1, wherein to migrate the
VM instance to the other compute sled comprises to transmit one or
more threads associated with the workload associated with the VM
instance to the other compute sled.
6. The resource manager server of claim 1, wherein to associate the
region of memory in the memory pool of the memory sled with the
other compute sled comprises to transmit a memory allocation
request to a memory pool controller of the memory pool that is
usable to map the allocated region of memory to the other compute
sled.
7. The resource manager server of claim 1, wherein to allocate the
second set of resources of the compute sled comprises to (i)
retrieve a set of resources required by a workload being processed
by the VM instance and (ii) allocate the second set of resources of
the compute sled as a function of the retrieved required set of
resources.
8. The resource manager server of claim 7, wherein to allocate the
second set of resources of the other compute sled further comprises
to (i) identify available resources of each of the plurality of
compute sleds and (ii) allocate the second set of resources of the
other compute sled as a function of the identified available
resources.
9. One or more machine-readable storage media comprising a
plurality of instructions stored thereon that, in response to being
executed, cause a resource manager server to: identify a compute
sled of a plurality of compute sleds for a virtual machine (VM)
instance, wherein each of the compute sleds is communicatively
coupled to the resource manager server; allocate a first set of
resources of the identified compute sled for the VM instance;
associate a region of memory in a memory pool of a memory sled with
the compute sled, wherein the memory sled is communicatively
coupled to the resource manager server; create the VM instance on
the compute sled; allocate, in response to determined determination
that the VM instance is to be migrated, a second set of resources
of another compute sled of the plurality of compute sleds for the
VM instance; migrate the VM instance to the other compute sled;
associate the region of memory in the memory pool with the other
compute sled; and start-up the VM instance on the other compute
sled.
10. The one or more machine-readable storage media of claim 9,
wherein to allocate the first set of resources of the compute sled
comprises to (i) determine a set of resources required by a
workload to be processed by the VM instance and (ii) allocate the
first set of resources of the compute sled as a function of the
determined required set of resources.
11. The one or more machine-readable storage media of claim 10,
wherein to allocate the first set of resources of the compute sled
further comprises to (i) identify available resources of each of
the plurality of compute sleds and (ii) allocate the first set of
resources of the compute sled as a function of the identified
available resources.
12. The one or more machine-readable storage media of claim 9,
wherein to associate the region of memory in the memory pool of the
memory sled with the compute sled comprises to transmit a memory
allocation request to a memory pool controller of the memory pool
that is usable to allocate the region of memory and map the
allocated region of memory to the compute sled.
13. The one or more machine-readable storage media of claim 9,
wherein to migrate the VM instance to the other compute sled
comprises to transmit one or more threads associated with the
workload associated with the VM instance to the other compute
sled.
14. The one or more machine-readable storage media of claim 9,
wherein to associate the region of memory in the memory pool of the
memory sled with the other compute sled comprises to transmit a
memory allocation request to a memory pool controller of the memory
pool that is usable to map the allocated region of memory to the
other compute sled.
15. The one or more machine-readable storage media of claim 9,
wherein to allocate the second set of resources of the compute sled
comprises to (i) retrieve a set of resources required by a workload
being processed by the VM instance and (ii) allocate the second set
of resources of the compute sled as a function of the retrieved
required set of resources.
16. The one or more machine-readable storage media of claim 15,
wherein to allocate the second set of resources of the other
compute sled further comprises to (i) identify available resources
of each of the plurality of compute sleds and (ii) allocate the
second set of resources of the other compute sled as a function of
the identified available resources.
17. A resource manager server for migrating virtual machines, the
resource manager server comprising: circuitry for identifying, by a
compute engine of the resource manager server, a compute sled of a
plurality of compute sleds for a virtual machine (VM) instance,
wherein each of the compute sleds is communicatively coupled to the
resource manager server; circuitry for allocating, by the compute
engine, a first set of resources of the identified compute sled for
the VM instance; means for associating, by the compute engine, a
region of memory in a memory pool of a memory sled with the compute
sled, wherein the memory sled is communicatively coupled to the
resource manager server; circuitry for creating, by the compute
engine, the VM instance on the compute sled; circuitry for
allocating, by the compute engine and in response to determined
determination that the VM instance is to be migrated, a second set
of resources of another compute sled of the plurality of compute
sleds for the VM instance; circuitry for migrating, by the compute
engine, the VM instance to the other compute sled; means for
associating, by the compute engine, the region of memory in the
memory pool with the other compute sled; and circuitry for
starting-up, by the compute engine, the VM instance on the other
compute sled.
18. The resource manager server of claim 17, wherein the circuitry
for allocating the first set of resources of the compute sled
comprises: means for determining a set of resources required by a
workload to be processed by the VM instance; and circuitry for
allocating the first set of resources of the compute sled as a
function of the determined required set of resources.
19. The resource manager server of claim 18, wherein the circuitry
for allocating the first set of resources of the compute sled
further comprises: means for identifying available resources of
each of the plurality of compute sleds; and circuitry for
allocating the first set of resources of the compute sled as a
function of the identified available resources.
20. The resource manager server of claim 17, wherein the means for
associating the region of memory in the memory pool of the memory
sled with the compute sled comprises means for transmitting a
memory allocation request to a memory pool controller of the memory
pool that is usable to allocate the region of memory and map the
allocated region of memory to the compute sled.
21. The resource manager server of claim 17, wherein the circuitry
for migrating the VM instance to the other compute sled comprises
circuitry for transmitting one or more threads associated with the
workload associated with the VM instance to the other compute
sled.
22. The resource manager server of claim 17, wherein the means for
associating the region of memory in the memory pool of the memory
sled with the other compute sled comprises means for transmitting a
memory allocation request to a memory pool controller of the memory
pool that is usable to map the allocated region of memory to the
other compute sled.
23. The resource manager server of claim 17, wherein the circuitry
for allocating the second set of resources of the compute sled
comprises: circuitry for retrieving a set of resources required by
a workload being processed by the VM instance; and circuitry for
allocating the second set of resources of the compute sled as a
function of the retrieved required set of resources.
24. The resource manager server of claim 23, wherein the circuitry
for allocating the second set of resources of the other compute
sled further comprises: means for identifying available resources
of each of the plurality of compute sleds; and circuitry for
allocating the second set of resources of the other compute sled as
a function of the identified available resources.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] The present application claims the benefit of U.S.
Provisional Patent Application No. 62/427,268, filed Nov. 29, 2016
and Indian Provisional Patent Application No. 201741030632, filed
Aug. 30, 2017.
BACKGROUND
[0002] Network operators and service providers typically rely on
various network virtualization technologies to manage complex,
large-scale computing environments, such as high-performance
computing (HPC) and cloud computing environments. Typically, these
computing environments, or data centers, are comprised of a
multitude of network computing devices (e.g., servers, switches,
routers, etc.) which are configured to perform various operations
(e.g., process network traffic through the data center, store data,
perform computations, etc.). In order to provide scalability to
meet demand and reduce operational costs, certain data center
operations are typically run inside containers or virtual machines
(VMs) in a virtualized environment of one or more of the network
computing devices.
[0003] Oftentimes, for various reasons (e.g., data center closures,
compromised server security, disaster recovery, network
infrastructure upgrades, etc.), a container or VM being executed on
one network computing device needs to be migrated to another.
Although container/VM migration can be a useful tool, the
migrations typically require the copying of data (e.g., the
container/VM requirements, the workload, the stored data associated
with the workload, etc.) across the network between the network
computing devices. The data copy typically introduces network
traffic, resulting in bandwidth consumption that could otherwise be
used for other operations.
BRIEF DESCRIPTION OF THE DRAWINGS
[0004] The concepts described herein are illustrated by way of
example and not by way of limitation in the accompanying figures.
For simplicity and clarity of illustration, elements illustrated in
the figures are not necessarily drawn to scale. Where considered
appropriate, reference labels have been repeated among the figures
to indicate corresponding or analogous elements.
[0005] FIG. 1 is a simplified diagram of at least one embodiment of
a data center for executing workloads with disaggregated
resources;
[0006] FIG. 2 is a simplified diagram of at least one embodiment of
a pod of the data center of FIG. 1;
[0007] FIG. 3 is a perspective view of at least one embodiment of a
rack that may be included in the pod of FIG. 2;
[0008] FIG. 4 is a side plan elevation view of the rack of FIG.
3;
[0009] FIG. 5 is a perspective view of the rack of FIG. 3 having a
sled mounted therein;
[0010] FIG. 6 is a is a simplified block diagram of at least one
embodiment of a top side of the sled of FIG. 5;
[0011] FIG. 7 is a simplified block diagram of at least one
embodiment of a bottom side of the sled of FIG. 6;
[0012] FIG. 8 is a simplified block diagram of at least one
embodiment of a compute sled usable in the data center of FIG.
1;
[0013] FIG. 9 is a top perspective view of at least one embodiment
of the compute sled of FIG. 8;
[0014] FIG. 10 is a simplified block diagram of at least one
embodiment of an accelerator sled usable in the data center of FIG.
1;
[0015] FIG. 11 is a top perspective view of at least one embodiment
of the accelerator sled of FIG. 10;
[0016] FIG. 12 is a simplified block diagram of at least one
embodiment of a storage sled usable in the data center of FIG.
1;
[0017] FIG. 13 is a top perspective view of at least one embodiment
of the storage sled of FIG. 12;
[0018] FIG. 14 is a simplified block diagram of at least one
embodiment of a memory sled usable in the data center of FIG. 1;
and
[0019] FIG. 15 is a simplified block diagram of a system that may
be established within the data center of FIG. 1 to execute
workloads with managed nodes composed of disaggregated
resources.
[0020] FIG. 16 is a simplified block diagram of at least one
embodiment of a system for migrating virtual machines which
includes multiple compute sleds, a memory sled, and a resource
manager server;
[0021] FIG. 17 is a simplified block diagram of at least one
embodiment of the resource manager server of the system of FIG.
16;
[0022] FIG. 18 is a simplified block diagram of at least one
embodiment of one of the compute sleds of the system of FIG.
16;
[0023] FIG. 19 is a simplified block diagram of at least one
embodiment of an environment that may be established by the
resource manager server of FIGS. 16 and 17;
[0024] FIG. 20 is a simplified flow diagram of at least one
embodiment of a method for creating a virtual machine instance that
may be performed by the resource manager server of FIGS. 16, 17,
and 19; and
[0025] FIG. 21 is a simplified flow diagram of at least one
embodiment of a method for migrating a virtual machine instance
that may be performed by the resource manager server of FIGS. 16,
17, and 19.
DETAILED DESCRIPTION OF THE DRAWINGS
[0026] While the concepts of the present disclosure are susceptible
to various modifications and alternative forms, specific
embodiments thereof have been shown by way of example in the
drawings and will be described herein in detail. It should be
understood, however, that there is no intent to limit the concepts
of the present disclosure to the particular forms disclosed, but on
the contrary, the intention is to cover all modifications,
equivalents, and alternatives consistent with the present
disclosure and the appended claims.
[0027] References in the specification to "one embodiment," "an
embodiment," "an illustrative embodiment," etc., indicate that the
embodiment described may include a particular feature, structure,
or characteristic, but every embodiment may or may not necessarily
include that particular feature, structure, or characteristic.
Moreover, such phrases are not necessarily referring to the same
embodiment. Further, when a particular feature, structure, or
characteristic is described in connection with an embodiment, it is
submitted that it is within the knowledge of one skilled in the art
to effect such feature, structure, or characteristic in connection
with other embodiments whether or not explicitly described.
Additionally, it should be appreciated that items included in a
list in the form of "at least one A, B, and C" can mean (A); (B);
(C); (A and B); (A and C); (B and C); or (A, B, and C). Similarly,
items listed in the form of "at least one of A, B, or C" can mean
(A); (B); (C); (A and B); (A and C); (B and C); or (A, B, and
C).
[0028] The disclosed embodiments may be implemented, in some cases,
in hardware, firmware, software, or any combination thereof. The
disclosed embodiments may also be implemented as instructions
carried by or stored on a transitory or non-transitory
machine-readable (e.g., computer-readable) storage medium, which
may be read and executed by one or more processors. A
machine-readable storage medium may be embodied as any storage
device, mechanism, or other physical structure for storing or
transmitting information in a form readable by a machine (e.g., a
volatile or non-volatile memory, a media disc, or other media
device).
[0029] In the drawings, some structural or method features may be
shown in specific arrangements and/or orderings. However, it should
be appreciated that such specific arrangements and/or orderings may
not be required. Rather, in some embodiments, such features may be
arranged in a different manner and/or order than shown in the
illustrative figures. Additionally, the inclusion of a structural
or method feature in a particular figure is not meant to imply that
such feature is required in all embodiments and, in some
embodiments, may not be included or may be combined with other
features.
[0030] Referring now to FIG. 1, a data center 100 in which
disaggregated resources may cooperatively execute one or more
workloads (e.g., applications on behalf of customers) includes
multiple pods 110, 120, 130, 140, each of which includes one or
more rows of racks. As described in more detail herein, each rack
houses multiple sleds, which each may be embodied as a compute
device, such as a server, that is primarily equipped with a
particular type of resource (e.g., memory devices, data storage
devices, accelerator devices, general purpose processors). In the
illustrative embodiment, the sleds in each pod 110, 120, 130, 140
are connected to multiple pod switches (e.g., switches that route
data communications to and from sleds within the pod). The pod
switches, in turn, connect with spine switches 150 that switch
communications among pods (e.g., the pods 110, 120, 130, 140) in
the data center 100. In some embodiments, the sleds may be
connected with a fabric using Intel Omni-Path technology. As
described in more detail herein, resources within sleds in the data
center 100 may be allocated to a group (referred to herein as a
"managed node") containing resources from one or more other sleds
to be collectively utilized in the execution of a workload. The
workload can execute as if the resources belonging to the managed
node were located on the same sled. The resources in a managed node
may even belong to sleds belonging to different racks, and even to
different pods 110, 120, 130, 140. Some resources of a single sled
may be allocated to one managed node while other resources of the
same sled are allocated to a different managed node (e.g., one
processor assigned to one managed node and another processor of the
same sled assigned to a different managed node). By disaggregating
resources to sleds comprised predominantly of a single type of
resource (e.g., compute sleds comprising primarily compute
resources, memory sleds containing primarily memory resources), and
selectively allocating and deallocating the disaggregated resources
to form a managed node assigned to execute a workload, the data
center 100 provides more efficient resource usage over typical data
centers comprised of hyperconverged servers containing compute,
memory, storage and perhaps additional resources). As such, the
data center 100 may provide greater performance (e.g., throughput,
operations per second, latency, etc.) than a typical data center
that has the same number of resources.
[0031] Referring now to FIG. 2, the pod 110, in the illustrative
embodiment, includes a set of rows 200, 210, 220, 230 of racks 240.
Each rack 240 may house multiple sleds (e.g., sixteen sleds) and
provide power and data connections to the housed sleds, as
described in more detail herein. In the illustrative embodiment,
the racks in each row 200, 210, 220, 230 are connected to multiple
pod switches 250, 260. The pod switch 250 includes a set of ports
252 to which the sleds of the racks of the pod 110 are connected
and another set of ports 254 that connect the pod 110 to the spine
switches 150 to provide connectivity to other pods in the data
center 100. Similarly, the pod switch 260 includes a set of ports
262 to which the sleds of the racks of the pod 110 are connected
and a set of ports 264 that connect the pod 110 to the spine
switches 150. As such, the use of the pair of switches 250, 260
provides an amount of redundancy to the pod 110. For example, if
either of the switches 250, 260 fails, the sleds in the pod 110 may
still maintain data communication with the remainder of the data
center 100 (e.g., sleds of other pods) through the other switch
250, 260. Furthermore, in the illustrative embodiment, the switches
150, 250, 260 may be embodied as dual-mode optical switches,
capable of routing both Ethernet protocol communications carrying
Internet Protocol (IP) packets and communications according to a
second, high-performance link-layer protocol (e.g., Intel's
Omni-Path Architecture's, Infiniband) via optical signaling media
of an optical fabric.
[0032] It should be appreciated that each of the other pods 120,
130, 140 (as well as any additional pods of the data center 100)
may be similarly structured as, and have components similar to, the
pod 110 shown in and described in regard to FIG. 2 (e.g., each pod
may have rows of racks housing multiple sleds as described above).
Additionally, while two pod switches 250, 260 are shown, it should
be understood that in other embodiments, each pod 110, 120, 130,
140 may be connected to different number of pod switches (e.g.,
providing even more failover capacity).
[0033] Referring now to FIGS. 3-5, each illustrative rack 240 of
the data center 100 includes two elongated support posts 302, 304,
which are arranged vertically. For example, the elongated support
posts 302, 304 may extend upwardly from a floor of the data center
100 when deployed. The rack 240 also includes one or more
horizontal pairs 310 of elongated support arms 312 (identified in
FIG. 3 via a dashed ellipse) configured to support a sled of the
data center 100 as discussed below. One elongated support arm 312
of the pair of elongated support arms 312 extends outwardly from
the elongated support post 302 and the other elongated support arm
312 extends outwardly from the elongated support post 304.
[0034] In the illustrative embodiments, each sled of the data
center 100 is embodied as a chassis-less sled. That is, each sled
has a chassis-less circuit board substrate on which physical
resources (e.g., processors, memory, accelerators, storage, etc.)
are mounted as discussed in more detail below. As such, the rack
240 is configured to receive the chassis-less sleds. For example,
each pair 310 of elongated support arms 312 defines a sled slot 320
of the rack 240, which is configured to receive a corresponding
chassis-less sled. To do so, each illustrative elongated support
arm 312 includes a circuit board guide 330 configured to receive
the chassis-less circuit board substrate of the sled. Each circuit
board guide 330 is secured to, or otherwise mounted to, a top side
332 of the corresponding elongated support arm 312. For example, in
the illustrative embodiment, each circuit board guide 330 is
mounted at a distal end of the corresponding elongated support arm
312 relative to the corresponding elongated support post 302, 304.
For clarity of the Figures, not every circuit board guide 330 may
be referenced in each Figure.
[0035] Each circuit board guide 330 includes an inner wall that
defines a circuit board slot 380 configured to receive the
chassis-less circuit board substrate of a sled 400 when the sled
400 is received in the corresponding sled slot 320 of the rack 240.
To do so, as shown in FIG. 4, a user (or robot) aligns the
chassis-less circuit board substrate of an illustrative
chassis-less sled 400 to a sled slot 320. The user, or robot, may
then slide the chassis-less circuit board substrate forward into
the sled slot 320 such that each side edge 414 of the chassis-less
circuit board substrate is received in a corresponding circuit
board slot 380 of the circuit board guides 330 of the pair 310 of
elongated support arms 312 that define the corresponding sled slot
320 as shown in FIG. 4. By having robotically accessible and
robotically manipulable sleds comprising disaggregated resources,
each type of resource can be upgraded independently of each other
and at their own optimized refresh rate. Furthermore, the sleds are
configured to blindly mate with power and data communication cables
in each rack 240, enhancing their ability to be quickly removed,
upgraded, reinstalled, and/or replaced. As such, in some
embodiments, the data center 100 may operate (e.g., execute
workloads, undergo maintenance and/or upgrades, etc.) without human
involvement on the data center floor. In other embodiments, a human
may facilitate one or more maintenance or upgrade operations in the
data center 100.
[0036] It should be appreciated that each circuit board guide 330
is dual sided. That is, each circuit board guide 330 includes an
inner wall that defines a circuit board slot 380 on each side of
the circuit board guide 330. In this way, each circuit board guide
330 can support a chassis-less circuit board substrate on either
side. As such, a single additional elongated support post may be
added to the rack 240 to turn the rack 240 into a two-rack solution
that can hold twice as many sled slots 320 as shown in FIG. 3. The
illustrative rack 240 includes seven pairs 310 of elongated support
arms 312 that define a corresponding seven sled slots 320, each
configured to receive and support a corresponding sled 400 as
discussed above. Of course, in other embodiments, the rack 240 may
include additional or fewer pairs 310 of elongated support arms 312
(i.e., additional or fewer sled slots 320). It should be
appreciated that because the sled 400 is chassis-less, the sled 400
may have an overall height that is different than typical servers.
As such, in some embodiments, the height of each sled slot 320 may
be shorter than the height of a typical server (e.g., shorter than
a single rank unit, "1 U"). That is, the vertical distance between
each pair 310 of elongated support arms 312 may be less than a
standard rack unit "1 U." Additionally, due to the relative
decrease in height of the sled slots 320, the overall height of the
rack 240 in some embodiments may be shorter than the height of
traditional rack enclosures. For example, in some embodiments, each
of the elongated support posts 302, 304 may have a length of six
feet or less. Again, in other embodiments, the rack 240 may have
different dimensions. Further, it should be appreciated that the
rack 240 does not include any walls, enclosures, or the like.
Rather, the rack 240 is an enclosure-less rack that is opened to
the local environment. Of course, in some cases, an end plate may
be attached to one of the elongated support posts 302, 304 in those
situations in which the rack 240 forms an end-of-row rack in the
data center 100.
[0037] In some embodiments, various interconnects may be routed
upwardly or downwardly through the elongated support posts 302,
304. To facilitate such routing, each elongated support post 302,
304 includes an inner wall that defines an inner chamber in which
the interconnect may be located. The interconnects routed through
the elongated support posts 302, 304 may be embodied as any type of
interconnects including, but not limited to, data or communication
interconnects to provide communication connections to each sled
slot 320, power interconnects to provide power to each sled slot
320, and/or other types of interconnects.
[0038] The rack 240, in the illustrative embodiment, includes a
support platform on which a corresponding optical data connector
(not shown) is mounted. Each optical data connector is associated
with a corresponding sled slot 320 and is configured to mate with
an optical data connector of a corresponding sled 400 when the sled
400 is received in the corresponding sled slot 320. In some
embodiments, optical connections between components (e.g., sleds,
racks, and switches) in the data center 100 are made with a blind
mate optical connection. For example, a door on each cable may
prevent dust from contaminating the fiber inside the cable. In the
process of connecting to a blind mate optical connector mechanism,
the door is pushed open when the end of the cable enters the
connector mechanism. Subsequently, the optical fiber inside the
cable enters a gel within the connector mechanism and the optical
fiber of one cable comes into contact with the optical fiber of
another cable within the gel inside the connector mechanism.
[0039] The illustrative rack 240 also includes a fan array 370
coupled to the cross-support arms of the rack 240. The fan array
370 includes one or more rows of cooling fans 372, which are
aligned in a horizontal line between the elongated support posts
302, 304. In the illustrative embodiment, the fan array 370
includes a row of cooling fans 372 for each sled slot 320 of the
rack 240. As discussed above, each sled 400 does not include any
on-board cooling system in the illustrative embodiment and, as
such, the fan array 370 provides cooling for each sled 400 received
in the rack 240. Each rack 240, in the illustrative embodiment,
also includes a power supply associated with each sled slot 320.
Each power supply is secured to one of the elongated support arms
312 of the pair 310 of elongated support arms 312 that define the
corresponding sled slot 320. For example, the rack 240 may include
a power supply coupled or secured to each elongated support arm 312
extending from the elongated support post 302. Each power supply
includes a power connector configured to mate with a power
connector of the sled 400 when the sled 400 is received in the
corresponding sled slot 320. In the illustrative embodiment, the
sled 400 does not include any on-board power supply and, as such,
the power supplies provided in the rack 240 supply power to
corresponding sleds 400 when mounted to the rack 240.
[0040] Referring now to FIG. 6, the sled 400, in the illustrative
embodiment, is configured to be mounted in a corresponding rack 240
of the data center 100 as discussed above. In some embodiments,
each sled 400 may be optimized or otherwise configured for
performing particular tasks, such as compute tasks, acceleration
tasks, data storage tasks, etc. For example, the sled 400 may be
embodied as a compute sled 800 as discussed below in regard to
FIGS. 8-9, an accelerator sled 1000 as discussed below in regard to
FIGS. 10-11, a storage sled 1200 as discussed below in regard to
FIGS. 12-13, or as a sled optimized or otherwise configured to
perform other specialized tasks, such as a memory sled 1400,
discussed below in regard to FIG. 14.
[0041] As discussed above, the illustrative sled 400 includes a
chassis-less circuit board substrate 602, which supports various
physical resources (e.g., electrical components) mounted thereon.
It should be appreciated that the circuit board substrate 602 is
"chassis-less" in that the sled 400 does not include a housing or
enclosure. Rather, the chassis-less circuit board substrate 602 is
open to the local environment. The chassis-less circuit board
substrate 602 may be formed from any material capable of supporting
the various electrical components mounted thereon. For example, in
an illustrative embodiment, the chassis-less circuit board
substrate 602 is formed from an FR-4 glass-reinforced epoxy
laminate material. Of course, other materials may be used to form
the chassis-less circuit board substrate 602 in other
embodiments.
[0042] As discussed in more detail below, the chassis-less circuit
board substrate 602 includes multiple features that improve the
thermal cooling characteristics of the various electrical
components mounted on the chassis-less circuit board substrate 602.
As discussed, the chassis-less circuit board substrate 602 does not
include a housing or enclosure, which may improve the airflow over
the electrical components of the sled 400 by reducing those
structures that may inhibit air flow. For example, because the
chassis-less circuit board substrate 602 is not positioned in an
individual housing or enclosure, there is no backplane (e.g., a
backplate of the chassis) to the chassis-less circuit board
substrate 602, which could inhibit air flow across the electrical
components. Additionally, the chassis-less circuit board substrate
602 has a geometric shape configured to reduce the length of the
airflow path across the electrical components mounted to the
chassis-less circuit board substrate 602. For example, the
illustrative chassis-less circuit board substrate 602 has a width
604 that is greater than a depth 606 of the chassis-less circuit
board substrate 602. In one particular embodiment, for example, the
chassis-less circuit board substrate 602 has a width of about 21
inches and a depth of about 9 inches, compared to a typical server
that has a width of about 17 inches and a depth of about 39 inches.
As such, an airflow path 608 that extends from a front edge 610 of
the chassis-less circuit board substrate 602 toward a rear edge 612
has a shorter distance relative to typical servers, which may
improve the thermal cooling characteristics of the sled 400.
Furthermore, although not illustrated in FIG. 6, the various
physical resources mounted to the chassis-less circuit board
substrate 602 are mounted in corresponding locations such that no
two substantively heat-producing electrical components shadow each
other as discussed in more detail below. That is, no two electrical
components, which produce appreciable heat during operation (i.e.,
greater than a nominal heat sufficient enough to adversely impact
the cooling of another electrical component), are mounted to the
chassis-less circuit board substrate 602 linearly in-line with each
other along the direction of the airflow path 608 (i.e., along a
direction extending from the front edge 610 toward the rear edge
612 of the chassis-less circuit board substrate 602).
[0043] As discussed above, the illustrative sled 400 includes one
or more physical resources 620 mounted to a top side 650 of the
chassis-less circuit board substrate 602. Although two physical
resources 620 are shown in FIG. 6, it should be appreciated that
the sled 400 may include one, two, or more physical resources 620
in other embodiments. The physical resources 620 may be embodied as
any type of processor, controller, or other compute circuit capable
of performing various tasks such as compute functions and/or
controlling the functions of the sled 400 depending on, for
example, the type or intended functionality of the sled 400. For
example, as discussed in more detail below, the physical resources
620 may be embodied as high-performance processors in embodiments
in which the sled 400 is embodied as a compute sled, as accelerator
co-processors or circuits in embodiments in which the sled 400 is
embodied as an accelerator sled, storage controllers in embodiments
in which the sled 400 is embodied as a storage sled, or a set of
memory devices in embodiments in which the sled 400 is embodied as
a memory sled.
[0044] The sled 400 also includes one or more additional physical
resources 630 mounted to the top side 650 of the chassis-less
circuit board substrate 602. In the illustrative embodiment, the
additional physical resources include a network interface
controller (NIC) as discussed in more detail below. Of course,
depending on the type and functionality of the sled 400, the
physical resources 630 may include additional or other electrical
components, circuits, and/or devices in other embodiments.
[0045] The physical resources 620 are communicatively coupled to
the physical resources 630 via an input/output (I/O) subsystem 622.
The I/O subsystem 622 may be embodied as circuitry and/or
components to facilitate input/output operations with the physical
resources 620, the physical resources 630, and/or other components
of the sled 400. For example, the I/O subsystem 622 may be embodied
as, or otherwise include, memory controller hubs, input/output
control hubs, integrated sensor hubs, firmware devices,
communication links (e.g., point-to-point links, bus links, wires,
cables, light guides, printed circuit board traces, etc.), and/or
other components and subsystems to facilitate the input/output
operations. In the illustrative embodiment, the I/O subsystem 622
is embodied as, or otherwise includes, a double data rate 4 (DDR4)
data bus or a DDR5 data bus.
[0046] In some embodiments, the sled 400 may also include a
resource-to-resource interconnect 624. The resource-to-resource
interconnect 624 may be embodied as any type of communication
interconnect capable of facilitating resource-to-resource
communications. In the illustrative embodiment, the
resource-to-resource interconnect 624 is embodied as a high-speed
point-to-point interconnect (e.g., faster than the I/O subsystem
622). For example, the resource-to-resource interconnect 624 may be
embodied as a QuickPath Interconnect (QPI), an UltraPath
Interconnect (UPI), or other high-speed point-to-point interconnect
dedicated to resource-to-resource communications.
[0047] The sled 400 also includes a power connector 640 configured
to mate with a corresponding power connector of the rack 240 when
the sled 400 is mounted in the corresponding rack 240. The sled 400
receives power from a power supply of the rack 240 via the power
connector 640 to supply power to the various electrical components
of the sled 400. That is, the sled 400 does not include any local
power supply (i.e., an on-board power supply) to provide power to
the electrical components of the sled 400. The exclusion of a local
or on-board power supply facilitates the reduction in the overall
footprint of the chassis-less circuit board substrate 602, which
may increase the thermal cooling characteristics of the various
electrical components mounted on the chassis-less circuit board
substrate 602 as discussed above. In some embodiments, power is
provided to the processors 820 through vias directly under the
processors 820 (e.g., through the bottom side 750 of the
chassis-less circuit board substrate 602), providing an increased
thermal budget, additional current and/or voltage, and better
voltage control over typical boards.
[0048] In some embodiments, the sled 400 may also include mounting
features 642 configured to mate with a mounting arm, or other
structure, of a robot to facilitate the placement of the sled 600
in a rack 240 by the robot. The mounting features 642 may be
embodied as any type of physical structures that allow the robot to
grasp the sled 400 without damaging the chassis-less circuit board
substrate 602 or the electrical components mounted thereto. For
example, in some embodiments, the mounting features 642 may be
embodied as non-conductive pads attached to the chassis-less
circuit board substrate 602. In other embodiments, the mounting
features may be embodied as brackets, braces, or other similar
structures attached to the chassis-less circuit board substrate
602. The particular number, shape, size, and/or make-up of the
mounting feature 642 may depend on the design of the robot
configured to manage the sled 400.
[0049] Referring now to FIG. 7, in addition to the physical
resources 630 mounted on the top side 650 of the chassis-less
circuit board substrate 602, the sled 400 also includes one or more
memory devices 720 mounted to a bottom side 750 of the chassis-less
circuit board substrate 602. That is, the chassis-less circuit
board substrate 602 is embodied as a double-sided circuit board.
The physical resources 620 are communicatively coupled to the
memory devices 720 via the I/O subsystem 622. For example, the
physical resources 620 and the memory devices 720 may be
communicatively coupled by one or more vias extending through the
chassis-less circuit board substrate 602. Each physical resource
620 may be communicatively coupled to a different set of one or
more memory devices 720 in some embodiments. Alternatively, in
other embodiments, each physical resource 620 may be
communicatively coupled to each memory devices 720.
[0050] The memory devices 720 may be embodied as any type of memory
device capable of storing data for the physical resources 620
during operation of the sled 400, such as any type of volatile
(e.g., dynamic random access memory (DRAM), etc.) or non-volatile
memory. Volatile memory may be a storage medium that requires power
to maintain the state of data stored by the medium. Non-limiting
examples of volatile memory may include various types of random
access memory (RAM), such as dynamic random access memory (DRAM) or
static random access memory (SRAM). One particular type of DRAM
that may be used in a memory module is synchronous dynamic random
access memory (SDRAM). In particular embodiments, DRAM of a memory
component may comply with a standard promulgated by JEDEC, such as
JESD79F for DDR SDRAM, JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3
SDRAM, JESD79-4A for DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR),
JESD209-2 for LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for
LPDDR4 (these standards are available at www.jedec.org). Such
standards (and similar standards) may be referred to as DDR-based
standards and communication interfaces of the storage devices that
implement such standards may be referred to as DDR-based
interfaces.
[0051] In one embodiment, the memory device is a block addressable
memory device, such as those based on NAND or NOR technologies. A
memory device may also include next-generation nonvolatile devices,
such as Intel 3D XPoint.TM. memory or other byte addressable
write-in-place nonvolatile memory devices. In one embodiment, the
memory device may be or may include memory devices that use
chalcogenide glass, multi-threshold level NAND flash memory, NOR
flash memory, single or multi-level Phase Change Memory (PCM), a
resistive memory, nanowire memory, ferroelectric transistor random
access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive
random access memory (MRAM) memory that incorporates memristor
technology, resistive memory including the metal oxide base, the
oxygen vacancy base and the conductive bridge Random Access Memory
(CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic
junction memory based device, a magnetic tunneling junction (MTJ)
based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer)
based device, a thyristor based memory device, or a combination of
any of the above, or other memory. The memory device may refer to
the die itself and/or to a packaged memory product. In some
embodiments, the memory device may comprise a transistor-less
stackable cross point architecture in which memory cells sit at the
intersection of word lines and bit lines and are individually
addressable and in which bit storage is based on a change in bulk
resistance.
[0052] Referring now to FIG. 8, in some embodiments, the sled 400
may be embodied as a compute sled 800. The compute sled 800 is
optimized, or otherwise configured, to perform compute tasks. Of
course, as discussed above, the compute sled 800 may rely on other
sleds, such as acceleration sleds and/or storage sleds, to perform
such compute tasks. The compute sled 800 includes various physical
resources (e.g., electrical components) similar to the physical
resources of the sled 400, which have been identified in FIG. 8
using the same reference numbers. The description of such
components provided above in regard to FIGS. 6 and 7 applies to the
corresponding components of the compute sled 800 and is not
repeated herein for clarity of the description of the compute sled
800.
[0053] In the illustrative compute sled 800, the physical resources
620 are embodied as processors 820. Although only two processors
820 are shown in FIG. 8, it should be appreciated that the compute
sled 800 may include additional processors 820 in other
embodiments. Illustratively, the processors 820 are embodied as
high-performance processors 820 and may be configured to operate at
a relatively high power rating. Although the processors 820
generate additional heat operating at power ratings greater than
typical processors (which operate at around 155-230 W), the
enhanced thermal cooling characteristics of the chassis-less
circuit board substrate 602 discussed above facilitate the higher
power operation. For example, in the illustrative embodiment, the
processors 820 are configured to operate at a power rating of at
least 250 W. In some embodiments, the processors 820 may be
configured to operate at a power rating of at least 350 W.
[0054] In some embodiments, the compute sled 800 may also include a
processor-to-processor interconnect 842. Similar to the
resource-to-resource interconnect 624 of the sled 400 discussed
above, the processor-to-processor interconnect 842 may be embodied
as any type of communication interconnect capable of facilitating
processor-to-processor interconnect 842 communications. In the
illustrative embodiment, the processor-to-processor interconnect
842 is embodied as a high-speed point-to-point interconnect (e.g.,
faster than the I/O subsystem 622). For example, the
processor-to-processor interconnect 842 may be embodied as a
QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or
other high-speed point-to-point interconnect dedicated to
processor-to-processor communications.
[0055] The compute sled 800 also includes a communication circuit
830. The illustrative communication circuit 830 includes a network
interface controller (NIC) 832, which may also be referred to as a
host fabric interface (HFI). The NIC 832 may be embodied as, or
otherwise include, any type of integrated circuit, discrete
circuits, controller chips, chipsets, add-in-boards, daughtercards,
network interface cards, other devices that may be used by the
compute sled 800 to connect with another compute device (e.g., with
other sleds 400). In some embodiments, the NIC 832 may be embodied
as part of a system-on-a-chip (SoC) that includes one or more
processors, or included on a multichip package that also contains
one or more processors. In some embodiments, the NIC 832 may
include a local processor (not shown) and/or a local memory (not
shown) that are both local to the NIC 832. In such embodiments, the
local processor of the NIC 832 may be capable of performing one or
more of the functions of the processors 820. Additionally or
alternatively, in such embodiments, the local memory of the NIC 832
may be integrated into one or more components of the compute sled
at the board level, socket level, chip level, and/or other
levels.
[0056] The communication circuit 830 is communicatively coupled to
an optical data connector 834. The optical data connector 834 is
configured to mate with a corresponding optical data connector of
the rack 240 when the compute sled 800 is mounted in the rack 240.
Illustratively, the optical data connector 834 includes a plurality
of optical fibers which lead from a mating surface of the optical
data connector 834 to an optical transceiver 836. The optical
transceiver 836 is configured to convert incoming optical signals
from the rack-side optical data connector to electrical signals and
to convert electrical signals to outgoing optical signals to the
rack-side optical data connector. Although shown as forming part of
the optical data connector 834 in the illustrative embodiment, the
optical transceiver 836 may form a portion of the communication
circuit 830 in other embodiments.
[0057] In some embodiments, the compute sled 800 may also include
an expansion connector 840. In such embodiments, the expansion
connector 840 is configured to mate with a corresponding connector
of an expansion chassis-less circuit board substrate to provide
additional physical resources to the compute sled 800. The
additional physical resources may be used, for example, by the
processors 820 during operation of the compute sled 800. The
expansion chassis-less circuit board substrate may be substantially
similar to the chassis-less circuit board substrate 602 discussed
above and may include various electrical components mounted
thereto. The particular electrical components mounted to the
expansion chassis-less circuit board substrate may depend on the
intended functionality of the expansion chassis-less circuit board
substrate. For example, the expansion chassis-less circuit board
substrate may provide additional compute resources, memory
resources, and/or storage resources. As such, the additional
physical resources of the expansion chassis-less circuit board
substrate may include, but is not limited to, processors, memory
devices, storage devices, and/or accelerator circuits including,
for example, field programmable gate arrays (FPGA),
application-specific integrated circuits (ASICs), security
co-processors, graphics processing units (GPUs), machine learning
circuits, or other specialized processors, controllers, devices,
and/or circuits.
[0058] Referring now to FIG. 9, an illustrative embodiment of the
compute sled 800 is shown. As shown, the processors 820,
communication circuit 830, and optical data connector 834 are
mounted to the top side 650 of the chassis-less circuit board
substrate 602. Any suitable attachment or mounting technology may
be used to mount the physical resources of the compute sled 800 to
the chassis-less circuit board substrate 602. For example, the
various physical resources may be mounted in corresponding sockets
(e.g., a processor socket), holders, or brackets. In some cases,
some of the electrical components may be directly mounted to the
chassis-less circuit board substrate 602 via soldering or similar
techniques.
[0059] As discussed above, the individual processors 820 and
communication circuit 830 are mounted to the top side 650 of the
chassis-less circuit board substrate 602 such that no two
heat-producing, electrical components shadow each other. In the
illustrative embodiment, the processors 820 and communication
circuit 830 are mounted in corresponding locations on the top side
650 of the chassis-less circuit board substrate 602 such that no
two of those physical resources are linearly in-line with others
along the direction of the airflow path 608. It should be
appreciated that, although the optical data connector 834 is
in-line with the communication circuit 830, the optical data
connector 834 produces no or nominal heat during operation.
[0060] The memory devices 720 of the compute sled 800 are mounted
to the bottom side 750 of the of the chassis-less circuit board
substrate 602 as discussed above in regard to the sled 400.
Although mounted to the bottom side 750, the memory devices 720 are
communicatively coupled to the processors 820 located on the top
side 650 via the I/O subsystem 622. Because the chassis-less
circuit board substrate 602 is embodied as a double-sided circuit
board, the memory devices 720 and the processors 820 may be
communicatively coupled by one or more vias, connectors, or other
mechanisms extending through the chassis-less circuit board
substrate 602. Of course, each processor 820 may be communicatively
coupled to a different set of one or more memory devices 720 in
some embodiments. Alternatively, in other embodiments, each
processor 820 may be communicatively coupled to each memory device
720. In some embodiments, the memory devices 720 may be mounted to
one or more memory mezzanines on the bottom side of the
chassis-less circuit board substrate 602 and may interconnect with
a corresponding processor 820 through a ball-grid array.
[0061] Each of the processors 820 includes a heatsink 850 secured
thereto. Due to the mounting of the memory devices 720 to the
bottom side 750 of the chassis-less circuit board substrate 602 (as
well as the vertical spacing of the sleds 400 in the corresponding
rack 240), the top side 650 of the chassis-less circuit board
substrate 602 includes additional "free" area or space that
facilitates the use of heatsinks 850 having a larger size relative
to traditional heatsinks used in typical servers. Additionally, due
to the improved thermal cooling characteristics of the chassis-less
circuit board substrate 602, none of the processor heatsinks 850
include cooling fans attached thereto. That is, each of the
heatsinks 850 is embodied as a fan-less heatsinks.
[0062] Referring now to FIG. 10, in some embodiments, the sled 400
may be embodied as an accelerator sled 1000. The accelerator sled
1000 is optimized, or otherwise configured, to perform specialized
compute tasks, such as machine learning, encryption, hashing, or
other computational-intensive task. In some embodiments, for
example, a compute sled 800 may offload tasks to the accelerator
sled 1000 during operation. The accelerator sled 1000 includes
various components similar to components of the sled 400 and/or
compute sled 800, which have been identified in FIG. 10 using the
same reference numbers. The description of such components provided
above in regard to FIGS. 6, 7, and 8 apply to the corresponding
components of the accelerator sled 1000 and is not repeated herein
for clarity of the description of the accelerator sled 1000.
[0063] In the illustrative accelerator sled 1000, the physical
resources 620 are embodied as accelerator circuits 1020. Although
only two accelerator circuits 1020 are shown in FIG. 10, it should
be appreciated that the accelerator sled 1000 may include
additional accelerator circuits 1020 in other embodiments. For
example, as shown in FIG. 11, the accelerator sled 1000 may include
four accelerator circuits 1020 in some embodiments. The accelerator
circuits 1020 may be embodied as any type of processor,
co-processor, compute circuit, or other device capable of
performing compute or processing operations. For example, the
accelerator circuits 1020 may be embodied as, for example, field
programmable gate arrays (FPGA), application-specific integrated
circuits (ASICs), security co-processors, graphics processing units
(GPUs), machine learning circuits, or other specialized processors,
controllers, devices, and/or circuits.
[0064] In some embodiments, the accelerator sled 1000 may also
include an accelerator-to-accelerator interconnect 1042. Similar to
the resource-to-resource interconnect 624 of the sled 600 discussed
above, the accelerator-to-accelerator interconnect 1042 may be
embodied as any type of communication interconnect capable of
facilitating accelerator-to-accelerator communications. In the
illustrative embodiment, the accelerator-to-accelerator
interconnect 1042 is embodied as a high-speed point-to-point
interconnect (e.g., faster than the I/O subsystem 622). For
example, the accelerator-to-accelerator interconnect 1042 may be
embodied as a QuickPath Interconnect (QPI), an UltraPath
Interconnect (UPI), or other high-speed point-to-point interconnect
dedicated to processor-to-processor communications. In some
embodiments, the accelerator circuits 1020 may be daisy-chained
with a primary accelerator circuit 1020 connected to the NIC 832
and memory 720 through the I/O subsystem 622 and a secondary
accelerator circuit 1020 connected to the NIC 832 and memory 720
through a primary accelerator circuit 1020.
[0065] Referring now to FIG. 11, an illustrative embodiment of the
accelerator sled 1000 is shown. As discussed above, the accelerator
circuits 1020, communication circuit 830, and optical data
connector 834 are mounted to the top side 650 of the chassis-less
circuit board substrate 602. Again, the individual accelerator
circuits 1020 and communication circuit 830 are mounted to the top
side 650 of the chassis-less circuit board substrate 602 such that
no two heat-producing, electrical components shadow each other as
discussed above. The memory devices 720 of the accelerator sled
1000 are mounted to the bottom side 750 of the of the chassis-less
circuit board substrate 602 as discussed above in regard to the
sled 600. Although mounted to the bottom side 750, the memory
devices 720 are communicatively coupled to the accelerator circuits
1020 located on the top side 650 via the I/O subsystem 622 (e.g.,
through vias). Further, each of the accelerator circuits 1020 may
include a heatsink 1070 that is larger than a traditional heatsink
used in a server. As discussed above with reference to the
heatsinks 870, the heatsinks 1070 may be larger than tradition
heatsinks because of the "free" area provided by the memory devices
750 being located on the bottom side 750 of the chassis-less
circuit board substrate 602 rather than on the top side 650.
[0066] Referring now to FIG. 12, in some embodiments, the sled 400
may be embodied as a storage sled 1200. The storage sled 1200 is
optimized, or otherwise configured, to store data in a data storage
1250 local to the storage sled 1200. For example, during operation,
a compute sled 800 or an accelerator sled 1000 may store and
retrieve data from the data storage 1250 of the storage sled 1200.
The storage sled 1200 includes various components similar to
components of the sled 400 and/or the compute sled 800, which have
been identified in FIG. 12 using the same reference numbers. The
description of such components provided above in regard to FIGS. 6,
7, and 8 apply to the corresponding components of the storage sled
1200 and is not repeated herein for clarity of the description of
the storage sled 1200.
[0067] In the illustrative storage sled 1200, the physical
resources 620 are embodied as storage controllers 1220. Although
only two storage controllers 1220 are shown in FIG. 12, it should
be appreciated that the storage sled 1200 may include additional
storage controllers 1220 in other embodiments. The storage
controllers 1220 may be embodied as any type of processor,
controller, or control circuit capable of controlling the storage
and retrieval of data into the data storage 1250 based on requests
received via the communication circuit 830. In the illustrative
embodiment, the storage controllers 1220 are embodied as relatively
low-power processors or controllers. For example, in some
embodiments, the storage controllers 1220 may be configured to
operate at a power rating of about 75 watts.
[0068] In some embodiments, the storage sled 1200 may also include
a controller-to-controller interconnect 1242. Similar to the
resource-to-resource interconnect 624 of the sled 400 discussed
above, the controller-to-controller interconnect 1242 may be
embodied as any type of communication interconnect capable of
facilitating controller-to-controller communications. In the
illustrative embodiment, the controller-to-controller interconnect
1242 is embodied as a high-speed point-to-point interconnect (e.g.,
faster than the I/O subsystem 622). For example, the
controller-to-controller interconnect 1242 may be embodied as a
QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or
other high-speed point-to-point interconnect dedicated to
processor-to-processor communications.
[0069] Referring now to FIG. 13, an illustrative embodiment of the
storage sled 1200 is shown. In the illustrative embodiment, the
data storage 1250 is embodied as, or otherwise includes, a storage
cage 1252 configured to house one or more solid state drives (SSDs)
1254. To do so, the storage cage 1252 includes a number of mounting
slots 1256, each of which is configured to receive a corresponding
solid state drive 1254. Each of the mounting slots 1256 includes a
number of drive guides 1258 that cooperate to define an access
opening 1260 of the corresponding mounting slot 1256. The storage
cage 1252 is secured to the chassis-less circuit board substrate
602 such that the access openings face away from (i.e., toward the
front of) the chassis-less circuit board substrate 602. As such,
solid state drives 1254 are accessible while the storage sled 1200
is mounted in a corresponding rack 204. For example, a solid state
drive 1254 may be swapped out of a rack 240 (e.g., via a robot)
while the storage sled 1200 remains mounted in the corresponding
rack 240.
[0070] The storage cage 1252 illustratively includes sixteen
mounting slots 1256 and is capable of mounting and storing sixteen
solid state drives 1254. Of course, the storage cage 1252 may be
configured to store additional or fewer solid state drives 1254 in
other embodiments. Additionally, in the illustrative embodiment,
the solid state drivers are mounted vertically in the storage cage
1252, but may be mounted in the storage cage 1252 in a different
orientation in other embodiments. Each solid state drive 1254 may
be embodied as any type of data storage device capable of storing
long term data. To do so, the solid state drives 1254 may include
volatile and non-volatile memory devices discussed above.
[0071] As shown in FIG. 13, the storage controllers 1220, the
communication circuit 830, and the optical data connector 834 are
illustratively mounted to the top side 650 of the chassis-less
circuit board substrate 602. Again, as discussed above, any
suitable attachment or mounting technology may be used to mount the
electrical components of the storage sled 1200 to the chassis-less
circuit board substrate 602 including, for example, sockets (e.g.,
a processor socket), holders, brackets, soldered connections,
and/or other mounting or securing techniques.
[0072] As discussed above, the individual storage controllers 1220
and the communication circuit 830 are mounted to the top side 650
of the chassis-less circuit board substrate 602 such that no two
heat-producing, electrical components shadow each other. For
example, the storage controllers 1220 and the communication circuit
830 are mounted in corresponding locations on the top side 650 of
the chassis-less circuit board substrate 602 such that no two of
those electrical components are linearly in-line with other along
the direction of the airflow path 608.
[0073] The memory devices 720 of the storage sled 1200 are mounted
to the bottom side 750 of the of the chassis-less circuit board
substrate 602 as discussed above in regard to the sled 400.
Although mounted to the bottom side 750, the memory devices 720 are
communicatively coupled to the storage controllers 1220 located on
the top side 650 via the I/O subsystem 622. Again, because the
chassis-less circuit board substrate 602 is embodied as a
double-sided circuit board, the memory devices 720 and the storage
controllers 1220 may be communicatively coupled by one or more
vias, connectors, or other mechanisms extending through the
chassis-less circuit board substrate 602. Each of the storage
controllers 1220 includes a heatsink 1270 secured thereto. As
discussed above, due to the improved thermal cooling
characteristics of the chassis-less circuit board substrate 602 of
the storage sled 1200, none of the heatsinks 1270 include cooling
fans attached thereto. That is, each of the heatsinks 1270 is
embodied as a fan-less heatsink.
[0074] Referring now to FIG. 14, in some embodiments, the sled 400
may be embodied as a memory sled 1400. The storage sled 1400 is
optimized, or otherwise configured, to provide other sleds 400
(e.g., compute sleds 800, accelerator sleds 1000, etc.) with access
to a pool of memory (e.g., in two or more sets 1430, 1432 of memory
devices 720) local to the memory sled 1200. For example, during
operation, a compute sled 800 or an accelerator sled 1000 may
remotely write to and/or read from one or more of the memory sets
1430, 1432 of the memory sled 1200 using a logical address space
that maps to physical addresses in the memory sets 1430, 1432. The
memory sled 1400 includes various components similar to components
of the sled 400 and/or the compute sled 800, which have been
identified in FIG. 14 using the same reference numbers. The
description of such components provided above in regard to FIGS. 6,
7, and 8 apply to the corresponding components of the memory sled
1400 and is not repeated herein for clarity of the description of
the memory sled 1400.
[0075] In the illustrative memory sled 1400, the physical resources
620 are embodied as memory controllers 1420. Although only two
memory controllers 1420 are shown in FIG. 14, it should be
appreciated that the memory sled 1400 may include additional memory
controllers 1420 in other embodiments. The memory controllers 1420
may be embodied as any type of processor, controller, or control
circuit capable of controlling the writing and reading of data into
the memory sets 1430, 1432 based on requests received via the
communication circuit 830. In the illustrative embodiment, each
storage controller 1220 is connected to a corresponding memory set
1430, 1432 to write to and read from memory devices 720 within the
corresponding memory set 1430, 1432 and enforce any permissions
(e.g., read, write, etc.) associated with sled 400 that has sent a
request to the memory sled 1400 to perform a memory access
operation (e.g., read or write).
[0076] In some embodiments, the memory sled 1400 may also include a
controller-to-controller interconnect 1442. Similar to the
resource-to-resource interconnect 624 of the sled 400 discussed
above, the controller-to-controller interconnect 1442 may be
embodied as any type of communication interconnect capable of
facilitating controller-to-controller communications. In the
illustrative embodiment, the controller-to-controller interconnect
1442 is embodied as a high-speed point-to-point interconnect (e.g.,
faster than the I/O subsystem 622). For example, the
controller-to-controller interconnect 1442 may be embodied as a
QuickPath Interconnect (QPI), an UltraPath Interconnect (UPI), or
other high-speed point-to-point interconnect dedicated to
processor-to-processor communications. As such, in some
embodiments, a memory controller 1420 may access, through the
controller-to-controller interconnect 1442, memory that is within
the memory set 1432 associated with another memory controller 1420.
In some embodiments, a scalable memory controller is made of
multiple smaller memory controllers, referred to herein as
"chiplets", on a memory sled (e.g., the memory sled 1400). The
chiplets may be interconnected (e.g., using EMIB (Embedded
Multi-Die Interconnect Bridge)). The combined chiplet memory
controller may scale up to a relatively large number of memory
controllers and I/O ports, (e.g., up to 16 memory channels). In
some embodiments, the memory controllers 1420 may implement a
memory interleave (e.g., one memory address is mapped to the memory
set 1430, the next memory address is mapped to the memory set 1432,
and the third address is mapped to the memory set 1430, etc.). The
interleaving may be managed within the memory controllers 1420, or
from CPU sockets (e.g., of the compute sled 800) across network
links to the memory sets 1430, 1432, and may improve the latency
associated with performing memory access operations as compared to
accessing contiguous memory addresses from the same memory
device.
[0077] Further, in some embodiments, the memory sled 1400 may be
connected to one or more other sleds 400 (e.g., in the same rack
240 or an adjacent rack 240) through a waveguide, using the
waveguide connector 1480. In the illustrative embodiment, the
waveguides are 64 millimeter waveguides that provide 16 Rx (i.e.,
receive) lanes and 16 Rt (i.e., transmit) lanes. Each lane, in the
illustrative embodiment, is either 16 Ghz or 32 Ghz. In other
embodiments, the frequencies may be different. Using a waveguide
may provide high throughput access to the memory pool (e.g., the
memory sets 1430, 1432) to another sled (e.g., a sled 400 in the
same rack 240 or an adjacent rack 240 as the memory sled 1400)
without adding to the load on the optical data connector 834.
[0078] Referring now to FIG. 15, a system for executing one or more
workloads (e.g., applications) may be implemented in accordance
with the data center 100. In the illustrative embodiment, the
system 1510 includes an orchestrator server 1520, which may be
embodied as a managed node comprising a compute device (e.g., a
compute sled 800) executing management software (e.g., a cloud
operating environment, such as OpenStack) that is communicatively
coupled to multiple sleds 400 including a large number of compute
sleds 1530 (e.g., each similar to the compute sled 800), memory
sleds 1540 (e.g., each similar to the memory sled 1400),
accelerator sleds 1550 (e.g., each similar to the memory sled
1000), and storage sleds 1560 (e.g., each similar to the storage
sled 1200). One or more of the sleds 1530, 1540, 1550, 1560 may be
grouped into a managed node 1570, such as by the orchestrator
server 1520, to collectively perform a workload (e.g., an
application 1532 executed in a virtual machine or in a container).
The managed node 1570 may be embodied as an assembly of physical
resources 620, such as processors 820, memory resources 720,
accelerator circuits 1020, or data storage 1250, from the same or
different sleds 400. Further, the managed node may be established,
defined, or "spun up" by the orchestrator server 1520 at the time a
workload is to be assigned to the managed node or at any other
time, and may exist regardless of whether any workloads are
presently assigned to the managed node. In the illustrative
embodiment, the orchestrator server 1520 may selectively allocate
and/or deallocate physical resources 620 from the sleds 400 and/or
add or remove one or more sleds 400 from the managed node 1570 as a
function of quality of service (QoS) targets (e.g., performance
targets associated with a throughput, latency, instructions per
second, etc.) associated with a service level agreement for the
workload (e.g., the application 1532). In doing so, the
orchestrator server 1520 may receive telemetry data indicative of
performance conditions (e.g., throughput, latency, instructions per
second, etc.) in each sled 400 of the managed node 1570 and compare
the telemetry data to the quality of service targets to determine
whether the quality of service targets are being satisfied. If the
so, the orchestrator server 1520 may additionally determine whether
one or more physical resources may be deallocated from the managed
node 1570 while still satisfying the QoS targets, thereby freeing
up those physical resources for use in another managed node (e.g.,
to execute a different workload). Alternatively, if the QoS targets
are not presently satisfied, the orchestrator server 1520 may
determine to dynamically allocate additional physical resources to
assist in the execution of the workload (e.g., the application
1532) while the workload is executing
[0079] Additionally, in some embodiments, the orchestrator server
1520 may identify trends in the resource utilization of the
workload (e.g., the application 1532), such as by identifying
phases of execution (e.g., time periods in which different
operations, each having different resource utilizations
characteristics, are performed) of the workload (e.g., the
application 1532) and pre-emptively identifying available resources
in the data center 100 and allocating them to the managed node 1570
(e.g., within a predefined time period of the associated phase
beginning). In some embodiments, the orchestrator server 1520 may
model performance based on various latencies and a distribution
scheme to place workloads among compute sleds and other resources
(e.g., accelerator sleds, memory sleds, storage sleds) in the data
center 100. For example, the orchestrator server 1520 may utilize a
model that accounts for the performance of resources on the sleds
400 (e.g., FPGA performance, memory access latency, etc.) and the
performance (e.g., congestion, latency, bandwidth) of the path
through the network to the resource (e.g., FPGA). As such, the
orchestrator server 1520 may determine which resource(s) should be
used with which workloads based on the total latency associated
with each potential resource available in the data center 100
(e.g., the latency associated with the performance of the resource
itself in addition to the latency associated with the path through
the network between the compute sled executing the workload and the
sled 400 on which the resource is located).
[0080] In some embodiments, the orchestrator server 1520 may
generate a map of heat generation in the data center 100 using
telemetry data (e.g., temperatures, fan speeds, etc.) reported from
the sleds 400 and allocate resources to managed nodes as a function
of the map of heat generation and predicted heat generation
associated with different workloads, to maintain a target
temperature and heat distribution in the data center 100.
Additionally or alternatively, in some embodiments, the
orchestrator server 1520 may organize received telemetry data into
a hierarchical model that is indicative of a relationship between
the managed nodes (e.g., a spatial relationship such as the
physical locations of the resources of the managed nodes within the
data center 100 and/or a functional relationship, such as groupings
of the managed nodes by the customers the managed nodes provide
services for, the types of functions typically performed by the
managed nodes, managed nodes that typically share or exchange
workloads among each other, etc.). Based on differences in the
physical locations and resources in the managed nodes, a given
workload may exhibit different resource utilizations (e.g., cause a
different internal temperature, use a different percentage of
processor or memory capacity) across the resources of different
managed nodes. The orchestrator server 1520 may determine the
differences based on the telemetry data stored in the hierarchical
model and factor the differences into a prediction of future
resource utilization of a workload if the workload is reassigned
from one managed node to another managed node, to accurately
balance resource utilization in the data center 100.
[0081] To reduce the computational load on the orchestrator server
1520 and the data transfer load on the network, in some
embodiments, the orchestrator server 1520 may send self-test
information to the sleds 400 to enable each sled 400 to locally
(e.g., on the sled 400) determine whether telemetry data generated
by the sled 400 satisfies one or more conditions (e.g., an
available capacity that satisfies a predefined threshold, a
temperature that satisfies a predefined threshold, etc.). Each sled
400 may then report back a simplified result (e.g., yes or no) to
the orchestrator server 1520, which the orchestrator server 1520
may utilize in determining the allocation of resources to managed
nodes.
[0082] Referring now to FIG. 16, a system 1600 for migrating
virtual machines may be implemented in accordance with the data
center 100 described above with reference to FIG. 1. The
illustrative system 1600 includes a resource manager server 1606
communicatively coupled to multiple compute sleds 1602 and a memory
sled 1608 via a network switch 1604. The resource manager server
1606 is configured to manage resources of the system 1600 to
perform various workload operations. The resource manager server
1606 is additionally configured to manage virtual machines (VMs) to
execute a workload (e.g., an application) using the allocated
resources. In some embodiments, one or more containers may be used
in conjunction with or independent of a virtual machine (VM)
instance.
[0083] In use, the resource manager server 1606 receives an
indication or otherwise identifies that a VM instance (e.g., the
virtual machine 1616) presently being executed on one compute sled
1602 (e.g., compute sled (1) 1602a) is to be migrated to another
compute sled 1602 (e.g., compute sled (2) 1602b). Accordingly, as
will be described in further detail below, the resource manager
server 1606 manages the migration. However, unlike present
technologies in which the VM instance 1616 and all associated data
would be required to be migrated from the initial compute sled
1602a to the other compute sled 1602b, a previously allocated
region of memory in a memory pool (e.g., the memory 1612 of the
memory pool 1614) which was associated with (i.e., mapped to) the
initial compute sled 1602a is re-mapped to be associated with the
other compute sled 1602b. As such, the data stored in the memory
pool 1614 does not need to be transferred across the network fabric
at any point in the migration of the VM, thereby eliminating the
bandwidth consumption associated with the network traffic which
would have otherwise been required to copy the data across the
network fabric.
[0084] The resource manager server 1606 may be embodied as any type
of computing device capable of monitoring and managing resources of
the compute sleds 1602, as well as performing the other functions
described herein. For example, the resource manager server 1606 may
be embodied as a computer, a distributed computing system, one or
more sleds, a server (e.g., stand-alone, rack-mounted, blade,
etc.), a multiprocessor system, a network appliance (e.g., physical
or virtual), a desktop computer, a workstation, a laptop computer,
a notebook computer, a processor-based system, or a network
appliance. As shown in FIG. 17, the illustrative resource manager
server 1606 includes a compute engine 1702, an input/output (I/O)
subsystem 1708, one or more data storage devices 1710,
communication circuitry 1712, and one or more peripheral devices
1716. It should be appreciated that the resource manager server
1606 may include other or additional components, such as those
commonly found in a typical computing device (e.g., various
input/output devices and/or other components), in other
embodiments. Additionally, in some embodiments, one or more of the
illustrative components may be incorporated in, or otherwise form a
portion of, another component.
[0085] The compute engine 1702 may be embodied as any type of
device or collection of devices capable of performing the various
compute functions as described herein. In some embodiments, the
compute engine 1702 may be embodied as a single device such as an
integrated circuit, an embedded system, a field-programmable-array
(FPGA), a system-on-a-chip (SOC), an application specific
integrated circuit (ASIC), reconfigurable hardware or hardware
circuitry, or other specialized hardware to facilitate performance
of the functions described herein. Additionally, in some
embodiments, the compute engine 1702 may include, or may be
embodied as, a processor 1704 (i.e., a central processing unit
(CPU)) and memory 1706.
[0086] The processor 1704 may be embodied as any type of processor
capable of performing the functions described herein. For example,
the processor 1704 may be embodied as a single or multi-core
processor(s), digital signal processor, microcontroller, or other
processor or processing/controlling circuit. In some embodiments,
the processor 1704 may be embodied as, include, or otherwise be
coupled to a field programmable gate array (FPGA), an application
specific integrated circuit (ASIC), reconfigurable hardware or
hardware circuitry, or other specialized hardware to facilitate
performance of the functions described herein.
[0087] The memory 1706 may be embodied as any type of volatile
(e.g., dynamic random access memory (DRAM), etc.) or non-volatile
memory or data storage capable of performing the functions
described herein. It should be appreciated that the memory 1706 may
include main memory (i.e., a primary memory) and/or cache memory
(i.e., memory that can be accessed more quickly than the main
memory). Volatile memory may be a storage medium that requires
power to maintain the state of data stored by the medium.
Non-limiting examples of volatile memory may include various types
of random access memory (RAM), such as dynamic random access memory
(DRAM) or static random access memory (SRAM).
[0088] One particular type of DRAM that may be used in a memory
module is synchronous dynamic random access memory (SDRAM). In
particular embodiments, DRAM of a memory component may comply with
a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM,
JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for
DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for
LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these
standards are available at www.jedec.org). Such standards (and
similar standards) may be referred to as DDR-based standards and
communication interfaces of the storage devices that implement such
standards may be referred to as DDR-based interfaces.
[0089] In one embodiment, the memory device is a block addressable
memory device, such as those based on NAND or NOR technologies. A
memory device may also include future generation nonvolatile
devices, such as a three dimensional crosspoint memory device
(e.g., Intel 3D XPoint.TM. memory), or other byte addressable
write-in-place nonvolatile memory devices. In one embodiment, the
memory device may be or may include memory devices that use
chalcogenide glass, multi-threshold level NAND flash memory, NOR
flash memory, single or multi-level Phase Change Memory (PCM), a
resistive memory, nanowire memory, ferroelectric transistor random
access memory (FeTRAM), anti-ferroelectric memory, magnetoresistive
random access memory (MRAM) memory that incorporates memristor
technology, resistive memory including the metal oxide base, the
oxygen vacancy base and the conductive bridge Random Access Memory
(CB-RAM), or spin transfer torque (STT)-MRAM, a spintronic magnetic
junction memory based device, a magnetic tunneling junction (MTJ)
based device, a DW (Domain Wall) and SOT (Spin Orbit Transfer)
based device, a thyristor based memory device, or a combination of
any of the above, or other memory. The memory device may refer to
the die itself and/or to a packaged memory product.
[0090] In some embodiments, 3D crosspoint memory (e.g., Intel 3D
XPoint.TM. memory) may comprise a transistor-less stackable cross
point architecture in which memory cells sit at the intersection of
word lines and bit lines and are individually addressable and in
which bit storage is based on a change in bulk resistance. In some
embodiments, all or a portion of the memory 1706 may be integrated
into the processor 1704. In operation, the memory 1706 may store
various software and data used during operation such as job request
data, kernel map data, telemetry data, applications, programs,
libraries, and drivers.
[0091] The compute engine 1702 is communicatively coupled to other
components of the resource manager server 1606 via the I/O
subsystem 1708, which may be embodied as circuitry and/or
components to facilitate input/output operations with the processor
1704, the memory 1706, and other components of the resource manager
server 1606. For example, the I/O subsystem 1708 may be embodied
as, or otherwise include, memory controller hubs, input/output
control hubs, integrated sensor hubs, firmware devices,
communication links (e.g., point-to-point links, bus links, wires,
cables, light guides, printed circuit board traces, etc.), and/or
other components and subsystems to facilitate the input/output
operations. In some embodiments, the I/O subsystem 1708 may form a
portion of a system-on-a-chip (SoC) and be incorporated, along with
one or more of the processor 1704, the memory 1706, and other
components of the resource manager server 1606, on a single
integrated circuit chip.
[0092] The one or more data storage devices 1710 may be embodied as
any type of storage device(s) configured for short-term or
long-term storage of data, such as, for example, memory devices and
circuits, memory cards, hard disk drives, solid-state drives, or
other data storage devices. Each data storage device 1710 may
include a system partition that stores data and firmware code for
the data storage device 1710. Each data storage device 1710 may
also include an operating system partition that stores data files
and executables for an operating system.
[0093] The communication circuitry 1712 may be embodied as any
communication circuit, device, or collection thereof, capable of
enabling communications between the resource manager server 1606
and other compute devices (e.g., the compute sleds 1602 of FIG. 16)
over a network. Accordingly, the communication circuitry 1712 may
be configured to use any one or more communication technology
(e.g., wired or wireless communications) and associated protocols
(e.g., Ethernet, Bluetooth.RTM., Wi-Fi.RTM., WiMAX, etc.) to effect
such communication.
[0094] The illustrative communication circuitry 1712 includes a
network interface controller (NIC) 1714, which may also be referred
to as a host fabric interface (HFI). The NIC 1714 may be embodied
as one or more add-in-boards, daughtercards, network interface
cards, controller chips, chipsets, or other devices that may be
used by the resource manager server 1606 to connect with another
compute device (e.g., one of the compute sleds 1602 of FIG. 16). In
some embodiments, the NIC 1714 may be embodied as part of a
system-on-a-chip (SoC) that includes one or more processors, or
included on a multichip package that also contains one or more
processors. In some embodiments, the NIC 1714 may include a local
processor (not shown) and/or a local memory (not shown) that are
both local to the NIC 1714. In such embodiments, the local
processor of the NIC 1714 may be capable of performing one or more
of the functions of the processor 1704 described herein.
Additionally or alternatively, in such embodiments, the local
memory of the NIC 1714 may be integrated into one or more
components of the resource manager server 1606 at the board level,
socket level, chip level, and/or other levels.
[0095] The one or more peripheral devices 1716 may include any type
of device that is usable to input information into the resource
manager server 1606 and/or receive information from the resource
manager server 1606. The peripheral devices 1716 may be embodied as
any auxiliary device usable to input information into the resource
manager server 1606, such as a keyboard, a mouse, a microphone, a
barcode reader, an image scanner, etc., or output information from
the resource manager server 1606, such as a display, a speaker,
graphics circuitry, a printer, a projector, etc. It should be
appreciated that, in some embodiments, one or more of the
peripheral devices 1716 may function as both an input device and an
output device (e.g., a touchscreen display, a digitizer on top of a
display screen, etc.). It should be further appreciated that the
types of peripheral devices 1716 connected to the resource manager
server 1606 may depend on, for example, the type and/or intended
use of the resource manager server 1606. Additionally or
alternatively, in some embodiments, the peripheral devices 1716 may
include one or more ports, such as a USB port, for example, for
connecting external peripheral devices to the resource manager
server 1606.
[0096] Referring back to FIG. 16, the network switch 1604 may be
embodied as any type of networking device capable of performing the
functions described herein, including switching network packets
between the compute sleds 1602, the resource manager server 1606,
and the memory sled 1608, as well as any other computing devices.
For example, the network switch 1604 may be embodied as a
top-of-rack switch, a middle-of-rack switch, or other Ethernet
switch. The network switch 1604, as described previously, is
communicatively coupled to multiple sleds including the compute
sleds 1602 and a memory sled 1608. Accordingly, the network switch
1604 is configured to facilitate communication between the resource
manager server 1606 and the compute sleds 1602, and between the
resource manager server 1606 and the memory sled 1608, as well as
between the compute sleds 1602 and the memory sled 1608. While the
network switch 1604 is illustratively shown as providing the
communication link between the compute sleds 1602 and the memory
sled 1608, it should be appreciated that, in other embodiments, the
compute sleds 1602 and the memory sled 1608 may be connected via a
set of dedicated links. In such embodiments, each of the compute
sleds 1602 may be communicatively coupled to the memory sled 1608
via a dedicated link.
[0097] The compute sleds 1602 may be embodied as any type of
compute device capable of performing the functions described
herein, including instantiating/stopping/starting a VM instance and
executing a workload (e.g., within the VM instance). As shown in
FIG. 18, an illustrative one of the compute sleds 1602, has similar
components to that of the resource manager server 1606, including a
compute engine 1802 with a processor 1804 and a memory 1806, an I/O
subsystem 1808, communication circuitry 1812 with a NIC 1814, and,
in some embodiments, one or more data storage devices 1810 and/or
one or more peripheral devices 1816. Accordingly, the similar or
like components are not described herein to preserve clarity of the
description. In some embodiments, the compute sleds 1602 may
include other or additional components, such as those commonly
found in a computing device. Additionally, in some embodiments, one
or more of the illustrative components may be incorporated in, or
otherwise form a portion of, another component.
[0098] Referring again to FIG. 16, the memory sled 1608 may be
embodied as any type of storage device capable of performing the
functions described herein, such as managing a memory pool 1614 of
memory 1612 (e.g., physical storage resources 205-1). To do so, the
illustrative memory sled 1608 includes a memory pool controller
1610, which is configured to manage data into and out of the memory
pool 1614 such that the data can be stored and retrieved by the
compute sleds 1602. It should be appreciated that the memory pool
controller 1610 may be embodied as virtual and/or physical
hardware, firmware, software, or a combination thereof. It should
be further appreciated that while only a single memory sled 1608 is
shown, other embodiments may include more than one memory sled
1608.
[0099] The memory 1612 of the memory pool 1614 may be embodied as
any type of volatile (e.g., dynamic random access memory (DRAM),
etc.) or non-volatile memory or data storage capable of performing
the functions described herein. Volatile memory may be a storage
medium that requires power to maintain the state of data stored by
the medium. Non-limiting examples of volatile memory may include
various types of random access memory (RAM), such as dynamic random
access memory (DRAM) or static random access memory (SRAM).
[0100] One particular type of DRAM that may be used in a memory
module is synchronous dynamic random access memory (SDRAM). In
particular embodiments, DRAM of a memory component may comply with
a standard promulgated by JEDEC, such as JESD79F for DDR SDRAM,
JESD79-2F for DDR2 SDRAM, JESD79-3F for DDR3 SDRAM, JESD79-4A for
DDR4 SDRAM, JESD209 for Low Power DDR (LPDDR), JESD209-2 for
LPDDR2, JESD209-3 for LPDDR3, and JESD209-4 for LPDDR4 (these
standards are available at www.jedec.org). Such standards (and
similar standards) may be referred to as DDR-based standards and
communication interfaces of the storage devices that implement such
standards may be referred to as DDR-based interfaces.
[0101] In one embodiment, the memory 1612 may be embodied as a
block addressable memory device, such as those based on NAND or NOR
technologies. A memory device may also include future generation
nonvolatile devices, such as a three dimensional (3D) crosspoint
memory device (e.g., Intel 3D XPoint.TM. memory), or other byte
addressable write-in-place nonvolatile memory devices. In such
embodiments, the 3D crosspoint memory (e.g., Intel 3D XPoint.TM.
memory) may comprise a transistor-less stackable cross point
architecture in which memory cells sit at the intersection of word
lines and bit lines and are individually addressable and in which
bit storage is based on a change in bulk resistance.
[0102] In another embodiment, the memory 1612 may be or may include
memory devices that use chalcogenide glass, multi-threshold level
NAND flash memory, NOR flash memory, single or multi-level Phase
Change Memory (PCM), a resistive memory, nanowire memory,
ferroelectric transistor random access memory (FeTRAM),
anti-ferroelectric memory, magnetoresistive random access memory
(MRAM) memory that incorporates memristor technology, resistive
memory including the metal oxide base, the oxygen vacancy base and
the conductive bridge Random Access Memory (CB-RAM), or spin
transfer torque (STT)-MRAM, a spintronic magnetic junction memory
based device, a magnetic tunneling junction (MTJ) based device, a
DW (Domain Wall) and SOT (Spin Orbit Transfer) based device, a
thyristor based memory device, or a combination of any of the
above, or other memory. The memory device may refer to the die
itself and/or to a packaged memory product.
[0103] The illustrative compute sleds 1602 include a first compute
sled, designated as compute sled (1) 1602a, a second compute sled,
designated as compute sled (2) 1602b, and a third compute sled,
designated as compute sled (N) 1602c (e.g., in which the compute
sled (N) 1602c represents the "Nth" compute sled 1602, wherein "N"
is a positive integer). It should be appreciated that, in some
embodiments, one or more of the compute sleds 1602 may be grouped
into a managed node, such as by the resource manager server 1606,
to collectively perform a workload, such as an application. A
managed node may be embodied as an assembly of resources, such as
compute resources, memory resources, storage resource, or other
resources, from the same or different sleds or racks.
[0104] Further, a managed node may be established, defined, or
"spun up" by the resource manager server 1606 at the time a
workload is to be assigned to the managed node or at any other
time, and may exist regardless of whether any workloads are
presently assigned to the managed node. The resource manager server
1606 may, in some embodiments, perform one or more orchestration
operations in support of a cloud operating environment, such as
OpenStack, and managed nodes established by the resource manager
server 1606 may execute one or more applications or processes
(i.e., workloads), such as in the VMs or containers, on behalf of a
user of a client device (not shown) communicatively coupled to the
resource manager server 1606 (e.g., via a network).
[0105] Referring now to FIG. 19, the resource manager server 1606
may establish an environment 1900 during operation. The
illustrative environment 1900 includes a network connection manager
1910, a memory pool communicator 1920, a resource allocator 1930,
and a VM instance manager 1940. Each of the components of the
environment 1900 may be embodied as hardware, firmware, software,
or a combination thereof. As such, in some embodiments, one or more
of the components of the environment 1900 may be embodied as
circuitry or a collection of electrical devices (e.g., network
connection management circuitry 1910, memory pool communication
circuitry 1920, resource allocation circuitry 1930, VM instance
management circuitry 1940, etc.). It should be appreciated that, in
such embodiments, one or more of the network connection management
circuitry 1910, the memory pool communication circuitry 1920, the
resource allocation circuitry 1930, and the VM instance management
circuitry 1940 may form a portion of one or more of the compute
engine 1702, the one or more data storage devices 1710, the
communication circuitry 1712, and/or any other components of the
resource manager server 1606.
[0106] In the illustrative embodiment, the environment 1900
additionally includes resource data 1902 and virtual machine data
1904, each of which may be embodied as any data established by the
resource manager server 1606. The resource data 1902 may include
any data usable to identify and/or allocate resources of the
compute sleds 1602 and/or the memory sled 1608. The virtual machine
data 1904 may include any data usable to identify VM instances
(e.g., the VM instance 1616 of FIG. 16) and the respective compute
sleds 1602 on which the VM instances are presently being executed.
The virtual machine data 1904 may additionally include VM resource
requirement data usable to identify what resources are required for
each VM instance.
[0107] The network connection manager 1910, which may be embodied
as hardware, firmware, software, virtualized hardware, emulated
architecture, and/or a combination thereof as discussed above, is
configured to facilitate inbound and outbound network
communications (e.g., network traffic, network packets, network
flows, etc.) to and from the resource manager server 1606,
respectively. To do so, the network connection manager 1910 is
configured to receive and process data packets from one system or
computing device (e.g., one of the compute sleds 1602) and to
prepare and send data packets to another computing device or system
(e.g., one of the compute sleds 1602). Accordingly, in some
embodiments, at least a portion of the functionality of the network
connection manager 1910 may be performed by the communication
circuitry 1712, or more particularly by the NIC 1714.
[0108] The memory pool communicator 1920, which may be embodied as
hardware, firmware, software, virtualized hardware, emulated
architecture, and/or a combination thereof as discussed above, is
configured to facilitate transmissions between the resource manager
server 1606 and a memory pool controller of a memory pool (e.g.,
the memory pool controller 1610 of the memory pool 1614 of FIG.
16). For example, the memory pool communicator 1920 is configured
to generate and transmit memory allocation and memory map requests
to the memory pool controller 1610 which are usable to allocate
regions of memory (i.e., in response to a received memory
allocation request) and map allocated regions of memory to a
particular compute sled 1602 (i.e., in response to a received
memory map request).
[0109] The resource allocator 1930, which may be embodied as
hardware, firmware, software, virtualized hardware, emulated
architecture, and/or a combination thereof as discussed above, is
configured to manage the available and allocated resources of the
compute sleds 1602. To do so, the resource allocator 1930 may be
configured to identify data associated with the resources, such as
a compute capacity/availability, a memory bandwidth
capacity/availability, a data storage capacity/availability, and/or
a level of reliability, resiliency, and/or availability of the
resources. In some embodiments, the resource allocator 1930 may be
configured to store data related to the presently and/or
historically available and/or allocated resources in the resource
data 1902.
[0110] The VM instance manager 1940, which may be embodied as
hardware, firmware, software, virtualized hardware, emulated
architecture, and/or a combination thereof as discussed above, is
configured to manage the creation, migration, and deletion of VM
instances on the compute sleds 1602. To do so, the illustrative VM
instance manager 1940 includes a resource identifier 1942 and a
migration manager 1944. The resource identifier 1942 is configured
to identify which resources to allocate for a particular purpose
(e.g., a workload). Such resources may be allocated by type,
amount, performance, intended use, etc., and may include network
communication resources, storage resources, compute resources,
etc.
[0111] The migration manager 1944 is configured to detect whether a
migration trigger has been detected. To do so, for example, the
migration manager 1944 may be configured to collect or otherwise
analyze collected telemetry data to determine whether certain
conditions exist such that a migration of a VM from one compute
sled 1602 to another compute sled 1602, or more particularly from a
CPU on a compute sled 1602 (e.g., the processor 1804 of the
illustrative compute sled 1602 of FIG. 18) to a different CPU on
another compute sled 1602, is required.
[0112] Additionally, the migration manager 1944 is configured to
manage the migration of a VM instance in response to having
detected a migration triggering event. To do so, the migration
manager 1944 may be configured to identify the compute sled 1602 on
which the VM instance to be migrated is presently being executed
and transmit an indication to the identified compute sled 1602 that
indicates which VM instance is to be migrated. Accordingly, upon
receipt, the compute sled 1602 can stop the VM instance and
initiate a data flush to a mapped region of memory in a memory pool
(e.g., the memory 1612 in the memory pool 1614 of FIG. 16). The
migration manager 1944 is further configured to migrate the
workload/VM instance to the new compute sled 1602 and initiate the
re-mapping of the region of memory to the new compute sled 1602 and
the startup of the VM instance on the new compute sled 1602. To
initiate the re-mapping of the region of memory to the new compute
sled 1602, the migration manager 1944 is configured to provide
identifying information of the old and new compute sleds 1602 to
the memory pool controller 1610 (e.g., via the memory pool
communicator 1920) which is usable by the memory pool controller
1610 to change the mapping of the data associated with the migrated
VM instance from the old compute sled 1602 to the new compute sled
1602. While the illustrative embodiment described herein is
referring to a VM instance, it should be appreciated that the
migration operations described herein may be performed on another
object, such as a container, in other embodiments.
[0113] Referring now to FIG. 20, in use, a resource manager server
(e.g., resource manager server 1606 of FIG. 16) may execute a
method 2000 for creating a VM instance (e.g., the VM instance 1616
of FIG. 16) on a compute sled (e.g., one of the compute sleds
1602), or more particularly on a CPU of the compute sled 1602. The
method 2000 begins in block 2002, in which the resource manager
server 1606 determines whether to create a VM instance 1616. If so,
the method 2000 advances to block 2004, in which the resource
manager server 1606 determines which resources (e.g., compute
resources, storage resources, network resources, etc.) are required
by a workload to be processed by or otherwise run on the VM
instance 1616.
[0114] In block 2006, the resource manager server 1606 determines a
compute sled 1602 (e.g., one of the compute sled (1) 1602a, the
compute sled (2) 1602b, the compute sled (N) 1602c of FIG. 16) on
which to launch the VM instance 1616. To do so, in block 2008, the
resource manager server 1606 first identifies the available
resources of each available compute sled 1602. Additionally, in
block 2010, the resource manager server 1606 determines the compute
sled to launch the VM instance 1616 based on the determined
resources required by the workload and the identified available
resources of each available compute sled 1602.
[0115] In block 2012, the resource manager server 1606 allocates
resources of the determined compute sled for use by the VM
instance. In block 2014, the resource manager server 1606 allocates
a region of memory in a memory pool (e.g., the memory 1612 in the
memory pool 1614 of FIG. 16) to be associated with the compute sled
1602. It should be appreciated that the regions of memory may be
private (i.e., dedicated to the compute sled 1602) or shared among
more than one compute sled 1602. To do so, in block 2016, the
resource manager server 1606 transmits a memory allocation request
to a memory pool controller (e.g., the memory pool controller 1610)
of the memory pool 1614. Additionally, in block 2018, the resource
manager server 1606 includes information usable to map the compute
sled to the allocated memory region (e.g., identifying information
of the compute sled 1602 and/or the CPU of the compute sled 1602 on
which the VM instance is to be run). In block 2020, the resource
manager server 1606 creates the VM instance 1616.
[0116] Referring now to FIG. 21, in use, a resource manager server
1606 (e.g., resource manager server 1606 of FIG. 16) may execute a
method 2100 for migrating an existing VM instance (e.g., the VM
instance 1616 of FIG. 16) from one compute sled 1602 (e.g., the
compute sled (1) 1602a) to another compute sled 1602 (e.g., the
compute sled (2) 1602b), or more particularly from one CPU (e.g.,
the processor 1804 of the illustrative compute sled 1602 of FIG.
18) of a compute sled 1602 to a CPU of another compute sled 1602.
The method 2100 begins in block 2102, in which the resource manager
server 1606 determines whether to migrate a VM instance 1616. If
so, the method 2100 advances to block 2104, in which the resource
manager server 1606 retrieves the resources (e.g., compute
resources, storage resources, network resources, etc.) which have
previously been determined as being required by the workload being
processed by or otherwise run on the VM instance 1616.
[0117] In block 2106, the resource manager server 1606 determines
another compute sled 1602 on which to migrate the VM instance 1616
to. To do so, in block 2108, the resource manager server 1606 first
identifies the available resources of each of the other available
compute sleds 1602. Additionally, in block 2110, the resource
manager server 1606 determines the compute sled to migrate the VM
instance 1616 to based on the retrieved resources required by the
workload and the identified available resources of each of the
other available compute sleds 1602.
[0118] In block 2112, the resource manager server 1606 allocates
resources of the determined other compute sled for use by the VM
instance 1616 upon being migrated. In block 2114, the resource
manager server 1606 migrates the VM instance 1616 to the other
determined compute sled 1602. In other words, the data (e.g.,
software/hardware thread states) associated with the workload being
processed by the VM instance 1616 and/or data corresponding to the
VM instance 1616 itself are migrated to the other compute sled
1602. In block 2116, the resource manager server 1606 re-maps the
region of memory in the memory pool from the previously associated
compute sled 1602 (i.e., from which the VM instance 1616 is being
migrated from) to the other compute sled 1602 (i.e., to which the
VM instance 1616 is being migrated to). To do so, in block 2118,
the resource manager server 1606 transmits a memory re-map request
to a memory pool controller (e.g., the memory pool controller 1610)
of the memory pool 1614. Additionally, in block 2120, the resource
manager server 1606 includes information usable to re-map the
allocated memory region from the previously associated compute sled
1602 to the compute sled 1602 which the VM instance 1616 is being
migrated to. In block 2122, the resource manager server 1606
starts-up the VM instance 1616 on the other compute sled 1602.
EXAMPLES
[0119] Illustrative examples of the technologies disclosed herein
are provided below. An embodiment of the technologies may include
any one or more, and any combination of, the examples described
below.
[0120] Example 1 includes a resource manager server for migrating
virtual machines, the resource manager server comprising a compute
engine to identify a compute sled of a plurality of compute sleds
for a virtual machine (VM) instance, wherein each of the compute
sleds is communicatively coupled to the resource manager server;
allocate a first set of resources of the identified compute sled
for the VM instance; associate a region of memory in a memory pool
of a memory sled with the compute sled, wherein the memory sled is
communicatively coupled to the resource manager server; create the
VM instance on the compute sled; allocate, in response to
determined determination that the VM instance is to be migrated, a
second set of resources of another compute sled of the plurality of
compute sleds for the VM instance; migrate the VM instance to the
other compute sled; associate the region of memory in the memory
pool with the other compute sled; and start-up the VM instance on
the other compute sled.
[0121] Example 2 includes the subject matter of Example 1, and
wherein to allocate the first set of resources of the compute sled
comprises to (i) determine a set of resources required by a
workload to be processed by the VM instance and (ii) allocate the
first set of resources of the compute sled as a function of the
determined required set of resources.
[0122] Example 3 includes the subject matter of any of Examples 1
and 2, and wherein to allocate the first set of resources of the
compute sled further comprises to (i) identify available resources
of each of the plurality of compute sleds and (ii) allocate the
first set of resources of the compute sled as a function of the
identified available resources.
[0123] Example 4 includes the subject matter of any of Examples
1-3, and wherein to associate the region of memory in the memory
pool of the memory sled with the compute sled comprises to transmit
a memory allocation request to a memory pool controller of the
memory pool that is usable to allocate the region of memory and map
the allocated region of memory to the compute sled.
[0124] Example 5 includes the subject matter of any of Examples
1-4, and wherein to migrate the VM instance to the other compute
sled comprises to transmit one or more threads associated with the
workload associated with the VM instance to the other compute
sled.
[0125] Example 6 includes the subject matter of any of Examples
1-5, and wherein to associate the region of memory in the memory
pool of the memory sled with the other compute sled comprises to
transmit a memory allocation request to a memory pool controller of
the memory pool that is usable to map the allocated region of
memory to the other compute sled.
[0126] Example 7 includes the subject matter of any of Examples
1-6, and wherein to allocate the second set of resources of the
compute sled comprises to (i) retrieve a set of resources required
by a workload being processed by the VM instance and (ii) allocate
the second set of resources of the compute sled as a function of
the retrieved required set of resources.
[0127] Example 8 includes the subject matter of any of Examples
1-7, and wherein to allocate the second set of resources of the
other compute sled further comprises to (i) identify available
resources of each of the plurality of compute sleds and (ii)
allocate the second set of resources of the other compute sled as a
function of the identified available resources.
[0128] Example 9 includes a method for migrating virtual machines,
the comprising identifying, by a compute engine of a resource
manager server, a compute sled of a plurality of compute sleds for
a virtual machine (VM) instance, wherein each of the compute sleds
is communicatively coupled to the resource manager server;
allocating, by the compute engine, a first set of resources of the
identified compute sled for the VM instance; associating, by the
compute engine, a region of memory in a memory pool of a memory
sled with the compute sled, wherein the memory sled is
communicatively coupled to the resource manager server; creating,
by the compute engine, the VM instance on the compute sled;
allocating, by the compute engine and in response to determined
determination that the VM instance is to be migrated, a second set
of resources of another compute sled of the plurality of compute
sleds for the VM instance; migrating, by the compute engine, the VM
instance to the other compute sled; associating, by the compute
engine, the region of memory in the memory pool with the other
compute sled; and starting-up, by the compute engine, the VM
instance on the other compute sled.
[0129] Example 10 includes the subject matter of Example 9, and
wherein allocating the first set of resources of the compute sled
comprises determining a set of resources required by a workload to
be processed by the VM instance; and allocating the first set of
resources of the compute sled as a function of the determined
required set of resources.
[0130] Example 11 includes the subject matter of any of Examples 9
and 10, and wherein allocating the first set of resources of the
compute sled further comprises identifying available resources of
each of the plurality of compute sleds; and allocating the first
set of resources of the compute sled as a function of the
identified available resources.
[0131] Example 12 includes the subject matter of any of Examples
9-11, and wherein associating the region of memory in the memory
pool of the memory sled with the compute sled comprises
transmitting a memory allocation request to a memory pool
controller of the memory pool that is usable to allocate the region
of memory and map the allocated region of memory to the compute
sled.
[0132] Example 13 includes the subject matter of any of Examples
9-12, and wherein migrating the VM instance to the other compute
sled comprises transmitting one or more threads associated with the
workload associated with the VM instance to the other compute
sled.
[0133] Example 14 includes the subject matter of any of Examples
9-13, and wherein associating the region of memory in the memory
pool of the memory sled with the other compute sled comprises
transmitting a memory allocation request to a memory pool
controller of the memory pool that is usable to map the allocated
region of memory to the other compute sled.
[0134] Example 15 includes the subject matter of any of Examples
9-14, and wherein allocating the second set of resources of the
compute sled comprises retrieving a set of resources required by a
workload being processed by the VM instance; and allocating the
second set of resources of the compute sled as a function of the
retrieved required set of resources.
[0135] Example 16 includes the subject matter of any of Examples
9-15, and wherein allocating the second set of resources of the
other compute sled further comprises identifying available
resources of each of the plurality of compute sleds; and allocating
the second set of resources of the other compute sled as a function
of the identified available resources.
[0136] Example 17 includes one or more machine-readable storage
media comprising a plurality of instructions stored thereon that,
in response to being executed, cause a resource manager server to
perform the method of any of Examples 9-16.
[0137] Example 18 includes a resource manager server for improving
throughput in a network, the resource manager server comprising one
or more processors; one or more memory devices having stored
therein a plurality of instructions that, when executed by the one
or more processors, cause the resource manager server to perform
the method of any of Examples 9-16.
[0138] Example 19 includes a resource manager server for migrating
virtual machines, the resource manager server comprising virtual
machine instance management circuitry to identify a compute sled of
a plurality of compute sleds for a virtual machine (VM) instance,
wherein each of the compute sleds is communicatively coupled to the
resource manager server; allocate a first set of resources of the
identified compute sled for the VM instance; associate a region of
memory in a memory pool of a memory sled with the compute sled,
wherein the memory sled is communicatively coupled to the resource
manager server; create the VM instance on the compute sled;
allocate, in response to determined determination that the VM
instance is to be migrated, a second set of resources of another
compute sled of the plurality of compute sleds for the VM instance;
migrate the VM instance to the other compute sled; associate the
region of memory in the memory pool with the other compute sled;
and start-up the VM instance on the other compute sled.
[0139] Example 20 includes the subject matter of Example 19, and
wherein to allocate the first set of resources of the compute sled
comprises to (i) determine a set of resources required by a
workload to be processed by the VM instance and (ii) allocate the
first set of resources of the compute sled as a function of the
determined required set of resources.
[0140] Example 21 includes the subject matter of any of Examples 19
and 20, and wherein to allocate the first set of resources of the
compute sled further comprises to (i) identify available resources
of each of the plurality of compute sleds and (ii) allocate the
first set of resources of the compute sled as a function of the
identified available resources.
[0141] Example 22 includes the subject matter of any of Examples
19-21, and wherein to associate the region of memory in the memory
pool of the memory sled with the compute sled comprises to transmit
a memory allocation request to a memory pool controller of the
memory pool that is usable to allocate the region of memory and map
the allocated region of memory to the compute sled.
[0142] Example 23 includes the subject matter of any of Examples
19-22, and wherein to migrate the VM instance to the other compute
sled comprises to transmit one or more threads associated with the
workload associated with the VM instance to the other compute
sled.
[0143] Example 24 includes the subject matter of any of Examples
19-23, and wherein to associate the region of memory in the memory
pool of the memory sled with the other compute sled comprises to
transmit a memory allocation request to a memory pool controller of
the memory pool that is usable to map the allocated region of
memory to the other compute sled.
[0144] Example 25 includes the subject matter of any of Examples
19-24, and wherein to allocate the second set of resources of the
compute sled comprises to (i) retrieve a set of resources required
by a workload being processed by the VM instance and (ii) allocate
the second set of resources of the compute sled as a function of
the retrieved required set of resources.
[0145] Example 26 includes the subject matter of any of Examples
19-25, and wherein to allocate the second set of resources of the
other compute sled further comprises to (i) identify available
resources of each of the plurality of compute sleds and (ii)
allocate the second set of resources of the other compute sled as a
function of the identified available resources.
[0146] Example 27 includes a resource manager server for migrating
virtual machines, the resource manager server comprising circuitry
for identifying, by a compute engine of the resource manager
server, a compute sled of a plurality of compute sleds for a
virtual machine (VM) instance, wherein each of the compute sleds is
communicatively coupled to the resource manager server; circuitry
for allocating, by the compute engine, a first set of resources of
the identified compute sled for the VM instance; means for
associating, by the compute engine, a region of memory in a memory
pool of a memory sled with the compute sled, wherein the memory
sled is communicatively coupled to the resource manager server;
circuitry for creating, by the compute engine, the VM instance on
the compute sled; circuitry for allocating, by the compute engine
and in response to determined determination that the VM instance is
to be migrated, a second set of resources of another compute sled
of the plurality of compute sleds for the VM instance; circuitry
for migrating, by the compute engine, the VM instance to the other
compute sled; means for associating, by the compute engine, the
region of memory in the memory pool with the other compute sled;
and circuitry for starting-up, by the compute engine, the VM
instance on the other compute sled.
[0147] Example 28 includes the subject matter of Example 27, and
wherein the circuitry for allocating the first set of resources of
the compute sled comprises means for determining a set of resources
required by a workload to be processed by the VM instance; and
circuitry for allocating the first set of resources of the compute
sled as a function of the determined required set of resources.
[0148] Example 29 includes the subject matter of any of Examples 27
and 28, and wherein the circuitry for allocating the first set of
resources of the compute sled further comprises means for
identifying available resources of each of the plurality of compute
sleds; and circuitry for allocating the first set of resources of
the compute sled as a function of the identified available
resources.
[0149] Example 30 includes the subject matter of any of Examples
27-29, and wherein the means for associating the region of memory
in the memory pool of the memory sled with the compute sled
comprises means for transmitting a memory allocation request to a
memory pool controller of the memory pool that is usable to
allocate the region of memory and map the allocated region of
memory to the compute sled.
[0150] Example 31 includes the subject matter of any of Examples
27-30, and wherein the circuitry for migrating the VM instance to
the other compute sled comprises circuitry for transmitting one or
more threads associated with the workload associated with the VM
instance to the other compute sled.
[0151] Example 32 includes the subject matter of any of Examples
27-31, and wherein the means for associating the region of memory
in the memory pool of the memory sled with the other compute sled
comprises means for transmitting a memory allocation request to a
memory pool controller of the memory pool that is usable to map the
allocated region of memory to the other compute sled.
[0152] Example 33 includes the subject matter of any of Examples
27-32, and wherein the circuitry for allocating the second set of
resources of the compute sled comprises circuitry for retrieving a
set of resources required by a workload being processed by the VM
instance; and circuitry for allocating the second set of resources
of the compute sled as a function of the retrieved required set of
resources.
[0153] Example 34 includes the subject matter of any of Examples
27-33, and wherein the circuitry for allocating the second set of
resources of the other compute sled further comprises means for
identifying available resources of each of the plurality of compute
sleds; and circuitry for allocating the second set of resources of
the other compute sled as a function of the identified available
resources.
* * * * *
References