U.S. patent application number 16/157642 was filed with the patent office on 2019-02-07 for semiconductor chip including a plurality of pads.
This patent application is currently assigned to SAMSUNG ELECTRONICS CO., LTD.. The applicant listed for this patent is SAMSUNG ELECTRONICS CO., LTD.. Invention is credited to KWANYEOB CHAE, Jin-Ho CHOI, Jong-Ryun CHOI, Sanghoon JOO.
Application Number | 20190043841 16/157642 |
Document ID | / |
Family ID | 58448028 |
Filed Date | 2019-02-07 |
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United States Patent
Application |
20190043841 |
Kind Code |
A1 |
CHAE; KWANYEOB ; et
al. |
February 7, 2019 |
SEMICONDUCTOR CHIP INCLUDING A PLURALITY OF PADS
Abstract
A semiconductor chip including a plurality of input/output units
includes: a plurality of additional pads disposed on a surface of
the semiconductor chip, wherein the plurality of additional pads
include at least one of a first additional pad to which a ground
voltage is applied and a second additional pad to which a power
supply voltage is applied; and a plurality of pads disposed on the
surface of the semiconductor chip, wherein the plurality of pads
include at least one of a first pad to which the ground voltage is
applied and a second pad to which the power supply voltage is
applied, and further include a third pad through which a signal is
input and/or output. The at least one of the first additional pad
and the second additional pad is disposed on an input/output unit
where the third pad is disposed, among the plurality of
input/output units.
Inventors: |
CHAE; KWANYEOB;
(Hwaseong-si, KR) ; JOO; Sanghoon; (Osan-si,
KR) ; CHOI; Jong-Ryun; (Hwaseong-si, KR) ;
CHOI; Jin-Ho; (Seoul, KR) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SAMSUNG ELECTRONICS CO., LTD. |
Suwon-si |
|
KR |
|
|
Assignee: |
SAMSUNG ELECTRONICS CO.,
LTD.
Suwon-si
KR
|
Family ID: |
58448028 |
Appl. No.: |
16/157642 |
Filed: |
October 11, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15277339 |
Sep 27, 2016 |
10115706 |
|
|
16157642 |
|
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|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 23/585 20130101;
H01L 23/60 20130101; H01L 24/02 20130101; H01L 23/5221 20130101;
H01L 24/14 20130101; H01L 25/0657 20130101; H01L 23/50 20130101;
H01L 24/06 20130101; H01L 2224/14131 20130101; H01L 2224/02375
20130101; H01L 2924/00012 20130101; H01L 24/05 20130101; H01L
2224/14135 20130101; H01L 2224/0233 20130101; H01L 2224/06131
20130101; H01L 2224/05552 20130101; H01L 2224/16145 20130101; H01L
2225/06555 20130101; H01L 2224/0235 20130101; H01L 2224/02377
20130101; H01L 24/00 20130101; H01L 24/16 20130101; H01L 2225/06513
20130101; H01L 2224/06135 20130101; H01L 2224/02381 20130101; H01L
2224/16227 20130101; H01L 23/5286 20130101; H01L 2224/0401
20130101; H01L 2224/02375 20130101; H01L 2924/00012 20130101; H01L
2224/02381 20130101; H01L 2924/00012 20130101; H01L 2224/0235
20130101; H01L 2924/00012 20130101; H01L 2224/0233 20130101; H01L
2924/00012 20130101; H01L 2224/05552 20130101; H01L 2924/00012
20130101 |
International
Class: |
H01L 25/065 20060101
H01L025/065; H01L 23/58 20060101 H01L023/58; H01L 23/60 20060101
H01L023/60; H01L 23/00 20060101 H01L023/00; H01L 23/50 20060101
H01L023/50 |
Foreign Application Data
Date |
Code |
Application Number |
Oct 2, 2015 |
KR |
10-2015-0139167 |
Feb 1, 2016 |
KR |
10-2016-0012408 |
Claims
1. A semiconductor chip comprising: a first to a fourth bump areas
that are provided on a surface of the semiconductor chip; a first
to a fourth conductive lines that are provided on the surface and
are connected to the first to the fourth bump areas, respectively;
and a first and a second conductive rings that are provided inside
the semiconductor chip, wherein the first conductive line and the
first conductive ring are electrically connected to each other
through a first internal interconnection line provided at a first
point of a first row of the surface, wherein the second conductive
line and the second conductive ring are electrically connected to
each other through a second internal interconnection line provided
at a second point of a second row of the surface, wherein the third
conductive line and the first conductive ring are electrically
connected to each other through a third internal interconnection
line provided at a third point of a third row of the surface, and
wherein the fourth conductive line and the second conductive ring
are electrically connected to each other through a fourth internal
interconnection line provided at a fourth point of the third row of
the surface.
2. The semiconductor chip of claim 1, wherein a ground voltage is
applied to the first and the third bump areas, and wherein a power
supply voltage is applied to the second and the fourth bump
areas.
3. The semiconductor chip of claim 1, further comprising: a fifth
bump area that is provided on the surface; and a fifth conductive
line that is provided on the surface and is connected to the fifth
bump area, wherein the fifth conductive line is electrically
connected to an input/output unit provided inside the semiconductor
chip through a fifth internal interconnection line provided at a
fifth point of a row of the surface, and wherein the row is other
than the first and the second rows.
4. The semiconductor chip of claim 3, wherein the row is the third
row.
5. The semiconductor chip of claim 3, wherein a signal is received
or transferred through the fifth bump area.
6. The semiconductor chip of claim 1, wherein the first internal
interconnection line is provided to have a first minimum distance
between the first conductive line and the first conductive ring,
and wherein the second internal interconnection line is provided to
have a second minimum distance between the second conductive line
and the second conductive ring.
7. The semiconductor chip of claim 6, wherein the third internal
interconnection line is provided not to have the first minimum
distance between the first conductive line and the first conductive
ring, and wherein the fourth internal interconnection line is
provided not to have the second minimum distance between the fourth
conductive line and the second conductive ring.
8. The semiconductor chip of claim 6, wherein the first minimum
distance is same as the second minimum distance.
9. A semiconductor chip comprising: a plurality of input/output
units, wherein each of the plurality of input/output units includes
a first point, first points of the plurality of input/output units
respectively connected to first bump areas through first conductive
lines, and a signal is input and/or output through at least one of
the first bump areas, wherein the first points of the plurality of
input/output units are arranged in a same row on a surface of the
semiconductor chip, and wherein at least one of the plurality of
input/output units includes at least one of: a second point
connected to a second bump area through a second conductive line;
and a third point connected to a third bump area through a third
conductive line.
10. The semiconductor chip of claim 9, wherein a ground voltage is
applied to the second bump area, and wherein a power supply voltage
is applied to the third bump area.
11. The semiconductor chip of claim 9, further comprising: a first
conductive ring provided inside the semiconductor chip; a second
conductive ring provided inside the semiconductor chip; a first
internal interconnection line that electrically connects the second
point with the first conductive line; and a second internal
interconnection line that electrically connects the third point
with the second conductive line.
12. The semiconductor chip of claim 9, wherein the plurality of
input/output units include input/output buffers, respectively, and
the input/output buffers are electrically connected to the first
points, respectively.
13. The semiconductor chip of claim 9, wherein the first and the
second bump areas are provided on the surface, and wherein the
first and the second conductive lines are provided on the
surface.
14. A semiconductor chip comprising: a first to a fourth bump areas
that are provided on a surface of the semiconductor chip; a first
to a fourth conductive lines that are provided on the surface and
are connected to the first to the fourth bump areas, respectively;
a first internal interconnection line that is vertically extending
at a first point of a first row of the surface and is electrically
connected to the first conductive line; a second internal
interconnection line that is vertically extending at a second point
of a second row of the surface and is electrically connected to the
second conductive line; a third internal interconnection line that
is vertically extending at a third point of a third row of the
surface and is electrically connected to the third conductive line;
and a fourth internal interconnection line that is vertically
extending at a fourth point of the third row of the surface and is
electrically connected to the fourth conductive line, wherein the
first and the third internal interconnection lines are electrically
connected to each other, and wherein the second and the fourth
internal interconnection lines are electrically connected to each
other.
15. The semiconductor chip of claim 14, further comprising: a first
conductive ring that is provided inside the semiconductor chip and
is electrically connected to the first and the third conductive
lines and the first and the third internal interconnection lines;
and a second conductive ring that is provided inside the
semiconductor chip and is electrically connected to the second and
the fourth conductive lines and the second and the fourth internal
interconnection lines.
16. The semiconductor chip of claim 15, wherein a ground voltage is
applied to the first and the third bump areas, and wherein a power
supply voltage is applied to the second and the fourth bump
areas.
17. The semiconductor chip of claim 15, further comprising: a fifth
bump area that is provided on the surface; a fifth conductive line
that is provided on the surface and is connected to the fifth bump
area; and a fifth internal interconnection line that is vertically
extending at a fifth point of the third row of the surface and is
electrically connected to the fifth conductive line, wherein the
fifth internal interconnection line is electrically connected to an
input/output unit provided inside the semiconductor chip.
18. The semiconductor chip of claim 17, wherein a signal is
received or transferred through the fifth bump area.
19. The semiconductor chip of claim 15, wherein the first internal
interconnection line is provided to have a first minimum distance
between the first conductive line and the first conductive ring,
and wherein the second internal interconnection line is provided to
have a second minimum distance between the second conductive line
and the second conductive ring.
20. The semiconductor chip of claim 19, wherein the third internal
interconnection line is provided not to have the first minimum
distance between the first conductive line and the first conductive
ring, and wherein the fourth internal interconnection line is
provided not to have the second minimum distance between the fourth
conductive line and the second conductive ring.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This is a continuation of U.S. application Ser. No.
15/277,339 filed Sep. 27, 2016, which claims priority from Korean
Patent Application No. 10-2016-0012408, filed on Feb. 1, 2016, and
Korean Patent Provisional Application No. 10-2015-0139167, filed on
Oct. 2, 2015, in the Korean Intellectual Property Office, the
disclosures of which are incorporated by reference in their
entireties.
BACKGROUND
[0002] Apparatuses consistent with exemplary embodiments relate to
semiconductor chips, and more particularly, to an arrangement of
pads of a semiconductor chip that is mounted on a package substrate
by a flip chip method.
[0003] A semiconductor chip may be mounted on a package substrate
by a wire bonding method or a flip chip method. In a case where a
semiconductor chip is mounted on the package substrate by a flip
chip method, the semiconductor chip may include a plurality of pads
to receive power and/or transmit and receive a signal. The
plurality of pads may be disposed on a semiconductor chip.
[0004] It is very important to sufficiently supply power to a
semiconductor chip to prevent an increase of a simultaneous
switching noise (SSN) of a signal while the signal is transmitted
and/or received. However, if the number of pads to which power is
supplied to is increased, this may cause an increase of a chip
size. On the other hand, if the number of pads to which power is
supplied is reduced, this may cause an increase of the simultaneous
switching noise (SSN). Thus, it is desirable to effectively dispose
pads on the semiconductor chip so that power is sufficiently
supplied to the semiconductor chip while a size of the
semiconductor chip is not increased.
SUMMARY
[0005] According to an aspect of an exemplary embodiment, provided
is a semiconductor chip including a plurality of input/output
units, the semiconductor chip including: a plurality of additional
pads disposed on a surface of the semiconductor chip, wherein the
plurality of additional pads include at least one of a first
additional pad to which a ground voltage is applied and a second
additional pad to which a power supply voltage is applied; and a
plurality of pads disposed on the surface of the semiconductor
chip, wherein the plurality of pads include at least one of a first
pad to which the ground voltage is applied and a second pad to
which the power supply voltage is applied, and further include a
third pad through which a signal is input and/or output, wherein
the at least one of the first additional pad and the second
additional pad is disposed on an input/output unit where the third
pad is disposed, among the plurality of input/output units.
[0006] The plurality of additional pads may include the first
additional pad, and the semiconductor chip may further include a
first conductive ring disposed within the semiconductor chip and
electrically connected to the first additional pad.
[0007] The plurality of pads may include the first pad, and the
first pad may be electrically connected to the first conductive
ring.
[0008] The plurality of additional pads may include the second
additional pad, and the semiconductor chip may further include a
second conductive ring disposed within the semiconductor chip and
electrically connected to the second additional pad.
[0009] The plurality of pads may include the second pad, and the
second pad may be electrically connected to the second conductive
ring.
[0010] The semiconductor chip may further include an input/output
buffer located corresponding to the input/output unit where the
third pad is disposed, among the plurality of input/output units,
and configured to receive and/or output the signal.
[0011] The semiconductor chip may further include at least one of:
a first bump area connected to at least one of the first additional
pad and the first pad through a first conductive line; a second
bump area connected to at least one of the second additional pad
and the second pad through a second conductive line; and a third
bump area connected to the third pad through a third conductive
line.
[0012] The semiconductor chip may be mounted on a package substrate
by a flip chip method.
[0013] According to an aspect of another exemplary embodiment,
provided is a semiconductor chip including a plurality of
input/output units, the semiconductor chip including: a plurality
of pads disposed on a surface of the semiconductor chip, wherein
the plurality of pads include at least one of a first pad, disposed
on a first row and configured to receive a ground voltage, and a
second pad, disposed on a second row and configured to receive a
power supply voltage; and a plurality of additional pads disposed
on the surface of the semiconductor chip, wherein the plurality of
additional pads include at least one of a first additional pad to
which the ground voltage is applied and a second additional pad to
which the power supply voltage is applied, wherein, when the
plurality of pads include the second pad and the plurality of
additional pads include the first additional pad, at least one of
the first additional pad is disposed on an input/output unit where
at least one of the second pad is disposed, among the plurality of
input/output units, and wherein, when the plurality of pads include
the first pad and the plurality of additional pads include the
second additional pad, at least one of the second additional pad is
disposed on an input/output unit where at least one of the first
pad is disposed, among the plurality of input/output units.
[0014] The plurality of pads may include the first pad, and the
semiconductor chip may further include a first conductive ring
disposed within the semiconductor chip and electrically connected
to the first pad.
[0015] The plurality of additional pads may include the first
additional pad, and the first additional pad may be electrically
connected to the first conductive ring.
[0016] The plurality of pads may include the second pad, and the
semiconductor chip may further include a second conductive ring
disposed within the semiconductor chip and electrically connected
to the second pad.
[0017] The plurality of additional pads may include the second
additional pad, and the second additional pad may be electrically
connected to the second conductive ring.
[0018] The plurality of pads may include a third pad disposed on a
third row and configured to receive and/or output a signal, and the
semiconductor chip may further include an input/output buffer
disposed within the semiconductor chip and configured to receive
and/or output the signal, the input/output buffer being located
corresponding to an input/output unit where the third pad is
disposed, among the plurality of input/output units.
[0019] The semiconductor chip may further include at least one of:
a first bump area connected to at least one of the first additional
pad and the first pad through a first conductive line; a second
bump area connected to at least one of the second additional pad
and the second pad through a second conductive line; and a third
bump area connected to a third pad through a third conductive line,
the third pad disposed on a third row and configured to receive
and/or output a signal.
[0020] The first conductive ring may be positioned to have a
minimum distance from the first pad.
[0021] According to an aspect of still another embodiment, provided
is a semiconductor chip including: a plurality of input/output
units, wherein at least one input/output unit among the plurality
of input/output units includes at least two from among: a first pad
to which a ground voltage is applied; a second pad to which a power
supply voltage is applied; and a third pad through which a signal
is input and/or output.
[0022] In the at least one input/output unit, the at least two from
among the first pad, the second pad, and the third pad may be
disposed on different rows on a surface of the semiconductor
chip.
[0023] The semiconductor chip may further include a plurality of
pads disposed on the plurality of input/output units, wherein the
plurality of pads include a plurality of first pads that are
disposed on different rows on a surface of the semiconductor chip
and/or a plurality of second pads that are disposed on different
rows on the surface of the semiconductor chip.
[0024] The semiconductor chip may further include a conductive ring
disposed within the semiconductor chip and electrically connected
to the plurality of first pads and/or the plurality of second pads
that are disposed on the different rows on the surface of the
semiconductor.
BRIEF DESCRIPTION OF THE FIGURES
[0025] The above and/or other aspects will be more apparent by
describing certain example embodiments with reference to the
accompanying drawings.
[0026] FIG. 1 is a top plan view of a semiconductor chip in
accordance with example embodiments.
[0027] FIG. 2 is a drawing illustrating an enlarged area of FIG.
1.
[0028] FIG. 3 is a top plan view illustrating a part of a
semiconductor chip in accordance with example embodiments.
[0029] FIG. 4A is a cross-sectional view taken along the line A-A'
of FIG. 3.
[0030] FIG. 4B is a cross-sectional view taken along the line B-B'
of FIG. 3.
[0031] FIG. 4C is a cross-sectional view taken along the line C-C'
of FIG. 3.
[0032] FIG. 5A is a cross-sectional view taken along the line D-D'
of FIG. 3.
[0033] FIG. 5B is a cross-sectional view taken along the line E-E'
of FIG. 3.
[0034] FIG. 5C is a cross-sectional view taken along the line F-F'
of FIG. 3.
[0035] FIG. 5D is a cross-sectional view taken along the line G-G'
of FIG. 3.
[0036] FIG. 6 is a drawing illustrating a part of FIG. 3 in three
dimensions.
[0037] FIG. 7 is a drawing illustrating a part of a semiconductor
chip in accordance with other example embodiments.
[0038] FIG. 8 is a top plan view illustrating a part of a
semiconductor chip in accordance with example embodiments.
[0039] FIG. 9A is a cross-sectional view taken along the line A-A'
of FIG. 8.
[0040] FIG. 9B is a cross-sectional view taken along the line B-B'
of FIG. 8.
[0041] FIG. 9C is a cross-sectional view taken along the line C-C'
of FIG. 8.
[0042] FIG. 10A is a cross-sectional view taken along the line D-D'
of FIG. 8.
[0043] FIG. 10B is a cross-sectional view taken along the line E-E'
of FIG. 8.
[0044] FIG. 10C is a cross-sectional view taken along the line F-F'
of FIG. 8.
[0045] FIG. 11 is a drawing illustrating a part of FIG. 8 in three
dimensions.
[0046] FIG. 12 is a drawing illustrating a part of a semiconductor
chip in accordance with other example embodiments.
[0047] FIG. 13 is a top plan view illustrating a part of a
semiconductor chip in accordance with example embodiments.
[0048] FIG. 14A is a cross-sectional view taken along the line A-A'
of FIG. 13.
[0049] FIG. 14B is a cross-sectional view taken along the line B-B'
of FIG. 13.
[0050] FIG. 14C is a cross-sectional view taken along the line C-C'
of FIG. 13.
[0051] FIG. 15A is a cross-sectional view taken along the line D-D'
of FIG. 13.
[0052] FIG. 15B is a cross-sectional view taken along the line E-E'
of FIG. 13.
[0053] FIG. 15C is a cross-sectional view taken along the line F-F'
of FIG. 13.
[0054] FIG. 16 is a drawing illustrating a part of FIG. 13 in three
dimensions.
DETAILED DESCRIPTION
[0055] Embodiments of inventive concepts will be described more
fully hereinafter with reference to the accompanying drawings, in
which embodiments of the invention are shown. This inventive
concept may, however, be embodied in many different forms and
should not be construed as limited to the embodiments set forth
herein. Rather, these embodiments are provided so that this
disclosure will be thorough and complete, and will fully convey the
scope to those skilled in the art. In the drawings, the size and
relative sizes of layers and regions may be exaggerated for
clarity. Like numbers refer to like elements throughout.
[0056] It will be understood that when an element is referred to as
being "connected" or "coupled" to another element, it can be
directly connected or coupled to the other element or intervening
elements may be present. In contrast, when an element is referred
to as being "directly connected" or "directly coupled" to another
element, there are no intervening elements present. Other words
used to describe the relationship between elements or layers should
be interpreted in a like fashion (e.g., "between" versus "directly
between," "adjacent" versus "directly adjacent," ""on" versus
"directly on") As used herein, the term "and/or" includes any and
all combinations of one or more of the associated listed items and
may be abbreviated as "/".
[0057] It will be understood that, although the terms first,
second, etc. may be used herein to describe various elements,
components, regions, layers and/or sections, these elements,
components, regions, layers and/or sections should not be limited
by these terms. These terms are only used to distinguish one
element from another. For example, a first region/layer could be
termed a second region/layer, and, similarly, a second region/layer
could be termed a first region/layer without departing from the
teachings of the disclosure.
[0058] The terminology used herein is for the purpose of describing
particular embodiments only and is not intended to be limiting of
the invention. As used herein, the singular forms "a", "an" and
"the" are intended to include the plural forms as well, unless the
context clearly indicates otherwise. It will be further understood
that the terms "comprises" and/or "comprising," or "includes"
and/or "including" when used in this specification, specify the
presence of stated features, regions, integers, steps, operations,
elements, and/or components, but do not preclude the presence or
addition of one or more other features, regions, integers, steps,
operations, elements, components, and/or groups thereof.
Expressions such as "at least one of" when preceding a list of
elements, modify the entire list of elements and do not modify the
individual elements of the list.
[0059] FIG. 1 is a top plan view of a semiconductor chip 100 in
accordance with example embodiments. The semiconductor chip 100 may
be mounted on a package substrate or another semiconductor chip by
a flip chip method. A plurality of pads may be provided on one side
of the semiconductor chip 100 and the plurality of pads may include
first pads 112 to which a ground voltage is supplied, second pads
122 to which a power supply voltage is supplied, and third pads 132
to which a signal is input or from which a signal is output. For
example, a signal being input or output through the third pads 132
may be a data signal, or a control signal that controls the
semiconductor chip 100.
[0060] The first pads 112 may be connected to at least one first
bump area 140_1 through first conductive lines 110. Although one
first bump area 140_1 is illustrated in FIG. 1, a plurality of
first bump areas may be further provided. The second pads 122 may
be connected to at least one second bump area 140_2 through second
conductive lines 120. Although one second bump area 140_2 is
illustrated in FIG. 1, a plurality of second bump areas may be
further provided. The third pads 132 may be connected to at least
one third bump area 140_3 through third conductive lines 130.
Although one third bump area 140_3 is illustrated in FIG. 1, a
plurality of third bump areas may be further provided.
[0061] A first bump (not illustrated) may be connected to the first
bump area 140_1. For example, the first bump may connect, to the
semiconductor chip 100, another semiconductor chip (not
illustrated) or a package substrate (not illustrated) that is
connected to the semiconductor chip 100 by a flip chip method. That
is, a ground voltage provided through the first bump area 140_1 may
be transmitted to the first pads 112 through the first conductive
lines 110.
[0062] A second bump (not illustrated) may be connected to the
second bump area 140_2. For example, the second bump may connect,
to the semiconductor chip 100, another semiconductor chip (not
illustrated) or a package substrate (not illustrated) that is
connected to the semiconductor chip 100 by a flip chip method. That
is, a ground voltage provided through the second bump area 140_2
may be transmitted to the second pads 122 through the second
conductive lines 120.
[0063] A third bump (not illustrated) may be connected to the third
bump area 140_3. For example, the third bump may connect, to the
semiconductor chip 100, another semiconductor chip (not
illustrated) or a package substrate (not illustrated) that is
connected to the semiconductor chip 100 by a flip chip method. That
is, a ground voltage provided through the third bump area 140_3 may
be transmitted to the third pads 132 through the third conductive
lines 130.
[0064] A connection relation between the bump areas 140_1, 140_2,
140_3 and the conductive lines 110, 120, 130 illustrated in FIG. 1
is only illustrative and is not limited thereto. An example method
of arranging the first through third pads 112, 122, 132 will be
described in detail with reference to the drawings below.
[0065] FIG. 2 is a drawing illustrating an enlarged area of FIG. 1.
For brevity of description, conductive lines connecting the bump
areas 140_1, 140 2, 140_3 and the pads 112, 122, 132 are omitted in
FIG. 2. Ring type conductive rings 116 and 126 disposed inside the
semiconductor chip 100 are illustrated as an example.
[0066] Referring to FIG. 2, the semiconductor chip 100 may include
a plurality of input/output units. Thirteen input/output units are
illustrated in FIG. 2 as an illustration, however, exemplary
embodiments are not limited thereto. Each input/output unit may
include at least one pad. For example, a first input/output unit
(I/O unit_1) is illustrated to include one second pad 122 and one
third pad 132. In particular, an input/output unit including the
third pad 132 through which a signal is input or output among the
input/output units (I/O unit) may further include an input/output
buffer (not illustrated) within the underlying semiconductor chip
100 that receives or outputs the signal. A ground voltage supplied
through the first pads 112 and first additional pads 112A and a
power supply voltage supplied through the second pads 122 and
second additional pads 122A are supplied to the input/output buffer
to prevent an increase of the simultaneous switching noise
(SSN).
[0067] The first pads 112 may be disposed along a third row Row3
which is parallel to a second direction D2. The first additional
pads 112A may be disposed along a first row Row1 which is parallel
to the second direction D2. The second pads 122 may also be
disposed along the third row Row3 which is parallel to the second
direction D2. The second additional pads 122A may be disposed along
a second row Row2 which is parallel to the second direction D2. The
third pads 132 may be disposed along the third row Row3.
[0068] Although the first pad 112, the second pad 122 and the third
pad 132 are illustrated to be disposed along the same row (e.g.,
Row3), the first pad 112, the second pad 122 and the third pad 132
may not be disposed in the same row as long as the first pad 112
and the second pad 122 are disposed on rows different from rows on
which the first additional pad 112A and the second additional pad
122A are disposed.
[0069] The first conductive ring 116 may be disposed inside the
semiconductor chip 100 under the first row Row1. That is, the first
conductive ring 116 may extend along the first row Row1. Although
only a part of the first conductive ring 116 is illustrated in FIG.
2, the first conductive ring 116 may be disposed to form a closed
curve inside the semiconductor chip 100. The first conductive ring
116 may be connected to the first pad 112 and the first additional
pad 112A through internal interconnection lines (not
illustrated).
[0070] The second conductive ring 126 may be disposed inside the
semiconductor chip 100 under the second row Row2. That is, the
second conductive ring 116 may extend along the second row Row2.
Although only a part of the second conductive ring 126 is
illustrated in FIG. 2, the second conductive ring 126 may be
disposed to form a closed curve inside the semiconductor chip 100.
The second conductive ring 126 may be connected to the second pad
122 and the second additional pad 122A through internal
interconnection lines (not illustrated).
[0071] According to example embodiments, an input/output unit
including the third pad 132 to receive a signal from the outside
may include the first pad 112 and/or the second pad 122. In this
case, the first pad 112 and the second pad 122 may be disposed on a
row different from a row along which the third pad 132 is disposed.
That is, at least two pads may be provided to a single input/output
unit and in this case, at least two pads may be disposed along a
first direction D1.
[0072] To prevent a short that may occur between the two conductive
rings 116 and 126 connected to the pads, a direction along which
the at least two pads are disposed on the single input/output unit
may not exactly coincide with the first direction D1. According to
example embodiments, instead of providing a separate input/output
unit to supply a ground voltage and a power supply voltage, the
first additional pad 112A and the second additional pad 122A may be
disposed in an input/output unit in which the third pad 132 is
already disposed. As a result, a ground voltage and a power supply
voltage may be stably supplied to an input/output unit without
increasing the number of a pad to which a ground voltage and a
power supply voltage are supplied and a chip size may be
reduced.
[0073] FIG. 3 is a top plan view illustrating a part of a
semiconductor chip 100 in accordance with example embodiments. FIG.
4A is a cross-sectional view taken along the line A-N of FIG. 3.
FIG. 4B is a cross-sectional view taken along the line B-B' of FIG.
3. FIG. 4C is a cross-sectional view taken along the line C-C' of
FIG. 3. FIG. 5A is a cross-sectional view taken along the line D-D'
of FIG. 3. FIG. 5B is a cross-sectional view taken along the line
E-E' of FIG. 3. FIG. 5C is a cross-sectional view taken along the
line F-F' of FIG. 3. FIG. 5D is a cross-sectional view taken along
the line G-G' of FIG. 3.
[0074] Referring to FIGS. 3 through 5D, first additional pads 112A
may be disposed along a first row Row1. A first conductive ring 116
may be disposed inside the semiconductor chip 100 under first
additional pads 112A. The first additional pads 112A may be
connected to the first conductive ring 116 through first additional
internal interconnection lines 114A. The first conductive ring 116
may be disposed inside the semiconductor chip 100 at a depth of h1.
As illustrated in FIG. 4A, the first additional pads 112A may be
connected to the first conductive ring 116 to have a minimum
distance therebetween. That is, each of the first additional pads
112A may be connected to the first conductive ring 116 to have a
distance of h1 therebetween.
[0075] Second additional pads 122A may be disposed along a second
row Row2. A second conductive ring 126 may be disposed inside the
semiconductor chip 100 under the second additional pads 122A. The
second additional pads 122A may be connected to the second
conductive ring 126 through second additional internal
interconnection lines 124A. The second conductive ring 126 may be
disposed inside the semiconductor chip 100 at a depth of h2. As
illustrated in FIG. 4B, the second additional pads 122A may be
connected to the second conductive ring 126 to have a minimum
distance therebetween. That is, each of the second additional pads
122A may be connected to the second conductive ring 126 to have a
distance of h2 therebetween. For example, a value of hl may be the
same as a value of h2 or may be different from the value of h2.
[0076] Third pads 132 may be disposed along a third row Row3. Third
internal interconnection lines 134 may connect the third pads 132
to a logical circuit (not illustrated), and a signal received
through the third pads 132 may be transmitted to the logical
circuit through the third internal interconnection lines 134.
Although the third internal interconnection lines 134 are
illustrated to penetrate the semiconductor chip 100 in FIG. 4C,
this is for brevity of description and the third internal
interconnection lines 134 may be connected to the logical circuit
disposed inside the semiconductor chip 100.
[0077] The first pad 112 and the second pad 122 may be disposed
along the third row Row3. A first internal interconnection line 114
may connect the first pad 112 to the first conductive ring 116. To
prevent a short that may occur between the first internal
interconnection line 114 and the second conductive ring 126, the
first internal interconnection line 114 may be disposed in a shape
of "U", as illustrated in FIG. 5B. A second internal
interconnection line 124 may connect the second pad 122 to the
second conductive ring 126. To prevent a short that may occur
between the second internal interconnection line 124 and the first
conductive ring 116, the second internal interconnection line 124
may be disposed in the shape of "U", as illustrated in FIG. 5D.
[0078] FIG. 6 is a drawing illustrating a part of FIG. 3 in three
dimensions.
[0079] Referring to FIG. 6, the first additional pad 112A is
disposed on the first row Row1 and the first conductive ring 116 is
disposed inside the semiconductor chip 100 under the first
additional pad 112A. The first additional pad 112A is connected to
the first conductive ring 116 through the first additional internal
interconnection line 114A. For example, the first additional pad
112A may be connected to the first conductive ring 116 to have a
minimum distance therebetween. The first pad 112 is disposed on the
third row Row3. The first pad 112 is connected to the first
conductive ring 116 by the first internal interconnection line 114
having a U'' shape to prevent a short that may occur between the
first conductive ring 116 and the second conductive ring 126.
However, this is only an example, and a shape of the first internal
interconnection line 114 is not limited to a "U" shape and may have
various shapes that may prevent a short between the first
conductive ring 116 and the second conductive ring 126.
[0080] The second additional pad 122A is disposed on the second row
Row2 and the second conductive ring 126 is disposed inside the
semiconductor chip 100 under the second additional pad 122A. The
second additional pad 122A is connected to the second conductive
ring 126 through the second additional internal interconnection
line 124A. For example, the second additional pad 122A may be
connected to the second conductive ring 126 to have a minimum
distance therebetween. The second pad 122 is disposed on the third
row Row3. The second pad 122 is connected to the second conductive
ring 126 by the second internal interconnection line 124 having a
"U" shape to prevent a short that may occur between the first
conductive ring 116 and the second conductive ring 126. However,
this is only an example, and a shape of the second internal
interconnection line 124 is not limited to a "U" shape and may have
various shapes that may prevent a short.
[0081] As described above, the first additional pad 112A and the
first pad 112 that are disposed on the first row Row1 and the third
row Row3, respectively, may be connected to the first conductive
ring 116, and the second additional pad 122A and the second pad 122
that are disposed on the second row Row2 and the third row Row3,
respectively, may be connected to the second conductive ring 126.
The first conductive ring 116 and the second conducive ring 126 may
be connected to an electrostatic discharge circuit (ESD) circuit
(not illustrated) disposed inside the semiconductor chip 100. The
ESD circuit may be connected to a logical circuit (not illustrated)
disposed inside the semiconductor chip 100 to stably supply power
to the logical circuit. The third pads 132 may be connected to the
logical circuit disposed inside the semiconductor chip 100 through
the third internal interconnection lines 134.
[0082] According to the example embodiments, instead of providing a
separate input/output unit to supply a ground voltage and a power
supply voltage, the first additional pad 112A and/or the second
additional pad 122A may be disposed in an input/output unit in
which the third pad 132 is already disposed. In this case, the
first additional pad 112A and/or the second additional pad 122A are
disposed on the first row Row1 and/or the second row Row2 of the
input/output unit in which the third pad is disposed. Thus,
according to example embodiments, since a ground voltage and a
power supply voltage can be sufficiently supplied without
increasing the number of pads for supplying the ground voltage and
the power supply voltage, an SSN of a signal being input through
the third pad 132 may be reduced. Additionally, according to
example embodiments, a separate input/output unit is not included
to supply the ground voltage and the power supply voltage, a chip
size may be reduced.
[0083] FIG. 7 is a drawing illustrating a part of a semiconductor
chip in accordance with other example embodiments. As described
above, a ground voltage may be supplied through the first pads 212,
a power supply voltage may be supplied through the second pads 222,
and signals may be provided through the third pads 232. For brevity
of description, conductive lines connecting the bump areas 240_1,
240 2, 240_3 and the pads 212, 212, 232 are omitted. The conductive
rings 216 and 226 of a ring type being disposed inside the
semiconductor chip are illustrated as an example.
[0084] Referring to FIG. 7, the semiconductor chip may include a
plurality of input/output unit (I/O unit). Thirteen input/output
units are illustrated in FIG. 7 as an illustration, however,
exemplary embodiments are not limited thereto. Each input/output
unit may include at least one pad. For example, a fifth
input/output unit (I/O unit_5) may include one first additional pad
212A and one second pad 222. An input/output unit including the
third pad 232 through which a signal is input and/or output among
the input/output units (I/O units) may further include an
input/output buffer (not illustrated) inside the underlying
semiconductor chip.
[0085] The first pads 212 may be disposed along the first row Row1
parallel to the second direction D2. The second pads 222 may be
disposed along the second row Row2 parallel to the second direction
D2. The third pads 232 may be disposed along the third row Row3
parallel to the second direction D2. The first additional pad 212A
may be disposed along the third row Row3 along which the third pads
232 are disposed. However, the first additional pad 212A may not be
disposed on the third row Row3 as long as the first additional pad
212A is disposed on a row different from the first row Row1 and the
second row Row2.
[0086] The first conductive ring 216 may be disposed inside the
semiconductor chip under the first row Row1. That is, the first
conductive ring 216 may extend along the first row Row1. Although
only a part of the first conductive ring 216 is illustrated in FIG.
7, the first conductive ring 216 may be disposed to form a closed
curve inside the semiconductor chip. The first conductive ring 216
may be connected to the first pads 212 through internal
interconnection lines (not illustrated).
[0087] The second conductive ring 226 may be disposed inside the
semiconductor chip under the second row Row2. That is, the second
conductive ring 226 may extend along the second row Row2.
Similarly, although only a part of the second conductive ring 226
is illustrated in FIG. 7, the second conductive ring 226 may be
disposed to form a closed curve inside the semiconductor chip. The
second conductive ring 226 may be connected to the second pads 222
through internal interconnection lines (not illustrated).
[0088] According to example embodiments, instead of providing a
separate input/output unit to include pads that receive a ground
voltage, a pad that receives a ground voltage may be disposed in an
input/output unit in which a pad that receives a power supply
voltage is disposed. For example, referring to FIG. 7, the first
additional pad 212A is disposed in the fifth input/output unit (I/O
Unit_5) separately provided to receive a power supply voltage. In
this case, instead of disposing a pad in a separate input/output
unit to receive a ground voltage, the first additional pad 212A may
be disposed inside the fifth input/output unit (I/O Unit_5). An SSN
of a signal being input through the third pad 232 may be reduced by
disposing the first additional pad 212A and the second pad 222 in
one input/output unit. Also, a size of the semiconductor chip may
be reduced.
[0089] FIG. 8 is a top plan view illustrating a part of a
semiconductor chip in accordance with example embodiments. FIG. 9A
is a cross-sectional view taken along the line A-N of FIG. 8. FIG.
9B is a cross-sectional view taken along the line B-B' of FIG. 8.
FIG. 9C is a cross-sectional view taken along the line C-C' of FIG.
8. FIG. 10A is a cross-sectional view taken along the line D-D' of
FIG. 8. FIG. 10B is a cross-sectional view taken along the line
E-E' of FIG. 8. FIG. 10C is a cross-sectional view taken along the
line F-F' of FIG. 8.
[0090] Referring to FIGS. 8 through 10C, first pads 212 may be
disposed along a first row Row1. A first conductive ring 216 may be
disposed inside a semiconductor chip 200 under the first pads 212.
The first pads 212 may be connected to the first conductive ring
216 through first internal interconnection lines 214. The first
conductive ring 216 may be disposed inside the semiconductor chip
200 at a depth of hl. As illustrated in FIG. 9A, the first pads 212
may be connected to the first conductive ring 216 to have a minimum
distance therebetween. That is, each of the first pads 212 may be
connected to the first conductive ring 216 to have a length of hl
therebetween.
[0091] Some of the first pads (or first additional pads 212A) may
be disposed along a third row Row3. A first additional internal
interconnection line 214A may connect the first additional pad 212A
to the first conductive ring 216. The first additional internal
interconnection line 214A, as illustrated in FIG. 10B, may be
disposed in the form of a "U" character.
[0092] Second pads 222 may be disposed along a second row Row2. A
second conductive ring 226 may be disposed inside the semiconductor
chip 200 under the second pads 222. The second pads 222 may be
connected to the second conductive ring 226 through second internal
interconnection lines 224. The second conductive ring 226 may be
disposed inside the semiconductor chip 200 at a depth of h2. As
illustrated in FIG. 9B, the second pads 222 may be connected to the
second conductive ring 226 to have a minimum distance therebetween.
That is, each of the second pads 222 may be connected to the second
conductive ring 226 to have a length of h2 therebetween. A value of
h1 and a value of h2 may be the same or different from each
other.
[0093] Third pads 232 may be disposed along a third row Row3. Third
internal interconnection lines (not illustrated) may connect the
third pads 232 to a logical circuit (not illustrated) and a signal
inputted through the third pads 232 may be transmitted to the
logical circuit through the third internal interconnection
lines.
[0094] FIG. 11 is a drawing illustrating a part of FIG. 8 in three
dimensions.
[0095] Referring to FIG. 11, the first pad 212 is disposed on the
first row Row1 and the first conductive ring 216 is disposed inside
the semiconductor chip 200 under the first pad 212. The first pad
212 is connected to the first conductive ring 216 to have a minimum
distance therebetween through the first internal interconnection
line 214. The first additional pad 212A is disposed on the third
row Row3. The first additional pad 212A is connected to the first
conductive ring 216 by a first additional internal interconnection
line 214A having a "U" character shape. A shape of the first
additional internal interconnection line 214A is not limited to the
"U" character and the first additional internal interconnection
line 214A may have various shapes.
[0096] The second pads 222 are disposed along the second row Row2
and the second conductive ring 226 is disposed inside the
semiconductor chip 200 under the second pad 222. The second pad 222
and the second conductive ring 226 are connected to each other by
the second internal interconnection line 224 to have a minimum
distance therebetween.
[0097] Although not shown in FIG. 11, the third pads 232 may be
disposed along the third row Row3 and the third pads 232 may be
connected to a logical circuit (not illustrated) through the third
internal interconnection lines 234.
[0098] As described above, the first pad 212 and the first
additional pad 212A that are disposed on the first row Row1 and the
third row Row3, respectively, are connected to the first conductive
ring 216 and the second pad 222 disposed on the third row Row3 may
be connected to the second conductive ring 216. The first
conductive ring 216 and the second conductive ring 226 may be
connected to an ESD circuit (not illustrated) disposed inside the
semiconductor chip 200. The ESD circuit may be connected to the
logical circuit disposed inside the semiconductor chip 200 to
stably supply a power supply voltage to the logical circuit. The
third pads 232 may be connected to the logical circuit disposed
inside the semiconductor chip 200 through the third internal
interconnection lines 234.
[0099] According to example embodiments, instead of providing a
separate input/output unit to supply a ground voltage, the first
additional pad 212A may be disposed in an input/output unit (e.g.,
I/O Unit_5) in which the second pad 222 to supply a power supply
voltage is already disposed. That is, according to example
embodiments, since a power supply voltage can be sufficiently
supplied without providing a separate input/output unit for
supplying a ground voltage, an SSN of a signal being input through
the third pad 232 may be reduced. Additionally, a separate
input/output unit is not included to supply a ground voltage and a
power supply voltage, a chip size may be reduced.
[0100] FIG. 12 is a drawing illustrating a part of a semiconductor
chip in accordance with other example embodiments. As described
above, a ground voltage is supplied through first pads 312, a power
supply voltage is supplied through second pads 322 and signals may
be provided through third pads 332. For brevity of description,
conductive lines that connect bump areas 340_1, 340_2, 340_3 and
the pads 312, 322, 332 are omitted. Conductive rings 316 and 326
being disposed inside the semiconductor chip are illustrated as an
example.
[0101] Referring to FIG. 12, the semiconductor chip may include a
plurality of input/output units (I/O units). Each of the
input/output units may include at least one pad. For example, the
fifth input/output unit (I/O unit_5) is illustrated to include one
first pad 312 and one second pad 322A. An input/output unit
including the third pad 332 through which a signal is input and/or
output among the input/output units (I/O unit) may further include
an input/output buffer (not illustrated) inside the underlying
semiconductor chip.
[0102] The first pads 312 may be disposed along a first row Row1
parallel to a second direction D2. The second pads 322 may be
disposed along a second row Row2 parallel to a second direction D2.
Some of the second pads (or second additional pads 322A) may be
disposed along a third row Row3 along which the third pads 332 are
disposed. The third pads 332 may be disposed along the third row
Row3 parallel to the second direction D2. However, the second
additional pad 322A may not be disposed on the third row Row3 as
long as the second additional pad 322A is disposed on a row
different from the first row Row1 and the second row Row2.
[0103] A first conductive ring 316 may be disposed inside the
semiconductor chip under the first row Row1. That is, the first
conductive ring 316 may extend along the first row Row1. Although
only a part of the first conductive ring 316 is illustrated, the
first conductive ring 316 may be disposed to form a closed curve
inside the semiconductor chip. The first conductive ring 316 may be
connected to the first pad 312 through internal interconnection
lines (not illustrated).
[0104] The second conductive ring 326 may be disposed inside the
semiconductor chip under the second row Row2. That is, the second
conducive ring 326 may extend along the second row Row2. Although
only a part of the second conductive ring 326 is illustrated, the
second conductive ring 326 may be disposed to form a closed curve
inside the semiconductor chip. The second conductive ring 326 may
be connected to the second pad 322 through internal interconnection
lines (not illustrated).
[0105] According to the example embodiments, instead of providing a
separate input/output unit to include pads receiving a power supply
voltage, a pad that receives a power supply voltage may be disposed
in an input/output unit in which a pad that receives a ground
voltage is disposed. For example, referring to FIG. 12, the second
additional pad 322A is disposed in the fifth input/output unit (I/O
Unit_5) separately provided to receive a ground voltage. That is,
instead of providing a separate input/output unit to receive a
power supply voltage, the second additional pad 322A may be
disposed inside the fifth input/output unit (I/O Unit_5) in which a
pad that receives a ground voltage is disposed. An SSN of a signal
being input through the third pad 332 may be reduced by disposing
the first pad 312 and the second additional pad 322A in one
input/output unit. Also, a size of the semiconductor chip may be
reduced.
[0106] FIG. 13 is a top plan view illustrating a part of a
semiconductor chip in accordance with example embodiments. FIG. 14A
is a cross-sectional view taken along the line A-A' of FIG. 13.
FIG. 14B is a cross-sectional view taken along the line B-B' of
FIG. 13. FIG. 14C is a cross-sectional view taken along the line
C-C' of FIG. 13. FIG. 15A is a cross-sectional view taken along the
line D-D' of FIG. 13. FIG. 15B is a cross-sectional view taken
along the line E-E' of FIG. 13. FIG. 15C is a cross-sectional view
taken along the line F-F' of FIG. 13.
[0107] Referring to FIGS. 13 through 15C, first pads 312 may be
disposed along a first row Row1. A first conductive ring 316 may be
disposed inside a semiconductor chip 300 under the first pads 312.
The first pads 312 may be connected to the first conductive ring
316 through first internal interconnection lines 314. The first
conductive ring 316 may be disposed inside the semiconductor chip
300 at a depth of h1. As illustrated in FIG. 14A, the first pads
312 may be connected to the first conductive ring 316 to have a
minimum distance therebetween. That is, each of the first pads 312
may be connected to the first conductive ring 316 to have a length
of hl therebetween.
[0108] Second pads 322 may be disposed along a second row Row2. A
second conductive ring 326 may be disposed inside the semiconductor
chip 300 under the second pads 322. The second pads 322 may be
connected to the second conductive ring 326 through second internal
interconnection lines 324. The second conductive ring 326 may be
disposed inside the semiconductor chip 300 to a depth of h2. As
illustrated in FIG. 14B, the second pads 322 may be connected to
the second conductive ring 326 to have a minimum distance
therebetween. That is, each of the second pads 322 may be connected
to the second conductive ring 326 to have a length of h2
therebetween.
[0109] In this case, some of the second pads (or second additional
pads 322A) may be disposed along a third row Row3. A second
additional internal interconnection line 324A may connect the
second additional pad 322A to the second conductive ring 326. As
illustrated in FIG. 15B, the second additional internal
interconnection line 324A may be disposed in the form of an "L"
character.
[0110] Third pads 332 may be disposed along the third row Row3.
Third internal interconnection lines (not illustrated) may connect
the third pads 332 to a logical circuit (not illustrated) and a
signal input through the third pads 332 may be transmitted to the
logical circuit through the third internal interconnection
lines.
[0111] FIG. 16 is a drawing illustrating a part of FIG. 13 in three
dimensions.
[0112] Referring to FIG. 16, the first pads 312 is disposed along
the first row Row1 and the first conductive ring 316 is disposed
inside the semiconductor chip 300 under the first pad 312. The
first pad 312 is connected to the first conductive ring 316 to have
a minimum distance therebetween through the first internal
interconnection line 314.
[0113] Although not shown in FIG. 16, the second pads may be
disposed along the second row and the second conductive ring may be
disposed inside the semiconductor chip 300 under the second pad.
The second pad and the second conductive ring may be connected to
each other by the second internal interconnection line to have a
minimum distance therebetween.
[0114] The second additional pad 322A is disposed on the third row
Row3. The second additional pad 322A is connected to the second
conductive ring 326 by a second additional internal interconnection
line 324A having an "L" character shape. A shape of the second
additional internal interconnection line 324A is not limited to the
"L" character and the second additional internal interconnection
line 324A may have various shapes.
[0115] Although not shown in FIG. 16, the third pads may be
disposed along the third row Row3 and the third pads may be
connected to a logical circuit (not illustrated) through the third
internal interconnection lines.
[0116] The first pad 312 disposed on the first row Row1 is
connected to the first conductive ring 316, and the second
additional pad 322A disposed on the third row Row3 is connected to
the second conductive ring 326. The first conductive ring 316 and
the second conductive ring 326 may be connected to an ESD circuit
(not illustrated) disposed inside the semiconductor chip 300. The
ESD circuit may be connected to the logical circuit disposed inside
the semiconductor chip 300 to stably supply a power supply voltage
to the logical circuit. The third pads may be connected to the
logical circuit disposed inside the semiconductor chip 300 by the
third internal interconnection lines.
[0117] According to the example embodiments, instead of providing a
separate input/output unit to supply a power supply voltage, the
second additional pad 322A may be disposed in an input/output unit
(e.g., I/O Unit_5) where the first pad 312 for supplying a ground
voltage is disposed. That is, since a power supply voltage can be
sufficiently supplied without providing a separate input/output
unit for supplying a supply voltage, an SSN of a signal being input
through the third pad 332 may be reduced. Additionally, since a
separate input/output unit for supplying a ground voltage and a
power supply voltage is omitted, a chip size may be reduced.
[0118] According to the example embodiments, a method of disposing
pads of a semiconductor chip capable of stably supplying a power
supply voltage may be provided.
[0119] According to the example embodiments, a method of disposing
pads of a semiconductor chip capable of reducing a chip size may be
provided.
[0120] Having described the exemplary embodiments, it is further
noted that it is readily apparent to those of reasonable skill in
the art that various modifications may be made without departing
from the spirit and scope which is defined by the metes and bounds
of the appended claims.
* * * * *