U.S. patent application number 15/643742 was filed with the patent office on 2019-01-10 for method for manufacturing fully aligned via structures having relaxed gapfills.
The applicant listed for this patent is GLOBALFOUNDRIES INC.. Invention is credited to Nicholas V. LiCausi, Errol Todd Ryan.
Application Number | 20190013236 15/643742 |
Document ID | / |
Family ID | 64872513 |
Filed Date | 2019-01-10 |
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United States Patent
Application |
20190013236 |
Kind Code |
A1 |
LiCausi; Nicholas V. ; et
al. |
January 10, 2019 |
METHOD FOR MANUFACTURING FULLY ALIGNED VIA STRUCTURES HAVING
RELAXED GAPFILLS
Abstract
The present disclosure generally relates to semiconductor
structures and, more particularly, to fully aligned via structures
having relaxed gapfills and methods of manufacture. The method
includes: selectively depositing a capping material on a conductive
material within a plurality of interconnect structures to form
capped interconnect structures; depositing at least one insulator
material over the capped interconnect structures; forming a fully
aligned via structure through the at least one insulator material
to expose the capping material; filling the fully aligned via
structure with an alternative metal; and depositing a metal
material on the alternative metal in the fully aligned via
structure.
Inventors: |
LiCausi; Nicholas V.;
(Watervliet, NY) ; Ryan; Errol Todd; (Clifton
Park, NY) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
GLOBALFOUNDRIES INC. |
Grand Cayman |
|
KY |
|
|
Family ID: |
64872513 |
Appl. No.: |
15/643742 |
Filed: |
July 7, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/76807 20130101;
H01L 21/76837 20130101; H01L 23/53238 20130101; H01L 23/5226
20130101; H01L 23/528 20130101; H01L 23/53209 20130101; H01L
21/76879 20130101; H01L 21/76897 20130101; H01L 21/76843 20130101;
H01L 21/76834 20130101; H01L 21/76883 20130101; H01L 21/76849
20130101; H01L 21/76877 20130101; H01L 21/76805 20130101 |
International
Class: |
H01L 21/768 20060101
H01L021/768; H01L 23/522 20060101 H01L023/522; H01L 23/528 20060101
H01L023/528; H01L 23/532 20060101 H01L023/532 |
Claims
1. A method, comprising: selectively depositing a capping material
on a conductive material within a plurality of interconnect
structures to form capped interconnect structures; depositing at
least one insulator material over the capped interconnect
structures; forming a fully aligned via structure through the at
least one insulator material to expose the capping material;
filling the fully aligned via structure with an alternative metal;
and depositing a metal material on the alternative metal in the
fully aligned via structure wherein the at least one insulator
material is a liner material over the metal material and an
interlevel dielectric layer.
2. The method of claim 1, wherein the conductive material is a
Cu.
3. The method of claim 1, wherein the capping material is Ru.
4. The method of claim 1, wherein the capping material is Co.
5. The method of claim 1, wherein the alternative metal is Ru.
6. The method of claim 5, wherein the alternative metal is Co.
7. (canceled)
8. The method of claim 1, wherein the capping material and the
metal material are the same material.
9. A method, comprising: forming a plurality of interconnect
structures; recessing the interconnect structures; selectively
depositing conductive capping material in the recesses in direct
contact with metal material of the interconnect structures; forming
a conformal dielectric layer over the conductive capping material;
forming a gapfill layer over the conformal dielectric layer;
forming a fully aligned via structure through the gapfill layer and
the dielectric layer, exposing the conductive capping material;
filling the fully aligned via structure with an alternative metal
in direct electrical contact with the conductive capping material;
and depositing a metal fill material in an upper interconnect layer
in direct electrical contact with the alternative metal in the
fully aligned via structure.
10. The method of claim 9, wherein the conductive capping material
and the alternative metal are composed of Ru.
11. The method of claim 9, wherein the conductive capping material
and the alternative metal are composed of Co.
12. The method of claim 9, wherein the conductive capping material
is a different metal from the alternative metal in the fully
aligned via structure.
13. The method of claim 9, wherein the gapfill layer is an ultra
low-k dielectric.
14. The method of claim 9, wherein the recesses have a depth in the
range of 5 to 12 nm.
15. The method of claim 9, wherein the metal material of the
interconnect structures is Cu.
16.-20. (canceled)
21. The method of claim 8, wherein the liner material is made of
SiN, SiCN, SiNO or SiC.
22. The method of claim 21, wherein the liner material has a
thickness in a range of 3 nm to 10 nm.
23. The method of claim 22, further comprising depositing a
sacrificial layer over the at least one insulator material prior to
forming the fully aligned via structure.
24. The method of claim 23, wherein further comprising covering the
sacrificial layer with a hardmask prior to forming the fully
aligned via structure.
25. The method of claim 24, wherein the hardmask is a TiN
material.
26. The method of claim 25, wherein the fully aligned via structure
is formed through the interlevel dielectric layer, the sacrificial
layer, the TiN material and the liner material.
Description
FIELD OF THE INVENTION
[0001] The present disclosure generally relates to semiconductor
structures and, more particularly, to fully aligned via structures
having relaxed gapfills and methods of manufacture.
BACKGROUND
[0002] A via is an electrical connection between wiring structures
(e.g., wiring layers) in a physical electronic circuit that goes
through the plane of one or more adjacent layers. For example, in
integrated circuit design, a via is a small opening in an
insulating oxide layer that allows a conductive connection between
different wiring layers. A via connecting the lowest layer of metal
to diffusion or poly is typically called a "contact".
[0003] Fully aligned vias can have challenging integration issues.
For example, gapfill of traditional ultra low-k (ULK) materials in
the topography is challenging. A reason is that due to the
relatively high aspect ratio of topography at advanced technology
nodes of 7 nm and beyond, standard ULK materials form voids when
deposited and/or cured, which prevents the filling of the
topography.
[0004] One way to alleviate this gapfill problem is to reduce the
recess depth of the fully aligned via structure. However, this
cannot be done without minimum insulator concerns. The minimum
insulator is a minimum space between two neighboring lines, and
pertains primarily to copper (Cu) to Cu separation in the line and
via structures. Specifically, the minimum insulator must be above a
certain tolerance in order to ensure the electric field between the
different conductors does not exceed a certain value. More
particularly, the closer the conductors (via structures) come with
respect to one another, the greater the likelihood of an
instantaneous breakdown of the dielectric occurring.
[0005] Another concern with the minimum insulator is the occurrence
of time dependent dielectric breakdown (TDDB). In TDDB, the
dielectric becomes stressed by the electric field over a period of
time, resulting in an eventual break down of the dielectric. In a
particular example, Cu ions from the via structure diffuse into the
dielectric and eventually form a filament, which creates the
dielectric breakdown.
[0006] In order to meet minimum insulator requirements, recess
depth of the skip via must be maintained at approximately 7 nm or
greater. Therefore, reducing the recess depth of the via structure
is not feasible. Another approach to address the gapfill issue is
to change the material used for the dielectric gap. However, other
materials, such as ultra low-k (ULK) materials having a dielectric
constant equal to or less than 2.7, may result in voids, or may not
have satisfactory electrical properties, amongst other
examples.
SUMMARY
[0007] In an aspect of the disclosure, a method comprises:
selectively depositing a capping material on a conductive material
within a plurality of interconnect structures; depositing at least
one insulator material over the capped interconnect structures;
forming a fully aligned via structure through the at least one
insulator material to expose the capping material; filling the
fully aligned via structure with an alternative metal; and
depositing a metal material on the alternative metal in the fully
aligned via structure.
[0008] In an aspect of the disclosure, a method comprises: forming
a plurality of interconnect structures; recessing the interconnect
structures; selectively depositing conductive capping material in
the recesses in direct contact with metal material of the
interconnect structures; forming a conformal dielectric layer over
the conductive capping material; forming a gapfill layer over the
conformal dielectric layer; forming a fully aligned via structure
in an upper interconnect layer through the gapfill layer and the
dielectric layer, exposing the conductive capping material; filling
the fully aligned via structure with an alternative metal in direct
electrical contact with the conductive capping material; and
depositing a metal fill material in the upper interconnect layer in
direct electrical contact with the alternative metal in the fully
aligned via structure.
[0009] In an aspect of the disclosure, a structure comprises: a
plurality of lower wiring structures comprising a conductive
material and a conductive capping material of a different material
than the conductive material; a via structure extending through an
upper wiring level and landing on at least one of the plurality of
lower wiring structures, the via structure comprising an
alternative metal fill material in electrical contact with the
conductive capping material; and at least one upper wiring
structure in electrical contact with the via structure, the at
least one upper wiring structure having a same material as the
conductive material of the lower wiring structures.
BRIEF DESCRIPTION OF THE DRAWINGS
[0010] The present disclosure is described in the detailed
description which follows, in reference to the noted plurality of
drawings by way of non-limiting examples of exemplary embodiments
of the present disclosure.
[0011] FIG. 1 shows an incoming structure and respective
fabrication processes in accordance with aspects of the present
disclosure.
[0012] FIG. 2 shows the structure of FIG. 1 with recessed conductor
metals, amongst other features, and respective fabrication
processes in accordance with aspects of the present disclosure.
[0013] FIG. 3 shows the structure of FIG. 2 with recessed liner and
barrier layers, amongst other features, and respective fabrication
processes in accordance with aspects of the present disclosure.
[0014] FIG. 4 shows capped interconnect structures, amongst other
features, and respective fabrication processes in accordance with
aspects of the present disclosure.
[0015] FIG. 5 shows a fully aligned via structure patterned through
an upper dielectric material extending to a capping layer, amongst
other features, and respective fabrication processes in accordance
with aspects of the present disclosure.
[0016] FIG. 6 shows the fully aligned via structure extending to a
metal capping layer, amongst other features, and respective
fabrication processes in accordance with aspects of the present
disclosure.
[0017] FIG. 7 shows the fully aligned via structure filled with a
metal, amongst other features, and respective fabrication processes
in accordance with aspects of the present disclosure.
[0018] FIG. 8 shows a filled fully aligned via structure and upper
interconnect layer, amongst other features, and respective
fabrication processes in accordance with aspects of the present
disclosure.
DETAILED DESCRIPTION
[0019] The present disclosure generally relates to semiconductor
structures and, more particularly, to fully aligned via structures
having relaxed gapfills and methods of manufacture. In embodiments,
the processes and structures provided herein implement via
structures having selective metals such as ruthenium (Ru) and/or
cobalt (Co). Advantageously, the selective metals relieve insulator
gapfill requirements for back-end-of-line (BEOL) ultra low-k (ULK)
materials.
[0020] In embodiments, the minimum insulator requirements of the
via structures can be relaxed because the critical dimension for
the minimum insulator is bordered by the selective metal material,
i.e., Ru or Co. In addition, use of the selective metals relaxes
metallization challenges by prefilling and/or filling the via
(interconnect) structure with similar metals, enabling higher
aspect ratio metal lines if desired, i.e., lower resistance.
Additionally, the use of selective metals will not intrinsically
lead to an increase in via resistance.
[0021] The structures of the present disclosure can be manufactured
in a number of ways using a number of different tools. In general,
though, the methodologies and tools are used to form structures
with dimensions in the micrometer and nanometer scale. The
methodologies, i.e., technologies, employed to manufacture the
structure of the present disclosure have been adopted from
integrated circuit (IC) technology. For example, the structures are
built on wafers and are realized in films of material patterned by
photolithographic processes on the top of a wafer. In particular,
the fabrication of the structure uses three basic building blocks:
(i) deposition of thin films of material on a substrate, (ii)
applying a patterned mask on top of the films by photolithographic
imaging, and (iii) etching the films selectively to the mask.
[0022] FIG. 1 shows an incoming structure and respective
fabrication processes in accordance with aspects of the present
disclosure. Specifically, FIG. 1 illustrates an initial structure
following BEOL metallization and CMP processes. More specifically,
the structure 100 includes a dielectric layer 105 having a
plurality of interconnect structures 110, i.e., lines, formed in
dielectric layer 105. The dielectric layer 105 can be any
interlevel dielectric (ILD) material including, e.g., a ULK
material and can be formed with multiple dielectric materials. In
embodiments, the dielectric layer 105 can be a dense oxide
material, ULK or SiN, amongst other materials.
[0023] The interconnect structures 110 can be formed by
conventional lithography and etching (reactive ion etching (RIE))
techniques followed by deposition of liner 125 and barrier 120
materials, followed by a conductive material 115 comprising a metal
or metal alloy or other via prefill material, e.g., Cu or Co. The
barrier 120 can be TaN and the liner 125 can be TiN, or materials
such as Ru and Co, amongst other examples. In embodiments, the
materials can be deposited using conventional deposition processes,
e.g., physical vapor deposition (PVD) or chemical vapor deposition
(CVD) process. Any residual material on a surface of the dielectric
layer can be removed by a chemical mechanical polishing (CMP)
processes.
[0024] FIG. 2 illustrates a selective etching process to the Cu,
i.e., the conductive material 115. As shown in FIG. 2, the
conductive material 115 is recessed without a mask by a wet
chemical etching process, as an example, to form the interconnect
structures 110'. For example, the wet etch process can use
chemistries to remove Cu. The recess formed by this process can
have a depth in a range of about 7 nm to 15 nm, and more
particularly, in a range of 5 nm to 12 nm; although other
dimensions which address gapfill and the minimum insulator concerns
are also contemplated herein.
[0025] In FIG. 3, the liner 125 and barrier 120 can be recessed by
a selective etching process. Specifically, the liner 125 and the
barrier 120 can be recessed by a wet etch process which uses
chemistries to remove the barrier 120 and liner 125, e.g., TiN,
TaN, Ru and Co, etc. In this process, the conductive material 115
will not be removed.
[0026] In FIG. 4, deposition of a metal (e.g., selective metal) is
provided in the via interconnect structure 110' to form capped
interconnect structures 110''. In embodiments, the metals 130, 130'
is a selective metal that will alleviate gapfill concerns; that is,
the deposition of the metals 130, 130' will relax minimum insulator
requirements in the top region near the via structure, where the
minimum insulator concerns are the strongest. In this way, the use
of the metals 130, 130' will prevent voids in the insulator
material, deposited over the capped interconnect structures
110''.
[0027] The metals 130, 130' can be selectively deposited, e.g.,
grown, directly on the conductive material 115 to form a cap on the
conductive material 115 (and not on the dielectric layer 105). The
selective growth of the metals 130, 130' (capping material)
directly on the conductive material 115 within the plurality of
interconnect structures 110' requires no polishing process, e.g.,
CMP. The deposition of the metals 130, 130' can be in a range of
about 3 nm to 10 nm, for example, and more particularly in a range
of about 5 nm to 12 nm to form capped interconnect structures
110''. The deposition of the metals 130, 130' can relax or
eliminate topography to a regime where traditional ULK can be used
for integration.
[0028] The metals 130, 130' can be Ru, Co, Mo, Ni and W, for
example, and should differ from the conductive material 115.
Therefore, the capped interconnect structures 110'' can have a
first conductive metal, e.g., Cu, and a second conductive metal,
e.g., Ru, Co, Mo, Ni or W. The use of the metals 130, 130' along
with the conductive material 115 such as Cu maintains a lower
resistance than solely using an alternative to Cu, like Ru or Co,
while resolving upper level dielectric gapfill and minimum
insulator concerns.
[0029] FIG. 5 shows a conformal dielectric capping layer 135
deposited over the capped (via) interconnect structures 110'',
amongst other features. The dielectric capping layer 135 can be
made of SiN, SiCN, SiNO or SiC, for example. Additionally, the
dielectric capping layer 135 can have a thickness in a range of
about 3 nm to 10 nm. The dielectric capping layer 135 can be
considered a liner material over the metals 130, 130'.
[0030] A dielectric layer 140 is deposited over the dielectric
capping layer 135. The dielectric layer 140 can be an ILD or ULK
material, for example. Further, the dielectric capping layer 135
and the dielectric layer 140 can act as an insulator material. A
sacrificial dielectric 145 is formed over the dielectric layer 140,
and is covered by a hardmask 150. The hardmask 150 can be a TiN
material deposited by any conventional deposition processes, e.g.,
physical vapor deposition (PVD) processes. A via structure 155 is
formed through the dielectric layer 140, the sacrificial dielectric
145 and the hardmask 150, initially exposing the dielectric capping
layer 135 (which acts as an etch stop layer). The fully aligned via
(FAV) via structure 155 can be formed by a lithography and etching
process. For example, a resist formed over the hardmask 150 is
exposed to light to form an opening. The opening is then etched by
a conventional etching process (e.g., RIE) to form the via
structure 155. The via structure 155 lands on the dielectric
capping layer 135, i.e., the SiN material.
[0031] FIG. 6 illustrates the via structure 155 extending (etched)
to the lower wiring (metallization) layer containing the capped
interconnect structures 110''. In embodiments, the FAV via
structure 155 is extended by an etching process through the
dielectric capping layer 135, exposing the metal 130 or metal 130'
of the capped interconnect structure 110''. During the etching
process, chemistries will also form a trench 155' at least
partially within the dielectric layer 140 while also etching
through the dielectric capping layer 135. This, in turn, will
result in a dual damascene structure. The resist and any
lithography materials can be removed by any conventional stripants,
e.g., oxygen ashing techniques. Additionally, the sacrificial
dielectric 145 and the hardmask 150 are removed, by conventional
wet etching processes.
[0032] In FIG. 7, a metal fill material (prefill) is deposited
directly over the exposed metals 130, 130' in the FAV via structure
155 by conventional deposition processes, e.g., electroless
deposition, or selective CVD, to form the fully aligned via in the
upper metallization layer. The metal 160 can be Ru, Co, Mo, Ni and
W. Further, the metal 160 can be the same as metals 130, 130'. As
an example, both can be Ru. Additionally, the metal 160 and the
metal 130 can be alternative metals, e.g., one can be Co and the
other Ru. That is, the metal 160 in the FAV via structure 155 can
be an alternative metal. In embodiments, the metal 160, i.e., the
via prefill conductive material, is grown on the exposed surface of
the metals 130, 130'. The selective growth of the metal 160 on the
metals 130, 130' requires no polishing process. In embodiments, the
metal 160 is Ru or Co.
[0033] In FIG. 8, after the growth of the metal 160, a liner 165
and barrier 170 are deposited over the metal 160, on sidewalls of
the trench 155' and on a surface of the dielectric layer (material)
140, i.e., on the metal 160 and the dielectric layer 140 by
conventional deposition processes, e.g., PVD or CVD. A metal (fill
material) 175 is deposited on the barrier 170 in an upper
interconnect layer by a CVD and/or plating process, followed by a
CMP process to planarize the metal 175. In embodiments, the metal
175 can be composed of any suitable conductive material such as Cu,
amongst other examples. The metal 175 is in direct electrical
contact with the metal 160 in the FAV via structure 155. As shown
in FIG. 8, the dielectric layer 140 now acts as a gapfill layer
over the conformal dielectric capping layer 135. The FAV via
structure 155 is formed through the dielectric layer (gapfill
layer) 140 and the dielectric capping layer 135. Further, the
capped (via) interconnect structures 110'' are shown as a plurality
of lower wiring structures , while the dielectric layer 140 serves
as a upper wiring level and the metal 175 acts as an upper wiring
structure in electrical contact with the FAV via structure 155.
[0034] The method(s) as described above is used in the fabrication
of integrated circuit chips. The resulting integrated circuit chips
can be distributed by the fabricator in raw wafer form (that is, as
a single wafer that has multiple unpackaged chips), as a bare die,
or in a packaged form. In the latter case the chip is mounted in a
single chip package (such as a plastic carrier, with leads that are
affixed to a motherboard or other higher level carrier) or in a
multichip package (such as a ceramic carrier that has either or
both surface interconnections or buried interconnections). In any
case the chip is then integrated with other chips, discrete circuit
elements, and/or other signal processing devices as part of either
(a) an intermediate product, such as a motherboard, or (b) an end
product. The end product can be any product that includes
integrated circuit chips, ranging from toys and other low-end
applications to advanced computer products having a display, a
keyboard or other input device, and a central processor.
[0035] The descriptions of the various embodiments of the present
disclosure have been presented for purposes of illustration, but
are not intended to be exhaustive or limited to the embodiments
disclosed. Many modifications and variations will be apparent to
those of ordinary skill in the art without departing from the scope
and spirit of the described embodiments. The terminology used
herein was chosen to best explain the principles of the
embodiments, the practical application or technical improvement
over technologies found in the marketplace, or to enable others of
ordinary skill in the art to understand the embodiments disclosed
herein.
* * * * *