U.S. patent application number 16/050094 was filed with the patent office on 2018-12-06 for reducing metal gate overhang by forming a top-wide bottom-narrow dummy gate electrode.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Shih Wei Bih, Yen-Yu Chen, Han-Wen Liao, Chun-Chih Lin, Xuan-You Yan.
Application Number | 20180350948 16/050094 |
Document ID | / |
Family ID | 61829147 |
Filed Date | 2018-12-06 |
United States Patent
Application |
20180350948 |
Kind Code |
A1 |
Bih; Shih Wei ; et
al. |
December 6, 2018 |
REDUCING METAL GATE OVERHANG BY FORMING A TOP-WIDE BOTTOM-NARROW
DUMMY GATE ELECTRODE
Abstract
A polysilicon layer is formed over a substrate. The polysilicon
layer is etched to form a dummy gate electrode having a top portion
with a first lateral dimension and a bottom portion with a second
lateral dimension. The first lateral dimension is greater than, or
equal to, the second lateral dimension. The dummy gate electrode is
replaced with a metal gate electrode.
Inventors: |
Bih; Shih Wei; (Taichung
City, TW) ; Liao; Han-Wen; (Taichung City, TW)
; Yan; Xuan-You; (Taichung City, TW) ; Chen;
Yen-Yu; (Taichung City, TW) ; Lin; Chun-Chih;
(Taipei City, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Hsinchu |
|
TW |
|
|
Family ID: |
61829147 |
Appl. No.: |
16/050094 |
Filed: |
July 31, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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15420580 |
Jan 31, 2017 |
|
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16050094 |
|
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62405301 |
Oct 7, 2016 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/28114 20130101;
H01L 29/4966 20130101; H01L 21/823828 20130101; H01L 21/32137
20130101; H01L 29/66545 20130101; H01L 29/517 20130101; H01L 27/092
20130101; H01L 29/42376 20130101; H01L 21/32135 20130101; H01L
21/823842 20130101; H01L 29/513 20130101 |
International
Class: |
H01L 29/66 20060101
H01L029/66; H01L 21/3213 20060101 H01L021/3213; H01L 29/51 20060101
H01L029/51; H01L 29/423 20060101 H01L029/423 |
Claims
1. A semiconductor device, comprising: a high-k gate dielectric
layer disposed over a substrate; and a metal gate electrode
disposed over the high-k gate dielectric layer; wherein: the metal
gate electrode has a top portion and a bottom portion, the bottom
portion being located closer to the high-k gate dielectric layer
than the top portion; the top portion has a first lateral
dimension; the bottom portion has a second lateral dimension; and
the first lateral dimension is no less than the second lateral
dimension.
2. The semiconductor device of claim 1, further comprising
fluorine-containing particles disposed on an upper surface of the
substrate.
3. The semiconductor device of claim 1, wherein the metal gate
electrode has a cross-sectional profile that resembles an
upside-down trapezoid.
4. The semiconductor device of claim 1, wherein the first lateral
dimension is greater than the second lateral dimension by at least
20%.
5. The semiconductor device of claim 1, further comprising: a
capping layer disposed between the high-k gate dielectric layer and
the metal gate electrode.
6. The semiconductor device of claim 5, wherein the capping layer
contains a rare earth oxide.
7. The semiconductor device of claim 1, wherein a side surface of
the metal gate electrode includes a concave segment or a convex
segment in a cross-sectional view.
8. The semiconductor device of claim 7, wherein the side surface of
the metal gate electrode includes both the concave segment and the
convex segment in the cross-sectional view.
9. The semiconductor device of claim 1, wherein a side surface of
the metal gate electrode includes a rounded profile in a
cross-sectional view.
10. The semiconductor device of claim 1, wherein the metal gate
electrode has more sloped side surfaces than the high-k gate
dielectric layer.
11. The semiconductor device of claim 1, wherein: the top portion
has a first cross-sectional profile that resembles a first
rectangle; the bottom portion has a second cross-sectional profile
that resembles a second rectangle; and the first rectangle is wider
than the second rectangle.
12. The semiconductor device of claim 1, wherein: the top portion
has a first cross-sectional profile that resembles a first
trapezoid; the bottom portion has a second cross-sectional profile
that resembles a second trapezoid; and the first trapezoid is wider
than the second trapezoid.
13. The semiconductor device of claim 1, wherein the metal gate
electrode further includes a middle portion disposed between the
top portion and the bottom portion, wherein the middle portion has
a third lateral dimension that is smaller than the first lateral
dimension but greater than the second lateral dimension.
14. A semiconductor device, comprising: a gate dielectric layer
formed over a substrate; a gate electrode formed over the gate
dielectric layer, wherein the gate electrode has sloped sidewalls;
and fluorine-containing particles disposed over the substrate.
15. The semiconductor device of claim 14, wherein an upper portion
of the gate electrode is wider than a bottom portion of the gate
electrode by at least 20%.
16. The semiconductor device of claim 14, wherein the gate
electrode includes a plurality of segments, and wherein each
segment has a wider lateral dimension than another segment disposed
therebelow.
17. The semiconductor device of claim 14, wherein the gate
dielectric layer contains a high-k gate dielectric material, and
wherein the gate electrode contains one or more metal materials,
and wherein the semiconductor device further comprises: a capping
layer disposed between the gate dielectric layer and the gate
electrode, wherein the capping layer contains LaO.sub.x, GdO.sub.x,
DyO.sub.x, or ErO.sub.x.
18. The semiconductor device of claim 14, wherein sidewalls of the
gate dielectric layer are sloped differently than the sidewalls of
the gate electrode.
19. The semiconductor device of claim 14, wherein at least a
portion of the sloped sidewalls of the gate electrode has a curved,
concave, or convex cross-sectional profile.
20. A semiconductor device, comprising: a gate dielectric layer
located over a substrate, wherein the gate dielectric layer
includes a material having a dielectric constant that is greater
than a dielectric constant of SiO.sub.2; a capping layer located
over the gate dielectric layer, wherein the capping layer includes
a rare earth oxide material; a gate electrode located over the
capping layer, wherein the gate electrode includes one or more
metal material, wherein an upper portion of the gate electrode is
at least as wide as a lower portion of the gate electrode; and
fluorine-containing particles disposed over the substrate.
Description
CROSS-REFERENCE
[0001] This application is a divisional of U.S. application Ser.
No. 15/420,580, filed Jan. 31, 2017 which claims benefit of U.S.
Provisional Application No. 62/405,301, filed Oct. 7, 2016, both of
which are herein incorporated by reference in their entirety.
BACKGROUND
[0002] The semiconductor integrated circuit (IC) industry has
experienced rapid growth. Technological advances in IC materials
and design have produced generations of ICs where each generation
has smaller and more complex circuits than the previous generation.
However, these advances have increased the complexity of processing
and manufacturing ICs and, for these advances to be realized,
similar developments in IC processing and manufacturing are needed.
In the course of integrated circuit evolution, functional density
(i.e., the number of interconnected devices per chip area) has
generally increased while geometry size (i.e., the smallest
component (or line) that can be created using a fabrication
process) has decreased.
[0003] To facilitate the semiconductor device scaling down process,
metal gate electrodes may be used instead of conventional
polysilicon electrodes. The formation of the metal gate electrodes
may involve a gate replacement process, in which a dummy gate
electrode is removed to form an opening in its place, and the
opening is subsequently filled by metal materials to form the metal
gate electrode. However, conventional gate replacement processes
may leave an overhang in the opening, which may impede the filling
of the opening by the metal material. As such, voids may form in
the metal gate, which degrades semiconductor device
performance.
[0004] Therefore, while existing gate replacement processes have
been generally adequate for their intended purposes, they have not
been entirely satisfactory in every aspect.
BRIEF DESCRIPTION OF THE DRAWINGS
[0005] The present disclosure is best understood from the following
detailed description when read with the accompanying figures. It is
emphasized that, in accordance with the standard practice in the
industry, various features are not drawn to scale and are used for
illustration purposes only. In fact, the dimensions of the various
features may be arbitrarily increased or reduced for clarity of
discussion.
[0006] FIG. 1 is a diagrammatic cross-sectional side view of a
semiconductor device at a stage of fabrication according to various
embodiments of the present disclosure.
[0007] FIG. 2 is a diagrammatic cross-sectional side view of a
semiconductor device at a stage of fabrication according to various
embodiments of the present disclosure.
[0008] FIG. 2A is a diagrammatic cross-sectional side view of a
semiconductor device at a stage of fabrication according to various
embodiments of the present disclosure.
[0009] FIG. 3 is a diagrammatic cross-sectional side view of a
semiconductor device at a stage of fabrication according to various
embodiments of the present disclosure.
[0010] FIG. 4 is a diagrammatic cross-sectional side view of a
semiconductor device at a stage of fabrication according to various
embodiments of the present disclosure.
[0011] FIG. 5 is a diagrammatic cross-sectional side view of a
semiconductor device at a stage of fabrication according to various
embodiments of the present disclosure.
[0012] FIG. 6 is a diagrammatic cross-sectional side view of a
semiconductor device at a stage of fabrication according to various
embodiments of the present disclosure.
[0013] FIG. 7 illustrates several suitable cross-sectional profiles
for the dummy gate electrodes fabricated according to various
embodiments of the present disclosure.
[0014] FIG. 8 is a flow chart of a method for fabricating a
semiconductor device in accordance with embodiments of the present
disclosure.
DETAILED DESCRIPTION
[0015] It is understood that the following disclosure provides many
different embodiments, or examples, for implementing different
features of the present disclosure. Specific examples of components
and arrangements are described below to simplify the present
disclosure. These are, of course, merely examples and are not
intended to be limiting. For example, the formation of a first
feature over or on a second feature in the description that follows
may include embodiments in which the first and second features are
formed in direct contact, and may also include embodiments in which
additional features may be formed between the first and second
features, such that the first and second features may not be in
direct contact. In addition, the present disclosure may repeat
reference numerals and/or letters in the various examples. This
repetition is for the sake of simplicity and clarity and does not
in itself dictate a relationship between the various embodiments
and/or configurations discussed. Moreover, various features may be
arbitrarily drawn in different scales for the sake of simplicity
and clarity.
[0016] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. For example,
if the device in the figures is turned over, elements described as
being "below" or "beneath" other elements or features would then be
oriented "above" the other elements or features. Thus, the
exemplary term "below" can encompass both an orientation of above
and below. The apparatus may be otherwise oriented (rotated 90
degrees or at other orientations) and the spatially relative
descriptors used herein may likewise be interpreted
accordingly.
[0017] As semiconductor fabrication technology advances, metal gate
transistors have been used in recent years to enhance the
performance of ICs. Metal gate transistors use metal gate
electrodes instead of the conventional polysilicon gate electrodes.
The fabrication processing of metal gate transistors may involve a
gate replacement process, where a polysilicon dummy gate electrode
is replaced by a metal gate electrode after the formation of the
source/drain regions. However, due to the scaling down of
semiconductor devices, critical dimensions (e.g., a width of the
gate) have become increasingly small, while an aspect ratio (e.g.,
a ratio between the height of the gate and the width of the gate)
may increase. The small CD and the high aspect ratio of the gate
may lead to problems or difficulties in replacing the polysilicon
dummy gate electrode with the metal gate electrode. For example,
the small CD and the high aspect ratio may lead to an "overhang"
situation, where the opening (formed by the removal of the dummy
polysilicon gate electrode) is partially blocked. This may result
in voids in the metal gate electrode subsequently formed in the
opening. The voids in metal gate electrodes degrade the performance
of the transistor device (e.g., excessive resistivity), which is
undesirable.
[0018] To overcome the problems discussed above, the present
disclosure uses a novel etching process in the formation of the
dummy gate electrodes. The novel etching processes change the
profile/shape of the dummy gate electrodes, such that a top portion
of the dummy gate electrode is wider than (or at least not narrower
than) a bottom portion of the dummy gate electrode. This is in
stark contrast to the conventionally-fabricated dummy gate
electrodes, where the top portion of the dummy gate electrode is
narrower than the bottom portion of the dummy gate electrode. As
will become more apparent based on the discussions below, the
unique profile of the dummy gate electrodes will cause the opening
(formed by their removal) to be more easily filled by metal
materials in later processes, which leads to substantially
void-free metal gate electrodes. The details of the present
disclosure are discussed below with reference to FIGS. 1-8.
[0019] FIGS. 1-6 are simplified diagrammatic fragmentary
cross-sectional side views of a semiconductor device 35 during
various fabrication stages. The semiconductor device 35 may be a
part of an integrated circuit (IC) chip, system on chip (SoC), or
portion thereof. It may include various passive and active
microelectronic devices such as resistors, capacitors, inductors,
diodes, metal-oxide semiconductor field effect transistors
(MOSFET), complementary metal-oxide semiconductor (CMOS)
transistors, laterally diffused MOS (LDMOS) transistors, high power
MOS transistors, or other types of transistors. It is understood
that FIGS. 1-6 have been simplified for a better understanding of
the inventive concepts of the present disclosure. Accordingly, it
should be noted that additional processes may be provided before,
during, and after the processes shown in FIGS. 1-6 to complete the
fabrication of the semiconductor device 35, and that some other
processes may only be briefly described herein.
[0020] Referring to FIG. 1, a semiconductor device 35 has a
substrate 40. The substrate 40 is a silicon substrate doped with a
P-type dopant such as boron (for example a P-type substrate).
Alternatively, the substrate 40 could be another suitable
semiconductor material. For example, the substrate 40 may be a
silicon substrate that is doped with an N-type dopant such as
phosphorous or arsenic (an N-type substrate). The substrate 40 may
alternatively be made of some other suitable elementary
semiconductor, such as diamond or germanium; a suitable compound
semiconductor, such as silicon carbide, indium arsenide, or indium
phosphide; or a suitable alloy semiconductor, such as silicon
germanium carbide, gallium arsenic phosphide, or gallium indium
phosphide. Further, the substrate 40 could include an epitaxial
layer (epi layer), may be strained for performance enhancement, and
may include a silicon-on-insulator (SOI) structure.
[0021] Still referring back to FIG. 1, shallow trench isolation
(STI) features 45 are formed in the substrate 40. The STI features
45 are formed by etching recesses (or trenches) in the substrate 45
and filling the recesses with a dielectric material. In the present
embodiment, the dielectric material of the STI features 45 includes
silicon oxide. In alternative embodiments, the dielectric material
of the STI features 45 may include silicon nitride, silicon
oxy-nitride, fluoride-doped silicate (FSG), and/or a low-k
dielectric material known in the art. In other embodiments, deep
trench isolation (DTI) features may be formed in place of, or in
combination with, the STI features 45.
[0022] An interfacial layer may be optionally formed over the
substrate 40. The interfacial layer may be formed by an atomic
layer deposition (ALD) process and includes silicon oxide
(SiO.sub.2).
[0023] A gate dielectric layer 60 is formed over the upper surface
of substrate 40 (or over the interfacial layer if the interfacial
layer is formed). The gate dielectric layer 60 may be formed by an
ALD process in some embodiments. In some embodiments, the gate
dielectric layer 60 includes a high-k dielectric material. A high-k
dielectric material is a material having a dielectric constant that
is greater than a dielectric constant of SiO.sub.2, which is
approximately 4. In an embodiment, the gate dielectric layer 60
includes hafnium oxide (HfO.sub.2), which has a dielectric constant
that is in a range from approximately 18 to approximately 40. In
alternative embodiments, the gate dielectric layer 60 may include
one of ZrO.sub.2, Y.sub.2O.sub.3, La.sub.2O.sub.5, Gd.sub.2O.sub.5,
TiO.sub.2, Ta.sub.2O.sub.5, HfErO, HfLaO, HfYO, HfGdO, HfAlO,
HfZrO, HfTiO, HfTaO, and SrTiO.
[0024] A capping layer 70 is formed over the gate dielectric layer
60. The formation of the capping layer 70 includes one or more
deposition and patterning processes. In some embodiments, the
capping layer 70 includes a lanthanum oxide material (LaO.sub.x,
where x is an integer), but it is understood that the capping layer
may include other suitable materials (e.g., rare earth oxides such
as LaOx, GdOx, DyOx, or ErOx) in other embodiments. In some
embodiments, the material of the capping layer may be selected so
that it can help tune a work function of a transistor gate (to be
formed later), such that a desired threshold voltage may be
achieved for the transistor. It is understood that the gate
dielectric layer 60 and the capping layer 70 are formed over both
an NMOS transistor region and a PMOS transistor region at this
stage of fabrication. In some embodiments, a thickness of the
capping layer is in a range from about 5 Angstroms to about 20
Angstroms.
[0025] A polysilicon layer 80 is formed over the capping layer 70.
The polysilicon layer 80 will be patterned later to form dummy gate
electrodes. A patterned hard mask layer 90 is formed over the
polysilicon layer 80. In some embodiments, the patterned hard mask
layer 90 includes multiple layers having different material
compositions. For example, the patterned hard mask layer 90 may
include a silicon nitride layer formed over the polysilicon layer
80, and it may also include a silicon oxide layer formed over the
silicon nitride layer. The patterned hard mask layer 90 may be
patterned through a photolithography process into a plurality of
segments, such as segments 90A and 90B.
[0026] Referring now to FIG. 2, the segments 90A and 90B of the
patterned hard mask layer 90 may be used as masks to define gate
structures of transistors. In more detail, an etching process 100
is performed to etch the polysilicon layer 80. The segments 90A and
90B of the patterned hard mask layer 90 serve as etching masks in
the etching process 100 to protect portions of the layers below
(including the polysilicon layer 80, the capping layer 70, and the
gate dielectric layer 60) from being etched.
[0027] The etching process 100 forms gate structures 120A and 120B
separated by an opening 130, where the gate structure 120A includes
the segment 90A, a remaining portion 80A of the polysilicon layer,
a remaining portion 70A of the capping layer, and a remaining
portion of the gate dielectric layer 60A, and the gate structure
120B includes the segment 90B, a remaining portion 80B of the
polysilicon layer, a remaining portion 70B of the capping layer,
and a remaining portion of the gate dielectric layer 60B. It is
understood that the remaining portions 80A and 80B of the
polysilicon layer serve as dummy gate electrodes herein and will be
removed in a dummy gate replacement process later.
[0028] According to embodiments of the present disclosure, the
etching process 100 is configured to form dummy gate electrodes
80A-80B whose sidewall profiles are sloped inwards. For example,
the dummy gate electrode 80A (or 80B) has a lateral dimension 140
near its upper surface and a lateral dimension 141 nears its bottom
surface. The lateral dimension 140 is greater than or equal to (or
no less than) the lateral dimension 141. In some embodiments, the
lateral dimension 140 is greater than the lateral dimension 141 by
at least 5%, for example by about 5%-20%. Consequently, the dummy
gate electrodes 80A and 80B shown in FIG. 2 each have a
cross-sectional profile/shape that loosely resembles an inverse or
upside-down trapezoid, though it is understood that in real world
fabrication, the sidewall surfaces of the dummy gate electrodes
80A-80B may not be as straight or smooth as they are shown in FIG.
2, since FIG. 2 provides merely a simplified illustration.
[0029] This upside-down trapezoidal shape of the dummy gate
electrodes 80A-80B is obtained by configuring the lateral etching
characteristics of the etching process 100. For example, the
etching process 100 may be configured to have increasingly stronger
lateral etching characteristics as the etching progresses deeper
(i.e., closer to the substrate 40). In some embodiments, the
etching process 100 includes a plurality of etching steps, where
each etching step has an associated lateral etching rate, and that
each subsequent etching step has a greater lateral etching rate
than a previous etching step.
[0030] The etching process (or the various etching steps included
therein) may include simultaneously applying a high
electronegativity etchant and a chlorine etchant inside an etching
chamber, with the wafer undergoing the etching process 100 placed
therein. In some embodiments, the chlorine etchant may include a
Cl.sub.2 gas or plasma with a flow rate in a range between about 30
standard cubic centimeters per minute (sccm) and about 36 sccm, and
the high electronegativity etchant may include a
fluorine-containing gas or plasma with a flow rate in a range
between about 80 sccm to about 120 sccm. As non-limiting examples,
the fluorine-containing gas or plasma may include a fluorine-rich
material such as C.sub.xF.sub.y, (where x and y are positive
integers, for example CF.sub.4 or C.sub.2F.sub.6), CHF.sub.3, HBr,
or NF.sub.3. The etching mechanism is as follows: [0031] The
fluorine-containing etchant reacts with a surface oxide (e.g.,
formed on the sidewalls of the dummy gate electrodes 80A-80B as
they are being etched) to produce silicon-containing and
oxygen-containing gases that can be removed from the etching
chamber by a purging mechanism. For example, with CF.sub.4 as an
etchant, the surface oxide may react with CF.sub.4 according to the
following chemical formula:
SiO.sub.2+CF.sub.4=>SiF.sub.4+CO.sub.2, where SiF.sub.4+CO.sub.2
are gases that can be removed from the etching chamber. [0032] The
chlorine-containing etchant reacts with the polysilicon material of
the dummy gate electrodes 80A-80B to form another gas (e.g.,
SiCl.sub.x, where x is a positive integer) that can be removed from
the etching chamber by a purging mechanism.
[0033] The flow rate of the fluorine-containing etchant may be
correlated with the lateral etching characteristics of the etching
process 100. For example, increasing the flow rate of the
fluorine-containing etchant enhances the lateral etching rate of
the etching process 100. As such, to achieve the desired top-wide
bottom-narrow profile of the dummy gate electrodes 80A-80B, the
etching process 100 may be configured such that the fluorine
content is increased (e.g., by increasing the flow rate of the
fluorine-containing etchant) as deeper and deeper portions of the
polysilicon layer 80 are etched. For example, in a first etching
step performed to etch a top portion of the dummy gate electrode
80A/80B, the flow rate of the fluorine-containing etchant may be
configured to be X sccm. In a second etching step performed to etch
a middle portion of the dummy gate electrode 80A/80B, the flow rate
of the fluorine-containing etchant may be configured to be Y sccm.
In a third etching step performed to etch a bottom portion of the
dummy gate electrode 80A/80B, the flow rate of the
fluorine-containing etchant may be configured to be Z sccm. Z is
greater than Y, and Y is greater than X, and X is no less than 80
sccm. Of course, the three etching steps are merely examples, and
the etching process 100 may be configured to have two etching steps
or four or more etching steps in other embodiments, as long as the
fluorine content in the etchant increases with each etching
step.
[0034] Due to the rich fluorine content of the etchant used herein,
fluorine particles 150 may remain on the surfaces of the substrate
40, the STI features 45, or even on the side surfaces of the gate
structures 120A-120B after the etching process 100 has been
completed. Due to the high fluorine content in the etching process
100, these fluorine particles may still remain after various
cleaning processes are performed. In other words, the removal of
the fluorine particles 150 may not be complete, and some traces of
them may be found in an actually fabricated semiconductor device.
The presence of the fluorine particles 150 may be detected by
certain semiconductor fabrication inspection tools. The remnants of
fluorine may be evidence that an etching process similar to the
etching process 100 according to the present disclosure is used to
fabricate the semiconductor device.
[0035] In some embodiments, a passivation gas may also be applied
along with the etchant to facilitate the formation of the dummy
gate electrodes 80A-80B with the top-wide bottom-narrow profiles.
The passivation gas forms a passivation material on the exposed
surfaces of the polysilicon layer 80 as the etching process 100
takes place. The passivation material helps prevent further etching
of the polysilicon material. A simplified example of this is shown
in FIG. 2A. Referring to FIG. 2A, as a top portion of the
polysilicon layer 80 is etched, the passivation gas forms the
passivation materials 170A-170B on the sidewalls of the dummy gate
electrodes 80A-80B near the top. This will allow the etching
process 100 to progress downwards and continue the lateral etching
of the lower portions of the polysilicon layer 80 without further
lateral etching of the dummy gate electrodes 80A-80B at the top,
because they are protected by the passivation materials
170A-170B.
[0036] It is also noted that since the dummy gate electrodes
80A-80B have top-wide bottom-narrow profiles, the opening 130
separating the dummy gate electrodes 80A-80B has a top-narrow and
bottom-wide profile.
[0037] Referring now to FIG. 3, gate spacers 190A-190B are formed
on sidewalls of the gate structures 120A-120B. The gate spacers
190A-190A include a dielectric material. In some embodiments, the
gate spacers 190A-190B include silicon nitride. In alternative
embodiments, the gate spacers 190A-190B may include silicon oxide,
silicon carbide, silicon oxy-nitride, or combinations thereof.
[0038] Thereafter, heavily doped source and drain regions 200A and
200B (also referred to as S/D regions) are formed in the NMOS and
PMOS portions of the substrate 40, respectively. The S/D regions
200A-200B may be formed by an ion implantation process, or by a
diffusion process. N-type dopants such as phosphorus or arsenic may
be used to form the NMOS S/D regions 200B, and P-type dopants such
as boron may be used to form the PMOS S/D regions 200A. As is
illustrated in FIG. 3, the S/D regions 200A-200B are aligned with
the outer boundaries of the gate spacers 190A-190B, respectively.
Since no photolithography process is required to define the area or
the boundaries of the S/D regions 200A-200B, it may be said that
the S/D regions 200A-200B are formed in a "self-aligning" manner.
One or more annealing processes are performed on the semiconductor
device 35 to activate the S/D regions 200A-200B. It is also
understood that in some embodiments, lightly-doped source/drain
(LDD) regions may be formed in both the NMOS and PMOS regions of
the substrate 40 before the gate spacers 190A-190B are formed. For
reasons of simplicity, the LDD regions are not specifically
illustrated herein.
[0039] Referring now to FIG. 4, an inter-layer (or inter-level)
dielectric (ILD) layer 220 is formed over the substrate 40 and the
gate structure 220. The ILD layer 220 may be formed by chemical
vapor deposition (CVD), high density plasma CVD, spin-on,
sputtering, or other suitable methods. The ILD layer 220 fills the
opening 130, for example. In an embodiment, the ILD layer 220
includes silicon oxide. In other embodiments, the ILD layer 220 may
include silicon oxy-nitride, silicon nitride, or a low-k material.
A polishing process (for example a chemical-mechanical-polishing
(CMP) process) may be performed on the ILD layer 220 to planarize
the ILD layer 220. The polishing is performed until top surfaces of
the dummy gate electrodes 80A of gate structures 120A-120B are
exposed. The hard masks 90A-90B are also removed by the polishing
process.
[0040] Still referring to FIG. 4, after the formation of the ILD
layer 200 and the subsequent planarization thereof, an etching
process 260 is performed to remove the dummy gate electrodes
80A-80B. In some embodiments, the etching process 260 may include a
dry etching process. The gate dielectric layer 60A-60B and the
capping layer 70A-70B are not removed by the etching process 260 in
the illustrated embodiment. As a result of the etching process 260,
trenches or openings 270A-270B are formed. Since the dummy gate
electrodes 80A-80B are formed to have a profile such that it is
wider at the top and narrower at the bottom (e.g., dimension
140>=dimension 141), the trenches 270A-270B also inherit this
profile, meaning that the trenches may also have a wider lateral
dimension 140 at its top and a narrower dimension 141 at its
bottom. This specifically-configured shape/profile of the trenches
270A-270B makes them easier to fill, even if the trenches 270A-270
have small CDs and high aspect ratios.
[0041] Referring now to FIG. 5, a plurality of metal deposition
processes 280 are performed to deposit a metal layer 290 and a
metal layer 291. The metal layer 290 is formed over the exposed
surfaces of the ILD layer 220, the spacers 190A-190B, the capping
layer 70A-70B, and partially fill the trenches 270A-270B. The metal
layer 291 is formed over the metal layer 290. In some embodiments,
the metal layer 290 includes a work function metal, which helps
tune a work function of a MOS transistor, such that a desired
threshold voltage may be achieved for the MOS transistor. In some
embodiments, the work function metal may include a P-type work
function metal, which may contain tungsten (W), tungsten nitride
(WN), or tungsten aluminum (WAl) as examples. In some embodiments,
the work function metal may include an N-type work function metal,
which may contain titanium nitride (TiN) as an example.
[0042] In some embodiments, the metal layer 291 includes a fill
metal, which serves as the main conductive portion of the gate
electrode. In some embodiments, the fill metal layers contain
tungsten (W), aluminum (Al), titanium (Ti), Copper (Cu), or
combinations thereof. In other embodiments, a blocking layer may be
formed between the fill metal layer and the work function metal, so
as to reduce diffusion between the work function metal and the fill
metal. The blocking layer may include TiN or TaN. Furthermore, a
wetting layer (e.g., containing Ti) may be optionally formed
between the blocking layer and the fill metal layer to enhance the
formation of the fill metal layer.
[0043] Referring now to FIG. 6, a planarization process 300 is
performed to polish the metal layers 291 and 290 until the upper
surfaces of the metal layers 291 and 290 are substantially coplanar
with the upper surface of the ILD layer 220. In some embodiments,
the planarization process 300 includes a CMP process. After the
planarization process 300 is performed, the remaining portions 290A
and 291A of the metal layers filling the trench 270A collectively
constitute a metal gate electrode for the PMOS, and the remaining
portions 290B and 291B of the metal layers filling the trench 270B
collectively constitute a metal gate electrode for the NMOS.
[0044] For reasons discussed above, the profile of the trenches
270A-270B allow for the metal layers 290-291 to easily fill in the
trenches 270A-270B without gaps or voids. In contrast, in
conventional gate replacement processes, the metal gate formation
may be impeded by overhangs that exist near the upper portions of
the openings (i.e., openings formed by the removal of the dummy
gate electrodes). Overhangs are formed as a result of conventional
fabrication, because of the tapered shape of the etched dummy gate
electrodes where the top is narrower than the bottom. Thus, the
resulting trench would also be narrower at the top and wider at the
bottom, thereby creating the overhangs. The overhangs may cause
difficulties in the metal layers filling the trenches, thus leading
to voids/gaps within the metal electrodes. This problem is overcome
by the present disclosure, because the etching process 100
discussed above with reference to FIG. 2 is specifically configured
(e.g., by increasing the lateral etching rate as the etching gets
deeper) to form dummy gate electrodes 80A-80B that are wider at the
top and narrower at the bottom, thereby allowing for easy filling
of the trenches 270A-270B without substantial voids or gaps in the
formed metal electrodes. Thus, semiconductor performance is
improved.
[0045] It is understood that although FIGS. 2-6 illustrate an
approximately inverse trapezoidal profile (i.e., loosely resembling
an upside-down trapezoid) for the etched dummy gate electrodes
80A-80B (and therefore the same profile for the metal gate
electrodes that replace the dummy gate electrodes), this particular
profile/shape is not required but can be changed in different
embodiments. For example, FIG. 7 illustrates several other suitable
cross-sectional profiles/shapes 400-405 for the dummy gate
electrodes 80A-80B (and thus the metal gate electrodes). The
profile 400 is shaped similar to a rectangle where a lateral
dimension and its top and a lateral dimension at its bottom are
similar to one another. The profile 401 is shaped to have side
surfaces that each include a concave segment and a convex segment.
The profile 402 is shaped to have more curved or rounded sidewall
surfaces. The profile 403 is shaped similar to two combined
rectangles where an upper rectangle is wider than a bottom
rectangle. The profile 404 is shaped similar to three combined
rectangles where an upper rectangle is wider than a middle
rectangle, which is wider than a bottom rectangle. The profile 405
is similar to two combined upside-down trapezoids, where a top
trapezoid is wider than a bottom trapezoid.
[0046] For all the profiles 400-405, they have the common factor
that the lateral dimension at the top is greater than or equal to
the lateral dimension at the bottom. Again, this is configured to
allow for easy filling to form void-free metal gate electrodes.
These profiles or shapes 400-405 shown in FIG. 7 can be achieved by
tuning the process recipes or process parameters of the etching
process 100 discussed above. Indeed, other suitable profiles/shapes
(not illustrated herein) may also be obtained for the dummy gate
electrodes (and thus the metal gate electrodes) according to the
various aspects of the present disclosure.
[0047] The gate replacement process discussed above pertain to a
"gate-last" process, where the high-k gate dielectric is formed,
and the dummy gate electrode is formed and then replaced by a metal
gate electrode. However, it is understood that the various aspects
of the present disclosure may also apply to a "high-k last" gate
replacement process as well. In a "high-k last" gate replacement
process, instead of forming a high-k gate dielectric, a dummy gate
dielectric (e.g., silicon oxide) is formed first, and a dummy gate
electrode (e.g., polysilicon) is formed on the dummy gate
dielectric. After the formation of the source/drain regions, the
dummy gate dielectric is replaced by the high-k gate dielectric,
and the dummy gate electrode is replaced by the metal gate
electrode. Regardless, the etching processes discussed above still
apply to form the dummy gate electrode and the dummy gate
dielectric to have the profiles where the top is wider than the
bottom, so as to facilitate the filling of the openings with the
high-k dielectric and the metal gate electrode. Furthermore, it is
understood that the aspects of the present disclosure may apply to
both "2-dimensional" planar devices or "3-dimensional" FinFET
devices.
[0048] It is also understood that additional processes may be
performed to complete the fabrication of the semiconductor device
35. For example, these additional processes may include formation
of contact holes for the gate structures, formation of interconnect
structures (e.g., lines and vias, metal layers, and interlayer
dielectric that provide electrical interconnection to the device
including the formed metal gate), deposition of passivation layers,
packaging, testing, etc. For the sake of simplicity, these
additional processes are not described herein. It is also
understood that some of the fabrication processes for the various
embodiments discussed above may be combined depending on design
needs and manufacturing requirements.
[0049] FIG. 8 is a flowchart of a method 600 for fabricating a
semiconductor device in accordance with various aspects of the
present disclosure. The method 600 includes a step 610 of forming a
high-k gate dielectric layer over a substrate.
[0050] The method 600 includes a step 620 of forming a polysilicon
layer over the high-k gate dielectric layer.
[0051] The method 600 includes a step 630 of etching the
polysilicon layer to form a dummy gate electrode having a top
portion with a first lateral dimension and a bottom portion with a
second lateral dimension. The first lateral dimension is greater
than, or equal to, the second lateral dimension.
[0052] The method 600 includes a step 640 of replacing the dummy
gate electrode with a metal gate electrode.
[0053] In some embodiments, the top portion of the dummy gate
electrode is formed when the etching is performed with a first
lateral etching rate, and the bottom portion of the dummy gate
electrode is formed when the etching is performed with a second
lateral etching rate greater than the first lateral etching
rate.
[0054] In some embodiments, the etching comprises using a
fluorine-containing etchant, and wherein the etching is performed
by increasing a fluorine content of the etchant as the etching
progresses deeper into the polysilicon layer. In some embodiments,
the increasing the fluorine content comprises increasing a flow
rate of the fluorine-containing etchant. In some embodiments, the
flow rate is no less than 80 standard cubic centimeters per minute
(sccm) throughout the etching. In some embodiments, the flow rate
is in a range between about 80 sccm and about 120 sccm. In some
embodiments, the etching comprises applying a chorine-containing
etchant simultaneously with the fluorine-containing etchant.
[0055] In some embodiments, the etching comprises applying a
passivation gas when the top portion of the dummy gate electrode is
etched.
[0056] In some embodiments, the etching is performed such that the
dummy gate electrode has a cross-sectional profile that resembles
an upside-down trapezoid.
[0057] In some embodiments, the first lateral dimension is greater
than the second lateral dimension by at least 20%.
[0058] It is understood that additional process steps may be
performed before, during, or after the steps 610-640 discussed
above to complete the fabrication of the semiconductor device. For
example, before the replacing of the dummy gate electrode, the
method 600 may include a step of forming spacers on sidewalls of
the dummy gate electrode, forming source/drain regions in the
substrate on opposite sides of the dummy gate electrode, and
forming an interlayer dielectric (ILD) over the substrate. Other
process steps are not discussed herein for reasons of
simplicity.
[0059] Based on the above discussions, it can be seen that the
present disclosure offers advantages over conventional systems and
methods of forming rail structures. It is understood, however, that
other embodiments may offer additional advantages, and not all
advantages are necessarily disclosed herein, and that no particular
advantage is required for all embodiments. One advantage is the
reduction or elimination of the overhang problem plaguing existing
gate replacement processes. By configuring the etching process
carefully, the resulting dummy gate electrode can be formed to have
a profile such that it is wider at the top and narrow at the
bottom. Once the dummy gate electrode is removed, the trench formed
in place of the removed dummy gate electrode also inherits this
top-wide and bottom-narrow profile. This profile makes the trench
easy to fill with a metal material, which is used to form the metal
gate electrode. Consequently, the formed metal gate electrode is
substantially void-free or gap-free, thereby having improved
performance than conventionally formed metal gates.
[0060] One aspect of the present disclosure involves a method of
fabricating a semiconductor device. A polysilicon layer is formed
over a substrate. The polysilicon layer is etched to form a dummy
gate electrode having a top portion with a first lateral dimension
and a bottom portion with a second lateral dimension. The first
lateral dimension is greater than, or equal to, the second lateral
dimension. The dummy gate electrode is replaced with a metal gate
electrode.
[0061] Another aspect of the present disclosure involves a method
of fabricating a semiconductor device. A gate dielectric layer is
formed over a substrate. A dummy gate electrode layer is formed
over the gate dielectric layer. The dummy gate electrode layer is
etched with an etchant that contains fluorine and chlorine to form
a dummy gate electrode. The etching comprising increasing a
fluorine content of the etchant as the etching progresses deeper
into the dummy gate electrode layer. Spacers are formed on
sidewalls of the dummy gate electrode. Source/drain regions are
formed in the substrate on opposite sides of the dummy gate
electrode. The dummy gate electrode is replaced with a metal gate
electrode.
[0062] Yet another aspect of the present disclosure involves a
semiconductor device. The semiconductor device includes a high-k
gate dielectric layer disposed over a substrate. The semiconductor
device includes a metal gate electrode disposed over the high-k
gate dielectric layer. The metal gate electrode has a top portion
and a bottom portion. The bottom portion is located closer to the
high-k gate dielectric layer than the top portion. The top portion
has a first lateral dimension. The bottom portion has a second
lateral dimension. The first lateral dimension is no less than the
second lateral dimension.
[0063] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *