U.S. patent application number 15/471483 was filed with the patent office on 2018-10-04 for fraction-n digital pll capable of canceling quantization noise from sigma-delta modulator.
This patent application is currently assigned to STMicroelectronics International N.V.. The applicant listed for this patent is STMicroelectronics International N.V.. Invention is credited to Kallol Chatterjee, Gagan Midha.
Application Number | 20180287620 15/471483 |
Document ID | / |
Family ID | 62404051 |
Filed Date | 2018-10-04 |
United States Patent
Application |
20180287620 |
Kind Code |
A1 |
Midha; Gagan ; et
al. |
October 4, 2018 |
FRACTION-N DIGITAL PLL CAPABLE OF CANCELING QUANTIZATION NOISE FROM
SIGMA-DELTA MODULATOR
Abstract
A phase locked loop (PLL) circuit disclosed herein includes a
phase detector receiving a reference frequency signal and a
feedback frequency signal, and configured to output a digital
signal indicative of a phase difference between the reference
frequency signal and the feedback frequency signal. A digital loop
filter filters the digital signal. A digital to analog converter
converts the filtered digital signal to a control signal. An
oscillator generates a PLL clock signal based on the control
signal. A sigma-delta modulator modulates a divider signal as a
function of a frequency control word. A divider divides the PLL
clock signal based on the divider signal, and generates a noisy
feedback frequency signal based thereupon. A noise filtering block
removes quantization noise from the noisy feedback frequency signal
to thereby generate the feedback frequency signal.
Inventors: |
Midha; Gagan; (Panipat,
IN) ; Chatterjee; Kallol; (Gananagar, IN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
STMicroelectronics International N.V. |
Schiphol |
|
NL |
|
|
Assignee: |
STMicroelectronics International
N.V.
Schiphol
NL
|
Family ID: |
62404051 |
Appl. No.: |
15/471483 |
Filed: |
March 28, 2017 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H03L 7/085 20130101;
H03L 7/081 20130101; H03L 7/1976 20130101; H03M 3/344 20130101;
H03L 7/0802 20130101 |
International
Class: |
H03L 7/093 20060101
H03L007/093; H03M 3/00 20060101 H03M003/00; H03L 7/081 20060101
H03L007/081; H03L 7/08 20060101 H03L007/08 |
Claims
1. A phase locked loop (PLL) circuit, comprising: a phase detector
receiving a reference frequency signal and a feedback frequency
signal and configured to output a digital signal indicative of a
phase difference between the reference frequency signal and the
feedback frequency signal; a digital loop filter configured to
filter the digital signal; a digital to analog converter configured
to convert the filtered digital signal to a control signal; an
oscillator configured to generate a PLL clock signal based on the
control signal; a sigma-delta modulator configured to modulate a
divider signal as a function of a frequency control word; a divider
configured to divide the PLL clock signal based on the divider
signal, and to generate a noisy feedback frequency signal based
thereupon; and a noise filtering block configured to remove
quantization noise from the noisy feedback frequency signal to
thereby generate the feedback frequency signal, wherein the noise
filtering block comprises: a delay chain configured to generate
multiple different delayed versions of the noisy feedback frequency
signal, and a multiplexer configured to receive the multiple
different delayed versions of the noisy feedback frequency signal
as input and to pass one of the multiple different delayed versions
of the noisy feedback frequency signal to the phase detector as the
feedback frequency signal as a function of the quantization noise;
and a control circuit configured to receive an unshaped
quantization error from the sigma-delta modulator and to generate a
multiplexer control signal for the multiplexer based thereupon.
2. (canceled)
3. The PLL circuit of claim 1, wherein the delay chain comprises a
plurality of series connected buffers each having a constant
delay.
4. The PLL circuit of claim 1, wherein the delay chain and
multiplexer cooperate to adjust a phase of the noisy feedback
frequency signal to remove the quantization noise therefrom.
5. (canceled)
6. The PLL circuit of claim 1, wherein the control circuit
generates the multiplexer control signal by: quantizing the
unshaped quantization error from a higher bit count to a lower bit
count to produce a first intermediate signal; applying a noise
transfer function to the first intermediate signal to produce a
second intermediate signal; and integrating the second intermediate
signal to produce the multiplexer control signal.
7. The PLL circuit of claim 6, wherein the control circuit
multiplies the unshaped quantization error by a scaling factor
prior to the quantizing.
8. The PLL circuit of claim 7, further comprising a scaling factor
circuit configured to calculate a number of delay elements of the
delay chain needed to delay the noisy feedback frequency signal by
a period of the PLL clock signal, and to generate the scaling
factor based upon the number.
9. The PLL circuit of claim 8, wherein the delay chain is comprised
of a plurality of series connected buffers, with one of the
multiple different delayed versions of the noisy feedback frequency
signal being produced at an output of each of the plurality of
series connected buffers; and wherein the scaling factor circuit
comprises: a plurality of flip flops, each having an input coupled
to an output of a different one of the plurality of series
connected buffers, and being clocked by a delayed version of the
noisy feedback frequency signal; a binary encoder receiving output
from each of the plurality of flip flops and configured to
calculate the number of delay elements of the delay chain needed to
delay the noisy feedback frequency signal by a period of the PLL
clock signal based upon the output from each of the plurality of
flip flops, and to generate the scaling factor based upon the
number divided by a number of bits in the frequency control
word.
10. The PLL circuit of claim 9, further comprising a delay flip
flop receiving the noisy feedback frequency signal as input, being
clocked by the PLL clock signal, and generating the delayed version
of the noisy feedback frequency signal as output.
11. The PLL circuit of claim 8, wherein the scaling factor circuit
is activated to calculate the scaling factor once after phases of
the reference frequency signal and the feedback frequency signal
are matched.
12. The PLL circuit of claim 8, wherein the scaling factor circuit
operates to continuously recalculate the scaling factor after
phases of the reference frequency signal and the feedback frequency
signal are matched.
13. The PLL circuit of claim 1, wherein the phase detector
comprises a bang-bang phase detector.
14. The PLL circuit of claim 1, wherein the oscillator comprises a
current controlled oscillator.
15. A method, comprising: generating a digital signal indicative of
a phase difference between a reference frequency signal and a
feedback frequency signal; filtering the digital signal; converting
the filtered digital signal to a control signal; generating a PLL
clock signal based on the control signal; modulating a divider
signal as a function of a frequency control word; dividing the PLL
clock signal based on the divider signal to generate a noisy
feedback frequency signal based thereupon; and removing
quantization noise from the noisy feedback frequency signal to
thereby generate the feedback frequency signal, the quantization
noise being removed by: generating a multiplexing control signal
by: quantizing an unshaped quantization error related to the
quantization noise from a higher bit count to a lower bit count to
produce a first intermediate signal, applying a noise transfer
function to the first intermediate signal to produce a second
intermediate signal, and integrating the second intermediate signal
to produce the multiplexing control signal; generating multiple
different delayed versions of the noisy feedback frequency signal,
and passing one of multiple different delayed versions of the noisy
feedback frequency signal as the feedback frequency signal in
response to the multiplexing control signal.
16. (canceled)
17. (canceled)
18. The method of claim 15, further comprising multiplying the
unshaped quantization error by a scaling factor prior to the
quantizing.
19. The method of claim 18, wherein the scaling factor is
determined by calculating a number of delay elements of a delay
chain needed to delay the noisy feedback frequency signal by a
period of the PLL clock signal, and to generate the scaling factor
based upon the number.
20. A circuit, comprising: a phase locked loop (PLL) circuit
comprising a feedback loop, the feedback loop comprising: a divider
operating based upon a divider control signal; a plurality of
series connected buffers; a multiplexer configured to select one
output from the plurality of series connected buffers to generate a
feedback signal for compensation based on a multiplexer control
signal; a control circuit configured to receive an unshaped
quantization error in the divider control signal and to: quantize
the unshaped quantization error in the divider control signal to
produce a first intermediate signal, apply a noise transfer
function to the first intermediate signal to produce a second
intermediate signal, and integrate the second intermediate signal
to produce the multiplexer control signal.
21. The circuit of claim 20, wherein the control circuit multiplies
the unshaped quantization error by a scaling factor prior to the
quantizing.
22. The circuit of claim 21, wherein the divider produces a noisy
feedback frequency signal for the PLL; and further comprising a
scaling factor circuit configured to calculate a number of the
plurality of series connected buffers needed to delay the noisy
feedback frequency signal by a period of a PLL clock signal, and to
generate the scaling factor based upon the number.
23. The circuit of claim 22, wherein one of multiple different
delayed versions of the noisy feedback frequency signal is produced
at an output of each of the plurality of series connected
buffers.
24. The circuit of claim 23, wherein the scaling factor circuit
comprises: a plurality of flip flops, each having an input coupled
to an output of a different one of the plurality of series
connected buffers, and being clocked by a delayed version of the
noisy feedback frequency signal; a binary encoder receiving output
from each of the plurality of flip flops and configured to
calculate a number of the plurality of series connected buffers
needed to delay the noisy feedback frequency signal by a period of
the PLL clock signal based upon the output from each of the
plurality of flip flops, and to generate the scaling factor based
upon the number divided by a number of bits in a frequency control
word used in generation of the divider control signal.
25. The circuit of claim 24, further comprising a delay flip flop
receiving the noisy feedback frequency signal as input, being
clocked by the PLL clock signal, and generating the delayed version
of the noisy feedback frequency signal as output.
Description
TECHNICAL FIELD
[0001] This disclosure relates to locked loop circuits such as, for
example, a fractional-N/interger-N phase locked loop (PLL) or a
frequency locked loop (FLL) circuit, and, in particular, to
techniques for canceling quantization noise induced by sigma-delta
modulation of a divider in the locked loop.
BACKGROUND
[0002] Locked loop circuits, such as phase locked loop circuits,
are basic components of radio, wireless, and telecommunication
technologies. A phaselocked loop or phase lock loop (PLL) is a
control system that generates an output signal having a phase
related to the phase of an input signal. A simple PLL includes
variable frequency oscillator and a phase detector. The oscillator
generates a periodic signal, and the phase detector compares the
phase of that signal with the phase of a reference periodic signal,
adjusting the oscillator to keep the phases matched. Keeping the
input and output phase in lock step also implies keeping the input
and output frequencies the same. Consequently, in addition to
synchronizing signals, a PLL can track an input frequency, or it
can generate a frequency that is a multiple (or fraction) of the
input frequency.
[0003] PLL circuits can be implemented in either analog only
technology, or with digital components. By using digital
components, the area consumed by a PLL can be reduced, lock time
can be decreased, and programmability of the PLL for use at
different frequencies can be easily implemented.
[0004] With reference to FIG. 1, a typical PLL 20 is now described.
The PLL 20 receives a reference frequency signal Fref that is fed
to a first input of a phase difference detector 22, which is
illustratively a time to digital converter (TDC) phase detector. A
second input of the TDC 22 receives a feedback frequency signal
Fdiv. The TDC 22 determines a difference in phase between the
reference frequency signal Fref and the feedback frequency signal
Fdiv and outputs a digital signal Ddif indicative of that measured
difference. A subtractor 24 receives the digital signal Ddif and
subtractors from it the quantization noise Qnoise. The output from
subtractor 24 is filtered by digital filter 26, which generates a
control signal Dcont.
[0005] A digital-to-analog converter (DAC) circuit 28 converts the
digital control signal Dcont to an analog control signal Acont. A
control input of an oscillator circuit 18, which is illustratively
a current controlled oscillator (CCO), receives the analog control
signal Acont and generates an output clock signal Fcco having a
frequency that is dependent on the magnitude of the analog control
signal Acont. A divider circuit (/N) 32 divides the output clock
signal Fcco by N to generate the feedback frequency signal Fdiv
which is compared to the reference frequency signal Fref to control
loop operation. When Fref matches Fdiv, the PLL 20 is said to have
"locked".
[0006] A sigma-delta modulator (SDM) 34 quantizes a frequency
control word FCW to generate a control signal S for the divider
circuit 32. The control signal S modulates the divider circuit 32
during operation to thereby cause a frequency of the output clock
signal to be a fractional multiple of the reference frequency
signal Fref.
[0007] The frequency control word FCW is subtracted from the output
S of the SDM 34 by subtractor 36 to produce a raw error signal E,
representing the quantization noise introduced by the quantization
of the frequency control word FCW. The raw error signal E is
accumulated by accumulator 38 to produce the quantization noise
signal Qnoise, which, as stated above, is subtracted from the
digital signal Ddif indicative of the measured difference in phase
between the reference signal Fref and feedback signal Fdiv.
[0008] While this implementation provides for a digitally
implemented fractional-N PLL, power consumption of the design due
may be undesirably high due to the TDC 22, and fractional spurs may
be generated, leading to undesirable performance when generating
certain frequencies of signal.
[0009] Therefore, further development of digital PLL circuits is
needed.
SUMMARY
[0010] This summary is provided to introduce a selection of
concepts that are further described below in the detailed
description. This summary is not intended to identify key or
essential features of the claimed subject matter, nor is it
intended to be used as an aid in limiting the scope of the claimed
subject matter.
[0011] A phase locked loop (PLL) circuit disclosed herein includes
a phase detector receiving a reference frequency signal and a
feedback frequency signal, and configured to output a digital
signal indicative of a phase difference between the reference
frequency signal and the feedback frequency signal. A digital loop
filter filters the digital signal. A digital to analog converter
converts the filtered digital signal to a control signal. An
oscillator generates a PLL clock signal based on the control
signal. A sigma-delta modulator modulates a divider signal as a
function of a frequency control word. A divider divides the PLL
clock signal based on the divider signal, and generates a noisy
feedback frequency signal based thereupon. A noise filtering block
removes quantization noise from the noisy feedback frequency signal
to thereby generate the feedback frequency signal.
[0012] The noise filtering block may include a delay chain
configured to generate multiple different delayed versions of the
noisy feedback frequency signal, and a multiplexer configured to
receive the multiple different delayed versions of the noisy
feedback frequency signal as input and to pass one of the multiple
different delayed versions of the noisy feedback frequency signal
to the phase detector as the feedback frequency signal as a
function of the quantization noise.
[0013] The delay chain may include a plurality of series connected
buffers each having a constant delay. The delay chain and
multiplexer may cooperate to adjust a phase of the noisy feedback
frequency signal to remove the quantization noise therefrom.
[0014] A control circuit may be configured to receive an unshaped
quantization error from the sigma-delta modulator and to generate a
control signal for the multiplexer based thereupon. The control
circuit may generate the control signal by quantizing the unshaped
quantization error from a higher bit count to a lower bit count to
produce a first intermediate signal, applying a noise transfer
function to the first intermediate signal to produce a second
intermediate signal, and integrating the second intermediate signal
to produce the control signal. The control circuit may multiply the
unshaped quantization error by a scaling factor prior to the
quantizing.
[0015] A scaling factor circuit may be configured to calculate a
number of delay elements of the delay chain needed to delay the
noisy feedback frequency signal by a period of the PLL clock
signal, and to generate the scaling factor based upon the
number.
[0016] The delay chain may include a plurality of series connected
buffers, with one of the multiple different delayed versions of the
noisy feedback frequency signal being produced at an output of each
of the plurality of series connected buffers. The scaling factor
circuit may include a plurality of flip flops, each having an input
coupled to an output of a different one of the plurality of series
connected buffers, and being clocked by a delayed version of the
noisy feedback frequency signal. A binary encoder may receive
output from each of the plurality of flip flops and may be
configured to calculate the number of delay elements of the delay
chain needed to delay the noisy feedback frequency signal by a
period of the PLL clock signal based upon the output from each of
the plurality of flip flops, and to generate the scaling factor
based upon the number divided by a number of bits in the frequency
control word.
[0017] A delay flip flop may receive the noisy feedback frequency
signal as input, be clocked by the PLL clock signal, and generate
the delayed version of the noisy feedback frequency signal as
output.
[0018] The scaling factor circuit may be activated to calculate the
scaling factor once after phases of the reference frequency signal
and the feedback frequency signal are matched. The scaling factor
circuit may operate to continuously recalculate the scaling factor
after phases of the reference frequency signal and the feedback
frequency signal are matched.
[0019] In some cases, the phase detector may be a bang-bang phase
detector. The oscillator may be a current controlled
oscillator.
BRIEF DESCRIPTION OF THE DRAWINGS
[0020] FIG. 1 is a schematic block diagram of a prior art digital
fractional-N phase locked loop circuit.
[0021] FIG. 2 is a schematic block diagram of a digital
fractional-N phase locked loop circuit in accordance with this
disclosure.
[0022] FIG. 3 is a schematic block diagram of a scaling factor
circuit for use with the digital fractional-N phase locked loop
circuit of FIG. 2.
DETAILED DESCRIPTION
[0023] One or more embodiments of the present disclosure will be
described below. These described embodiments are only examples of
the presently disclosed techniques. Additionally, in an effort to
provide a concise description, some features of an actual
implementation may not be described in the specification. When
introducing elements of various embodiments of the present
disclosure, the articles "a," "an," and "the" are intended to mean
that there are one or more of the elements. The terms "comprising,"
"including," and "having" are intended to be inclusive and mean
that there may be additional elements other than the listed
elements.
[0024] With reference to FIG. 2, a digital fractional-N/integer-N
phase locked loop 50 is now described. The phase locked loop 50
includes a phase difference detector 52, which, as shown, may be a
bang-bang phase detector (BBPD). The BBPD 52 receives as input a
reference frequency signal Fref and a feedback signal Sfb. The BBPD
52 determines a difference in phase between the reference frequency
signal Fref and the feedback frequency signal Sfb and outputs a
digital signal Ddif indicative of that measured difference. The
digital signal Ddif is filtered by digital filter 54, such as a low
pass digital filter, which generates a control signal Dcont.
[0025] A digital-to-analog converter (DAC) 56 converts the digital
control signal Dcont to an analog control signal Acont. A control
input of an oscillator circuit 58, which is illustratively a
current controlled oscillator (CCO), receives the analog control
signal Acont and generates an output clock signal Fcco having a
frequency Fco that is dependent on the magnitude of the analog
control signal Acont. A divider circuit (/N) 60 divides the output
clock signal Fcco by N to generate a signal Sn.
[0026] The divider circuit 60 is modulated and controlled by a
control signal S generated by sigma-delta modulator (SDM) 62.
Sigma-delta modulator 62 quantizes a K bit (16 bit, for example)
fractional frequency control word FCW into a multilevel integer
control signal S for the divider circuit 60 such that the
quantization error is high pass shaped. The integer divider 60 is
modulated by the control signal S to cause the fractional divide.
Other bit frequency control words may be used, and may be quantized
into other numbers of bits for the control signal.
[0027] The control signal S can be represented as S=FCW+E*NTF,
where E represents the unshaped quantization error or noise
introduced by the sigma-delta modulator 62, and where NTF
represents the noise transfer function of the sigma-delta modulator
62.
[0028] The output Sn produced by the divider circuit 60, which is a
feedback frequency signal that contains quantization noise from the
sigma-delta modulator 62, can be represented as
Sn = S * 1 1 - z - 1 . ##EQU00001##
Since S undergoes a frequency to phase conversion through the
divider circuit 60, Sn represents the phase input to the PLL after
the divider circuit 60.
[0029] Cancelation of the quantization noise from the signal Sn
will now be discussed. Control circuitry 63 includes a multiplier
64 which receives the unshaped quantization error E from the
sigma-delta modulator 62 and multiplies it by a scaling factor SF
(which will be described below). The unshaped quantization error E
is still sixteen bits in length as a 16 bit fractional resolution
for FCW is chosen. To cancel this quantization error, the signal E
is quantized to K bits (for example, to a target of 4 bits or 24 db
noise improvement over E) by quantizing block 66 to produce signal
EQ. Q represents the quantization error added in the quantization
process and can be represented as Q=E/16. EQ can be represented as
EQ=E+Q.
[0030] The resulting signal EQ is passed through the noise transfer
function block 68 and integrator 70. This produces the control
signal Ef as
Ef = EQ * NTF * 1 1 - z - 1 . ##EQU00002##
The goal is therefore to subtract Ef from Sn to produce the
feedback signal Sf. Mathematically, this can be represented as:
Sfb = Sn - Ef = FCW * 1 1 - z - 1 + Q * NTF * 1 1 - z - 1 .
##EQU00003##
[0031] Since the desired signal Sfb is
FCW * 1 1 - z - 1 , ##EQU00004##
the phase error introduced in the loop is
Q * NTF * 1 1 - z - 1 . ##EQU00005##
Without this quantization error cancellation being performed, the
phase error introduced would instead be
E * NTF * 1 1 - z - 1 , ##EQU00006##
meaning that the quantization error cancellation reduces the phase
error by 1/16.
[0032] To implement this goal of subtracting quantization error Ef
from Sn, delay chain 71 is used. Delay chain 71 is comprised of
multiple buffers 72, 74, 76, 78 coupled in series to the output
signal Sn of the divider circuit 60, and outputs multiple different
delayed versions of Sn to multiplexer 80, with each delayed version
of Sn having a different delay than others. The multiplexer 80 is
controlled by the control signal Ef, which is generated by control
circuitry 63. This serves to cancel out the quantization error E
and what remains is Q shaped by NTF 68 and integrator function 70.
A constant delay (CD) is introduced at summer 59 and kept, so that
the phase can be delayed (if Ef is positive) and advanced (if Ef is
negative). CD can be half of the total delay elements and Ef is
added to it to form the control signal to the multiplexer 80. For
example 64 delay elements are used, then the control signal will be
(32+Ef), under the assumption that Ef would be in the range of +32
to -32. This works well for a second order MASH 1-1 modulator as
the NTF is (1-z-1).sup.2. The phase excursion due to E after the
integrating function of 1/(1-z-1) will be 1*Tvco, i.e +16 to -16
delay elements for each buffer delay of Tcco/16. So, the total
delay elements to be used are 32. As the delay will change with
temperature, 64 delay elements may be chosen to provide for a
comfortable margin.
[0033] The buffers 72, 74, 76, 78 may each introduce a same amount
of delay.
[0034] In the case where the delay of each buffer is equal to
Tcco/16, where Tcco represents the period of Fcco, additional
circuitry beyond the delay chain 71 and multiplexer 80 is not
needed. However, so as to preserve programmability of the PLL 50,
in some cases, scaling circuitry 79 (shown in FIG. 3) may be used
to calculate how many of the buffers 72, 74, 76, 78 are needed to
have a delay equal to Tcco. In some cases, the delay of the buffers
72, 74, 76, 78 may vary with temperature, and thus the scaling
circuitry 79 may change the numbers of buffers 72, 74, 76, 78
active to compensate.
[0035] The scaling circuitry 79 includes a clock flip flop 80
receiving Sn at its D input, being clocked by Fcco, and providing
output that clocks flip flops 82, 84, 86, 88. Thus, the clock flip
flop 80 delays Sn by one period of Fcco. Flip flop 82 has its D
input coupled to the output of buffer 72, flip flop 84 has its D
input coupled to the output of buffer 74, flip flop 86 has its D
input coupled to the output of buffer 76, and flip flop 88 has its
D input coupled to the output of buffer 78. The Q outputs of flip
flops 82, 84, 86, and 88 are fed to binary encoder 90, which
generates the scaling factor SF therefrom. The scaling factor SF is
calculated as the number of delay elements equal to the period of
Fcco, denoted as NB, divided by the number of bits of the frequency
control word FCW. Thus, here, SF can be calculated as SF=NB/16.
[0036] In some cases, the binary encoder 90 activates, performing a
thermometric to binary conversion to calculate the scaling factor
SF once after the PLL 50 has locked. In other cases, the binary
encoder 90 may operate continuously. In yet others, the binary
encoder 90 may be activated infrequently, to adjust for variation
in the delay provided by the buffers 72, 74, 76, 78 due to
temperature variation. This activation of the binary encoder 90 may
be once every 10 ms, for example.
[0037] It should be noted that where the implementation is such
that the scaling circuitry 79 is used, the noise reduction depends
on NB. If NB is equal to 14, then E/Q becomes 14.
[0038] It should be appreciated that the sigma-delta modulator 34
need not operate to modulate the divider circuit 60, and that the
PLL 50 may thus operate in an integer divide mode instead of in a
fractional divide mode. Of note is that, due to the novel design of
the PLL 50, power consumption in fractional divide mode is not
higher than in integer divide mode. Therefore, the PLL 50 not only
has low noise, but also has low power consumption.
[0039] While the disclosure has been described with respect to a
limited number of embodiments, those skilled in the art, having
benefit of this disclosure, will appreciate that other embodiments
can be envisioned that do not depart from the scope of the
disclosure as disclosed herein. Accordingly, the scope of the
disclosure shall be limited only by the attached claims.
* * * * *