U.S. patent application number 15/996636 was filed with the patent office on 2018-09-27 for stacked grid design for improved optical performance and isolation.
The applicant listed for this patent is Taiwan Semiconductor Manufacturing Co., Ltd.. Invention is credited to Yun-Wei Cheng, Chun-Hao Chou, Tzu-Hsuan Hsu, Yung-Lung Hsu, Kuo-Cheng Lee, Tsung-Han Tsai, Horng Huei Tseng, Chao-Hsiung Wang.
Application Number | 20180277577 15/996636 |
Document ID | / |
Family ID | 57129369 |
Filed Date | 2018-09-27 |
United States Patent
Application |
20180277577 |
Kind Code |
A1 |
Cheng; Yun-Wei ; et
al. |
September 27, 2018 |
STACKED GRID DESIGN FOR IMPROVED OPTICAL PERFORMANCE AND
ISOLATION
Abstract
A back side illumination (BSI) image sensor with a dielectric
grid opening having a planar lower surface is provided. A pixel
sensor is arranged within a semiconductor substrate. A metallic
grid is arranged over the pixel sensor and defines a sidewall of a
metallic grid opening. A dielectric grid is arranged over the
metallic grid and defines a sidewall of the dielectric grid
opening. A capping layer is arranged over the metallic grid, and
defines the planar lower surface of the dielectric grid
opening.
Inventors: |
Cheng; Yun-Wei; (Taipei
City, TW) ; Tseng; Horng Huei; (Hsinchu, TW) ;
Wang; Chao-Hsiung; (Hsin-Chu, TW) ; Chou;
Chun-Hao; (Tainan City, TW) ; Tsai; Tsung-Han;
(Zhunan Township, TW) ; Lee; Kuo-Cheng; (Tainan
City, TW) ; Hsu; Tzu-Hsuan; (Kaohsiung City, TW)
; Hsu; Yung-Lung; (Tainan, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Taiwan Semiconductor Manufacturing Co., Ltd. |
Hsin-Chu |
|
TW |
|
|
Family ID: |
57129369 |
Appl. No.: |
15/996636 |
Filed: |
June 4, 2018 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
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14713172 |
May 15, 2015 |
9991307 |
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15996636 |
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14688084 |
Apr 16, 2015 |
9570493 |
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14713172 |
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 27/14621 20130101;
H01L 27/14623 20130101; H01L 27/14629 20130101; H01L 27/14627
20130101; H01L 27/1464 20130101; H01L 27/14685 20130101 |
International
Class: |
H01L 27/146 20060101
H01L027/146 |
Claims
1. An image sensor comprising: a semiconductor substrate; pixel
sensors provided within the semiconductor substrate; a stacked grid
including a dielectric grid and a metallic grid; color filters
protruding through the dielectric grid; and micro-lenses on the
color filters, wherein the stacked grid and the color filters are
provided in between the micro-lenses and the pixel sensors; and a
center of one of the micro-lenses is laterally offset from a center
of a corresponding one of the pixel sensors.
2. The image sensor according to claim 1, wherein the metallic grid
includes tungsten.
3. The image sensor according to claim 1, further comprising: a
capping layer provided on sidewalls of the metallic grid.
4. The image sensor according to claim 3, wherein the capping layer
is provided in between the metallic grid and the color filters.
5. The image sensor according to claim 1, further comprising: an
interconnect structure under the semiconductor substrate, wherein
the interconnect structure comprises a plurality of wires and a
plurality of vias, and wherein the wires and the vias are
alternatingly stacked to define a conductive path to the pixel
sensors.
6. The image sensor according to claim 1, wherein a bottom surface
of one of the color filters is non-planar.
7. The image sensor according to claim 1, wherein the metallic grid
comprises a pair of opposing segments when viewed in cross section,
and wherein the center of the corresponding one of the pixel
sensors is laterally offset from a center between the opposing
segments.
8. The image sensor according to claim 1, wherein the dielectric
grid comprises a pair of opposing segments when viewed in cross
section, and wherein the center of the corresponding one of the
pixel sensors is laterally offset from a center between the
opposing segments.
9. An image sensor comprising: a semiconductor substrate; pixel
sensors provided within the semiconductor substrate; a stacked grid
including a dielectric grid and a metallic grid; color filters
protruding through the dielectric grid; and micro-lenses on the
color filters, wherein the stacked grid and the color filters are
provided in between the micro-lenses and the pixel sensors; the
metallic grid comprises a pair of opposing segments when viewed in
cross section; and a center between the opposing segments is
laterally offset from a center of a corresponding one of the pixel
sensors.
10. The image sensor according to claim 9, further comprising: a
dielectric layer comprising a plurality of protrusions, wherein the
protrusions protrude through the metallic grid, and wherein the
protrusions are individual to and respectively aligned to the pixel
sensors.
11. The image sensor according to claim 10, wherein the dielectric
layer is between the color filters and the metallic grid.
12. The image sensor according to claim 9, further comprising: a
plurality of wires; and a plurality of vias, wherein the wires and
the vias are alternatingly stacked on an underside of the
semiconductor substrate to define conductive paths to the pixel
sensors.
13. The image sensor according to claim 9, wherein the metallic
grid includes tungsten, and wherein the dielectric grid includes
oxide.
14. The image sensor according to claim 9, wherein a bottom surface
of one of the color filters is curved.
15. The image sensor according to claim 9, wherein the dielectric
grid comprises a pair of opposing dielectric segments when viewed
in cross section, and wherein the center of the corresponding one
of the pixel sensors is laterally offset from a center between the
opposing dielectric segments.
16. An image sensor comprising: a semiconductor substrate; pixel
sensors provided within the semiconductor substrate; a stacked grid
including a dielectric grid and a metallic grid; color filters
protruding through the dielectric grid; and micro-lenses on the
color filters, wherein the stacked grid and the color filters are
provided in between the micro-lenses and the pixel sensors; the
dielectric grid comprises a pair of opposing segments when viewed
in cross section; and a center between the opposing segments is
laterally offset from a center of a corresponding one of the pixel
sensors.
17. The image sensor according to claim 16, further comprising: a
back-end-of-line (BEOL) interconnect structure, wherein the
semiconductor substrate is between the BEOL interconnect structure
and the metallic grid, and wherein the BEOL interconnect structure
defines a conductive path to at least one of the pixel sensors.
18. The image sensor according to claim 16, wherein at least one of
the micro-lenses is symmetrical.
19. The image sensor according to claim 16, further comprising: a
dielectric layer between the metallic grid and the dielectric grid,
wherein the dielectric layer is on sidewalls of the metallic
grid.
20. The image sensor according to claim 19, wherein the dielectric
layer and the dielectric grid comprise the same material.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application is a Continuation of U.S. application Ser.
No. 14/713,172, filed on May 15, 2015, which is a
Continuation-in-Part of U.S. application Ser. No. 14/688,084, filed
on Apr. 16, 2015. The contents of the above referenced applications
are hereby incorporated by reference in their entirety.
BACKGROUND
[0002] Many modern day electronic devices comprise optical imaging
devices (e.g., digital cameras) that use image sensors. Image
sensors convert optical images to digital data that may represent
the images. An image sensor may include an array of pixel sensors
and supporting logic. The pixel sensors measure incident radiation
(e.g., light), and the supporting logic facilitates readout of the
measurements. One type of image sensor commonly used in optical
imaging devices is a back-side illumination (BSI) image sensor. BSI
image sensor fabrication can be integrated into conventional
semiconductor processes for low cost, small size, and high
through-put. Further, BSI image sensors have low operating voltage,
low power consumption, high quantum efficiency, low read-out noise,
and allow random access.
BRIEF DESCRIPTION OF THE DRAWINGS
[0003] Aspects of the present disclosure are best understood from
the following detailed description when read with the accompanying
figures. It is noted that, in accordance with the standard practice
in the industry, various features are not drawn to scale. In fact,
the dimensions of the various features may be arbitrarily increased
or reduced for clarity of discussion.
[0004] FIG. 1A illustrates a cross-sectional view of some
embodiments of a back-side illuminated (BSI) image sensor having
color filters with concave lower surfaces.
[0005] FIG. 1B illustrates a cross-sectional view of some
embodiments of a BSI image sensor having color filters with convex
lower surfaces.
[0006] FIG. 1C illustrates a cross-sectional view of some
embodiments of a BSI image sensor having color filters with planar
lower surfaces.
[0007] FIG. 2A illustrates a ray diagram of some embodiments of a
BSI image sensor having a color filter with a concave lower
surface.
[0008] FIG. 2B illustrates a ray diagram of some embodiments of a
BSI image sensor having a color filter with a convex lower
surface.
[0009] FIG. 3 illustrates a cross-sectional view of some
embodiments of a BSI image sensor having color filters with curved
lower surfaces.
[0010] FIG. 4 illustrates a flowchart of some embodiments of a
method for manufacturing a BSI image sensor having color filters
with curved lower surfaces.
[0011] FIGS. 5-11, 12A & 12B, and 13A & 13B illustrate a
series of cross-sectional views of some embodiments of a BSI image
sensor at various stages of manufacture.
[0012] FIGS. 14A-14C illustrate some embodiments of graphs showing
the effect design parameters have on optical performance and
isolation.
DETAILED DESCRIPTION
[0013] The present disclosure provides many different embodiments,
or examples, for implementing different features of this
disclosure. Specific examples of components and arrangements are
described below to simplify the present disclosure. These are, of
course, merely examples and are not intended to be limiting. For
example, the formation of a first feature over or on a second
feature in the description that follows may include embodiments in
which the first and second features are formed in direct contact,
and may also include embodiments in which additional features may
be formed between the first and second features, such that the
first and second features may not be in direct contact. In
addition, the present disclosure may repeat reference numerals
and/or letters in the various examples. This repetition is for the
purpose of simplicity and clarity and does not in itself dictate a
relationship between the various embodiments and/or configurations
discussed.
[0014] Further, spatially relative terms, such as "beneath,"
"below," "lower," "above," "upper" and the like, may be used herein
for ease of description to describe one element or feature's
relationship to another element(s) or feature(s) as illustrated in
the figures. The spatially relative terms are intended to encompass
different orientations of the device in use or operation in
addition to the orientation depicted in the figures. The apparatus
may be otherwise oriented (rotated 90 degrees or at other
orientations) and the spatially relative descriptors used herein
may likewise be interpreted accordingly.
[0015] Back side illumination (BSI) image sensors typically include
pixels sensors arranged within a semiconductor substrate of an
integrated circuit. The pixel sensors are arranged between a back
side of the integrated circuit and a back-end-of-line (BEOL)
metallization stack of the integrated circuit. Micro-lenses and
color filters corresponding to the pixel sensors are stacked on the
back side of the integrated circuit over the corresponding pixel
sensors. The color filters are configured to selectively transmit
assigned wavelengths of radiation to the corresponding pixel
sensors, and the micro-lenses are configured to focus incident
radiation (e.g., photons) onto the color filters.
[0016] A stacked grid is typically arranged on the back side of the
integrated circuit. The stacked grid includes a metallic grid and a
dielectric grid overlying the metallic grid. The metallic grid is
laterally arranged around metallic grid openings corresponding to
the pixel sensors. The metallic grid openings are filled by a
capping layer that vertically spaces the dielectric grid from the
metallic grid. The dielectric grid is laterally arranged around
dielectric grid openings corresponding to the pixel sensors and
having planar lower surfaces. The dielectric grid openings are
filled with the color filters. The dielectric grid is configured to
guide or otherwise focus radiation entering the color filters
towards the pixel sensors by total internal reflection. However,
after reaching the planar lower surfaces of the dielectric grid
openings, the radiation may diverge (e.g., by refraction). Such
divergence may increase crosstalk between neighboring pixel sensors
and reduce optical performance. Further, the stacked grid calls for
a careful control of design parameters to achieve suitable optical
performance and isolation.
[0017] In view of the foregoing, the present disclosure is directed
to a BSI image sensor that has a dielectric grid opening with a
curved lower surface for focusing radiation, as well as a method
for manufacturing the BSI image sensor. In some embodiments, the
BSI image sensor includes a pixel sensor arranged within a
semiconductor substrate. A metallic grid is arranged over the
semiconductor substrate, and a dielectric grid is arranged over the
metallic grid. The metallic grid and the dielectric grid
respectively define sidewalls for a metallic grid opening and a
dielectric grid opening overlying the pixel sensor. A capping layer
is arranged between the metallic and the dielectric grids, and
fills the metallic grid opening. Further, the capping layer defines
a curved lower surface of the dielectric grid opening. A color
filter is arranged in the dielectric grid opening, and a micro lens
is arranged over the color filter. The color filter has a
refractive index differing from that of the capping layer.
[0018] The different refractive indexes of the color filter and the
capping layer, and the curved lower surface of the dielectric grid
opening, focus radiation entering the color filter and impinging on
the curved lower surface towards the pixel sensor. In a sense, the
curved lower surface acts as a lens. By focusing radiation towards
the pixel sensor, crosstalk between neighboring pixel sensors is
reduced and optical performance is improved. Further, the curved
lower surface can advantageously be achieved without additional
processing steps through etching process tuning.
[0019] Further, the present disclosure is directed to a BSI image
sensor that has carefully controlled design parameters for improved
optical performance and isolation. In some embodiments, the BSI
image sensor includes a pixel sensor arranged within a
semiconductor substrate. A metallic grid is arranged over the
semiconductor substrate, and a dielectric grid is arranged over the
metallic grid. A ratio of a dielectric grid height to a metallic
grid height may be, for example, between about 1.0 to about 8.0.
Further, an angle between a lower surface of the dielectric grid
and a sidewall of the dielectric grid may be, for example, about 60
degrees to about 90 degrees. In some embodiments, the angle between
the lower surface of the dielectric grid and the sidewall of the
dielectric grid may be, for example, less than about 90 degrees.
The metallic grid and the dielectric grid respectively define
sidewalls for a metallic grid opening and a dielectric grid opening
overlying the pixel sensor. At least one of: 1) a ratio of the a
top dielectric grid width to a top metallic grid width may be, for
example, between about 0.1 to about 2.0; and 2) a ratio of the top
dielectric grid width to a metallic grid opening width may be, for
example, about 0.1 to about 0.9. A capping layer is arranged
between the metallic and the dielectric grids, and defines a lower
surface of the dielectric grid opening. A ratio of a stacked grid
structure height to the metallic grid opening width may be, for
example, about 0.5 to about 2.0, where the stacked grid structure
includes the dielectric and metallic grids and the capping
layer.
[0020] Advantageously, by controlling design parameters, optical
performance and optical isolation may be improved. Such design
parameters may include, for example, one or more of stacked grid
structure height, metallic grid height, dielectric grid height,
metallic grid opening width, metallic grid width, and dielectric
grid width. Optical performance and optical isolation may be
improved by reducing crosstalk, the minimum luminance to achieve a
signal-to-noise ratio (SNR) of about 10 (i.e., SNR-10), quantum
efficiency (QE), and so on.
[0021] With reference to FIG. 1A, a cross-sectional view 100A of
some embodiments of a BSI image sensor is provided. The BSI image
sensor includes a semiconductor substrate 102 and pixel sensors 104
arranged within the semiconductor substrate 102, typically in rows
and/or columns. The pixels sensors 104 are configured to convert
incident radiation (e.g., photons) into electrical signals. The
pixel sensors 104 include corresponding photodetectors 106 and, in
some embodiments, corresponding amplifiers (not shown). The
photodetectors 106 may be, for example, photodiodes, and the
amplifiers may be, for example, transistors. The photodiodes may
include, for example, corresponding first regions (not shown)
within the semiconductor substrate 102 having a first doping type
(e.g., n-type doping), and corresponding second regions (not shown)
overlying the first regions within the semiconductor substrate 102
having a second doping type (e.g., p-type doping) that is different
than the first doping type.
[0022] An antireflective coating (ARC) 108 and/or a buffer layer
110 are arranged over the semiconductor substrate 102 along an
upper surface 112 of the semiconductor substrate 102. In
embodiments where both the ARC 108 and the buffer layer 110 are
present, the buffer layer 110 is typically arranged over the ARC
108. The ARC 108 may be, for example, an organic polymer or a
metallic oxide. The buffer layer 110 may be, for example, an oxide,
such as silicon dioxide. The ARC 108 and/or the buffer layer 110
vertically space the semiconductor substrate 102 from a stacked
grid 113 that overlies the semiconductor substrate 102.
[0023] The stacked grid 113 includes a metallic grid 114 and a
dielectric grid 116 overlying the metallic grid 114. The metallic
grid 114 and the dielectric grid 116 respectively define sidewalls
for metallic grid openings 118 and dielectric grid openings 120A
corresponding to the pixel sensors 104, and are configured to
confine and guide radiation entering the openings 118, 120A towards
the pixel sensors 104. Typically, the metallic and/or dielectric
grid openings 118, 120A at least partially overly the corresponding
pixel sensors 104. In some embodiments, as illustrated, centers of
the metallic grid openings 118 and/or the dielectric grid openings
120A are aligned over centers of the corresponding pixel sensors
104. In alternative embodiments, centers of the metallic grid
openings 118 and/or the dielectric grid openings 120A are laterally
shifted or offset from centers of the corresponding pixel sensors
104. The metallic grid openings 118 have substantially planar lower
surfaces 122, which may be defined by the ARC 108 and/or the buffer
layer 110. The dielectric grid openings 120A have curved lower
surfaces. The curved lower surfaces are configured with a curvature
that is dependent upon refractive indices of color filters
(described hereafter) and an underlying capping layer (described
hereafter). For example, as shown in FIG. 1A, if the color filter
has a greater refractive index than the capping layer, the
dielectric grid openings 120A will have concave lower surfaces
124A.
[0024] The metallic grid 114 and the dielectric grid 116 are
respectively arranged within metallic and dielectric grid layers
126, 128 stacked over the ARC 108 and/or the buffer layer 110. The
metallic grid 114 is arranged within a metallic grid layer 126
overlying the ARC 108 and/or the buffer layer 110. The metallic
grid layer 126 may be, for example, tungsten, copper, or aluminum
copper. The dielectric grid 116 is arranged within a dielectric
grid layer 128 stacked over the metallic grid layer 126. In some
embodiments, the dielectric grid 116 is further arranged within an
etch stop layer 130 and/or some other layer (e.g., one or more
additional dielectric grid layers) underlying the dielectric grid
layer 128. The dielectric grid layer 128 may be, for example, an
oxide, such as silicon dioxide. The etch stop layer 130 may be, for
example, a nitride, such as silicon nitride.
[0025] A capping layer 132A is arranged over the metallic grid
layer 126 between the metallic grid layer 126 and the dielectric
grid layer 128. The capping layer 132A spaces the dielectric grid
116 from the metallic grid 114 and fills the metallic grid openings
118. Further, the capping layer 132A defines the concave lower
surfaces 124A of the dielectric grid openings 120A and, in some
embodiments, partially defines sidewalls of the dielectric grid
openings 120A. The capping layer 132A is a dielectric, such as
silicon dioxide. In some embodiments, the capping layer 132A is or
otherwise includes the same material as the buffer layer 110 and/or
the dielectric grid layer 128. For example, in some embodiments
without the etch stop layer 130, the capping layer 132A and the
dielectric grid layer 128 have the same molecular structure and/or
correspond to different regions of a continuous layer (e.g., a
layer formed by a single deposition).
[0026] Color filters 134A, 136A, 138A corresponding to the pixel
sensors 104 are arranged in the dielectric grid openings 120A to
fill the dielectric grid openings 120A. The color filters 134A,
136A, 138A typically have planar upper surfaces 140 that are
approximately coplanar with an upper surface 142 of the dielectric
grid layer 128. The color filters 134A, 136A, 138A are assigned
corresponding colors or wavelengths of radiation, and are
configured to transmit radiation corresponding to the assigned
colors or wavelengths to the corresponding pixel sensors 104.
Typically, the color filter 134A, 136A, 138A assignments alternate
between red, green, and blue, such that the color filters 134A,
136A, 138A include red color filters 134A, green color filters
136A, and blue color filters 138A. In some embodiments, the color
filter assignments alternative between red, green, and blue light
according to a Bayer mosaic. The color filters 134A, 136A, 138A are
of a first material with a refractive index greater than that of a
second material abutting the first material at the concave lower
surfaces 124A of the dielectric grid openings 120A. Typically, the
second material is that of the capping layer 132A and/or the
dielectric grid layer 128.
[0027] Micro-lenses 144 corresponding to the pixel sensors 104 are
arranged over the color filters 134A, 136A, 138A and the pixel
sensors 104. Centers of the micro-lenses 144 are typically aligned
with centers of the pixel sensors 104, but centers of the
micro-lenses 144 may be laterally shifted or offset from centers of
the pixel sensors 104. The micro-lenses 144 are configured to focus
incident radiation (e.g., light) towards the pixel sensors 104. In
some embodiments, the micro-lenses 144 have convex upper surfaces
146 configured to focus radiation towards the color filters 134A,
136A, 138A and/or the pixel sensors 104.
[0028] In operation, the concave lower surfaces 124A of the
dielectric grid openings 120A serve as lenses to focus or
concentrate radiation on the corresponding pixel sensors 104.
Radiation entering the color filters 134A, 136A, 138A, and
impinging on the concave lower surfaces 124A of the dielectric grid
openings 120A, may refract towards the metallic grid 114 with an
angle of refraction greater than an angle of incidence. Upon
impinging on the metallic grid 114, the radiation may reflect
towards the pixel sensors 104. For example, suppose a light ray
148A enters a color filter 136A, reflects off a sidewall of the
color filter 136A towards a concave lower surface of the
corresponding dielectric grid opening, and impinges on the concave
lower surface with an angle of incidence .theta..sub.1. Further,
suppose the color filter 136A has a refractive index n.sub.1, and
the capping layer 132A has a refractive index n.sub.2. In such
instances, since n.sub.1 is greater than n.sub.2, .theta..sub.2 is
greater than .theta..sub.1 and can be computed according to Snell's
law as follows.
.theta. 2 = sin - 1 ( n 1 sin ( .theta. 1 ) n 2 ) ##EQU00001##
Advantageously, focusing or concentrating radiation on the pixel
sensors 104 reduces crosstalk between neighboring pixel sensors and
improves optical performance.
[0029] With reference to FIG. 1B, a cross-sectional view 100B of
other embodiments of a BSI image sensor is provided. The BSI image
sensor includes a dielectric grid 116 arranged over a capping layer
132B. The dielectric grid 116 defines sidewalls for dielectric grid
openings 120B overlying corresponding pixel sensors 104, and the
capping layer 132B defines a convex lower surface 124B of the
dielectric grid openings 120B. Color filters 134B, 136B, 138B
corresponding to the pixel sensors 104 are arranged in the
dielectric grid openings 120B to fill the dielectric grid openings
120B. The color filters 134B, 136B, 138B are of a first material
with a refractive index less than that of a second material
abutting the first material at the convex lower surfaces 124B of
the dielectric grid openings 120B. Typically, the second material
is that of the capping layer 132B and/or the dielectric grid layer
128.
[0030] In operation, the convex lower surfaces 124B of the
dielectric grid openings 120B serve as lenses to focus or
concentrate radiation on the corresponding pixel sensors 104.
Radiation entering the color filters 134B, 136B, 138B, and
impinging on the convex lower surfaces 124B of the dielectric grid
openings 120B, may refract towards the pixel sensors 104 with an
angle of refraction .theta..sub.2 less than an angle of incidence
.theta..sub.1. For example, suppose a light ray 148B enters a color
filter 136B, reflects off a sidewall of the color filter 136B
towards a convex lower surface of the corresponding dielectric grid
opening, and impinges on the convex lower surface with an angle of
incidence .theta..sub.1. Further, suppose the color filter 136B has
a refractive index n.sub.1, and the capping layer 132B has a
refractive index n.sub.2. In such instances, since n.sub.1 is less
than n.sub.2, .theta..sub.2 is less than .theta..sub.1 and can be
computed according to Snell's Law. Advantageously, focusing or
concentrating radiation on the pixel sensors 104 reduces crosstalk
between neighboring pixel sensors and improves optical
performance.
[0031] The foregoing embodiments dealt with dielectric grid
openings having curved lower surfaces. However, in some
embodiments, the dielectric grid openings have planar lower
surfaces. In such embodiments, improved control over the design
parameters is important to achieve suitable optical performance and
optical isolation. Such design parameters may include, for example,
one or more of grid height, metallic grid opening width, and top
width.
[0032] With reference to FIG. 1C, a cross-sectional view 100C of
other embodiments of a BSI image sensor is provided. The BSI image
sensor includes a stacked grid structure 150 overlying a
semiconductor substrate 102. The stacked grid structure 150
includes a stacked grid 113 vertically spaced from the
semiconductor substrate 102 by an ARC 108 and/or a buffer layer
110. The ARC 108 and/or the buffer layer 110 are arranged between
the stacked grid 113 and the semiconductor substrate 102, typically
with the buffer layer 110 overlying the ARC 108. The stacked grid
structure 150 has a height H.sub.SG and, in some embodiments (as
illustrated), includes the buffer layer 110.
[0033] The stacked grid 113 includes a metallic grid 114 and a
dielectric grid 116 overlying the metallic grid 114. The metallic
grid 114 has a height H.sub.MG, and the dielectric grid has a
height H.sub.DG. In some embodiments, a ratio of dielectric grid
height H.sub.DG to metallic grid height H.sub.MG (i.e.,
H.sub.DG/H.sub.MG) is about 1.0 to about 8.0. For example, the
ratio H.sub.DG/H.sub.MG may be about 1.0 to about 3.0, about 3.0 to
about 6.0, or about 6.0 to 8.0. The metallic and dielectric grids
114, 116 respectively define sidewalls for dielectric and metallic
grid openings 118, 120C corresponding to pixel sensors 104 arranged
in the semiconductor substrate 102. The metallic grid openings 118
have lower widths W.sub.MGO, and the dielectric grid openings 120C
have lower surfaces 124C that are typically planar. In some
embodiments, a ratio of stacked grid structure height H.sub.SG to
metallic grid opening width W.sub.MGO (i.e., H.sub.SG/W.sub.MGO) is
about 0.5 to about 2.0. For example, the ratio H.sub.SG/W.sub.MGO
may be about 0.5 to about 1, or about 1.0 to about 2.0. The
metallic and dielectric grids 114, 116 are configured to confine
and guide radiation entering the metallic and dielectric grid
openings 118, 120C towards the corresponding pixel sensors 104. The
metallic and dielectric grids 114, 116 are respectively made up of
a plurality of overlapping dielectric and metallic grid segments
152, 154.
[0034] The metallic and dielectric grid segments 152, 154 are
ring-shaped, such as square-shaped or rectangular-shaped, and have
sidewalls angled relative to corresponding lower surfaces at angles
.theta., .PHI.. In some embodiments, dielectric grid sidewall
angles .theta. are about 60 degrees to about 90 degrees. For
example, the dielectric grid sidewall angles .theta. may be about
70 degrees to about 80 degrees. Further, the metallic and
dielectric grid segments 152, 154 correspond to the metallic and
dielectric grid openings 118, 120C and laterally surround the
corresponding metallic and dielectric grid openings 118, 120C. The
metallic grid segments 152 have top widths W.sub.MG, and the
dielectric grid segments 154 have top widths W.sub.DG. The top
width W.sub.MG, W.sub.DG spans from an interior sidewall of the
corresponding grid segments 152, 154 to an exterior sidewall of the
corresponding grid segments 152, 154 (recall that the grid segments
152, 154 are ring-shaped). In some embodiments, a ratio of
dielectric grid segment width W.sub.DG to metallic grid segment
width W.sub.MG (i.e., W.sub.DG/W.sub.MG) is about 0.1 to about 2.0.
For example, the ratio W.sub.DG/W.sub.MG may be about 0.1 to about
1.0, or about 1.0 to about 2.0. Further, in some embodiments, a
ratio of dielectric grid segment width W.sub.DG to metallic grid
opening width W.sub.MGO (i.e., W.sub.DG/W.sub.MGO) is about 0.1 to
about 0.9. For example, the ratio W.sub.DG/W.sub.MGO may be about
0.1 to about 0.5, or about 0.5 to about 0.9.
[0035] A capping layer 132C of the stacked grid structure 150 is
arranged between the metallic grid 114 and the dielectric grid 116
to define the lower surfaces 124C of the dielectric grid openings
120C. Further, color filters 134C, 136C, 138C corresponding to the
pixel sensors 104 are arranged in the dielectric grid openings 120C
to at least partially fill the dielectric grid openings 120C. The
color filters 134C, 136C, 138C have a refractive index different
than that of the dielectric grid 116, and have heights H.sub.CF. In
some embodiments, a ratio of dielectric grid height H.sub.DG to
color filter height H.sub.CF (i.e., H.sub.DG/H.sub.CF) is about 0.1
to about 2.0. For example, the ratio H.sub.DG/H.sub.CF may be about
0.1 to about 1.0, or about 1.0 to about 2.0.
[0036] Advantageously, by controlling design parameters, optical
performance and optical isolation may be improved (e.g., by
reducing cross talk, SNR-10, and so on). Such design parameters may
include, for example, one or more of stacked grid structure height
H.sub.SG, metallic grid height H.sub.MG, dielectric grid height
H.sub.DG, color filter height H.sub.CF, metallic grid opening width
W.sub.MGO, metallic grid segment width W.sub.MG, and dielectric
grid segment width W.sub.DG. Further, while the discussion of FIG.
1C dealt with metallic grid opening width W.sub.MGO, it is to be
appreciated that pixel pitch (e.g., the lateral distance between
the centers of neighboring pixel sensors) may be used in place of
metallic grid opening width W.sub.MGO for the various ratios.
[0037] With reference to FIG. 14A, some embodiments of a graph
1400A are provided to illustrate the effect that a ratio of
dielectric grid height H.sub.DG to color filter height H.sub.CF
(i.e., H.sub.DG/H.sub.CF) has on optical performance. The
independent axis corresponds to the ratio and spans from about -0.1
to about 1.1. The dependent axis corresponds to either normalized
SNR-10 or normalized sensitivity, depending upon which side of the
graph 1400A is used for the dependent axis. On the left side of the
graph 1400A, the dependent axis corresponds to normalized SNR-10
and spans from about 0.8 to about 1.15. On the right side of the
graph 1400A, the dependent axis corresponds to normalized
sensitivity and spans from about 0.88 to about 1.02.
[0038] Diamond shaped markers and triangle shaped markers are
respectively plotted on the graph 1400A for normalized SNR-10 and
normalized sensitivity, and lines interconnect the markers to make
the trends clearer. Markers corresponding to known values for the
ratio are demarcated by a dashed oval. As seen, normalized SNR-10
advantageously decreases as the ratio increases from about 0.1 to
about 2. Further, normalized sensitivity advantageously increases
as the ratio increases. Similar trends with SNR-10 and normalized
sensitivity are expected with a ratio of dielectric grid height
H.sub.DG to metallic grid height H.sub.MG (i.e.,
H.sub.DG/H.sub.MG).
[0039] With reference to FIG. 14B, some embodiments of a graph
1400B are provided to illustrate the effect that a ratio of
dielectric grid segment width W.sub.DG to metallic grid opening
width W.sub.MGO (i.e., W.sub.DG/W.sub.MGO) has on normalized
SNR-10. The independent axis corresponds to the ratio and spans
from about 0.12 to about 0.16. The dependent axis corresponds to
normalized SNR-10 and spans from about 0.88 to about 1.00.
[0040] Diamond shaped markers and triangle shaped markers are
respectively plotted on the graph 1400B for different ratios of
dielectric grid height H.sub.DG to color filter height H.sub.CF
(see, e.g., FIG. 14A), and best-fit lines span between the markers
to make the trends clearer. The diamond shaped markers correspond
to a ratio of dielectric grid height H.sub.DG to color filter
height H.sub.CF that is about 1.00. The triangle shaped markers
correspond to a ratio of dielectric grid height H.sub.DG to color
filter height H.sub.CF that is about 0.56. As seen, normalized
SNR-10 increases as the ratio of dielectric grid segment width
W.sub.DG to metallic grid opening width W.sub.MGO increases from
about 0.125 to about 0.155. This is because, as the dielectric grid
segment width W.sub.DG increases, less light enters the color
filters 134C, 136C, 138C, thereby reducing the signal along with
noise. Similar trends with SNR-10 are expected with a ratio of
dielectric grid segment width W.sub.DG to metallic grid segment
width W.sub.MG (i.e., W.sub.DG/W.sub.MG). Thus, a ratio of
dielectric grid segment width W.sub.DG to width of metallic grid
openings W.sub.MGO, ranging between 0.1 and 0.9 is preferred.
[0041] With reference to FIG. 14C, some embodiments of a graph
1400C are provided to illustrate the effect that metallic grid
opening width W.sub.MGO has on optical performance. The independent
axis corresponds to metallic grid opening width W.sub.MGO in
micrometers (.mu.m). The dependent axis corresponds to either
optical QE (as a percentage) or average crosstalk (as a
percentage), depending upon which side of the graph 1400C is used
for the dependent axis. On the left side of the graph 1400C, the
dependent axis corresponds to optical QE and spans from about 45%
to about 75%. On the right side of the graph 1400C, the dependent
axis corresponds to average crosstalk and spans from about 15% to
about 40%.
[0042] Diamond shaped markers and triangle shaped markers are
respectively plotted on the graph 1400C for average crosstalk and
optical QE, and lines interconnect the markers to make the trends
clearer. As seen, average crosstalk decreases as metallic grid
opening width W.sub.MGO increases. Further, optical QE increases as
metallic grid opening width W.sub.MGO increases.
[0043] With reference to FIG. 2A, a ray diagram 200A of some
embodiments of a BSI image sensor having a color filter 202 with a
concave lower surface 204 is provided. As illustrated, light rays
206 enter the color filter 202 and impinge on the concave lower
surface 204 in parallel. Since the color filter 202 has a first
index of refraction that is greater than a second index of
refraction of an underlying, abutting layer 208, the light rays 206
will refract away from corresponding normal axes 210 to an
underlying focal point 212 (similar to a convex lens) proximate to
an underlying pixel sensor. In other words, the higher refractive
index of the color filter 202 relative to the underlying layer 208
causes the light rays 206 to have angles of refraction
.theta..sub.2 that are greater than corresponding angles of
incidence .theta..sub.1, thereby focusing the light rays 206
towards the underlying pixel sensor. Other light rays (not shown)
that are not parallel to the light rays 206 and that enter the
color filter 202 refract as described above and intersect other
focal points along a focal plane 214, which includes the focal
point 212.
[0044] With reference to FIG. 2B, a ray diagram 200B of some
embodiments of a BSI image sensor having a color filter 216 with a
convex lower surface 218 is provided. As illustrated, light rays
220 enter the color filter 216 and impinge on the convex lower
surface 218 in parallel. Since the color filter 216 has a first
index of refraction that is less than a second index of refraction
of an underlying, abutting layer 222, the light rays 220 will
refract towards corresponding normal axes 224 to an underlying
focal point 226 (similar to a convex lens) proximate to an
underlying pixel sensor. In other words, the low refractive index
of the color filter 216 relative to the underlying layer 222 causes
the light rays 220 to have angles of refraction .theta..sub.2 that
are less than corresponding angles of incidence .theta..sub.1,
thereby focusing the light rays 220 towards the underlying pixel
sensor. Other light rays (not shown) that are not parallel to the
light rays 220 and that enter the color filter 216 refract as
described above and intersect other focal points along a focal
plane 228, which includes the focal point 226.
[0045] With reference to FIG. 3, a cross-sectional view 300 of yet
other embodiments of a BSI image sensor is provided. The BSI image
sensor includes an array of pixel sensors 104 arranged in rows and
columns in a semiconductor substrate 102 of an integrated circuit
302 between a back side 304 of the integrated circuit 302 and a
BEOL metallization stack 306 of the integrated circuit 302. The
pixel sensors 104 include corresponding photodetectors 106 and, in
some embodiments, amplifiers (not shown). The photodetectors 106
are configured to convert incident radiation (e.g., photons) into
electrical signals, and may be, for example, photodiodes.
[0046] The BEOL metallization stack 306 underlies the semiconductor
substrate 102 between the semiconductor substrate 102 and a carrier
substrate 308. The BEOL metallization stack 306 includes a
plurality of metallization layers 310, 312 stacked within an
interlayer dielectric (ILD) layer 314. One or more contacts 316 of
the BEOL metallization stack 306 extend from a metallization layer
310 to the pixel sensors 104. Further, one or more vias 318 of the
BEOL metallization stack 306 extend between the metallization
layers 310, 312 to interconnect the metallization layers 310, 312.
The ILD layer 314 may be, for example, a low .kappa. dielectric
(i.e., a dielectric with a dielectric constant less than about 3.9)
or an oxide. The metallization layers 310, 312, the contacts 316,
and the vias 318 may be, for example, a metal, such as copper or
aluminum.
[0047] An ARC 108 and/or a buffer layer 110 are arranged along the
back side 304 of the integrated circuit 302, and a stacked grid 113
is arranged over the ARC 108 and/or the buffer layer 110. The
stacked grid 113 includes a metallic grid 114 and a dielectric grid
116 overlying the metallic grid 114. The metallic grid 114 and the
dielectric grid 116 are respectively arranged within metallic and
dielectric grid layers 126, 128 stacked over the ARC 108 and/or the
buffer layer 110. In some embodiments, the dielectric grid 116 is
further arranged within an etch stop layer 130 underlying a
dielectric grid layer 128 of the dielectric grid 116. Further, the
metallic grid 114 and the dielectric grid 116 respectively define
sidewalls for metallic grid openings 118 and dielectric grid
openings 120 corresponding to the pixel sensors 104. The metallic
grid openings 118 have substantially planar lower surfaces 122,
which may be defined by the ARC 108 and/or the buffer layer 110,
whereas the dielectric grid openings 120 have curved lower surfaces
124. The curved lower surfaces 124 may be concave (e.g., as
illustrated, and described in FIG. 1A) or convex (e.g., as
described in FIG. 1B).
[0048] A capping layer 132 is arranged over the metallic grid 114
between the metallic grid layer 126 and the dielectric grid layer
128. Further, color filters 134, 136, 138 and micro lenses 144
corresponding to the pixel sensors 104 are over the corresponding
pixel sensors 104. The color filters 134, 136, 138 fill the
dielectric grid openings 120, and the micro lenses 144 mask the
color filters 134, 136, 138 to focus light into the color filters
134, 136, 138.
[0049] With reference to FIG. 4, a flowchart 400 of some
embodiments of a method for manufacturing a BSI image sensor having
color filters with curved lower surfaces.
[0050] At 402, an integrated circuit is provided with pixel sensors
arranged in a semiconductor substrate of the integrated circuit
between a back side of the integrated circuit and a BEOL
metallization stack of the integrated circuit.
[0051] At 404, an ARC is formed over the back side, a buffer layer
is formed over the ARC, and a metallic grid layer is formed over
the buffer layer.
[0052] At 406, a first etch is performed into the metallic grid
layer to form a metallic grid. The metallic grid defines sidewalls
for metallic grid openings corresponding to the pixel sensors.
[0053] At 408, a capping layer is formed over the metallic grid and
filling the metallic grid openings.
[0054] At 410, a chemical mechanical polish (CMP) is performed into
the capping layer to planarize an upper surface of the capping
layer.
[0055] At 412, an etch stop layer is formed over the capping layer,
and a dielectric grid layer is formed over the etch stop layer.
[0056] At 414, a second etch into the dielectric grid layer to the
etch stop layer to form a dielectric grid. The dielectric grid
defines dielectric grid openings corresponding to the pixel
sensors.
[0057] At 416, a third etch is performed into the etch stop layer
to remove exposed regions of the etch stop layer in the dielectric
grid openings.
[0058] At 418, a fourth etch is performed into the capping layer to
curve lower surfaces of the dielectric grid openings.
[0059] At 420, color filters are formed filling the dielectric grid
openings with refractive indexes different than a refractive index
of the capping layer. Advantageously, the differing refractive
indexes, combined with the curved lower surfaces of the dielectric
grid openings, focus radiation towards underlying pixel sensors.
This advantageously reduces dispersion of radiation proximate the
lower surface of the dielectric grid, and reduces crosstalk between
neighboring pixel sensors. Further, this advantageously improves
optical performance.
[0060] At 422, micro lenses are formed over the color filters.
[0061] While the method described by the flowchart 400 is
illustrated and described herein as a series of acts or events, it
will be appreciated that the illustrated ordering of such acts or
events are not to be interpreted in a limiting sense. For example,
some acts may occur in different orders and/or concurrently with
other acts or events apart from those illustrated and/or described
herein. Further, not all illustrated acts may be required to
implement one or more aspects or embodiments of the description
herein, and one or more of the acts depicted herein may be carried
out in one or more separate acts and/or phases.
[0062] In some alternative embodiments, the second and third
etches, and/or the third and fourth etches, may be performed
together (e.g., with a common etchant). Further, in some
embodiments, the etch stop layer and Act 416 may be omitted. In
such embodiments, the second etch may be time based using known
etch rates. Even more, in some alternative embodiments, the capping
layer and the dielectric grid layer may correspond to different
regions of a common layer. In such embodiments, Acts 408, 410, 412
may be omitted. In place of Acts 408, 410, 412, a common layer may
formed (e.g., with a single deposition) over the metallic grid and
filling the metallic grid openings. Further, a CMP may be performed
into the common layer to planarize an upper surface of the common
layer, and Acts 414-422 may be performed. Moreover, in some
embodiments, the fourth etch may be omitted.
[0063] With reference to FIGS. 5-11, 12A & B, and 13A & B,
cross-sectional views of some embodiments of a BSI image sensor at
various stages of manufacture are provided to illustrate the method
of FIG. 4. Although FIGS. 5-11, 12A & B, and 13A & B are
described in relation to the methods, it will be appreciated that
the structures disclosed in FIGS. 5-11, 12A & B, and 13A &
B are not limited to the methods, but instead may stand alone as
structures independent of the methods. Similarly, although the
methods are described in relation to FIGS. 5-11, 12A & B, and
13A & B, it will be appreciated that the methods are not
limited to the structures disclosed in FIGS. 5-11, 12A & B, and
13A & B, but instead may stand alone independent of the
structures disclosed in FIGS. 5-11, 12A & B, and 13A &
B.
[0064] FIG. 5 illustrates a cross-sectional view 500 of some
embodiments corresponding to Act 402. As illustrated, a
semiconductor substrate 102 with pixel sensors 104 arranged within
the substrate 102 is provided. In some embodiments, the
semiconductor semiconductor substrate 102 is part of an integrated
circuit and the pixel sensors 104 are arranged between a back side
of the integrated circuit (e.g., an upper surface 112 of the
semiconductor substrate 102) and a BEOL metallization stack (not
shown) of the integrated circuit. The pixel sensors 104 include
photodetectors 106, such as photodiodes. The semiconductor
substrate 102 may be, for example, a bulk semiconductor substrate
or a silicon-on-insulator (SOI) substrate.
[0065] FIG. 6 illustrates a cross-sectional view 600 of some
embodiments corresponding to Act 404. As illustrated, an ARC 108
and/or a buffer layer 110 are formed stacked in that order over the
semiconductor substrate 102. Further, a metallic grid layer 126' is
formed over the ARC 108 and/or the buffer layer 110. The ARC 108,
the buffer layer 110, and the metallic grid layer 126' may be
sequentially formed by deposition techniques, such as spin coating
or vapor deposition. The ARC 108 may be formed of, for example, an
organic polymer or a metallic oxide. The buffer layer 110 may be
formed of, for example, an oxide, such as silicon dioxide. The
metallic grid layer 126' may be formed of, for example, tungsten,
copper, aluminum, or aluminum copper.
[0066] FIG. 7 illustrates a cross-sectional view 700 of some
embodiments corresponding to Act 406. As illustrated, a first etch
is performed into the metallic grid layer 126', through regions
overlying the pixel sensors 104, to the ARC 108 and/or the buffer
layer 110. The first etch forms a metallic grid 114 defining
sidewalls for metallic grid openings 118 corresponding to the pixel
sensors 104. Typically, the metallic grid openings 118 at least
partially overly the corresponding pixel sensors 104.
[0067] The process for performing the first etch may include
forming a first photoresist layer 702 masking regions of the
metallic grid layer 126' corresponding to the metallic grid 114. An
etchant 704 may then be applied to the metallic grid layer 126'
according to a pattern of the first photoresist layer 702, thereby
defining the metallic grid 114. The etchant 704 may be selective of
the metallic grid layer 126' relative to the ARC 108 and/or the
buffer layer 110. Further, the etchant 704 may be, for example, a
dry etchant. After applying the etchant 704, the first photoresist
layer 702 may be removed or otherwise stripped.
[0068] FIG. 8 illustrates a cross-sectional view 800 of some
embodiments corresponding to Act 408. As illustrated, a capping
layer 132' is formed over the metallic grid 114 and the remaining
metallic grid layer 126, and filling the metallic grid openings
118. The capping layer 132' may be formed of, for example, a
dielectric, such as an oxide, and/or may be formed of, for example,
the same material as the buffer layer 110. Further, the capping
layer 132' may be formed using, for example, a deposition
technique, such as spin coating or vapor deposition.
[0069] FIG. 9 illustrates a cross-sectional view 900 of some
embodiments corresponding to Acts 410 and 412. As illustrated, a
CMP is performed into the capping layer 132' to a point over the
remaining metallic grid layer 126, thereby resulting in a
substantially planar upper surface 902. Also illustrated, an etch
stop layer 130' and a dielectric grid layer 128' are formed stacked
in that order over the remaining capping layer 132''. The etch stop
layer 130' and the dielectric grid layer 128' may be formed using,
for example, a deposition technique, such as vapor deposition. The
etch stop layer 130' may be formed of, for example, a nitride, such
as silicon nitride. The dielectric grid layer 128' may be formed
of, for example, silicon dioxide, and/or may be formed of, for
example, the same material as the remaining capping layer 132''. In
alternative embodiments, the etch stop layer 130' may be
omitted.
[0070] FIG. 10 illustrates a cross-sectional view 1000 of some
embodiments corresponding to Act 414. As illustrated, a second etch
is performed into the dielectric grid layer 128', through regions
overlying the pixel sensors 104, to the etch stop layer 130'. The
second etch forms a dielectric grid 116' defining sidewalls for
dielectric grid openings 120' corresponding to the pixel sensors
104. Typically, the dielectric grid openings 120' at least
partially overly the corresponding pixel sensors 104.
[0071] The process for performing the second etch may include
forming a second photoresist layer 1002 masking regions of the
dielectric grid layer 128' corresponding to the dielectric grid
116'. An etchant 1004 may then be applied to the dielectric grid
layer 128' according to a pattern of the second photoresist layer
1002, thereby defining the dielectric grid 116'. The etchant 1004
may be selective of the dielectric grid layer 128' relative to the
etch stop layer 130'. Further, the etchant 1004 may be, for
example, a dry etchant. After applying the etchant 1004, the second
photoresist layer 1002 may be removed or otherwise stripped.
[0072] FIG. 11 illustrates a cross-sectional view 1100 of some
embodiments corresponding to Act 416. As illustrated, a third etch
is performed into the etch stop layer 130', through exposed regions
in the dielectric grid openings 120', to the remaining capping
layer 132''. The third etch removes regions of the etch stop layer
130' in the dielectric grid openings 120'. The process for
performing the third etch may include, for example, applying an
etchant 1102 to the etch stop layer 130'. The etchant 1102 may be
selective of the etch stop layer 130' relative to the dielectric
grid layer 128 and/or the remaining capping layer 132''. Further,
the etchant 1102 may be, for example, a wet etchant.
[0073] FIGS. 12A & B illustrate cross-sectional views 1200A,
1200B of some embodiments corresponding to Acts 418, 420, and 422.
These embodiments are directed towards dielectric grid openings
with concave lower surfaces.
[0074] As illustrated by FIG. 12A, a fourth etch is performed into
the remaining capping layer 132'', through exposed regions of the
remaining capping layer 132'', to form concave lower surfaces 124A
for the remaining dielectric grid openings 120''. The process for
performing the fourth etch may include, for example, applying one
or more etchants 1202 to the remaining capping layer 132'' with
etching parameters, such as etch rates, tuned to define the concave
lower surfaces 124A. For example, the etching parameters may be
tuned so the remaining capping layer 132'' is etched faster at
centers of the remaining dielectric grid openings 120'' than at
peripheries of the remaining dielectric grid openings 120''. The
one or more etchants 1202 may be selective of the remaining capping
layer 132'' relative to the remaining etch stop layer 130, and/or
may be, for example, a wet or dry etchant. Since the one or more
etchants 1202 are applied through the remaining dielectric grid
openings 120'', and the remaining dielectric grid layer 128 and the
remaining capping layer 132'' may be the same material, the one or
more etchants 1202 may erode sidewalls of the remaining dielectric
grid openings 120''.
[0075] In alternative embodiments, the fourth etch may be replaced
with another approach for forming the concave lower surfaces 124A.
In some of such alternative embodiments, the concave lower surfaces
124A may be formed by a reflow process (e.g., a servo controlled
reflow process). In others of such alternative embodiments, the
concave lower surfaces 124A may be formed by a deposition with
deposition parameters, such as deposition rates, tuned to define
the concave lower surfaces 124A. For example, the deposition
parameters may be tuned so the deposition rate is slower at centers
of the remaining dielectric grid openings 120'' than at peripheries
of the remaining dielectric grid openings 120''. Such a deposition
may be construed as a second capping layer and/or an extension of
the remaining capping layer 132''.
[0076] As illustrated by FIG. 12B, color filters 134A, 136A, 138A
corresponding to the pixel sensors 104 are formed in the remaining
dielectric grid openings 120A of the corresponding pixel sensors
104, typically with upper surfaces 140 approximately even with an
upper surface 142 of the remaining dielectric grid layer 128. The
color filters 134A, 136A, 138A are assigned corresponding colors or
wavelengths of radiation (e.g., according to a Bayer filter
mosaic), and formed of materials configured to transmit the
assigned colors or wavelengths of radiation to the corresponding
pixel sensors 104. Further, the color filters 134A, 136A, 138A are
formed with materials having refractive indexes greater than the
remaining capping layer 132A, and/or any other material abutting
and underlying the concave lower surfaces 124A. The process for
forming the color filters 134A, 136A, 138A may include, for each of
the different color filter assignments, forming a color filter
layer and patterning the color filter layer. The color filter layer
may be formed so as to fill the remaining dielectric grid openings
120A and to cover the remaining dielectric grid layer 128. The
color filter layer may then be planarized (e.g., by CMP) and/or
etched back to about even with the upper surface 142 of the
remaining dielectric grid layer 128, before patterning the color
filter layer.
[0077] As also illustrated by FIG. 12B, micro lenses 144
corresponding to the pixel sensors 104 are formed over the color
filters 134A, 136A, 138A of the corresponding pixel sensors 104.
The process for forming the micro lenses 144 may include forming a
micro lens layer above the color filters 134A, 136A, 138A (e.g., by
a spin-on method or a deposition process). Further, a micro lens
template having a curved upper surface may be patterned above the
micro lens layer. The micro lens layer may then be selectively
etched according to the micro lens template to form the micro
lenses 144.
[0078] FIGS. 13A & B illustrate cross-sectional views 1300A,
1300B of other embodiments corresponding to Acts 418, 420, and 422.
These embodiments are directed towards dielectric grid openings
with convex lower surfaces.
[0079] As illustrated by FIG. 13A, a fourth etch is performed into
the remaining capping layer 132'', through exposed regions of the
remaining capping layer 132'', to form convex lower surfaces 124B
for the remaining dielectric grid openings 120''. The process for
performing the fourth etch may include, for example, applying one
or more etchants 1302 to the remaining capping layer 132'' with
etching parameters tuned to define the convex lower surfaces 124B.
For example, the etching parameters may be tuned so the remaining
capping layer 132'' is etched faster at peripheries of the
remaining dielectric grid openings 120'' than at centers of the
remaining dielectric grid openings 120''. The one or more etchants
1302 may be selective of the remaining capping layer 132'' relative
to the remaining etch stop layer 130, and/or may be, for example, a
wet or dry etchant.
[0080] In alternative embodiments, the fourth etch may be replaced
with another approach for forming the convex lower surfaces 124B.
In some of such alternative embodiments, the convex lower surfaces
124B may be formed by a reflow process. In others of such
alternative embodiments, the convex lower surfaces 124B may be
formed by a deposition with deposition parameters tuned to define
the convex lower surfaces 124B. For example, the deposition
parameters may be tuned so the deposition rate is slower at
peripheries of the remaining dielectric grid openings 120'' than at
centers of the remaining dielectric grid openings 120''. Such a
deposition may be construed as a second capping layer and/or an
extension of the remaining capping layer 132''.
[0081] As illustrated by FIG. 13B, color filters 134B, 136B, 138B
corresponding to the pixel sensors 104 are formed in the remaining
dielectric grid openings 120A of the corresponding pixel sensors
104, typically with upper surfaces 140 approximately even with an
upper surface 142 of the remaining dielectric grid layer 128.
Further, the color filters 134B, 136B, 138B are formed with
materials having refractive indexes less than the remaining capping
layer 132B, and/or any other material abutting and underlying the
convex lower surfaces 124B.
[0082] Also illustrated by FIG. 13B, micro lenses 144 corresponding
to the pixel sensors 104 are formed over the color filters 134B,
136B, 138B, of the corresponding pixel sensors 104.
[0083] Thus, as can be appreciated from above, the present
disclosure provides a back-side illuminated (BSI) image sensor
including a pixel sensor arranged within a semiconductor substrate.
A metallic grid segment is arranged over the pixel sensor, having a
metallic grid opening therein, wherein the metallic grid segment
has a metallic grid height. A dielectric grid segment is arranged
over the metallic grid segment having a dielectric grid opening
therein, wherein the dielectric grid segment has a dielectric grid
height. A ratio of the dielectric grid height to the metallic grid
height is between about 1.0 to about 8.0.
[0084] In other embodiments, the present disclosure provides a
back-side illuminated (BSI) image sensor including a pixel sensor
arranged within a semiconductor substrate. A metallic grid segment
is arranged over the pixel sensor having a metallic grid opening
therein. The metallic grid segment has a top metallic grid width
and the metallic grid opening has a bottom metallic grid opening
width. A dielectric grid segment is arranged over the metallic grid
segment having a dielectric grid opening therein. The dielectric
grid segment has a top dielectric grid width, wherein at least one
of, a ratio of the top dielectric grid width to the top metallic
grid width is between about 0.1 to about 2.0, and a ratio of the
top dielectric grid width to the bottom metallic grid opening width
is between about 0.1 to about 0.9.
[0085] In another embodiment, the present disclosure provides a
back-side illuminated (BSI) image sensor including a pixel sensor
arranged within a semiconductor substrate. A metallic grid segment
is arranged over the pixel sensor having a metallic grid opening
therein. The metal grid opening has a bottom metallic grid opening
width. A dielectric grid segment is arranged over the metallic grid
segment, having a dielectric grid opening therein. A stacked grid
structure height extends from between the semiconductor substrate
and the metallic grid segment to an upper surface of the dielectric
grid segment. A ratio of the stacked grid structure height to the
bottom metallic grid opening width is about 0.5 to about 2.0.
[0086] In yet other embodiments, the present disclosure provides a
back-side illuminated (BSI) image sensor including a pixel sensor
arranged within a semiconductor substrate. A metallic grid segment
is arranged over the pixel sensor, having a metallic grid opening
therein. A dielectric grid segment is arranged over the metallic
grid segment, having a dielectric grid opening therein. An angle
between a lower surface of the dielectric grid segment and a
sidewall of the dielectric grid segment is about 60 degrees to
about less than 90 degrees.
[0087] The foregoing outlines features of several embodiments so
that those skilled in the art may better understand the aspects of
the present disclosure. Those skilled in the art should appreciate
that they may readily use the present disclosure as a basis for
designing or modifying other processes and structures for carrying
out the same purposes and/or achieving the same advantages of the
embodiments introduced herein. Those skilled in the art should also
realize that such equivalent constructions do not depart from the
spirit and scope of the present disclosure, and that they may make
various changes, substitutions, and alterations herein without
departing from the spirit and scope of the present disclosure.
* * * * *