U.S. patent application number 15/853477 was filed with the patent office on 2018-07-19 for method for preparing a semiconductor package.
The applicant listed for this patent is NANYA TECHNOLOGY CORPORATION. Invention is credited to CHIN-LUNG CHU, PO-CHUN LIN.
Application Number | 20180204814 15/853477 |
Document ID | / |
Family ID | 61711645 |
Filed Date | 2018-07-19 |
United States Patent
Application |
20180204814 |
Kind Code |
A1 |
LIN; PO-CHUN ; et
al. |
July 19, 2018 |
METHOD FOR PREPARING A SEMICONDUCTOR PACKAGE
Abstract
The present disclosure provides a method far preparing a
semiconductor package. The semiconductor package includes a
semiconductor device having an upper surface and a side, wherein
the upper surface and the side form a corner of the semiconductor
device. The semiconductor package also includes a lateral bump
structure disposed on the side and implementing a lateral signal
path of the semiconductor device. The semiconductor package further
includes a vertical hump structure disposed over the upper surface
and implementing a vertical signal path of the semiconductor
device.
Inventors: |
LIN; PO-CHUN; (CHANGHUA
CITY, TW) ; CHU; CHIN-LUNG; (TAOYUAN CITY,
TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
NANYA TECHNOLOGY CORPORATION |
New Taipei City |
|
TW |
|
|
Family ID: |
61711645 |
Appl. No.: |
15/853477 |
Filed: |
December 22, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
15410246 |
Jan 19, 2017 |
9935071 |
|
|
15853477 |
|
|
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Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/14183
20130101; H01L 2224/13111 20130101; H01L 2224/81805 20130101; H01L
2924/18162 20130101; H01L 2224/12105 20130101; H01L 2224/05568
20130101; H01L 24/94 20130101; H01L 2224/05569 20130101; H01L
2224/05611 20130101; H01L 2224/131 20130101; H01L 2224/05548
20130101; H01L 2224/24137 20130101; H01L 24/11 20130101; H01L
2224/11849 20130101; H01L 2224/13139 20130101; H01L 2224/0401
20130101; H01L 2224/05647 20130101; H01L 24/81 20130101; H01L
2224/1147 20130101; H01L 2924/15192 20130101; H01L 2224/05655
20130101; H01L 24/16 20130101; H01L 2224/05639 20130101; H01L 24/05
20130101; H01L 2224/16137 20130101; H01L 24/13 20130101; H01L
2224/06183 20130101; H01L 2224/1132 20130101; H01L 2224/13147
20130101; H01L 24/96 20130101; H01L 2224/1403 20130101; H01L
2224/04105 20130101; H01L 2224/94 20130101; H01L 2224/0603
20130101; H01L 2224/1418 20130101; H01L 2224/05624 20130101; H01L
2224/13026 20130101; H01L 2224/81815 20130101; H01L 24/03 20130101;
H01L 2224/05644 20130101; H01L 25/0655 20130101; H01L 2225/06551
20130101; H01L 23/3114 20130101; H01L 24/14 20130101; H01L 2224/94
20130101; H01L 2224/03 20130101; H01L 2224/94 20130101; H01L
2224/11 20130101; H01L 2224/05655 20130101; H01L 2924/00014
20130101; H01L 2224/13111 20130101; H01L 2924/014 20130101; H01L
2924/01029 20130101; H01L 2924/01047 20130101; H01L 2924/00014
20130101; H01L 2224/05639 20130101; H01L 2924/00014 20130101; H01L
2224/05647 20130101; H01L 2924/00014 20130101; H01L 2224/05644
20130101; H01L 2924/00014 20130101; H01L 2224/05624 20130101; H01L
2924/00014 20130101; H01L 2224/13147 20130101; H01L 2924/014
20130101; H01L 2924/01047 20130101; H01L 2924/0105 20130101; H01L
2924/00014 20130101; H01L 2224/13139 20130101; H01L 2924/014
20130101; H01L 2924/01029 20130101; H01L 2924/0105 20130101; H01L
2924/00014 20130101; H01L 2224/131 20130101; H01L 2924/01322
20130101; H01L 2924/014 20130101; H01L 2924/00014 20130101; H01L
2224/05611 20130101; H01L 2924/00014 20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00; H01L 23/31 20060101 H01L023/31; H01L 21/56 20060101
H01L021/56 |
Claims
1. A method for preparing a semiconductor package, comprising:
providing a semiconductor device having a bulk region and an edge
region adjacent to the bulk region; forming a depression in the
edge region, wherein the depression exposes a side of the bulk
region; and forming a lateral bump structure in the depression,
wherein the lateral bump structure is formed on the side and
implements a lateral signal path of the semiconductor device.
2. The method for preparing a semiconductor package of claim 1,
comprising: forming a mask over an upper surface of the
semiconductor device, wherein the mask has an aperture exposing a
portion of the edge region; and performing an etching process to
remove a portion of the edge region exposed by the aperture to form
the depression.
3. The method for preparing a semiconductor package of claim 2,
further comprising: forming a bumping material in the depression;
removing the mask; and performing a thermal process to form the
lateral bump structure.
4. The method for preparing a semiconductor package of claim 3,
further comprising: performing an etching process to increase a
depth of the depression before the thermal process.
5. The method for preparing a semiconductor package of claim 3,
further comprising: performing a grinding process from a bottom
surface of the semiconductor device to remove the edge region of
the semiconductor device after the thermal process.
6. The method for preparing a semiconductor package of claim 1,
forming a mask over an upper surface of the semiconductor device,
wherein the mask has an opening exposing a portion of the bulk
region.
7. The method for preparing a semiconductor package of claim 6,
further comprising: forming a bumping material in the opening;
removing the mask; and performing a thermal process to form a
vertical bump structure on the bulk region.
8. The method for preparing a semiconductor package of claim 1,
further comprising: forming a vertical bump structure over an upper
surface of the semiconductor device and implementing a vertical
signal path of the semiconductor device.
9. The method for preparing a semiconductor package of claim 8,
wherein the vertical bump structure is integrally formed with the
lateral bump structure.
Description
PRIORITY CLAIM AND CROSS-REFERENCE
[0001] This patent application is a divisional application of and
claims priority to U.S. patent application Ser. No. 15/410,246,
filed on Jan. 19, 2017, which is incorporated by reference in its
entirety.
TECHNICAL FIELD
[0002] The present disclosure relates to a semiconductor package
and to a method for preparing the same, and particularly relates to
a semiconductor package having a lateral bump structure
implementing a lateral signal path between two laterally adjacent
devices and a method for preparing the same.
DISCUSSION OF THE BACKGROUND
[0003] Semiconductor devices are essential for many modern
applications. With the advancement of electronic technology,
semiconductor devices are becoming smaller in size while having
greater functionality and greater amounts of integrated circuitry.
Due to the miniaturized scale of semiconductor devices,
chip-on-chip technique is now widely used for manufacturing
semiconductor devices. Numerous manufacturing steps are undertaken
in the production of such semiconductor packages.
[0004] Accordingly, the manufacturing of semiconductor devices in a
miniaturized scale is becoming more complicated. An increase in the
complexity of manufacturing semiconductor devices may cause
deficiencies such as poor electrical interconnection, development
of cracks, or delamination of components. As such, there are many
challenges to be overcome when modifying the structure and
manufacture of semiconductor devices.
[0005] This Discussion of the Background section is provided for
background information only. The statements in this Discussion of
the Background are not an admission that the subject matter
disclosed in this section constitutes prior art to the present
disclosure, and no part of this Discussion of the Background
section may be used as an admission that any part of this
application, including this Discussion of the Background section,
constitutes prior art to the present disclosure.
SUMMARY
[0006] One aspect of the present disclosure provides a
semiconductor package comprising a semiconductor device having an
upper surface and a side, wherein the upper surface and the side
form a corner of the semiconductor device; and a lateral hump
structure disposed on the side and implementing a lateral signal
path of the semiconductor device.
[0007] In some embodiments, the semiconductor package further
comprises a vertical bump structure disposed aver the upper surface
and implementing a vertical signal path of the semiconductor
device, wherein the vertical bump structure is separated from the
lateral bump structure.
[0008] in some embodiments, the lateral bump structure extends
laterally from the side.
[0009] In some embodiments, the vertical bump structure extends
vertically from the upper surface.
[0010] In some embodiments, the semiconductor package further
comprises a contact pad disposed between the side and the lateral
bump structure.
[0011] Another aspect of the present disclosure provides a
semiconductor package, comprising: a first semiconductor device
having a first upper surface and a first side, wherein the first
upper surface and the first side form a first corner of the first
semiconductor device; a second semiconductor device laterally
adjacent to the first semiconductor device, wherein the second
semiconductor device comprises a second upper surface and a second
side, and the second upper surface and the second side form a
second corner of the second semiconductor device; and a lateral
bump structure extending from the first side to the second side and
implementing a lateral signal path between the first semiconductor
device and the second semiconductor device.
[0012] In some embodiments, the semiconductor package further
comprises: a molding member surrounding the first semiconductor
device and the second semiconductor device, wherein an intervening
portion of the molding member is disposed between the first
semiconductor device and the second semiconductor device; wherein
the lateral bump structure extends laterally across the intervening
portion.
[0013] In some embodiments, the semiconductor package further
comprises a first hump structure disposed over the first upper
surface, wherein the first vertical bump structure is separated
from the lateral bump structure.
[0014] In some embodiments, the semiconductor package further
comprises a second bump structure disposed over the second upper
surface, wherein the second vertical bump structure is separated
from the lateral bump structure.
[0015] In some embodiments, the lateral bump structure extends
vertically across the first upper surface and the second upper
surface.
[0016] In some embodiments, the semiconductor package further
comprises a contact pad disposed between the first side and the
lateral bump structure.
[0017] Another aspect of the present disclosure provides a method
for preparing a semiconductor package, comprising: providing a
semiconductor device having a bulk region and an edge region
adjacent to the bulk region; forming a depression in the edge
region, wherein the depression exposes a side of the bulk region;
and forming a lateral bump structure in the depression, wherein the
lateral bump structure is formed on the side and implements a
lateral signal path of the semiconductor device.
[0018] In some embodiments, the method for preparing a
semiconductor package comprises: forming a mask over an upper
surface of the semiconductor device, wherein the mask has an
aperture exposing a portion of the edge region; and performing an
etching process to remove a portion of the edge region exposed by
the aperture to form the depression.
[0019] In some embodiments, the method for preparing a
semiconductor package comprises: forming a bumping material in the
depression; removing the mask; and performing a thermal process to
form the lateral hump structure.
[0020] In some embodiments, the method for preparing a
semiconductor package further comprises performing an etching
process to increase a depth of the depression before the thermal
process.
[0021] In some embodiments, the method for preparing a
semiconductor package further comprises performing a grinding
process from a bottom surface of the semiconductor device to remove
the edge region of the semiconductor device after the thermal
process.
[0022] In sonic embodiments, the method for preparing a
semiconductor package comprises forming a mask over an upper
surface of the semiconductor device, wherein the mask has an
opening exposing a portion of the bulk region.
[0023] In some embodiments, the method for preparing a
semiconductor package further comprises: forming a bumping material
in the opening; removing the mask; and performing a thermal process
to form a vertical bump structure on the bulk region.
[0024] In some embodiments, the method for preparing a
semiconductor package further comprises forming a vertical bump
structure over an upper surface of the semiconductor device and
implementing a vertical signal path of the semiconductor
device.
[0025] In some embodiments, the method for preparing a
semiconductor package integrally forms the vertical bump structure
with the lateral bump structure.
[0026] The embodiments of the present disclosure provide a
semiconductor package with a lateral bump structure implementing
the lateral signal path between the two laterally adjacent
semiconductor devices in the absence of a redistribution structure.
Consequently, the height of the semiconductor package of the
present disclosure is less than the height of the semiconductor
package with a redistribution structure. In other words, the
semiconductor package of the present disclosure can meet the
miniaturized scale demand (small form factor) of the semiconductor
packages. In addition, the absence of the redistribution structure
is a key factor in the reduction of the fabrication cost of the
semiconductor package.
[0027] The lateral extension of the lateral bump structure from the
side of the semiconductor device can contact a corresponding
conductor of a laterally adjacent device to implement a lateral
signal path between the semiconductor device and the laterally
adjacent device in the absence of a redistribution structure
corresponding to the redistribution layer.
[0028] The foregoing has outlined rather broadly the features and
technical advantages of the present disclosure in order that the
detailed description of the disclosure that follows may be better
understood. Additional features and advantages of the disclosure
will be described hereinafter, and form the subject of the claims
of the disclosure. It should be appreciated by those skilled in the
art that the conception and specific embodiment disclosed may be
readily utilized as a basis for modifying or designing other
structures or processes for carrying out the same purposes of the
present disclosure. It should also be realized by those skilled in
the art that such equivalent constructions do not depart from the
spirit and scope of the disclosure as set forth in the appended
claims.
BRIEF DESCRIPTION OF THE DRAWINGS
[0029] A more complete understanding of the present disclosure may
be derived by referring to the detailed description and claims when
considered in connection with the Figures, where like reference
numbers refer to similar elements throughout the Figures.
[0030] FIG. 1 is a cross-sectional view of a semiconductor package
in accordance with a comparative embodiment of the present
disclosure.
[0031] FIG. 2 is a cross-sectional view of a semiconductor package
in accordance with some embodiments of the present disclosure.
[0032] FIG. 3 is a cross-sectional view of a semiconductor package
in accordance with some embodiments of the present disclosure.
[0033] FIG. 4 is a cross-sectional view of a semiconductor package
in accordance with some embodiments of the present disclosure.
[0034] FIG. 5 is a flow chart of a method for preparing a
semiconductor package in accordance with some embodiments of the
present disclosure.
[0035] FIGS. 6 to 10 are schematic views of a process for preparing
the semiconductor package by the method of FIG. 5 in accordance
with some embodiments of the present disclosure.
[0036] FIGS. 11 to 15 are schematic views of a process for
preparing the semiconductor package by the method of FIG. 5 in
accordance with some embodiments of the present disclosure.
[0037] FIGS. 16 to 21 are schematic views of a process for
preparing the semiconductor package by the method of FIG. 5 in
accordance with some embodiments of the present disclosure.
DETAILED DESCRIPTION
[0038] The following description of the disclosure accompanies
drawings, which are incorporated in and constitute a part of this
specification, and which illustrate embodiments of the disclosure,
but the disclosure is not limited to the embodiments. In addition,
the following embodiments can be properly integrated to complete
another embodiment.
[0039] References to "one embodiment," "an embodiment," "exemplary
embodiment," "other embodiments," "another embodiment," etc.
indicate that the embodiment(s) of the disclosure so described may
include a particular feature, structure, or characteristic, but not
every embodiment necessarily includes the particular feature,
structure, or characteristic. Further, repeated use of the phrase
"in the embodiment" does not necessarily refer to the same
embodiment, although it may.
[0040] The present disclosure is directed to a semiconductor
package having a lateral bump structure implementing a lateral
signal path between two laterally adjacent devices and a method for
preparing the same. In order to make the present disclosure
completely comprehensible, detailed steps and structures are
provided in the following description. Obviously, implementation of
the present disclosure does not limit special details known by
persons skilled in the art. In addition, known structures and steps
are not described in detail, so as not to unnecessarily limit the
present disclosure. Preferred embodiments of the present disclosure
will be described below in detail. However, in addition to the
detailed description, the present disclosure may also be widely
implemented in other embodiments. The scope of the present
disclosure is not limited to the detailed description, and is
defined by the claims.
[0041] FIG. 1 is a cross-sectional view of a semiconductor package
10 in accordance with a comparative embodiment of the present
disclosure. The semiconductor package 10 includes a redistribution
layer 11, a semiconductor chip and a semiconductor chip 13B
disposed on the redistribution layer 11, a molding member 15
encapsulating the semiconductor chip 13A and the semiconductor chip
13B on the redistribution layer 11, and a plurality of conductive
bumps 17 disposed on the redistribution layer 11. In some
embodiments, the conductive bumps 17 are disposed on the upper side
of the redistribution layer 11, while the semiconductor chip 13A
and the semiconductor chip 13B are disposed on the bottom side of
the redistribution layer 11.
[0042] In some embodiments, a vertical signal path of the
semiconductor chip 13A is implemented by a conductive line 11A in
the redistribution layer 11 and one of the conductive bumps 17, a
vertical signal path of the semiconductor chip 13B is implemented
by a conductive line 11B in the redistribution layer 11 and one of
the conductive bumps 17, and a lateral signal path between the
semiconductor chip 13A and the semiconductor chip 13B is
implemented by a conductive line 11C in the redistribution layer 11
in the absence of the conductive bumps 17.
[0043] FIG. 2 is a cross-sectional view of a semiconductor package
100A in accordance with some embodiments of the present disclosure.
In some embodiments, the semiconductor package 100A comprises a
semiconductor device 110A having an upper surface 111 and a side
113, a lateral bump structure 121A disposed on the side 113, and a
vertical bump structure 123A disposed aver the upper surface 111.
In some embodiments, the upper surface 111 and the side 113 form a
corner 114 of the semiconductor device 110A. In some embodiments,
the first side 113 is substantially perpendicular to the first
upper surface 111.
[0044] In some embodiments, the lateral bump structure 121A extends
laterally along the lateral direction (X-direction in the drawing)
from the side 113 of the semiconductor device 110.A and implements
a lateral signal path of the semiconductor device 110A. In some
embodiments, the vertical bump structure 123A extends vertically
along the vertical direction (Z-direction in the drawing) from the
upper surface 111 of the semiconductor device 110A and implements a
vertical signal path of the semiconductor device 110A. In sonic
embodiments, the vertical bump structure 123A is separated from the
lateral bump structure 121A.
[0045] In some embodiments, the semiconductor package 100A
comprises a semiconductor substrate 101 and an electrical
interconnect 103A; the semiconductor substrate 101 can be a silicon
substrate, a semiconductor-on-insulator (SUI) substrate, or any
construction comprising semiconductor materials; and the electrical
interconnect 103A comprises dielectric material and conductive
elements made of, for example, Ti, Al, Ni, nickel vanadium (NiV),
Cu, or a Cu alloy. In some embodiments, the semiconductor package
100A includes integrated circuits (IC) or semiconductor components
such as transistors, capacitors, resistors, diodes, photo-diodes,
fuses, and the like configured to perform one or more functions,
wherein the IC and semiconductor components are not shown for
clarity in this illustration.
[0046] In some embodiments, the electrical interconnect 103A of the
semiconductor package 100A comprises a lateral conductive contact
pad 105A, and the lateral bump structure 121A is disposed on the
lateral conductive contact pad 105A. In some embodiments, the
electrical interconnect 103A of the semiconductor package 100A
comprises a conductive contact pad 107A, and the vertical bump
structure 123A is disposed on the conductive contact pad 107A. In
some embodiments, the lateral conductive contact pad 105A and the
conductive contact pad 107A are made of aluminum (Al), copper C(u),
tin (Sn), nickel (Ni), gold (Au), silver (Ag), or other
electrically conductive materials.
[0047] In some embodiments, the lateral extension of the lateral
bump structure 121A from the side 113 of the semiconductor device
110A can be used to contact a corresponding conductor of a
laterally adjacent device to implement the lateral signal path
between the semiconductor device 110A and the laterally adjacent
device in the absence of a redistribution structure corresponding
to the redistribution layer 11 shown in FIG. 1.
[0048] FIG. 3 is a cross-sectional view of a semiconductor package
100B in accordance with some embodiments of the present disclosure.
The semiconductor package 100B shown in FIG. 3 is substantially the
same as the semiconductor package 100A shown in FIG. 2, except for
differences in the position of the lateral conductive contact pad
and the lateral bump structure. In FIG. 2, the lateral conductive
contact pad 105A of the semiconductor device 110A is embedded on
the left of the side 113, whereas in FIG. 3, the conductive contact
pad 105B of the semiconductor device 110B is implemented by
conductive elements of the electrical interconnect 103B and
disposed on the right of the side 113. In some embodiments, the
lateral bump structure 121B of the semiconductor device 110B
extends vertically across the upper surface 111, as shown in FIG.
3.
[0049] FIG. 4 is a cross-sectional view of a semiconductor package
100D in accordance with some embodiments of the present disclosure.
In some embodiments, the semiconductor package 100D comprises: a
first semiconductor device 130A; a second semiconductor device 130B
laterally adjacent to the first semiconductor device 130A; a
molding member 140 encapsulating the first semiconductor device
130A and the second semiconductor device 130B; and a lateral hump
structure 121D implementing a lateral signal path between the first
semiconductor device 130A and the second semiconductor device 130B.
In some embodiments, the first semiconductor device 130A and the
second semiconductor device 130B may be the semiconductor device
110A shown in FIG. 2 or the semiconductor device 110B shown in FIG.
3.
[0050] In some embodiments, the lateral bump structure 121D extends
laterally from one side 133A of the first semiconductor device 130A
to one side 133B of the second semiconductor device 130B, and the
side 133A faces the side 133B. In some embodiments, an intervening
portion 141 of the molding member 140 is disposed between the first
semiconductor device 130A and the second semiconductor device 130B,
and the lateral bump structure 121D extends laterally across the
intervening portion 141 of the molding member 140.
[0051] In some embodiments, the first semiconductor device 130A and
the second semiconductor device 130B are two adjacent chips of a
single wafer. In some embodiments, the first semiconductor device
130A and the second semiconductor device 130B are two chips from
different wafers. In some embodiments, the semiconductor package
100D further comprises a vertical bump structure 131A implementing
a vertical signal path of the first semiconductor device 130A and a
vertical bump structure 131B implementing a vertical signal path of
the second semiconductor device 130B.
[0052] In some embodiments, the lateral bump structure 121D
implements the lateral signal path between the first semiconductor
device 130A and the second semiconductor device 130B in the absence
of a redistribution structure corresponding to the redistribution
layer 11 shown in FIG. 1. Consequently, the height of the
semiconductor package 100D in FIG. 4 is less than the height of the
semiconductor package 10 in FIG. 1. In other words, the
semiconductor package 100D in FIG. 4 can meet the miniaturized
scale demand (small form factor) of the semiconductor packages. In
addition, the absence of a redistribution structure corresponding
to the redistribution layer 11 shown in FIG. 1 is a key factor in
the reduction of the fabrication cost of the semiconductor package
100D in FIG. 4.
[0053] FIG. 5 is a flow chart of a method for preparing a
semiconductor package in accordance with some embodiments of the
present disclosure. In some embodiments, the semiconductor package
can be formed by a method 300 of FIG. 5. The method 300 includes a
number of operations and the description and illustration are not
deemed as a limitation to the sequence of the operations. The
method 300 includes a number of steps (301, 303, and 305).
[0054] FIGS. 6 to 10 are schematic views of a process for preparing
the semiconductor package by the method of FIG. 5 in accordance
with some embodiments of the present disclosure. In step 301, a
semiconductor device 110A is provided as shown in FIG. 6. In some
embodiments, the semiconductor device 110A comprises a
semiconductor substrate 101 and an electrical interconnect 103A on
the semiconductor substrate 101.
[0055] In some embodiments, the semiconductor device 110A has a
bulk region 103 and an edge region 105 adjacent to the bulk region
103, several vertical conductive contact pads 1032 are formed in
the bulk region 103 and electrically connected to conductive vias
1034A of the electrical interconnect 103A, and a lateral conductive
contact pad 105A is formed in the bulk region 103 adjacent to the
edge region 105 and electrically connected to the electrical
interconnect 103A. In some embodiments, integrated circuits (IC) or
semiconductor components such as transistors, capacitors,
resistors, diodes, photo-diodes, fuses, and the like are formed in
the bulk region 103.
[0056] In step 303, a depression 1053A is formed in the edge region
105 of the semiconductor device 110A, as shown in FIG. 7. The
preparation of the depression 1053A includes forming a mask 109
over an upper surface 111 of the semiconductor device 110A, wherein
the mask 109 has an aperture 1091 exposing a portion of the edge
region 105 and a plurality of openings 1093 exposing a portion of
the bulk portion 103. Subsequently, an etching process such as a
dry etching with etchant 115 is performed to remove a portion of
the edge region 105 exposed by the aperture 1091 to form the
depression 1053A. In some embodiments, the depression 1053A exposes
the lateral conductive contact pad 105A, and the openings 1093
expose the vertical conductive contact pads 1032A.
[0057] In step 305, a lateral bump structure 121A is formed in the
depression 1053A, as shown in FIGS. 8-10. In FIG. 8, a bumping
material 117 is formed in the depression 1053A and on the vertical
conductive contact pads 1032A in the openings 1093. In some
embodiments, the bumping material 117 includes lead-free solders,
including tin, copper, and silver, or "SAC" compositions, and other
eutectics that have a common melting point and form conductive
solder connections in electrical applications.
[0058] In FIG. 9, the mask 109 is removed and a portion of the edge
portion 105 is then removed, for example by an etching process with
etchant 119. Subsequently, a thermal treating process such as an
infrared (IR) reflow process is performed to integrally form the
lateral bump structure 105A on the side 113 of the semiconductor
device 110A and the vertical bump structure 123A over the vertical
conductive contact pads 1032A on the semiconductor device 110A.
[0059] In FIG. 10, a grinding process is performed from a bottom
surface of the semiconductor device 110A to remove a bottom
portion. 102 such that the edge region 105 of the semiconductor
device 110A is completely removed after the thermal process.
Consequently, the lateral bump structure 121A on the lateral
conductive contact pad 105A can contact a contact pad of an
adjacent device and implements a lateral signal path of the
semiconductor device 110A and the adjacent device, while the
vertical bump structure 123A on the vertical conductive contact
pads 1032A implements a vertical signal path of the semiconductor
device 110A.
[0060] FIGS. 11 to 15 are schematic views of a process for
preparing the semiconductor package by the method of FIG. 5 in
accordance with some embodiments of the present disclosure. In step
301, a semiconductor device 110B is provided as shown in FIG. 11.
In some embodiments, the semiconductor device 110B comprises a
semiconductor substrate 101 and an electrical interconnect 103B on
the semiconductor substrate 101.
[0061] In some embodiments, the semiconductor device 110B has a
bulk region 103 and an edge region 105 adjacent to the bulk region
103, and several vertical conductive contact pads 1103B are formed
in the bulk region 103 and electrically connected to conductive
vias 1034B of the electrical interconnect 103B; in addition, a
lateral conductive contact pad 105B is implemented by conductive
elements of the electrical interconnect 103B in the bulk region 103
adjacent to the edge region 105. In some embodiments, integrated
circuits (IC) or semiconductor components such as transistors,
capacitors, resistors, diodes, photo-diodes, fuses, and the like
are formed in the bulk region 103.
[0062] In step 303, a depression 1053B is formed in the edge region
105 of the semiconductor device 110B, as shown in FIG. 12. The
preparation of the depression 1053B includes forming a mask 109
over an upper surface 111 of the semiconductor device 110B, wherein
the mask 109 has an aperture 1091 exposing a portion of the edge
region 105 and a plurality of openings 1093 exposing a portion of
the bulk portion 103. Subsequently, an etching process such as a
dry etching with etchant 115 is performed to remove a portion of
the edge region 105 exposed by the aperture 1091 to form the
depression 1053B. In some embodiments, the depression 1053B exposes
the lateral conductive contact pad 105B, and the openings 1093
expose the vertical conductive contact pads 1032B.
[0063] In step 305, a lateral bump structure 121B is formed in the
depression 1053B, as shown in FIGS. 13-15. In FIG. 13, a bumping
material 117 is formed in the depression 1053B and on the vertical
conductive contact pads 1032B in the openings 113. In some
embodiments, the bumping material 117 includes lead-free solders,
including tin, copper, and silver, or "SAC" compositions, and other
eutectics that have a common melting point and form conductive
solder connections in electrical applications.
[0064] in FIG. 14, the mask 109 is removed and a portion of the
edge portion 105 is then removed, for example by an etching process
with etchant 119. Subsequently, a thermal treating process such as
an. infrared (IR) reflow process is performed to integrally form
the lateral bump structure 121B on the side 113 of the
semiconductor device 110B and the vertical bump structure 123A on
the vertical conductive contact pads 1032B of the semiconductor
device 110B.
[0065] In FIG. 15, a grinding process is performed from a bottom
surface of the semiconductor device 110B to remove a bottom
portion. 102 such that the edge region 105 of the semiconductor
device 110A is completely removed after the thermal process.
Consequently, the lateral bump structure 121B on the lateral
conductive contact pad 105B can contact a contact pad of an
adjacent device and implements a lateral signal path of the
semiconductor device 110B and the adjacent device, while the
vertical bump structure 123A on the vertical conductive contact
pads 1032B implement a vertical signal path of the semiconductor
device 110B.
[0066] FIGS. 16 to 20 are schematic views of a process for
preparing the semiconductor package by the method of FIG. 5 in
accordance with some embodiments of the present disclosure. In step
301, a semiconductor device 110C is provided as shown in FIG. 16.
In some embodiments, the semiconductor device 110C comprises a
semiconductor substrate 101 and an electrical interconnect 103C on
the semiconductor substrate 101.
[0067] In some embodiments, the semiconductor device 110C has a
bulk region 103 and an edge region 105 adjacent to the bulk region
103, and several vertical conductive contact pads 1032C are formed
in the bulk region 103 and electrically connected to conductive
vias 1034C of the electrical interconnect 103C; in addition, a
lateral conductive contact pad 105C is formed in the bulk region
103 adjacent to the edge region 105 and electrically connected to
the conductive vias 1034C of the electrical interconnect 1030. In
some embodiments, integrated circuits (IC) or semiconductor
components such as transistors, capacitors, resistors, diodes,
photo-diodes, fuses, and the like are formed in the bulk region
103.
[0068] In step 303, a depression 1053C is formed in the edge region
105 of the semiconductor device 110C, as shown in FIG. 17. The
preparation of the depression 1053C includes forming a mask 109
over an upper surface 111 of the semiconductor device 110C, wherein
the mask 109 has an aperture 1091 exposing a portion of the edge
region 105 and a plurality of openings 1093 exposing a portion of
the bulk portion 103. Subsequently, an etching process such as a
dry etching with etchant 115 is performed to remove a portion of
the edge region. 105 exposed by the aperture 1091 to form the
depression 1053C. In some embodiments, the depression 1053C exposes
the lateral conductive contact pad 105C, and the openings 1093
expose the vertical conductive contact pads 1032C.
[0069] In step 305, a lateral bump structure 121C is formed in the
depression 1053C, as shown in FIGS. 18-20. In FIG. 18, a bumping
material 117 is formed in the depression 10530 and on the vertical
conductive contact pads 1032C in the openings 1093. In some
embodiments, the bumping material 117 includes lead-free solders,
including tin, copper, and silver, or "SAC" compositions, and other
eutectics that have a common melting point and form conductive
solder connections in electrical applications.
[0070] In FIG. 19, the mask 109 is removed and a portion of the
edge portion 105 is then removed, for example by an etching process
with etchant 119. Subsequently, a thermal treating process such as
an infrared (IR) reflow process is performed to integrally form the
lateral bump structure 121C on the side 113 of the semiconductor
device 110C and the vertical bump structure 123A on the vertical
conductive contact pads 1032C of the semiconductor device 110C.
[0071] In FIG. 20, a grinding process is performed from a bottom
surface of the semiconductor device 110C to remove a bottom
portion. 102 such that the edge region 105 of the semiconductor
device 110C is completely removed after the thermal process.
Consequently, the lateral bump structure 121C on the lateral
conductive contact pad 105C can contact a contact pad of an
adjacent device and implements a lateral signal path of the
semiconductor device 110C and the adjacent device, while the
vertical bump structure 123A on the vertical conductive contact
pads 1032C implements a vertical signal path of the semiconductor
device 110C.
[0072] Referring to FIG. 21, in some embodiments, after finishing
the semiconductor device 110C shown in FIG. 20, two semiconductor
devices 110C are laterally disposed and adjacent to one another,
and a molding member 140 is then formed to encapsulate the two
semiconductor devices 110C. In alternative embodiments, the two
semiconductor devices can be the semiconductor device 110B in FIG.
15 or the semiconductor device 110A in FIG. 10. Subsequently, a
thermal treating process such as an infrared (IR) reflow process is
performed to form a lateral bump structure 121D implementing a
lateral signal path between the two semiconductor devices 110C. In
some embodiments, the lateral bump structure 121D extends laterally
across an intervening portion 141 of the molding member 100 to
implement a lateral signal path between the two laterally adjacent
semiconductor devices 110C.
[0073] The lateral extension of the lateral bump structure from the
side of the semiconductor device can contact a corresponding
conductor of a laterally adjacent device to implement a lateral
signal path between the semiconductor device and the laterally
adjacent device in the absence of a redistribution structure
corresponding to the redistribution layer.
[0074] The embodiments of the present disclosure provide a
semiconductor package with a lateral bump structure implementing
the lateral signal path between the two laterally adjacent
semiconductor devices in the absence of a redistribution structure.
Consequently, the height of the semiconductor package of the
present disclosure is less than the height of the semiconductor
package with a redistribution structure. In other words, the
semiconductor package of the present disclosure can meet the
miniaturized scale demand (small form factor) of the semiconductor
packages. In addition, the absence of the redistribution structure
is a key factor in the reduction of the fabrication cost of the
semiconductor package.
[0075] One embodiment of the present disclosure provides a
semiconductor package that includes a semiconductor device having
an upper surface and a side, wherein the upper surface and the side
form a corner of the semiconductor device. The semiconductor
package also includes a lateral bump structure disposed on the side
and implementing a lateral signal path of the semiconductor device.
The semiconductor package further includes a vertical bump
structure disposed over the upper surface and implementing a
vertical signal path of the semiconductor device.
[0076] Another embodiment of the present disclosure provides a
semiconductor package including a first semiconductor device, a
second semiconductor device laterally adjacent to the first
semiconductor device, and a lateral bump structure extending from
the first side to the second side and implementing a lateral signal
path between the first semiconductor device and the second
semiconductor device. The first semiconductor device has a first
upper surface and a first side, wherein the first upper surface and
the first side form a first corner of the first semiconductor
device. The second semiconductor device has a second upper surface
and a second side, and the second upper surface and the second side
form a second corner of the second semiconductor device. The
semiconductor package further includes a first vertical bump
structure disposed over the first upper surface, and a second
vertical bump structure disposed over the second upper surface.
[0077] Another embodiment of the present disclosure provides a
method for preparing a semiconductor package including: providing a
semiconductor device having a bulk region and an edge region
adjacent to the bulk region; forming a depression in the edge
region, wherein the depression exposes a side of the bulk region;
and forming a lateral bump structure in the depression, wherein the
lateral hump structure is formed on the side and implements a
lateral signal path of the semiconductor device.
[0078] Although the present disclosure and its advantages have been
described in detail, it should be understood that various changes,
substitutions and alterations can be made herein without departing
from the spirit and scope of the disclosure as defined by the
appended claims. For example, many of the processes discussed above
can be implemented through different methods, replaced by other
processes, or a combination thereof.
[0079] Moreover, the scope of the present application is not
intended to he limited to the particular embodiments of the
process, machine, manufacture, composition of matter, means,
methods and steps described in the specification. As one of
ordinary skill in the art will readily appreciate from the present
disclosure, processes, machines, manufacture, compositions of
matter, means, methods, or steps, presently existing or later to be
developed, that perform substantially the same function or achieve
substantially the same result as the corresponding embodiments
described herein, may be utilized according to the present
disclosure. Accordingly, the appended claims are intended to
include within their scope such processes, machines, manufacture,
compositions of matter, means, methods, or steps.
* * * * *