U.S. patent application number 15/649474 was filed with the patent office on 2018-03-08 for semiconductor package device and method of manufacturing the same.
This patent application is currently assigned to Advanced Semiconductor Engineering, Inc.. The applicant listed for this patent is Advanced Semiconductor Engineering, Inc.. Invention is credited to Kuang-Hsiung CHEN, Yu-Ying LEE, Wun-Jheng SYU, Yu-Hsuan TSAI, Sheng-Ming WANG.
Application Number | 20180068962 15/649474 |
Document ID | / |
Family ID | 61280775 |
Filed Date | 2018-03-08 |
United States Patent
Application |
20180068962 |
Kind Code |
A1 |
CHEN; Kuang-Hsiung ; et
al. |
March 8, 2018 |
SEMICONDUCTOR PACKAGE DEVICE AND METHOD OF MANUFACTURING THE
SAME
Abstract
In one or more embodiments, a micro-electromechanical systems
(MEMS) package structure comprises a MEMS die, a conductive pillar
adjacent to the MEMS die, a package body and a binding layer on the
package body. The package body encapsulates the MEMS die and the
conductive pillar, and exposes a top surface of the conductive
pillar. A glass transition temperature (Tg) of the package body is
greater than a temperature for forming the binding layer (Tc).
Inventors: |
CHEN; Kuang-Hsiung;
(Kaohsiung, TW) ; TSAI; Yu-Hsuan; (Kaohsiung,
TW) ; LEE; Yu-Ying; (Kaohsiung, TW) ; WANG;
Sheng-Ming; (Kaohsiung, TW) ; SYU; Wun-Jheng;
(Kaohsiung, TW) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
Advanced Semiconductor Engineering, Inc. |
Kaohsiung |
|
TW |
|
|
Assignee: |
Advanced Semiconductor Engineering,
Inc.
Kaohsiung
TW
|
Family ID: |
61280775 |
Appl. No.: |
15/649474 |
Filed: |
July 13, 2017 |
Related U.S. Patent Documents
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Application
Number |
Filing Date |
Patent Number |
|
|
62383094 |
Sep 2, 2016 |
|
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|
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 2224/05556
20130101; H01L 21/563 20130101; B81C 2203/0792 20130101; H01L 24/16
20130101; H01L 2224/11462 20130101; H01L 2224/13018 20130101; H01L
2224/13082 20130101; H01L 24/02 20130101; H01L 2224/81193 20130101;
H01L 24/20 20130101; H01L 25/50 20130101; B81C 1/0023 20130101;
H01L 24/19 20130101; H01L 2224/171 20130101; H01L 2224/02373
20130101; H01L 2224/04105 20130101; H01L 2224/05548 20130101; H01L
24/13 20130101; H01L 2224/81191 20130101; H01L 2224/81192 20130101;
B81C 1/00333 20130101; H01L 2224/02377 20130101; H01L 2224/16237
20130101; H01L 2224/12105 20130101; H01L 24/11 20130101; H01L
23/3157 20130101; B81B 2207/012 20130101; H01L 2224/18 20130101;
H01L 2224/0235 20130101; B81B 7/0006 20130101; H01L 25/0657
20130101; H01L 2224/96 20130101; H01L 2224/18 20130101; H01L
2924/0001 20130101; H01L 2224/96 20130101; H01L 2224/19
20130101 |
International
Class: |
H01L 23/00 20060101
H01L023/00; B81B 7/00 20060101 B81B007/00; B81C 1/00 20060101
B81C001/00; H01L 25/00 20060101 H01L025/00; H01L 25/065 20060101
H01L025/065; H01L 21/56 20060101 H01L021/56; H01L 23/31 20060101
H01L023/31 |
Claims
1. A micro-electromechanical systems (MEMS) package structure,
comprising: a MEMS die; a conductive pillar adjacent to the MEMS
die; a package body encapsulating the MEMS die and the conductive
pillar, and exposing a top surface of the conductive pillar; and a
binding layer on the package body, wherein a glass transition
temperature (Tg) of the package body is greater than a temperature
for forming the binding layer (Tc).
2. The MEMS package structure of claim 1, wherein the binding layer
comprises polyimide (PI), polybenzoxazole (PBO), solder resist,
Ajinomoto build-up film (ABF), molding compound, epoxy-based
material, or a combination of two or more thereof.
3. The MEMS package structure of claim 1, wherein the Tg of the
package body is in a range from about 150.degree. C. to about
195.degree. C.
4. The MEMS package structure of claim 1, wherein the package body
comprises a filler, and a content of the filler in the package body
is greater than or equal to about 80% by mass.
5. The MEMS package structure of claim 1, wherein a coefficient of
thermal expansion (CTE) of the package body is in a range from
about 4 ppm/.degree. C. to about 12 ppm/.degree. C.
6. The MEMS package structure of claim 1, wherein a sidewall of the
conductive pillar directly contacts the package body.
7. The MEMS package structure of claim 1, wherein the conductive
pillar comprises a first portion and a second portion on the first
portion, and a thickness of the first portion is greater than a
thickness of the second portion.
8. The MEMS package structure of claim 7, wherein the first portion
of the conductive pillar and the second portion of the conductive
pillar comprise different materials.
9. The MEMS package structure of claim 1, further comprising a
redistribution layer (RDL) on the binding layer and electrically
connected to at least a portion of the top surface of the
conductive pillar that is exposed from the binding layer.
10. The MEMS package structure of claim 1, further comprising a
conductive pad on the package body to electrically connected to an
exposed portion of the top surface of the conductive pillar,
wherein a portion of the conductive pad is exposed from the binding
layer.
11. The MEMS package structure of claim 1, further comprising an
electronic component on which the MEMS die and the conductive
pillar are disposed, wherein the MEMS die is electrically connected
to the electronic component.
12. The MEMS package structure of claim 11, further comprising a
seed layer between the conductive pillar and the electronic
component.
13. The MEMS package structure of claim 1, further comprising a
substrate, wherein the MEMS die is electrically connected to the
substrate through the conductive pillar.
14. A micro-electromechanical systems (MEMS) package structure,
comprising a substrate including a dielectric layer and a
redistribution layer (RDL), at least a portion of a top surface of
the RDL exposed from the dielectric layer; a MEMS die on the
substrate; a conductive pillar electrically connecting the MEMS die
to the RDL of the substrate by flip-chip bonding; and a package
body on the substrate and encapsulating the MEMS die and the
conductive pillar.
15. The MEMS package structure of claim 14, further comprising a
seed layer adjacent to the conductive pillar.
16. The MEMS package structure of claim 14, wherein a sidewall of
the conductive pillar directly contacts the package body.
17. The MEMS package structure of claim 14, wherein the top surface
of the RDL does not protrude from a top surface of the dielectric
layer.
18. The MEMS package structure of claim 14, wherein the dielectric
layer defines at least one opening to expose at least a portion of
a bottom surface of the RDL.
19. The MEMS package structure of claim 14, wherein the dielectric
layer is a solder resist layer.
20. A method for manufacturing a micro-electromechanical systems
(MEMS) package structure, the method comprising: disposing a MEMS
die on a carrier; forming a conductive pillar on the carrier and
adjacent to the MEMS die; forming a package body to encapsulate the
MEMS die and the conductive pillar and to expose a top surface of
the conductive pillar; and forming a binding layer on the package
body, wherein a glass transition temperature (Tg) of the package
body is greater than a temperature for forming the binding layer
(Tc).
21. The method of claim 20, wherein the Tg of the package body is
in a range from about 150.degree. C. to about 195.degree. C.
22. The method of claim 20, wherein the package body comprises a
filler, and a content of the filler in the package body is greater
than or equal to about 80% by mass.
23. The method of claim 20, wherein a coefficient of thermal
expansion (CTE) of the package body is in a range from about 4
ppm/.degree. C. to about 12 ppm/.degree. C.
24. The method of claim 20, wherein the operation of forming the
conductive pillar comprises: forming a first portion of the
conductive pillar on the carrier by electroplating; and forming a
second portion of the conductive pillar on the first portion of the
conductive pillar by electroplating, wherein a time for forming the
first portion of the conductive pillar is longer than a time for
forming the second portion of the conductive pillar.
25. The method of claim 24, wherein a thickness of the first
portion of the conductive pillar is greater than a thickness of the
second portion of the conductive pillar.
26. The method of claim 20, further comprising forming a conductive
pad on the package body to electrically connect to the conductive
pillar before forming the binding layer.
27. The method of claim 20, wherein the binding layer comprises
polyimide (PI), polybenzoxazole (PBO), solder resist, Ajinomoto
build-up film (ABF), molding compound, epoxy-based material, or a
combination of two or more thereof.
28. The method of claim 20, further comprising forming a
redistribution layer (RDL) on the binding layer and electrically
connecting to at least a portion of the top surface of the
conductive pillar that is exposed from the binding layer.
Description
CROSS-REFERENCE TO RELATED APPLICATIONS
[0001] This application claims the benefit of and priority to U.S.
Provisional Patent Application No. 62/383,094, filed Sep. 2, 2016,
the contents of which are incorporated herein by reference in its
entirety.
BACKGROUND
1. Technical Field
[0002] The present disclosure relates generally to a semiconductor
package device and a method of manufacturing the same. More
particularly, the present disclosure relates to a semiconductor
package device including a micro-electromechanical systems (MEMS)
structure and a method of manufacturing the same.
2. Description of the Related Art
[0003] The comparative MEMS package structure is formed by Quad
Flat No-leads (QFN) technique. For example, a MEMS die is placed on
a die paddle of a lead frame and the electrical connection between
the MEMS die and the lead frame is attained by wire bonding.
However, the use of the wire bond technique may limit
miniaturization of the MEMS package structure (e.g. a bottleneck of
the dimension of the MEMS package structure is 4.5 millimeters
(mm)*4.5 mm*1.2 mm). Moreover, due to the loop height of the
bonding wire, the conductive path is relatively long, which causes
relatively high resistance (compared with the conductive pillar).
The high resistance can adversely affect electrical performance of
the MEMS package structure. Further, in the process of packaging
the MEMS, the molding compound is selected to have a coefficient of
thermal expansion (CTE) close to the CTE of the lead frame;
however, such arrangement may inevitably cause a CTE mismatch
between the molding compound and the MEMS die, which may hinder
performance of the MEMS die or even damage the MEMS die.
SUMMARY
[0004] In one aspect according to some embodiments, a
micro-electromechanical systems (MEMS) package structure comprises
a MEMS die, a conductive pillar adjacent to the MEMS die, a package
body and a binding layer on the package body. The package body
encapsulates the MEMS die and the conductive pillar, and exposes a
top surface of the conductive pillar. A glass transition
temperature (Tg) of the package body is greater than a temperature
for forming the binding layer (Tc).
[0005] In another aspect according to some embodiments, a MEMS
package structure comprises a substrate, a MEMS die, a conductive
pillar and a package body. The substrate includes a dielectric
layer and a redistribution layer (RDL). At least a portion of a top
surface of the RDL is exposed from the dielectric layer. The MEMS
die is disposed over the substrate. A conductive pillar
electrically connects the MEMS die to the RDL of the substrate by
flip-chip bonding. The package body is disposed on the substrate
and encapsulates the MEMS die and the conductive pillar.
[0006] In yet another aspect according to some embodiments, a
method for manufacturing a MEMS package structure comprises:
disposing a MEMS die on a carrier; forming a conductive pillar on
the carrier and adjacent to the MEMS die; forming a package body to
encapsulate the MEMS die and the conductive pillar and to expose a
top surface of the conductive pillar; and forming a binding layer
on the package body, wherein a glass transition temperature (Tg) of
the package body is greater than a temperature for forming the
binding layer (Tc).
BRIEF DESCRIPTION OF THE DRAWINGS
[0007] Aspects of some embodiments of the present disclosure are
best understood from the following detailed description when read
with the accompanying figures. It is noted that various structures
may not be drawn to scale, and dimensions of the various structures
may be arbitrarily increased or reduced for clarity of
discussion.
[0008] FIG. 1A illustrates a cross-sectional view of a
semiconductor package device in accordance with some embodiments of
the present disclosure;
[0009] FIG. 1B illustrates a cross-sectional view of a
semiconductor package device in accordance with some embodiments of
the present disclosure;
[0010] FIG. 1C illustrates a cross-sectional view of a
semiconductor package device in accordance with some embodiments of
the present disclosure;
[0011] FIG. 1D illustrates a cross-sectional view of a
semiconductor package device in accordance with some embodiments of
the present disclosure;
[0012] FIG. 1E illustrates a cross-sectional view of a
semiconductor package device in accordance with some embodiments of
the present disclosure;
[0013] FIG. 1F illustrates a cross-sectional view of a
semiconductor package device in accordance with some embodiments of
the present disclosure;
[0014] FIG. 1G illustrates a cross-sectional view of a
semiconductor package device in accordance with some embodiments of
the present disclosure;
[0015] FIG. 1H illustrates a cross-sectional view of a
semiconductor package device in accordance with some embodiments of
the present disclosure;
[0016] FIG. 1I illustrates a cross-sectional view of a
semiconductor package device in accordance with some embodiments of
the present disclosure;
[0017] FIG. 2A illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0018] FIG. 2B illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0019] FIG. 2C illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0020] FIG. 2D illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0021] FIG. 2D' illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0022] FIG. 2E illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0023] FIG. 2F illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0024] FIG. 2G illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0025] FIG. 2H illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0026] FIG. 3A illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0027] FIG. 3B illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0028] FIG. 4A illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0029] FIG. 4B illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0030] FIG. 4C illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0031] FIG. 5A illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0032] FIG. 5B illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0033] FIG. 5C illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0034] FIG. 5D illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0035] FIG. 6A illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0036] FIG. 6B illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure;
[0037] FIG. 6C illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure; and
[0038] FIG. 6D illustrates various stage(s) of a method of
manufacturing a semiconductor package in accordance with some
embodiments of the present disclosure.
[0039] Common reference numerals are used throughout the drawings
and the detailed description to indicate the same or similar
elements. The present disclosure will be more apparent from the
following detailed description taken in conjunction with the
accompanying drawings.
DETAILED DESCRIPTION
[0040] FIG. 1A illustrates a cross-sectional view of a
semiconductor package device 1A in accordance with some embodiments
of the present disclosure. The semiconductor package device 1A
includes a circuit layer 10, a MEMS device 11, conductive pillars
12, a package body 13, a binding layer 14a, an insulation layer
14b, a redistribution layer (RDL) 15 and one or more electrical
contacts 16.
[0041] The circuit layer 10 may include one or more electronic
components, such as passive electronic components and/or active
electronic components. In some embodiments, the circuit layer 10
may include, e.g., a microprocessor (e.g., a single-core or
multi-core microprocessor), a memory device, a chipset, a graphics
device, or an application specific integrated circuit (ASIC)
according to various embodiments of the present disclosure.
[0042] The MEMS device 11 is disposed on the circuit layer 10. In
some embodiments, MEMS refers to a class of structures or devices
fabricated using semiconductor-like processes and exhibiting
mechanical characteristics such as the ability to move or deform.
MEMS often, but not always, interact with electrical signals. The
MEMS device 11 may be or include, but is not limited to, one or
more gyroscopes, accelerometers, pressure sensors, microphones,
actuators, mirrors, heaters, printer nozzles magnetometers, or a
combination of two or more thereof.
[0043] The package body 13 is disposed on the circuit layer 10 to
cover or encapsulate at least a portion of the MEMS device 11 or
the entire MEMS device 11. In some embodiments, the package body 13
includes, e.g., an epoxy resin including fillers, a molding
compound (e.g., an epoxy molding compound or other molding
compound), a polyimide, a phenolic compound or material, a material
including a silicone dispersed therein, or a combination of two or
more thereof. In some embodiments, the composition of the filler in
the package body 13 is greater than or equal to, e.g., about 60%,
about 70%, about 80%, about 90%, or about 95% by mass. For example,
the composition of the filler in the package body 13 may be, e.g.,
about 87% or about 89%.
[0044] In some embodiments, a glass transition temperature (Tg) of
the package body 13 is greater than a temperature (Tc) for forming
the binding layer 14a or the insulation layer 14b. In some
embodiments, the glass transition temperature of the package body
13 is in a range from about 100.degree. C. to about 250.degree. C.,
from about 125.degree. C. to about 220.degree. C., or from about
150.degree. C. to about 195.degree. C. For example, the glass
transition temperature of the package body 13 is in a range from
about 155.degree. C. to about 161.degree. C., from about
151.degree. C. to about 160.degree. C. or from about 184.degree. C.
to about 195.degree. C. In some embodiments, a coefficient of
thermal expansion (CTE) of the package body 13 is in a range from
about 4 ppm/.degree. C. to about 12 ppm (parts per
million)/.degree. C. For example, the CTE of the package body 13 is
in a range from about 7 ppm/.degree. C. to about 9 ppm/.degree. C.,
from about 10 ppm/.degree. C. to about 12 ppm/.degree. C. or from
about 4 ppm/.degree. C. to about 6 ppm/.degree. C.
[0045] The conductive pillar 12 penetrates the package body to
electrically connect to one or more conductive contacts of the
circuit layer 10. A portion of the conductive pillar 12 is
encapsulated by the package body 13; and a top surface of the
conductive pillar 12 is exposed from the package body 13. In some
embodiments, the conductive pillar 12 is disposed adjacent to the
MEMS device 11. In some embodiments, a seed layer 12s is disposed
between the conductive pillar 12 and the circuit layer 10. In some
embodiments, there is no seed layer between the conductive pillar
12 and the package body 13. In other words, lateral surface(s) of
the conductive pillar 12 may directly contact the package body 13.
In some embodiments, the seed layer 12s comprises, e.g., titanium
(Ti), copper (Cu) or a combination thereof.
[0046] In some embodiments, the conductive pillar 12 includes a
first portion on the circuit layer 10 and a second portion on the
first portion. In some embodiments, a thickness of the first
portion may be greater than a thickness of the second portion. A
time for forming the first portion may be longer than a time for
forming the second portion. In some other embodiments, the
thickness of the first portion may be less than, or substantially
equal to, the thickness of the second portion. In some embodiments,
the first portion of the conductive pillar 12 and the second
portion of the conductive pillar 12 are made of (or include) the
same material. Alternatively, the first portion of the conductive
pillar 12 and the second portion of the conductive pillar 12 are
made of (or include) different materials. For example, in some
embodiments, the first portion of the conductive pillar 12 is made
of Cu, while the second portion of the conductive pillar 12 is made
of tin (Sn), silver (Ag), nickel (Ni), or a combination of two or
more thereof.
[0047] The binding layer 14a is disposed on the package body 13 and
the top surface of the conductive pillar 12. The binding layer 14a
may include at least one recess to expose at least one portion of
the top surface of the conductive pillar 12. In some embodiments,
the binding layer 14a comprises polyimide (PI), polybenzoxazole
(PBO), solder resist, Ajinomoto build-up film (ABF), molding
compound, epoxy-based material, or a combination of two or more
thereof.
[0048] The RDL 15 is disposed on the binding layer 14. The RDL 15
extends into the recess of the binding layer 14a and electrically
contacts at least a portion of the top surface of the conductive
pillar 12 that is exposed from the package body 13.
[0049] The insulation layer 14b is disposed on the binding layer
14a to cover or encapsulate at least a portion of the RDL 15 or the
entire RDL 15. The insulation layer 14b may include at least one
recess to expose a portion of RDL 15. In some embodiments, the
insulation layer 14b comprises PI, PBO, solder resist, ABF, molding
compound, epoxy-based material, or a combination of two or more
thereof.
[0050] A conductive layer 16u (e.g., under bump metallurgy (UBM))
is disposed within the recess of the insulation layer 14b to
electrically contact on the exposed portion of the RDL 15. The
electrical contact 16 (e.g., C4 pad (controlled collapse chip
connection pad)) is disposed on the conductive layer 16u to provide
electrical connections between the circuit layer 10 and external
device(s). In some embodiments, the semiconductor package device 1A
does not include the conductive layer 16u; and the electrical
contact 16 is directly disposed within the recess of the insulation
layer 14b to electrically contact the exposed portion of the RDL
15.
[0051] As mentioned above, the comparative MEMS package structure
formed by Quad Flat No-leads (QFN) technique may limit
miniaturization of the MEMS package structure (e.g. a bottleneck of
the dimension of the MEMS package structure is 4.5 mm*4.5 mm*1.2
mm). In addition, due to the loop height of the bonding wire, the
relatively long conductive path may cause high resistance, which
would adversely affect electrical performance of the comparative
MEMS package structure. In some embodiments shown in FIG. 1A of the
present disclosure, by using a conductive pillar 12 to provide an
electrical connection, the total size of the semiconductor package
device 1A can be reduced (e.g., to about 3.5 mm*2.6 mm*0.5 mm,
about 3.0 mm*2.2 mm*0.4 mm, about 2.5 mm*2.0 mm*0.3 mm, or less).
In addition, due to the relatively smaller resistance of the
conductive pillar 12 (compared to the bonding wire in the
comparative MEMS package structure), the semiconductor package
device 1 can have a better performance for signal transmission.
[0052] Moreover, in the process of packaging the comparative QFN
MEMS structure, the molding compound is selected to have a CTE
close to the CTE of the lead frame. However, such arrangement may
cause a CTE mismatch between the molding compound and the MEMS die.
The CTE mismatch may damage the MEMS die or hinder performance of
the MEMS die. As shown in the embodiments shown in FIG. 1A of the
present disclosure, the semiconductor package device 1A does not
include a lead frame structure, and thus the material of the
molding compound (e.g., the package body 13) can be selected so
that the CTE of the molding compound can match the CTE of the MEMS
device 11 to avoid warpage of the semiconductor package device
1A.
[0053] In some embodiments, the binding layer 14a may be omitted.
FIG. 1B illustrates a cross-sectional view of a semiconductor
package device 1B in accordance with some embodiments of the
present disclosure. The semiconductor package device 1B is similar
to the semiconductor package device 1A shown in FIG. 1A, except
that the semiconductor package device 1B includes the insulation
layer 14b but does not include a binding layer 14a.
[0054] As shown in FIG. 1B, the RDL 15 is disposed on the package
body 13 and electrically contacts at least a portion of the top
surface of the conductive pillar 12 that is exposed from the
package body 13.
[0055] The insulation layer 14b is disposed on the package body 13
to cover or encapsulate at least a portion of the RDL 15 or the
entire RDL 15. The insulation layer 14b may include at least one
recess to expose at least a portion of RDL 15. In some embodiments,
the insulation layer 14b comprises PI, PBO, solder resist, ABF,
molding compound, epoxy-based material, or a combination of two or
more thereof.
[0056] The conductive layer 16u (e.g., under bump metallurgy (UBM))
is disposed within the recess of the insulation layer 14b to
electrically contact on the exposed portion of the RDL 15. The
electrical contact 16 (e.g., C4 pad) is disposed on the conductive
layer 16u to provide electrical connections between the circuit
layer 10 and external device(s). In some embodiments, the
semiconductor package device 1B does not include the conductive
layer 16u; and the electrical contact 16 is directly disposed
within the recess of the insulation layer 14b to electrically
contact on the exposed portion of the RDL 15.
[0057] FIG. 1C illustrates a cross-sectional view of a
semiconductor package device 1C in accordance with some embodiments
of the present disclosure. The semiconductor package device 1C is
similar to the semiconductor package device 1A shown in FIG. 1A,
and at least one difference therebetween is that in the
semiconductor package device 1A of FIG. 1A, an active surface of
the MEMS device 11 is connected to the circuit layer 10 by, for
example, flip-chip technique; while in semiconductor package device
1C of FIG. 1C, a back surface of the MEMS device 11 is connected to
the circuit layer 10 through an adhesive layer 11h (e.g., glue).
The active surface of the MEMS device is electrically connected to
the RDL 15 through electrical connections 15v (e.g., vias)
penetrating the package body 13.
[0058] FIG. 1D illustrates a cross-sectional view of a
semiconductor package device 1D in accordance with some embodiments
of the present disclosure. The semiconductor package device 1D is
similar to the semiconductor package device 1A shown in FIG. 1A,
except that the semiconductor package device 1D does not include
the RDL 15 and the binding layer 14a.
[0059] As shown in FIG. 1D, a conductive pad 12p is disposed on the
package body 13 and electrically contacts at least a portion of the
top surface of the conductive pillar 12 that is exposed from the
package body 13. The insulation layer 14b is disposed on the
package body 13 to cover or encapsulate the conductive pad 12p. The
insulation layer 14b includes at least one recess to expose at
least one portion of the conductive pad 12p. The electrical contact
16 is disposed on the insulation layer 14b and extends into the
recess of the insulation layer 14b to electrically contact the
conductive pad 12p.
[0060] In accordance with the embodiments shown in FIG. 1D, since
the electrical contact 16 is directly disposed on the conductive
pad 12p to be electrically connected to the conductive pillar 12,
the semiconductor package device 1D does not include additional
RDL, reducing the manufacturing cost.
[0061] FIG. 1E illustrates a cross-sectional view of a
semiconductor package device 1E in accordance with some embodiments
of the present disclosure. The semiconductor package device 1E
includes the semiconductor package device 1D as shown in FIG. 1D, a
package body 19 and a substrate 18.
[0062] The substrate 18 may be a flexible substrate or a rigid
substrate, depending upon the applications according to various
embodiments. In some embodiments, the substrate 18 includes a
dielectric layer 18d and a conductive patterned layer 18r. At least
a portion of a top surface of the conductive patterned layer 18r is
exposed from the dielectric layer 18d. The electrical contact of
the semiconductor package device 1D is disposed on the exposed
portion of the top surface of the conductive patterned layer 18r.
In some embodiments, an external contact layer may be also formed
or disposed on the substrate 18. In some embodiments, the external
contact layer includes a ball grid array (BGA). In other
embodiments, the external contact layer includes an array such as,
but not limited to, a land grid array (LGA) or a pin grid array
(PGA). In some embodiments, the external contact layer includes
solder balls 18b, which may include lead or may be leadfree (e.g.,
including one or more materials such as alloys of gold and tin
solder or alloys of silver and tin solder).
[0063] The package body 19 is disposed on the substrate 18 to cover
or encapsulate the semiconductor package device 1D. In some
embodiments, the package body 19 includes an epoxy resin including
fillers, a molding compound (e.g., an epoxy molding compound or
other molding compound), a polyimide, a phenolic compound or
material, a material including a silicone dispersed therein, or a
combination of two or more thereof.
[0064] FIG. 1F illustrates a cross-sectional view of a
semiconductor package device 1F in accordance with some embodiments
of the present disclosure. The semiconductor package device 1F is
similar to the semiconductor package device 1A shown in FIG. 1A,
except that the semiconductor package device 1F does not include
the package body 13, the binding layers 14a, the insulation layer
14b or the RDL 15.
[0065] As shown in FIG. 1F, the conductive pillar 12 is disposed on
the circuit layer 10 and electrically connected to the conductive
contacts of the circuit layer 10. The seed layer 12s may be
disposed between the conductive pillar 12 and the circuit layer 10.
The electrical contact 12c is disposed on the conductive pillar 12.
The conductive pillar 12 and the electrical contact 12c provide
electrical connections between the circuit layer 10 and external
device(s).
[0066] FIG. 1G illustrates a cross-sectional view of a
semiconductor package device 1G in accordance with some embodiments
of the present disclosure. The semiconductor package device 1G is
similar to the semiconductor package device 1F shown in FIG. 1F,
except that the semiconductor package device 1G further includes a
package body 13.
[0067] The package body 13 is disposed on the circuit layer 10 to
cover or encapsulate the MEMS device 11 and lateral surface(s) of
the conductive pillar 12. A top surface of the conductive pillar 12
is exposed from the package body 13. In some embodiments, the
package body 13 includes an epoxy resin including fillers, a
molding compound (e.g., an epoxy molding compound or other molding
compound), a polyimide, a phenolic compound or material, a material
including a silicone dispersed therein, or a combination of two or
more thereof.
[0068] The electrical contact 12c is disposed on the top surface of
the conductive pillar 12 that is exposed from the package body 13.
The conductive pillar 12 and the electrical contact 12c provide
electrical connections between the circuit layer 10 and external
device(s).
[0069] FIG. 1H illustrates a cross-sectional view of a
semiconductor package device 1H in accordance with some embodiments
of the present disclosure. The semiconductor package device 1H is
similar to the semiconductor package device 1G shown in FIG. 1G,
except that the semiconductor package device 1H further includes
one or more support elements 12c1.
[0070] The support elements 12c1 are disposed on the package body
and electrically isolated from the MEMS device 11 or the circuit
layer 10. In some embodiments, the support elements 12c1 may be
solder balls or other suitable structures. In some embodiments, the
support elements 12c1 may be dummy balls. The dummy balls 12c1 are
used to provide an additional support for the semiconductor package
device 1H when the semiconductor package device 1H is connected or
bonded to other device(s) or circuit board(s).
[0071] FIG. 1I illustrates a cross-sectional view of a
semiconductor package device 1I in accordance with some embodiments
of the present disclosure. The semiconductor package device 1I
includes the semiconductor package device 1F as shown in FIG. 1F, a
package body 19 and a substrate 18.
[0072] The substrate 18 may be a flexible substrate or a rigid
substrate, depending upon the applications according to various
embodiments. In some embodiments, the substrate 18 includes a
dielectric layer 18d and a conductive patterned layer 18r. At least
a portion of a top surface of the conductive patterned layer 18r is
exposed from the dielectric layer 18d. The electrical contact 12c
of the semiconductor package device 1F is disposed on the exposed
portion of the top surface of the conductive patterned layer 18r.
In some embodiments, an external contact layer may be also formed
or disposed on the substrate 18. In some embodiments, the external
contact layer includes a BGA. In other embodiments, the external
contact layer includes an array such as, but not limited to, an LGA
or a PGA. In some embodiments, the external contact layer includes
solder balls 18b, which may include lead or may be lead-free (e.g.,
including one or more materials such as alloys of gold and tin
solder or alloys of silver and tin solder).
[0073] The package body 19 is disposed on the substrate 18 to cover
or encapsulate the semiconductor package device 1F. In some
embodiments, the package body 18 includes an epoxy resin including
fillers, a molding compound (e.g., an epoxy molding compound or
other molding compound), a polyimide, a phenolic compound or
material, a material including a silicone dispersed therein, or a
combination of two or more thereof.
[0074] FIGS. 2A, 2B, 2C, 2D, 2D', 2E, 2F, 2G and 2H are
cross-sectional views of a semiconductor structure fabricated at
various stages, in accordance with some embodiments of the present
disclosure. Various figures may be simplified for a better
understanding of the aspects of the present disclosure.
[0075] Referring to FIG. 2A, a circuit layer 20 is provided. The
circuit layer 20 may include one or more electronic components,
such as passive electronic components and/or active electronic
components. In some embodiments, the circuit layer 20 may include,
a microprocessor (e.g., a single-core or multi-core
microprocessor), a memory device, a chipset, a graphics device, or
an ASIC according to various embodiments of the present
disclosure.
[0076] The MEMS device 21 is disposed on the circuit layer 20. The
MEMS device 21 may be or include, but is not limited to, one or
more gyroscopes, accelerometers, pressure sensors, microphones,
actuators, mirrors, heaters, printer nozzles magnetometers, or a
combination of two or more thereof. In some embodiments, the MEMS
device 21 can be connected to the circuit layer 20 by, for example,
flip-chip technique.
[0077] Referring to FIG. 2B, a seed layer 22s is formed on a top
surface of the circuit layer 20 and a top surface and lateral
surface(s) of the MEMS device 21. In some embodiments, the seed
layer 22s comprises Ti, Cu or a combination thereof. In some
embodiments, the seed layer 22s can be formed by, e.g., sputtering
or other suitable techniques.
[0078] Referring to FIG. 2C, a photoresist layer 27 is formed on
the seed layer 22s; and one or more openings 27h are formed at
predetermined location(s) to penetrate the photoresist layer 27 and
to expose the seed layer 22s. In some embodiments, the photoresist
layer 27 is a dry film photoresist or other suitable photoresist.
In some embodiments, the openings 27h can be formed by, e.g.,
etching, laser drilling or other suitable processes.
[0079] Referring to FIG. 2D, a conductive pillar 22 is formed
within the openings 27h and on at least a portion of the seed layer
22s that is exposed from the photoresist layer 27. In some
embodiments, the conductive pillar 22 is formed by, e.g.,
electroplating or other suitable processes. In some embodiments,
the conductive pillar 22 may be formed by a single electroplating
process. In some other embodiments, referring to FIG. 2D', the
conductive pillar 22' may include two (or more) portions (e.g., a
first portion 22a' on the seed layer 22s and a second portion 22b'
on the first portion 22a') formed by two (or more) electroplating
processes. A thickness of the first portion 22a' is greater than a
thickness of the second portion 22b'. In some other embodiments,
the thickness of the first portion 22a' may be less than, or
substantially equal to, the thickness of the second portion 22b'.
In some embodiments, the first portion 22a' of the conductive
pillar 22' and the second portion 22b' of the conductive pillar 22'
are made of (or include) the same material. Alternatively, the
first portion 22a' of the conductive pillar 22' and the second
portion 22b' of the conductive pillar 22' are made of (or include)
different materials. For example, in some embodiments, the first
portion 22a' of the conductive pillar 22' is made of Cu, while the
second portion 22b' of the conductive pillar 22' is made of Sn, Ag,
Ni, or a combination of two or more thereof.
[0080] Referring to FIG. 2E, the photoresist layer 27 and at least
a portion of the seed layer 22s are removed. In some embodiments,
the photoresist layer 27 and the portion of the seed layer 22s can
be removed by, e.g., etching or other suitable processes. After the
operation shown in FIG. 2E, there may be seed layer 22s that exists
between the conductive pillar 22 and the circuit layer 20.
[0081] Referring to FIG. 2F, a package body 23 is formed or
disposed to cover or encapsulate a top surface of the circuit layer
20, the MEM device 21 and the conductive pillar 22. In some
embodiments, the package body 23 includes an epoxy resin including
fillers (e.g., SiO.sub.2), a molding compound (e.g., an epoxy
molding compound or other molding compound), a polyimide, a
phenolic compound or material, a material including a silicone
dispersed therein, or a combination of two or more thereof. In some
embodiments, the composition of the filler in the package body 23
is greater than or equal to, e.g., about 60%, about 70%, about 80%,
about 90%, or about 95% by mass. For example, the composition of
the filler in the package body 23 may be, e.g., about 87% or about
89%. In some embodiments, the glass transition temperature of the
package body 23 is in a range from about 100.degree. C. to about
250.degree. C., from about 125.degree. C. to about 220.degree. C.,
or from about 150.degree. C. to about 195.degree. C. For example,
the glass transition temperature of the package body 23 is in a
range from about 155.degree. C. to about 161.degree. C., from about
151.degree. C. to about 160.degree. C. or from about 184.degree. C.
to about 195.degree. C. In some embodiments, a CTE of the package
body 23 is in a range from about 4 ppm/.degree. C. to about 12
ppm/.degree. C. For example, the CTE of the package body 23 is in a
range from about 7 ppm/.degree. C. to about 9 ppm/.degree. C., from
about 10 ppm/.degree. C. to about 12 ppm/.degree. C. or from about
4 ppm/.degree. C. to about 6 ppm/.degree. C.
[0082] In some embodiments, a portion of the package body 23 is
then removed to expose a top surface of the conductive pillar 22.
In some embodiments, the removing operation is carried out by,
e.g., grinding or other suitable processes.
[0083] Referring to FIG. 2G, a binding layer 24a is formed on the
package body 23. The binding layer 24a may include at least one
recess to expose at least a portion of the top surface of the
conductive pillar 22. In some embodiments, the binding layer 24a
comprises PI, PBO, solder resist, ABF, molding compound,
epoxy-based material, or a combination of two or more thereof. In
some embodiments, a temperature for forming the binding layer 24a
is less than the glass transition temperature of the package body
23. In some embodiments, the temperature for forming the binding
layer 24a is a curing temperature of a material of the binding
layer 24a. In some embodiments, if the temperature for forming the
binding layer 24a is greater than, or substantially equal to, the
glass transition temperature of the package body 23 and the time
for forming the binding layers 24 is long (e.g., 2 hours), the CTE
of the package body 23 may increase (e.g., as a result of
undergoing a conversion at or above the glass transition
temperature). In this case, the difference between the CTE of the
package body 23 and the CTE of the MEMS device 21 or the CTE of the
circuit layer 20 may increase as well, which may lead to warpage of
the semiconductor package device.
[0084] A RDL 25 is formed on the binding layer 24a and extends into
the recess of the binding layer 24 to electrically contact the
exposed portion of the top surface of the conductive pillar 22.
[0085] An insulation layer 24b is formed on the RDL 25. The
insulation layer 24b may include a recess to expose a portion of
the RDL 25. In some embodiments, the insulation layer 24b comprises
PI, PBO, solder resist, ABF, molding compound, epoxy-based
material, or a combination of two or more thereof. In some
embodiments, a temperature for forming the insulation layer 24b is
less than the glass transition temperature of the package body 23.
In some embodiments, the temperature for forming the insulation
layer 24b is a curing temperature of a material of the insulation
layer 24b.
[0086] A conductive layer 26u (e.g., UBM) is formed or disposed in
the recess of the insulation layer 24b to contact the exposed
portion of the RDL 25, and then an electrical contact 26 (e.g., a
C4 pad) is formed or disposed on the conductive layer 26u. In some
embodiments, at least a portion of a back side of the circuit layer
20 may be removed by, e.g., grinding process.
[0087] Referring to FIG. 2H, a singulation is performed to form the
semiconductor package device 2. For example, the singulation may be
performed through the binding layer 24a, the insulation layer 24b,
the RDL 25, the package body 23 and the circuit layer 20. The
singulation may be performed, for example, by using a dicing saw,
laser or other appropriate cutting technique. In some embodiments,
the semiconductor package device 2 is similar to the semiconductor
package device 1A shown in FIG. 1A.
[0088] FIGS. 3A and 3B are cross-sectional views of a semiconductor
structure fabricated at various stages, in accordance with some
embodiments of the present disclosure. Various figures may have
been simplified for a better understanding of the aspects of the
present disclosure. In some embodiments, the operations shown in
FIG. 3A may be carried out after the operations shown in FIG.
2F.
[0089] Referring to FIG. 3A, a conductive layer 35 is formed on at
least a portion of the top surface of the conductive pillar 22 that
is exposed from the package body 23. In some embodiments, the
conductive layer 35 may be formed by the following operations: (i)
defining regions for the following physical vapor deposition (PVD)
process by using a shadow mask; and (ii) depositing conductive
material (e.g., Cu) to form the conductive layer 35. Alternatively,
the conductive layer 35 may be formed by the following operations:
(i) defining regions of the conductive layer 35 by using laser
drilling to remove a portion of the package body 23; and (ii)
forming the conductive layer 35 by printing.
[0090] After the conductive layer 35 is deposited, an oxide layer
34 is formed on the package body 23. At least a portion of the
conductive layer 35 is exposed from the oxide layer 34. In some
embodiments, the oxide layer 35 is formed by using, e.g., a PVD
process.
[0091] Referring to FIG. 3B, an electrical contact 36 (e.g., a C4
pad) is formed or disposed on the exposed portion of the conductive
layer 35. In some embodiments, the electrical contact 36 is a
solder ball (e.g., Sn ball). In some embodiments, a Ni layer may be
deposited on the conductive layer 35 before the formation of the
oxide layer 35 to improve the adhesion between the conductive layer
35 and the electrical contact 36.
[0092] In some embodiments as shown in FIG. 2G, the binding layer
24a and the insulation layer 24b may be selected from, e.g., PI or
PBO or a combination thereof. However, the temperature (e.g., about
200.degree. C. to about 450.degree. C., about 200.degree. C. to
about 400.degree. C., or about 200.degree. C. to about 350.degree.
C.) for curing the PI or PBO is higher than the glass transition
temperature (e.g., about 150.degree. C. to about 195.degree. C.) of
the package body 23. Therefore, after the PI or PBO binding layer
is formed, the wafer may be bent (e.g., wafer warpage), which may
lead to robot handling issue, wafer crack or increased stress of
the die. As shown in the operations shown in FIGS. 3A and 3B, since
the conductive layer 35 and the oxide layer 34 are formed by PVD
process, the manufacturing process does not involve a process with
a temperature higher than the glass transition temperature of the
package body 23 (e.g., photolithography, electroplating, PI or PBO
curing), and therefore avoids reliability issues as mentioned
above.
[0093] FIGS. 4A, 4B and 4C are cross-sectional views of a
semiconductor structure fabricated at various stages, in accordance
with some embodiments of the present disclosure. Various figures
may have been simplified for a better understanding of the aspects
of the present disclosure.
[0094] Referring to FIG. 4A, a circuit layer 40 is provided. The
circuit layer 40 may include one or more electronic components,
such as passive electronic components and/or active electronic
components. In some embodiments, the circuit layer 40 may include,
a microprocessor (e.g., a single-core or multi-core
microprocessor), a memory device, a chipset, a graphics device, or
an ASIC according to various embodiments of the present
disclosure.
[0095] The MEMS device 41 is disposed on the circuit layer 40. The
MEMS device 41 may be or include, but is not limited to, one or
more gyroscopes, accelerometers, pressure sensors, microphones,
actuators, mirrors, heaters, printer nozzles magnetometers or a
combination of two or more thereof. In some embodiments, the MEMS
device 41 can be connected to the circuit layer 40 by, for example,
flip-chip technique.
[0096] A package body 43 is formed or disposed to cover or
encapsulate a top surface of the circuit layer 40 and the MEM
device 41. In some embodiments, the package body 43 includes an
epoxy resin including fillers, a molding compound (e.g., an epoxy
molding compound or other molding compound), a polyimide, a
phenolic compound or material, a material including a silicone
dispersed therein, or a combination of two or more thereof.
[0097] Referring to FIG. 4B, a portion of the package body 43 is
removed to form openings 43h to expose the circuit layer 40. In
some embodiments, the package body 43 can be removed by using,
e.g., laser drilling or other suitable processes.
[0098] Referring to FIG. 4C, a conductive material (e.g., Cu, Ni or
a combination thereof) is filled within the one or more openings
43h to form the conductive pillar 42 by, e.g., screen printing
process. An electrical contact 46 (e.g., a C4 pad) is then formed
or disposed on the conductive pillar 42. In some embodiments, the
electrical contact 46 is a solder ball (e.g., Sn ball).
[0099] As shown in the operations shown in FIGS. 4A-4C, since the
conductive pillar 42 is formed by screen printing process, the
manufacturing process does not involve a process with a temperature
higher than the glass transition temperature of the package body 43
(e.g., photolithography, electroplating, PI or PBO curing), and
therefore avoids reliability issues as mentioned above.
[0100] FIGS. 5A, 5B, 5C and 5D are cross-sectional views of a
semiconductor structure fabricated at various stages, in accordance
with some embodiments of the present disclosure. Various figures
may have been simplified for a better understanding of the aspects
of the present disclosure.
[0101] Referring to FIG. 5A, the conductive pillar 22 is formed on
the circuit layer 20 and electrically connected to the conductive
contacts of the circuit layer 20. In some embodiments, an
electrical contact 22c may be formed on the conductive pillar
22.
[0102] Referring to FIG. 5B, a singulation is performed to form the
semiconductor package device 5'. For example, the singulation may
be performed through the circuit layer 20. The singulation may be
performed, for example, by using a dicing saw, laser or other
appropriate cutting technique. In some embodiments, the
semiconductor package device 5' is similar to the semiconductor
package device 1B shown in FIG. 1B.
[0103] Referring to FIG. 5C, the semiconductor package device 5' is
inverted and connected to a substrate 28. The substrate 28 is
placed on a carrier 28c. The substrate 28 includes a dielectric
layer 28d and a conductive patterned layer 28r. At least a portion
of a top surface of the conductive patterned layer 28r is exposed
from the dielectric layer 28d. The electrical contact 22c of the
semiconductor package device 5' is disposed on the exposed portion
of the top surface of the conductive patterned layer 28r.
[0104] Referring to FIG. 5D, the carrier 28c is removed from the
substrate 28. A package body 29 is formed on the substrate 28 to
encapsulate or cover the semiconductor package device 5'. In some
embodiments, the package body 29 includes an epoxy resin including
fillers, a molding compound (e.g., an epoxy molding compound or
other molding compound), a polyimide, a phenolic compound or
material, a material including a silicone dispersed therein, or a
combination of two or more thereof.
[0105] An electrical contact 28b is then formed or disposed on the
conductive patterned layer 28d of the substrate 28 to form the
semiconductor package device 5. In some embodiments, the
semiconductor package device 5 is similar to the semiconductor
package device 1H shown in FIG. 1H.
[0106] In some embodiments, the processes shown in FIGS. 5A, 5B, 5C
and 5D are carried out in substrate level rather than wafer level.
Therefore, a binding layer can be eliminated and the semiconductor
package device 5' (including the circuit layer 20 and the MEMS
device 21) can be connected to the substrate 28 without performing
the process under wafer level, which may reduce the cost for
manufacturing the semiconductor package device 5 having a fan-out
structure.
[0107] FIGS. 6A, 6B and 6C are cross-sectional views of a
semiconductor structure fabricated at various stages, in accordance
with some embodiments of the present disclosure. Various figures
may have been simplified for a better understanding of the aspects
of the present disclosure.
[0108] The operations shown in FIG. 6A are similar to those shown
in FIG. 5A, except that the conductive contact 22c (instead of a
conductive pillar) is formed on the circuit layer 20.
[0109] Referring to FIG. 6B, a singulation is performed to form the
semiconductor package device 6'. For example, the singulation may
be performed through the circuit layer 20. The singulation may be
performed, for example, by using a dicing saw, laser or other
appropriate cutting technique.
[0110] Referring to FIG. 6C, the semiconductor package device 6' is
inverted and connected to conductive pillars 22 of the substrate
28. As shown in FIG. 6C, the conductive contacts 22c are aligned
with the corresponding conductive pillars 22. The substrate 28 is
placed on a carrier 28c. The substrate 28 includes a dielectric
layer 28d and a conductive patterned layer 28r. At least a portion
of a top surface of the conductive patterned layer 28r is exposed
from the dielectric layer 28d. The electrical contact 22c of the
semiconductor package device 5' is disposed on the exposed portion
of the top surface of the conductive patterned layer 28r.
[0111] Referring to FIG. 6D, the carrier 28c is removed from the
substrate 28. A package body 29 is formed on the substrate 28 to
encapsulate or cover the semiconductor package device 6'. In some
embodiments, the package body 29 includes an epoxy resin including
fillers, a molding compound (e.g., an epoxy molding compound or
other molding compound), a polyimide, a phenolic compound or
material, a material including a silicone dispersed therein, or a
combination of two or more thereof.
[0112] An electrical contact 28b is then formed or disposed on the
conductive patterned layer 28r of the substrate 28 to form the
semiconductor package device 6.
[0113] As used herein, the terms "approximately," "substantially,"
"substantial" and "about" are used to describe and account for
small variations. When used in conjunction with an event or
circumstance, the terms can refer to instances in which the event
or circumstance occurs precisely as well as instances in which the
event or circumstance occurs to a close approximation. For example,
when used in conjunction with a numerical value, the terms can
refer to a range of variation less than or equal to .+-.10% of that
numerical value, such as less than or equal to .+-.5%, less than or
equal to .+-.4%, less than or equal to .+-.3%, less than or equal
to .+-.2%, less than or equal to .+-.1%, less than or equal to
.+-.0.5%, less than or equal to .+-.0.1%, or less than or equal to
.+-.0.05%. For example, two numerical values can be deemed to be
"substantially" the same or "substantially" equal if a difference
between the values is less than or equal to .+-.10% of an average
of the values, such as less than or equal to .+-.5%, less than or
equal to .+-.4%, less than or equal to .+-.3%, less than or equal
to .+-.2%, less than or equal to .+-.1%, less than or equal to
.+-.0.5%, less than or equal to .+-.0.1%, or less than or equal to
.+-.0.05%. For example, "substantially" parallel can refer to a
range of angular variation relative to 0.degree. that is less than
or equal to .+-.10.degree., such as less than or equal to
.+-.5.degree., less than or equal to .+-.4.degree., less than or
equal to .+-.3.degree., less than or equal to .+-.2.degree., less
than or equal to .+-.1.degree., less than or equal to
.+-.0.5.degree., less than or equal to .+-.0.1.degree., or less
than or equal to .+-.0.05.degree.. For example, "substantially"
perpendicular can refer to a range of angular variation relative to
90.degree. that is less than or equal to .+-.10.degree., such as
less than or equal to .+-.5.degree., less than or equal to
.+-.4.degree., less than or equal to .+-.3.degree., less than or
equal to .+-.2.degree., less than or equal to .+-.1.degree., less
than or equal to .+-.0.5.degree., less than or equal to
.+-.0.1.degree., or less than or equal to .+-.0.05.degree..
[0114] Two surfaces can be deemed to be coplanar or substantially
coplanar if a displacement between the two surfaces is no greater
than 5 .mu.m, no greater than 2 .mu.m, no greater than 1 .mu.m, or
no greater than 0.5 .mu.m.
[0115] As used herein, the terms "conductive," "electrically
conductive" and "electrical conductivity" refer to an ability to
transport an electric current. Electrically conductive materials
typically indicate those materials that exhibit little or no
opposition to the flow of an electric current. One measure of
electrical conductivity is Siemens per meter (S/m). Typically, an
electrically conductive material is one having a conductivity
greater than approximately 10.sup.4 S/m, such as at least 10.sup.5
S/m or at least 10.sup.6 S/m. The electrical conductivity of a
material can sometimes vary with temperature. Unless otherwise
specified, the electrical conductivity of a material is measured at
room temperature.
[0116] In the description of some embodiments, a component provided
"on" or "over" another component can encompass cases where the
former component is directly on (e.g., in physical contact with)
the latter component, as well as cases where one or more
intervening components are located between the former component and
the latter component.
[0117] Additionally, amounts, ratios, and other numerical values
are sometimes presented herein in a range format. It is to be
understood that such range format is used for convenience and
brevity and should be understood flexibly to include numerical
values explicitly specified as limits of a range, but also to
include all individual numerical values or sub-ranges encompassed
within that range as if each numerical value and sub-range is
explicitly specified.
[0118] While the present disclosure has been described and
illustrated with reference to specific embodiments thereof, these
descriptions and illustrations do not limit the present disclosure.
It can be clearly understood by those skilled in the art that
various changes may be made, and equivalent components may be
substituted within the embodiments without departing from the true
spirit and scope of the present disclosure as defined by the
appended claims. The illustrations may not necessarily be drawn to
scale. There may be distinctions between the artistic renditions in
the present disclosure and the actual apparatus, due to variables
in manufacturing processes and such. There may be other embodiments
of the present disclosure which are not specifically illustrated.
The specification and drawings are to be regarded as illustrative
rather than restrictive. Modifications may be made to adapt a
particular situation, material, composition of matter, method, or
process to the objective, spirit and scope of the present
disclosure. All such modifications are intended to be within the
scope of the claims appended hereto. While the methods disclosed
herein have been described with reference to particular operations
performed in a particular order, it can be understood that these
operations may be combined, sub-divided, or re-ordered to form an
equivalent method without departing from the teachings of the
present disclosure. Therefore, unless specifically indicated
herein, the order and grouping of the operations are not
limitations of the present disclosure.
* * * * *