U.S. patent application number 15/283271 was filed with the patent office on 2018-02-01 for method for forming shallow trenches of the dual active regions.
The applicant listed for this patent is SHANGHAI HUALI MICROELECTRONICS CORPORATION. Invention is credited to Minjie Chen, Quan Jing, Yukun Lv, Yu Ren, Jin Xu, Xusheng Zhang, Jun Zhu.
Application Number | 20180033810 15/283271 |
Document ID | / |
Family ID | 57533978 |
Filed Date | 2018-02-01 |
United States Patent
Application |
20180033810 |
Kind Code |
A1 |
Jing; Quan ; et al. |
February 1, 2018 |
METHOD FOR FORMING SHALLOW TRENCHES OF THE DUAL ACTIVE REGIONS
Abstract
The invention disclosed a method for forming shallow trenches of
the dual active regions. Firstly, forming an etch stop layer on a
semiconductor substrate; secondly, using a first accurate photomask
to expose and develop the semiconductor substrate, until the etch
stop layer has been exposed on the top of the first shallow trench
regions and the second shallow trench regions; thirdly, etching the
etch stop layer entirely in the exposed regions; fourthly, using a
second photomask to expose and develop the first shallow trench
regions which require a deeper etch depth of the trench than that
of the second shallow trench regions; fifthly, etching and forming
preliminary entirely depth in the first shallow trench regions, and
then removing the second photomask; at last, taking the etch stop
layer as a mask, and simultaneously etching the first shallow
trench regions and the second shallow trench regions to form the
first hallow trenches and the second shallow trenches having
different depths. The invention has realized a low-cost photomask
application and an optimization of the etching process by
optimizing the photomask design.
Inventors: |
Jing; Quan; (Shanghai,
CN) ; Xu; Jin; (Shanghai, CN) ; Chen;
Minjie; (Shanghai, CN) ; Ren; Yu; (Shanghai,
CN) ; Lv; Yukun; (Shanghai, CN) ; Zhu;
Jun; (Shanghai, CN) ; Zhang; Xusheng;
(Shanghai, CN) |
|
Applicant: |
Name |
City |
State |
Country |
Type |
SHANGHAI HUALI MICROELECTRONICS CORPORATION |
Shanghai |
|
CN |
|
|
Family ID: |
57533978 |
Appl. No.: |
15/283271 |
Filed: |
September 30, 2016 |
Current U.S.
Class: |
1/1 |
Current CPC
Class: |
H01L 21/0475 20130101;
H01L 27/1461 20130101; H01L 27/14687 20130101; H01L 21/31 20130101;
H01L 21/02057 20130101; H01L 21/31116 20130101; H01L 21/76229
20130101; H01L 21/3213 20130101; H01L 21/0274 20130101; H01L
21/31138 20130101 |
International
Class: |
H01L 27/146 20060101
H01L027/146 |
Foreign Application Data
Date |
Code |
Application Number |
Jul 28, 2016 |
CN |
201610604747.7 |
Claims
1. A method for forming shallow trenches of the dual active
regions, comprising the steps of Step S01: providing a
semiconductor substrate having first shallow trench regions and
second shallow trench regions, on which forming an etch stop layer;
Step S02: using a first accurate photomask to expose and develop a
first photoresist covering the semiconductor substrate, until the
etch stop layer has been exposed on the top of the first shallow
trench regions and the second shallow trench regions; Step S03:
etching the etch stop layer entirely in the exposed regions; Step
S04: using a second low-cost photomask to expose and develop a
second photoresist to expose the first shallow trench regions; Step
S05: etching and forming the first shallow trenches with a
preliminary depth in the first shallow trench regions, and then
removing the second photomask, wherein an in-situ stripping process
is utilized to remove polymer residues generated by the etching
reaction; Step S06: taking the etch stop layer as a mask, and
simultaneously etching the first shallow trench regions and the
second shallow trench regions to form the first hallow trenches and
second shallow trenches having different depths, wherein the depth
of the first shallow trenches are deeper than that of the second
shallow trenches.
2. The method of claim 1, wherein the etch stop layer is a hard
mask layer in the Step S01.
3. The method of claim 1, wherein the second shallow trench regions
are completely covered by the second photomask in the Step S04.
4. The method of claim 1, wherein in the Step S03, a stripping
process and a cleaning process are employed subsequently to remove
polymer residues generated by the etching reaction.
5. The method of claim 4, wherein the stripping process in the Step
S03 is a dry stripping process.
6. The method of claim 5, wherein the dry stripping process is an
oxidation stripping process or a plasma stripping process.
7. (canceled)
8. The method of claim 7, wherein the process condition of the
in-situ stripping process in the Step S05 is that the oxygen the
gas flow is 100-300 sccm, the power is 500-1500 W, the pressure is
2-10 mT, and the temperature is 40-60.degree. C.
9. The method of claim 1, wherein in the Step S06, the subsequent
cleaning process is utilized to remove polymer residues generated
by the etching reaction.
10. The method of claim 9, wherein the process condition of the
cleaning process in the Step S06 is that a DHF and an APM are
adopted for cleaning in turn.
Description
CROSS-REFERENCE TO RELATED APPLICATION
[0001] This application claims the priority benefit of China patent
application serial No. 201610604747.7, filed Jul. 28, 2016. The
entire contents of the above-mentioned patent application are
hereby incorporated by reference herein and made a part of the
specifications.
FIELD OF THE INVENTION
[0002] The present invention relates to the field of semiconductor
manufacturing technology, and particularly to a new method for
forming shallow trenches of the dual active regions.
BACKGROUND OF THE INVENTION
[0003] CMOS image sensors are electrical solid-state imaging
sensors, which are exhibiting more superiority in the aspects of
system complexity and reliability, data output and exposure
control, etc., than traditional CCD, due to their intrinsic high
integration. Therefore, audio and video products based the CMOS
image sensors will replace the CCD products to become the main
trend of market in the future.
[0004] In the semiconductor manufacturing process, the CMOS image
sensors proposes special requirements for structures of their
shallow trenches. In addition to having active regions as the
traditional CMOS, pixel regions are also required to manufacture to
meet the needs of image sensor. Therefore, in the shallow trench
etching process, two different etch depths are required to form two
kinds of active regions structure.
[0005] Referring to FIGS. 1-5, which are schematic views
illustrating a shallow trench forming process at the dual active
regions of the prior art. As shown in FIGS. 1-5, the solutions of
the prior art are that adopting two separate photoresist exposure
processes to meet the shallow trench etching's needs of different
depths at the active regions I and the pixel regions II of the CMOS
image sensors respectively. Detailed steps are as follows:
[0006] 1) using a first accurate photomask to accomplish the
exposure of active regions I of the CMOS image sensors, as shown in
FIG. 1;
[0007] 2) accomplishing a shallow trench etching process with
required depth for active regions I of the CMOS image sensors in
the etching process chamber, as shown in FIG. 2;
[0008] 3) adopting subsequent a stripping process and a cleaning
process to remove polymer residues generated by the reaction;
[0009] 4) using a second accurate photomask to accomplish the
exposure of the pixel regions II , as shown in FIG. 3;
[0010] 5) accomplishing a shallow trench etching process with
required depth for the pixel regions II in the etching process
chamber, as shown in FIG. 4;
[0011] 6) adopting subsequent a stripping process and a cleaning
process to remove the polymer residues generated by the reaction.
Finally, the shallow trench structure with different depths at the
dual active regions is formed, as shown in FIG. 5.
[0012] However, above solutions of the prior art exist some
problems, which are:
[0013] 1) the two accurate photomasks are needed which increases
the cost;
[0014] 2) the shallow trench depths at the active regions of the
CMOS image sensors after the first etching process will bring great
difficulties for the refilling ability and flatness of the BARC
layer 1 (bottom anti-reflective coating) of the second accurate
photomask.
BRIEF SUMMARY OF THE DISCLOSURE
[0015] To overcome the problems as mentioned above, it is an object
of the present invention to provide a new method for forming
shallow trenches of dual active regions to accomplish a low-cost
photomask application and an optimization of the etching process by
optimizing the photomask design.
[0016] To achieve above object, technical solutions of the present
invention are as follows:
[0017] A method for forming shallow trenches of the dual active
regions, comprising the steps of
[0018] Step S01: providing a semiconductor substrate having first
shallow trench regions and second shallow trench regions, on which
forming an etch stop layer;
[0019] Step S02: using a first accurate photomask to expose and
develop the semiconductor substrate, until the etch stop layer has
been exposed on the top of the first shallow trench regions and the
second shallow trench regions;
[0020] Step S03: etching the etch stop layer entirely in the
exposed regions;
[0021] Step S04: using a second photomask to expose and develop the
first shallow trench regions;
[0022] Step S05: etching and forming the first shallow trenches
with a preliminary depth in the first shallow trench regions, and
then removing the second photomask;
[0023] Step S06: taking the etch stop layer as a mask, and
simultaneously etching the first shallow trench regions and the
second shallow trench regions to form the first shallow trenches
and the second shallow trenches having different depths, wherein
the depth of the first shallow trenches are deeper than that of the
second shallow trenches.
[0024] Preferably, the etch stop layer is a hard mask layer in the
Step S01.
[0025] Preferably, the second shallow trench regions are completely
covered by the second photomask in the Step S04.
[0026] Preferably, in the Step S03, a stripping process and a
cleaning process are employed subsequently to remove polymer
residues generated by the etching reaction.
[0027] Preferably, the stripping process in the Step S03 is a dry
stripping process.
[0028] Preferably, the dry stripping process is an oxidation
stripping process or a plasma stripping process.
[0029] Preferably, in the Step S05, an in-situ stripping process is
utilized to remove the polymer residues generated by the etching
reaction.
[0030] Preferably, the process condition of the in-situ stripping
process in the Step S05 is that the oxygen gas flow is 100-300
sccm, the power is 500-1500 W, the pressure is 2-10 mT, and the
temperature is 40-60.degree. C.
[0031] Preferably, in the Step S06, subsequent cleaning processes
are utilized to remove polymer residues generated by the etching
reaction.
[0032] Preferably, the process condition of the cleaning process in
the Step S06 is that a DHF and an APM are adopted for cleaning in
turn.
[0033] Concluded from the above technical solutions, in order to
meet the needs of two different etching depths of shallow trench in
different regions for certain special chip design, firstly, the
present invention uses a first accurate photomask to etch the etch
stop layer, secondly, adopting the low-cost second photomask to
accomplish the subsequent etching processes, wherein the in-situ
stripping process is utilized to complete the integral etching of
shallow trench regions with two different depths. The present
invention has realized a low-cost photomask application and an
optimization of the etching process by optimizing the photomask
design, and has provided a new solution for the shallow trench
process of the dual active regions.
BRIEF DESCRIPTION OF THE DRAWINGS
[0034] FIGS. 1-5 are schematic views illustrating the shallow
trench forming process of the dual active regions of the prior
art;
[0035] FIG. 6 is a flow sheet illustrating the shallow trench
forming method of the dual active regions of the present
invention;
[0036] FIGS. 7-10 are schematic views illustrating the shallow
trench forming process of the dual active regions according to a
preferred embodiment of the present invention;
[0037] FIG. 11 is a referential photomicrograph illustrating the
etching morphology of the shallow trenches;
[0038] FIG. 12 is a photomicrograph illustrating the etching
morphology of the shallow trenches according to the method of the
present invention;
[0039] FIG. 13 is a schematic view illustrating referential defects
performance after the etching of the shallow trenches;
[0040] FIG. 14 is a schematic view illustrating referential defects
performance after the etching of the shallow trenches according to
the method of the present invention.
DETAILED DESCRIPTION OF THE EMBODIMENTS
[0041] The present invention will be described in further details
hereinafter by referring to the accompanying drawings, so as to
provide a better understanding of the present invention.
[0042] It should be noted that, in the following specific
embodiments, when these embodiments of the present invention are
described in detail, in order to clearly illustrate the structure
of the present invention to facilitate explanation, the
accompanying drawings are not necessarily drawn to scale, some
features in the drawings may have been fragmentary enlarged,
deformed or simplified. Therefore, it would be avoided to
understand this as a limitation to the present invention.
[0043] Referring to FIG. 6, which is a flow sheet illustrating the
shallow trench forming method of the dual active regions of the
present invention. As shown in FIG. 6, which discloses a method for
forming shallow trenches of the dual active regions, comprising the
steps of
[0044] Executing Step S01: providing a semiconductor substrate
having first shallow trench regions and second shallow trench
regions, on which forming an etch stop layer.
[0045] Referring to FIG. 7, taking the semiconductor substrate of
silicon wafer used to manufacture the CMOS image sensors as an
example, active regions I and pixel regions II of the CMOS image
sensors adjacent to each other are disposed at the region of the
chips of the CMOS image sensors on the semiconductor substrate 10.
Firstly, a hard mask layer 11 such as silicon nitride is deposited
on the semiconductor substrate 10 through a conventional CMOS
process, which is used as an etch stop layer 11.
[0046] Executing Step S02: using a first accurate photomask to
expose and develop the semiconductor substrate, until the etch stop
layer has been exposed on the top of the first shallow trench
regions and the second shallow trench regions.
[0047] Specifically, referring to FIG. 7 again, taking an accurate
photomask as the first photomask, the active regions I (the first
shallow trench regions) and the pixel regions II (the second
shallow trench regions) of the CMOS image sensors requiring
different etch depths of the shallow trenches are simultaneously
exposed and developed, until the hard mask layer 11 has been
exposed out on the top of the first shallow trench regions and the
second shallow trench regions.
[0048] Executing Step S03: etching the etch stop layer entirely in
the exposed regions.
[0049] Specifically, referring to FIG. 7 again, then, the etching
of the exposed hard mask layer 11 in the exposed regions is
proceeded in the etching chamber through a conventional etching
process, until the semiconductor substrate 10 has been exposed out
on the top of the shallow trenches in the first shallow trench
regions and the shallow trenches in the second shallow trench
regions.
[0050] After the above etching process, a stripping process and a
cleaning process are employed subsequently to remove polymer
residues generated by the etching reaction. Wherein, the stripping
process is a dry stripping process (ASH), such as the conventional
oxidation stripping process or plasma stripping process. Of course,
other proper processes could also be utilized to remove polymer
residues generated by the etching reaction.
[0051] Executing Step S04: using a second photomask to expose and
develop the first shallow trench regions.
[0052] Specifically, referring to FIG. 8, then, the second
photomask with a low-cost, such as the low-cost photoresist 12, is
utilized to cover completely the pixel regions II (the second
shallow trench regions) which are avoided to be exposed, so that
only the active regions I (the first shallow trench regions) of the
CMOS image sensors are exposed and developed.
[0053] Executing Step S05: etching and forming the first shallow
trenches with a preliminary depth in the first shallow trench
regions, and then removing the second photomask.
[0054] Specifically, referring to FIG. 8 again, then, taking the
hard mask layer 11 of silicon nitride in the active regions I of
the CMOS image sensors as a mask, the exposed regions of the CMOS
image sensors are firstly etched to a T1 depth which is the
preliminary entirely depth of etching for the CMOS image
sensors.
[0055] Specifically, referring now to FIG. 9, after the above
etching process, the second photomask needs to be removed. An
in-situ strip process can be utilized to remove the photoresist
residues generated by the second photomask and the polymer residues
generated by the etching reaction in the etching chamber mentioned
above. Wherein, the process condition of the in-situ stripping
process is that the oxygen gas flow is 100-300 sccm, the power is
500-1500 W, the pressure is 2-10 mT, and the temperature is
40-60.degree. C.
[0056] Executing Step S06: taking the etch stop layer as a mask,
and simultaneously etching the first shallow trench regions and the
second shallow trench regions to form the first shallow trenches
and the second shallow trenches having different depths, wherein
the depth of the first shallow trenches are deeper than that of the
second shallow trenches.
[0057] Specifically, referring now to FIG. 10, finally, taking the
hard mask layer 11 of silicon nitride in the active regions I and
the pixel regions II of the CMOS image sensors as a mask, the first
shallow trench regions and the second shallow trench regions are
simultaneously etched a T2 depth in the etching chamber mentioned
above, again. In other words, if the shallow trench depths of the
pixel regions II and the active regions I are set as Ta and Tb
respectively, the shallow trench depth Ta of the pixel regions II
is equal to T2, and the shallow trench depth Tb of the active
regions I is equal to the sum of T1 and T2.
[0058] The subsequent cleaning process is then utilized to remove
polymer residues generated by the etching reaction, in which a DHF
(hydrofluoric acid dilution) is firstly adopted for cleaning, and
then an APM (solution mixed by NH.sub.4OH, H.sub.2O.sub.2, and
H.sub.2O, also called SC-1 cleaning solution) is adopted
subsequently for cleaning.
[0059] Applicability of the present invention can be further
disclosed by comparison with the prior art in FIGS. 11-15.
[0060] As shown in FIGS. 11-12, compared with the prior art, the
present invention can reach the same requirement for the structure
of the shallow trench (text and arrows in FIGS. 11-12 can be
ignored), and can also reach the same requirement for the depth
uniformity.
[0061] As shown in FIGS. 13-14, compared with the prior art, the
present invention can reach the same requirement for the defects
performance.
[0062] In summary, the present invention completes the integral
etching of the shallow trench regions with two different depths by
two etching processes, which employs a first accurate photomask to
expose and develop the etch stop layer and a low-cost second
photomask to accomplish the subsequent etching process
respectively, according to the requirements of two different
etching depths of the shallow trench at the different regions for
certain special chip design. Wherein the in-situ stripping process
is employed in the second etching process. The present invention
has realized a low-cost photomask application and an optimization
of etching process by optimizing the photomask design, so that a
new solution has been provided to satisfy the requirements for the
shallow trench process at the dual active regions.
[0063] Although the present invention has been disclosed as above
with respect to the preferred embodiments, they should not be
construed as limitations to the present invention. Various
modifications and variations can be made by the ordinary skilled in
the art without departing the spirit and scope of the present
invention. Therefore, the protection scope of the present invention
should be defined by the appended claims.
* * * * *